JP4781230B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a method for manufacturing a semiconductor device.

  As portable electronic devices such as mobile phones, PDAs, DVCs, and DSCs are accelerating their functions, miniaturization and weight reduction are essential for their acceptance in the market. There is a need for a system LSI.

  One example of a module that realizes such a highly integrated system LSI is a high-frequency bipolar transistor. An example of a structure that aims to improve the performance of a high-frequency bipolar transistor is a heterojunction bipolar transistor whose base layer is made of a silicon germanium (SiGe) alloy. .

  A configuration of a SiGe-based heterojunction bipolar transistor in the bipolar transistor manufacturing technique described in Patent Document 1 will be described with reference to FIGS. 17 and 18. FIG. 17 is an element cross-sectional view of a SiGe-based heterojunction bipolar transistor, and FIG. 18 is a partially enlarged view centering on an emitter / base region.

In FIG. 17, an n ⁻ type layer (epitaxial layer) 102 serving as a collector layer is epitaxially grown on a p ⁻ type silicon substrate (not shown) via an n ⁺ type collector buried layer 101. The n ⁻ -type layer 102 is removed by etching leaving portions necessary as a collector layer and a collector take-out layer. A trench is formed in the element isolation region, and a polycrystalline silicon film 104 is embedded in the trench via an oxide film 103. The substrate surface on which collector formation and element isolation embedding have been performed is planarized by an oxide film (buried oxide film) 105, and a base and an emitter are further formed thereon by epitaxial growth. That is, a p-type SiGe layer (SiGe alloy layer) 106 serving as an internal base layer is epitaxially grown, and an n-type silicon layer 107 serving as an emitter layer and an n ⁺ -type silicon layer 108 serving as an emitter contact layer (emitter electrode) are formed thereon. Sequentially epitaxially grown. The n ⁺ -type silicon layer 108 and the n-type silicon layer 107 are removed by etching using the oxide film 109 as a mask, leaving only a region necessary as an emitter. Of the remaining p-type SiGe layer 106, the outside of the region serving as the internal base layer is etched to a predetermined depth using the oxide film (side wall film) 110 and the oxide film 109 as a mask, and p ^{+ serving as the} external base layer is formed here. The type SiGe layer 111 is formed by selective epitaxial growth.

As shown in FIG. 18, in the conventional SiGe-based heterojunction bipolar transistor structure, the n-type silicon layer 107 serving as the emitter layer has a convex cross section (the contact surface 150 between the emitter layer 107 and the emitter electrode 108 is the side wall film 110). The shape is located above the lower surface 160). Since the emitter-base junction is formed on the bottom side of the convex portion, the dimension width of the junction portion (dimension width of the emitter layer) is W _e2 , and from the dimension width W _{e1 of} the n ⁺ -type silicon layer (emitter electrode) 108. Is also getting bigger.
Japanese Patent Laid-Open No. 4-179235

In the future, when manufacturing a high-performance semiconductor device (SiGe-based heterojunction bipolar transistor) with less variation in performance, the n ⁺ -type silicon layer (emitter electrode) 108 can be finely processed with higher accuracy in the conventional structure. It is necessary to reduce W _e1 and, as a result, to reduce the dimension width W _e2 of the emitter layer. However, for this purpose, it is indispensable to introduce a highly accurate exposure apparatus, which leads to an increase in manufacturing cost.

In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention provides an opening in a predetermined region on the side including an active region on a semiconductor substrate on which an active region surrounded by an element isolation film is formed. A first step of forming a protective film having a portion, a second step of forming a conductive layer functioning as a base layer and an n-type first impurity-free silicon film in the opening of the protective film, and an active region A third step of forming an emitter electrode containing an n-type first impurity on the upper silicon film; a fourth step of etching the silicon film using the emitter electrode as a mask; and a sidewall film covering the sidewall of the emitter electrode A fifth step of forming a p-type second impurity so as to reach the surface of the active region and forming an impurity region in the conductive layer and the silicon film, and an n-type included in the emitter electrode First A seventh step of diffusing a pure material on the surface of the silicon film, and forming a first region containing the n-type first impurity and a second region not containing the n-type first impurity in the silicon film; comprising, in the fourth step, the silicon film, the upper surface of the portion in contact with the emitter electrode, is processed from the top surface of the portion which is not in contact with the emitter electrode in a convex shape so as to be positioned above, in the fifth step, the side walls The film is formed so as to cover the side wall of the emitter electrode and the side wall of the silicon film in contact with the emitter electrode. In the seventh step, at least a part of the second region of the silicon film is formed of the conductive layer, the side wall film, And is formed so as to be in contact with the conductive layer and the sidewall film.

  In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention provides an opening in a predetermined region on the side including an active region on a semiconductor substrate on which an active region surrounded by an element isolation film is formed. A first step of forming a protective film having a portion, a second step of forming a conductive layer and a silicon film functioning as a base layer in the opening of the protective film, and on the silicon film above the active region, A third step of forming an emitter electrode containing a first impurity; a fourth step of etching the silicon film using the emitter electrode as a mask; a fifth step of forming a sidewall film covering the sidewall of the emitter electrode; A second step of introducing a second impurity so as to reach the surface of the region to form an impurity region in the conductive layer and the silicon film; and a step of diffusing the first impurity contained in the emitter electrode to the surface of the silicon film, And a seventh step of forming a first region containing the first impurity and a second region not containing the first impurity in the con film. In the fourth step, the silicon film has the first region The contact surface between the region and the emitter electrode is processed into a convex shape such that the contact surface is located above the lower surface of the sidewall film. In the seventh step, at least a part of the second region of the silicon film is formed on the conductive layer and the sidewall. It is characterized by being located between the film and being in contact with the conductive layer and the sidewall film.

  With this manufacturing method, the dimension width of the first region which is the emitter layer is smaller than the dimension width of the interface between the silicon film and the conductive layer. Compared with the case where the width is the same, the same current density can be obtained with a small current, and a high current amplification factor can be obtained. Therefore, a transistor with low power consumption can be formed. In addition, since at least a part of the second region of the silicon film is located between the conductive layer and the side wall film and is in contact with the conductive layer and the side wall film, the emitter-base junction area has a conventional structure ( The second region is narrower than the case where the second region also functions as an emitter layer. For this reason, a transistor in which the junction capacitance is reduced because the junction area is smaller than that of the conventional structure can be obtained. As a result, a high-performance semiconductor device can be provided.

  Further, according to this manufacturing method, at least a part of the second region of the silicon film is located between the conductive layer and the sidewall film, and the conductive layer and the sidewall film are not in direct contact with each other. Recombination of the base current at the interface with the film can be suppressed, and a semiconductor device having good base current characteristics can be manufactured.

  Further, in the diffusion of the first impurity in the seventh step, the contact surface between the first region and the emitter electrode is located above the lower surface of the side wall film, so that the side wall film serves as a diffusion barrier for the first impurity and laterally. Diffusion in the direction is suppressed, and the dimension width of the first region can be reduced with better controllability.

  Furthermore, according to this manufacturing method, since the conductive layer and the silicon film are formed in the opening of the protective film, there is no portion where the conductive layer and the silicon film run on the protective film, and the emitter electrode formed on the protective film The height of the material is arranged lower by the thickness of the conductive layer and the silicon film than the height of the emitter electrode material formed in the opening. For this reason, when forming a resist pattern for processing the emitter electrode material into a desired emitter electrode, the exposure light scattering (emitter electrode) caused by the emitter electrode material on the portion (end portion of the protective film) riding on the protective film (Scattering to the resist pattern side for processing into a resist pattern) is reduced, and deformation and shape variation of the resist pattern can be suppressed. As a result, a semiconductor device with small performance variation can be provided.

  In such a manufacturing method, it is desirable that the upper surface of the protective film is on the lower surface than the contact surface between the first region and the emitter electrode. By doing so, the height of the emitter electrode material formed on the protective film becomes lower than the height of the emitter electrode material formed in the opening, so that the resist pattern for processing into the emitter electrode Scattering to the side is further suppressed, and deformation and shape variation of the resist pattern can be further suppressed.

  Further, in such a manufacturing method, it is desirable that the conductive layer is a silicon germanium (SiGe) alloy layer, and the lower surface of the first region reaches the conductive layer. By doing so, since the band gap of the SiGe alloy layer is narrower than the band gap of the silicon film, the lower surface of the first region does not reach the conductive layer (the lower surface of the first region is the silicon film). Compared to the case of the above, the height of the barrier against electrons injected from the emitter layer to the base layer is reduced. As a result, the emitter injection efficiency is increased, and a higher current amplification factor can be obtained. A semiconductor device can be provided.

  In the present invention, the conductive layer includes a conductive layer obtained by introducing a P-type or N-type impurity into a semiconductor.

  According to the method for manufacturing a semiconductor device of the present invention, a high-performance semiconductor device is provided in which the dimensional width of the emitter layer is miniaturized, the performance variation is small.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. In all the drawings, the same reference numerals are given to the same components, and the description will be omitted as appropriate.
(First embodiment)
1st Embodiment of this invention is described based on FIG. 1 and FIG. FIG. 1 is an element cross-sectional view of a SiGe-based heterojunction bipolar transistor according to the present invention, and FIG. 2 is a partially enlarged view centering on an emitter / base region.

In FIG. 1, an epitaxial layer 2 used as a collector layer and an element isolation film 3 that is STI (Shallow Trench Isolation) are formed on a part of the epitaxial layer 2 on a silicon substrate 1. A part of the epitaxial layer 2 surrounded by the element isolation film 3 becomes an active region A1. Further, a protective film 4 made of a silicon oxide film having an opening A2 in a predetermined region on the side including the active region A1 is provided on the element isolation film 3. Further, a SiGe alloy layer 6a used as a base region is formed on the active region A1 in the opening A2 of the protective film 4, and a silicon film 7 and an n-type used as an emitter layer are formed on the SiGe alloy layer 6a. A diffusion layer 13 is formed. The n-type diffusion layer 13 is formed by diffusing an n-type impurity in a silicon film 7 having a convex cross section, and the silicon film 7 before diffusion is processed into a convex shape. On the n-type diffusion layer 13, a polycrystalline silicon film 8a and a silicide film 15a are formed. Further, the n-type diffusion layer 13, the polycrystalline silicon film 8a, and the silicide film 15a are surrounded by a sidewall film 11 (commonly referred to as a sidewall) made of an insulating film. Here, the contact surface 50 between the n-type diffusion layer 13 and the polycrystalline silicon film 8 a is located above the lower surface 60 of the sidewall film 11. The silicon film 7 is located between the sidewall film 11 made of an insulating film and the SiGe alloy layer 6a, and is in contact with the sidewall film 11 and the SiGe alloy layer 6a. A p ⁺ diffusion layer 12a connected to the base region is formed in the periphery thereof, and a silicide used as a low resistance layer of the external base layer is formed on the surface of the p ⁺ diffusion layer 12 in the region opened by the protective film 14 made of a silicon oxide film. A film 15b is formed. The SiGe alloy layer 6a is the “conductive layer” of the present invention, the silicon film 7 is the “second region” of the present invention, the n-type diffusion layer 13 is the “first region” of the present invention, and the polycrystalline silicon film 8a. The “emitter electrode” of the present invention and the p ⁺ diffusion layer 12a are examples of the “impurity region” of the present invention.

As shown in FIG. 18 above, in the emitter layer having the conventional structure, the dimension width of the emitter-base junction portion was _We2 . On the other hand, in the first embodiment of the present invention, as shown in FIG. 2, the first region and the second region exist inside the silicon film having the same processing size, and this first region is further used as the emitter. Used as a layer. Since the emitter-base junction is formed at the bottom portion of the emitter layer, the dimension width of the junction is W _e3 , which is smaller than the dimension width of the interface between the silicon film and the SiGe alloy layer (dimension width W _e2 in the conventional structure). Become. Further, by controlling the diffusion of the n-type impurity into the silicon film 7, the dimension width of the junction portion of the emitter layer can be made substantially equal to _We1 . As a result, the dimension width of the emitter layer can be reduced without introducing a high-precision exposure apparatus. When the dimensional width of the emitter layer is reduced, that is, when the dimensional width is W _e3 or W _e1 , the same current density can be obtained with a smaller current than in the case of the dimensional width W _{e2 at} the interface between the silicon film and the SiGe alloy layer. Therefore, a transistor with low power consumption can be formed, and as a result, a high-performance semiconductor device can be obtained.

  In the first embodiment of the present invention, since at least a part of the silicon film 7 is located between the SiGe alloy layer 6a and the sidewall film 11 and is in contact with the SiGe alloy layer 6a and the sidewall film 11, the emitter The base junction area is narrower than that of the conventional structure (when the silicon film 7 also functions as an emitter layer). Therefore, it is possible to provide a transistor (semiconductor device) in which the junction capacitance is reduced because the junction dimension area is smaller than that of the conventional structure.

  3 to 15 are cross-sectional views for explaining a semiconductor device manufacturing process according to the first embodiment of the present invention.

(Step 1: See FIG. 3) An element isolation film 3 such as STI is formed on a p-type silicon substrate 1. Next, in order to produce the collector layer 2 including the active region A1, n-type impurities are ion-implanted and activated. For example, phosphorus (P) is implanted at an acceleration energy of about 500 to 4000 keV to a concentration of about 3 × 10 ¹³ cm ⁻² to about 3 × 10 ¹⁵ cm ⁻² , and heat treatment is performed at about 1000 ° C. Here, the collector layer 2 is applied to the p-type silicon substrate 1 and, for example, arsenic (As) is accelerated to an energy of about 50 to 200 keV to a concentration of about 1 × 10 ¹⁵ cm ⁻² to 1 × 10 ¹⁶ cm ^−2. Alternatively, an n ⁻ -type doped silicon epitaxial layer may be grown and formed thereon, and then an element isolation film 3 such as STI may be formed.

  (Step 2: see FIG. 4) A silicon oxide film 4 and a polycrystalline silicon film 5 are each formed to a thickness of about 50 nm by low pressure CVD (Chemical Vapor Deposition). A resist pattern is provided by lithography, and unnecessary portions of the polycrystalline silicon film 5 are removed by dry etching, and then the silicon oxide film 4 is removed by wet etching. Thus, the silicon oxide film 4 and the polycrystalline silicon film 5 having a predetermined opening (bipolar transistor formation region) A2 including the active region A1 are provided on the element isolation film 3.

(Step 3: refer to FIG. 5) A silicon germanium (SiGe) alloy layer 6 doped with boron (B) by about 1 × 10 ¹⁹ cm ⁻³ and a silicon film 7 not containing germanium (Ge) are formed by using a low pressure CVD method. Epitaxially grow. The film thicknesses of the SiGe alloy layer 6 and the silicon film 7 are each about 40 nm and about 80 nm in total. Here, both the SiGe alloy layer 6 and the silicon film 7 are conformally formed at the boundary of the opening of the silicon oxide film 4 and the polycrystalline silicon film 5. The SiGe alloy layer 6 is formed by epitaxial growth to have the same lattice constant as that of the underlying substrate (p-type silicon substrate 1), and the silicon film 7 formed thereon also reflects the lattice constant of the underlying SiGe alloy layer 6. Formed.

  The Ge concentration in the SiGe alloy layer 6 may be constant in the layer, but a gradient profile in which the Ge concentration gradually increases from the side in contact with the silicon film 7 toward the active region A1 (collector layer 2). By doing so, it is possible to shorten the travel time of electrons traveling through the base, and to form a transistor that operates at high speed. At this time, the Ge concentration is preferably about 0% on the side in contact with the silicon film 7 and about 15% to 20% on the side in contact with the collector layer 2.

  Further, the silicon film 7 may be doped with boron (B) similarly to the SiGe alloy layer 6 or may not be doped.

  Further, before the formation of the SiGe alloy layer 6, a silicon film not containing boron (B) or a SiGe alloy layer not containing boron (B) may be epitaxially grown by a low pressure CVD method.

(Step 4: see FIG. 6) A resist pattern is provided by lithography, and unnecessary portions of the silicon film 7 and the SiGe alloy layer 6 are removed by dry etching. At this time, the polycrystalline silicon film 5 is also removed by etching. As a result, the SiGe alloy layer 6a and the silicon film 7 used as the base region processed into the desired pattern A3 are formed in the bipolar transistor formation region A2. As dry etching conditions, for example, the pressure is 2 Pa (15 mT), the gas flow rate is O ₂ / HBr = 2/180 ml / min (sccm), and the RF power Upper / Lower is 250/12 W. A spacer-like SiGe alloy layer 6 b is formed on the side wall (opening boundary) of the silicon oxide film 4.

(Step 5: see FIG. 7) A polycrystalline silicon film 8 doped with an n-type impurity of about 1 × 10 ²⁰ cm ⁻³ or more is formed by a low pressure CVD method, and a silicon nitride film 9 is further formed. For example, arsenic (As) or phosphorus (P) is used as the n-type impurity. The thickness of the polycrystalline silicon film 8 is about 200 nm, and the thickness of the silicon nitride film 9 is about 50 nm. The n-type impurity is an example of the “first impurity” in the present invention.
(Step 6: see FIG. 8) A resist pattern 10 for processing a desired emitter electrode is formed in the bipolar transistor formation region A2 by lithography.

Here, since the SiGe alloy layer 6a and the silicon film 7 are formed in the bipolar transistor formation region A2, there is no portion where the SiGe alloy layer 6a and the silicon film 7 run on the silicon oxide film 4, and on the silicon oxide film 4 The height of the polycrystalline silicon film 8 formed on the polycrystalline silicon film 5, the SiGe alloy layer 6a, and the silicon film 7 is higher than that of the polycrystalline silicon film 8 formed in the bipolar transistor formation region A2. The thickness is set low. For this reason, when forming the resist pattern 10 for processing the polycrystalline silicon film 8 into the desired emitter electrode 8a, the portion that runs on the silicon oxide film 4 as shown in FIG. 19 (the end of the silicon oxide film 4). Scattering of exposure light (scattering toward the resist pattern 10a for processing into the emitter electrode 8a) due to the polycrystalline silicon film 8 is reduced, and deformation and shape variation of the resist pattern 10 can be suppressed.
(Step 7: see FIG. 9) The silicon nitride film 9, the polycrystalline silicon film 8, and the silicon film 7 are etched in this order by dry etching. At this time, the dry etching is not performed until the silicon film 7 is completely removed, and is finished in a state where a part remains on the entire surface of the SiGe alloy layer 6a. As a result, the silicon film 7 is finished in a shape 70 having a convex cross section. Furthermore, etching damage enters the surface 80a of the silicon film 7, and a damaged layer is formed. At this time, the polycrystalline silicon film 8 is processed as a polycrystalline silicon film 8 a serving as an emitter electrode, and a sidewall film 8 b made of a polycrystalline silicon film around the SiGe alloy layer 6 a and the silicon film 7. The silicon nitride film 9 is processed as a silicon nitride film 9a and functions as a mask when the polycrystalline silicon film 8 is etched. As dry etching conditions, for example, the pressure is 2 Pa (15 mT), the gas flow rate is O ₂ / HBr = 2/180 ml / min (sccm), and the RF power Upper / Lower is 250/12 W.

  Here, since the SiGe alloy layer 6a and the silicon film 7 are formed only in the bipolar transistor formation region A2, the portion where the SiGe alloy layer 6a and the silicon film 7 run on the silicon oxide film 4 as shown in FIG. Instead, the SiGe alloy layer 6 a and the silicon film 7 are formed on the silicon oxide film 4. Therefore, when the dry etching of the polycrystalline silicon film 8 is advanced, the silicon oxide film 4 is exposed outside the bipolar transistor formation region A2 when the silicon film 7 is exposed. Etching control between the same materials (between the polycrystalline silicon film 8 and the silicon film 7 in this embodiment) is usually difficult, but the exposure time of the silicon oxide film 4 is an end point used in normal dry etching. By considering this as the exposure time of the silicon film 7, the etching process to the silicon film 7 can be performed with good control, and the silicon film 7 can be reproduced in a highly convex shape 70 with high accuracy. Can be finished.

(Step 8: see FIG. 10) A silicon oxide film, which is an insulating film, is formed using a CVD method, and then etched back using dry etching, whereby the silicon nitride film 9a, the polycrystalline silicon film 8a, and A sidewall film 11 made of a silicon oxide film called a sidewall is formed around the convex portion of the silicon film 7. By this dry etching, etching damage is further applied to the surface 80b of the silicon film 7, and a damaged layer is formed. The silicon oxide film is formed by, for example, heat-treating a tetraethoxysilane (TEOS) / oxygen (O ₂ ) mixed gas at about 720 ° C., and has a thickness of about 200 nm. The dry etching conditions are, for example, a pressure of 33 Pa (250 mT), a gas flow rate: CHF ₃ / CF ₄ / Ar = 20/20/400 ml / min (sccm), and an RF power of 395 W.

(Step 9: see FIG. 11) After ion implantation of boron (B) using an ion implantation method, activation by heat treatment is performed to form a p ⁺ diffusion layer 12a that functions as an external base layer. At this time, the SiGe alloy layer 6b on the side wall (opening boundary) of the silicon oxide film 4 becomes the p ⁺ diffusion layer 12b. As the ion implantation conditions, for example, BF ₂ is implanted at an acceleration energy of 1 keV to 40 keV and an implantation amount of 1 × 10 ¹⁴ cm ⁻² to 5 × 10 ¹⁵ cm ⁻² . Under this implantation condition, since ions do not pass through the silicon nitride film 9a having a thickness of about 50 nm existing on the polycrystalline silicon film 8a, boron is not implanted into the polycrystalline silicon film 8a. Boron is an example of the “second impurity” in the present invention.

  (Step 10: see FIG. 12) Heat treatment is performed to diffuse the n-type impurity of the polycrystalline silicon film 8a into the silicon film 7, thereby forming the n-type diffusion layer 13. As a result, an emitter-base junction is formed in the silicon film 7. The heat treatment is performed at about 1050 ° C. for about 5 seconds to 30 seconds using an RTA apparatus.

  Here, the emitter layer (n-type diffusion layer) 13 formed in the silicon film 7 is formed by the diffusion of n-type impurities from the polycrystalline silicon film 8a, but the diffusion is not only in the depth direction but also in the lateral direction. Therefore, the effective emitter width may be wider than the width of the polycrystalline silicon film 8a. However, in the first embodiment of the present invention, the contact surface 50 between the emitter layer (n-type diffusion layer) 13 and the emitter electrode (polycrystalline silicon film) 8 a is located above the lower surface 60 of the sidewall film 11. The sidewall film 11 serves as a diffusion barrier, and the lateral diffusion of the n-type diffusion layer 13 is suppressed. For this reason, the dimension width of the emitter layer is miniaturized.

  (Step 11: see FIG. 13) After the heat treatment, the silicon nitride film 9a on the base electrode (not shown), the emitter electrode, and the collector electrode (not shown) is removed using dilute hydrofluoric acid and phosphoric acid. .

(Step 12: see FIG. 14) After the silicon oxide film 14 is formed using the CVD method, a resist pattern is provided by the lithography method, and unnecessary portions of the silicon oxide film 14 are removed by dry etching. Thereby, a silicon oxide film 14 having an opening in a predetermined region and used as a salicide block is provided. By this dry etching, etching damage is further applied to the surface 80c of the silicon film 7, and a damaged layer is formed. The silicon oxide film 14 is formed by, for example, heat-treating a TEOS / O ₂ mixed gas at about 720 ° C., and the film thickness is about 50 nm. The dry etching conditions are, for example, a pressure of 33 Pa (250 mT), a gas flow rate: CHF ₃ / CF ₄ / Ar = 20/20/400 ml / min (sccm), and an RF power of 395 W.

(Step 13: see FIG. 15) In order to remove the etching damage (damage layer) applied to the surfaces 80a, 80b, and 80c of the silicon film 7 in the above-described Step 7, Step 8, and Step 12, dry etching is used. A part of the surface side of the p ⁺ diffusion layer 12 (silicon film 7) is removed. Here, the dry etching conditions are, for example, a pressure of 166 Pa (1250 mT), a gas flow rate: O ₂ / CF ₄ = 200/100 ml / min (sccm), an RF power of 450 W, and in steps 7, 8 and 12 Unlike the dry etching conditions, the p ⁺ diffusion layer 12 (silicon film 7) is subjected to conditions with little damage. The thickness of the p ⁺ diffusion layer 12 (silicon film 7) removed by this dry etching is, for example, about 10 nm.

  The etching damage (damage layer) on the surface 80a of the silicon film 7 is removed after the dry etching in step 7, or the etching damage (damage layer) on the surface 80b of the silicon film 7 is removed after the dry etching in step 8. However, when the etching damage (damage layer) is removed for each process, the silicon film 7 is greatly reduced. For example, the silicon film 7 is removed by etching, and the SiGe alloy layer 6a is removed. When exposed, the formation of a silicide film is hindered at that portion, and it becomes difficult to provide a silicide film having a uniform film quality and film thickness. For this reason, it is more preferable to remove the etching damage (damage layer) immediately before the silicide film formation step (step 14) described later.

(Step 14: see FIG. 1) Cobalt (Co) is formed on the surface of the polycrystalline silicon 8a and the surface of the p ⁺ diffusion layer 12, and heat treatment is performed to form cobalt silicide films (silicide films) 15a and 15b. The sheet resistance value of the silicide films 15a and 15b is about 7Ω / □, which is an extremely low resistance value compared with the sheet resistance value of about 100Ω / □ of the conventional p ⁺ type SiGe layer (p ⁺ diffusion layer 12). . For this reason, the parasitic resistance which generate | occur | produces between an internal base layer and the base electrode (not shown) connected to an external base layer can be lowered | hung.

  In the silicidation process, the same effect can be obtained by forming titanium (Ti) instead of cobalt to form a titanium silicide film.

  Next, although not particularly shown, an interlayer insulating film such as a plasma TEOS film is deposited on the surface of the semiconductor substrate, and contact openings of the collector electrode part, the base electrode part, and the emitter electrode part of the NPN transistor are made and made of titanium or the like. A bipolar transistor having an NPN transistor can be manufactured by forming a barrier metal layer and a conductive layer made of aluminum or an aluminum alloy.

According to the manufacturing method of the semiconductor device of the first embodiment, the following effects can be obtained.
(1) By adopting such a manufacturing method, the dimension width of the n-type diffusion layer 13 which is an emitter layer is smaller than the dimension width of the interface between the silicon film 7 and the SiGe alloy layer 6a. Compared with the case where the dimension width of the interface between the silicon film 7 and the SiGe alloy layer 6a is the same, the same current density can be obtained with a small current, and a high current amplification factor can be obtained. Therefore, a transistor with low power consumption can be formed. In addition, since at least a part of the silicon film 7 is located between the SiGe alloy layer 6a and the side wall film 11 and is in contact with the SiGe alloy layer 6a and the side wall film 11, the emitter-base junction area is conventionally increased. It is narrower than the structure (when the silicon film 7 also functions as an emitter layer). For this reason, a transistor in which the junction capacitance is reduced because the junction area is smaller than that of the conventional structure can be obtained. As a result, a high-performance semiconductor device can be provided.
(2) According to the present manufacturing method, at least a part of the silicon film 7 is located between the SiGe alloy layer 6a and the sidewall film 11, and the SiGe alloy layer 6a and the sidewall film 11 are not in direct contact with each other. The recombination of the base current at the interface between the alloy layer 6a and the sidewall film 11 can be suppressed, and a semiconductor device having good base current characteristics can be manufactured.
(3) In the diffusion of the first impurity in the seventh step, since the contact surface 50 between the n-type diffusion layer 13 and the emitter electrode is located above the lower surface 60 of the sidewall film 11, the sidewall film 11 is the first. It becomes an impurity diffusion barrier, and lateral diffusion is suppressed, and the dimensional width of the n-type diffusion layer 13 can be reduced with better controllability.
(4) According to this manufacturing method, since the SiGe alloy layer 6a and the silicon film 7 are formed in the opening A2 of the protective film 4, there is a portion where the SiGe alloy layer 6a and the silicon film 7 run on the protective film 4. The thickness of the SiGe alloy layer 6a and the silicon film 7 is less than the height of the polycrystalline silicon film 8 formed in the opening A2. Only placed low. For this reason, when forming the resist pattern 10 for processing the polycrystalline silicon film 8 into a desired emitter electrode 8a, it is caused by the polycrystalline silicon film 8 on the portion (end portion of the protective film 4) riding on the protective film 4. Scattering of exposure light (scattering toward the resist pattern 10 for processing into the emitter electrode 8a) is reduced, and deformation and shape variation of the resist pattern 10 can be suppressed. As a result, a semiconductor device with small performance variation can be provided.
(5) In such a manufacturing method, it is desirable that the upper surface of the protective film 4 is on the lower surface than the contact surface 50 between the n-type diffusion layer 13 and the emitter electrode 8a. By doing so, the height of the polycrystalline silicon film 8 formed on the protective film 4 becomes lower than the height of the polycrystalline silicon film 8 formed in the opening A2, so that the emitter electrode Scattering toward the resist pattern 10 for processing into 8a is further suppressed, and deformation and shape variation of the resist pattern 10 can be further suppressed.
(6) When a silicide film is formed on the surface of the p ⁺ diffusion layer 12a including etching damage (damage layer), the silicide film quality deterioration corresponding to the etching damage (damage layer) and the silicide film shape variation are caused. However, according to the present manufacturing method, a silicide film is formed on the surface of the p ⁺ diffusion layer 12a (silicon film 7) from which etching damage (damage layer) has been removed. The film quality of the silicide film is improved and the wiring resistance can be reduced. In particular, when the process is performed just before the step 14 of removing the etching damage (damage layer) on the surface of the p ⁺ diffusion layer 12a (silicon film 7), not only the cost is reduced by the reduction of the number of processes but also the etching damage. Since the film loss of the p ⁺ diffusion layer 12a (silicon film 7) accompanying the removal of the (damage layer) can be minimized, the silicon film 7 can be made thinner during film formation, further reducing the manufacturing cost. can do.
(Second Embodiment)
FIG. 16 is a device cross-sectional view of a SiGe-based heterojunction bipolar transistor according to a second embodiment of the present invention. The difference from the first embodiment is that the lower surface of the n-type diffusion layer 13 is provided in the SiGe alloy layer 6a. The silicon film 7a is an example of the “second region” in the present invention, and the n-type diffusion layer 13a is an example of the “first region” in the present invention.

In order to manufacture the semiconductor device according to the second embodiment of the present invention, in Step 3 of the first embodiment, the SiGe alloy layer 6a and the silicon film 7a are formed at about 40 nm and about 30 nm (about 70 nm in total) by the low pressure CVD method, respectively. In step 10, heat treatment at about 1050 ° C. is performed for about 5 seconds using an RTA apparatus. By doing so, the n-type impurity of the polycrystalline silicon film 8a diffuses about 40 nm toward the collector layer 2, so that it passes through the silicon film 7a with a thickness of about 30 nm and reaches the SiGe alloy layer 6a. .

According to the semiconductor device manufacturing method of the second embodiment, the following effects can be obtained in addition to the effects (1) to (6) of the first embodiment.
(7) Since the lower surface of the n-type diffusion layer 13a reaches the SiGe alloy layer 6a, the lower surface of the n-type diffusion layer 13a functioning as the emitter layer is compared with the case where the lower surface does not reach the SiGe alloy layer 6a. The distance to the active region A1 (collector layer 2) is shortened, the movement time of electrons flowing from the emitter layer side to the collector layer can be shortened, and a transistor operating at high speed can be formed. Therefore, a higher performance semiconductor device can be provided.
(8) Compared to the case where the lower surface (emitter-base junction) of the n-type diffusion layer 13a does not reach the SiGe alloy layer 6a (when the lower surface of the n-type diffusion layer 13a is in the silicon film 7a). The emitter injection efficiency is high, and a higher current amplification factor can be obtained. This is because when the lower surface of the n-type diffusion layer 13a is in the SiGe alloy layer 6a, the lower surface of the n-type diffusion layer 13a is less than the silicon film 7a because the band gap of the SiGe alloy layer is narrower than the band gap of the silicon film. This is because the height of the barrier against electrons injected from the emitter layer to the base layer is smaller than that in the case of the above. As a result, the height of the barrier against electrons injected from the emitter layer into the base layer can be made smaller than the height of the barrier against holes injected from the base layer into the emitter layer, thereby increasing the emitter injection efficiency. And a higher current gain can be realized. Therefore, a higher performance semiconductor device can be provided.
(Third embodiment)
FIG. 20 is a device cross-sectional view of a SiGe-based heterojunction bipolar transistor according to a third embodiment of the present invention. The difference from the first embodiment is that a part of the p ⁺ diffusion layer 12a1 and the silicide film 15b1 connected to the base region straddles from the inside of the opening A2 of the silicon oxide film (protective film) 4 onto the silicon oxide film outside thereof. It is formed. The rest is the same as the previous first embodiment.

  21 and 23 to 31 are cross-sectional views for explaining a semiconductor device manufacturing process according to the third embodiment of the present invention. 22 is a top view in the middle of manufacturing the semiconductor device corresponding to FIG. 21, and FIG. 21 is a sectional view taken along line XX in FIG.

(Step 4A: See FIGS. 5 and 21) After Steps 1 to 3 shown in the first embodiment, a resist pattern (not shown) is provided by lithography, and silicon film 7 and dry etching are performed. Unnecessary portions of the SiGe alloy layer 6 are removed. At this time, unnecessary portions of the polycrystalline silicon film 5 are also removed by etching. The resist pattern here is patterned so that the silicon film 7 and the SiGe alloy layer 6 are formed over the silicon oxide film (protective film) 4. As a result, as shown in FIGS. 21 and 22, the SiGe alloy layer 6a1 and the silicon film 7a1 used as the base region, which are processed into a desired pattern A4 extending from the inside of the opening A2 to the silicon oxide film 4, are formed. Is done. The dry etching conditions are, for example, pressure 2 Pa, gas flow rate O ₂ / HBr = 2/180 ml / min, and RF power Upper / Lower = 250/12 W. In the first embodiment, the spacer-like SiGe alloy layer 6b is formed on the side wall (opening boundary) of the silicon oxide film 4, but here the silicon oxide film is adjusted by adjusting the etching time. 4, the portion corresponding to the SiGe alloy layer 6b is completely removed from the side wall (opening boundary).

(Step 5A: See FIG. 23) A polycrystalline silicon film 8 doped with n-type impurities of about 1 × 10 ²⁰ cm ⁻³ or more is formed by low pressure CVD, and a silicon nitride film 9 is further formed. For example, arsenic (As) or phosphorus (P) is used as the n-type impurity. The thickness of the polycrystalline silicon film 8 is about 200 nm, and the thickness of the silicon nitride film 9 is about 50 nm.
(Step 6A: see FIG. 24) A resist pattern 10 for processing a desired emitter electrode is formed in the opening (bipolar transistor formation region) A2 by lithography.
(Step 7A: See FIG. 25) The silicon nitride film 9, the polycrystalline silicon film 8, and the silicon film 7a1 are etched in this order by dry etching. At this time, the dry etching is not performed until the silicon film 7a1 is completely removed, and is finished in a state where a part remains on the entire surface of the SiGe alloy layer 6a1. As a result, the silicon film 7a1 is finished in a shape 70 having a convex cross section. Furthermore, etching damage enters the surface 80a1 of the silicon film 7a1, and a damaged layer is formed. At this time, the polycrystalline silicon film 8 includes a polycrystalline silicon film 8a1 serving as an emitter electrode, a sidewall film 8b1 composed of a polycrystalline silicon film around the SiGe alloy layer 6a1 and the silicon film 7a1, and a sidewall of the silicon oxide film 4. A side wall film 8c1 made of a polycrystalline silicon film is processed at the portion (opening boundary). The silicon nitride film 9 is processed as a silicon nitride film 9a and functions as a mask when the polycrystalline silicon film 8 is etched. The dry etching conditions are, for example, pressure 2 Pa, gas flow rate O ₂ / HBr = 2/180 ml / min, and RF power Upper / Lower = 250/12 W.

  Here, as with the first embodiment, when the dry etching of the polycrystalline silicon film 8 is advanced, the silicon oxide film except the opening (bipolar transistor formation region) A2 and the desired pattern A4 is exposed when the silicon film 7a1 is exposed. 4 will be exposed. Etching control between the same materials (between the polycrystalline silicon film 8 and the silicon film 7a1 in this embodiment) is usually difficult, but the exposure time of the silicon oxide film 4 is an end point used in normal dry etching. By considering this as the exposure time of the silicon film 7a1, the etching process to the silicon film 7a1 can be performed with good control, and the silicon film 7a1 is reproducibly formed into a convex shape 70 with high accuracy. Can be finished.

(Step 8A: see FIG. 26) A silicon oxide film, which is an insulating film, is formed using a CVD method, and subsequently etched back using dry etching, whereby a silicon nitride film 9a, a polycrystalline silicon film 8a1, and A sidewall film 11 made of a silicon oxide film called a sidewall is formed around the convex portion of the silicon film 7a1. By this dry etching, etching damage is further applied to the surface 80b1 of the silicon film 7a1, and a damaged layer is formed. The silicon oxide film is formed by, for example, heat-treating a tetraethoxysilane (TEOS) / oxygen (O ₂ ) mixed gas at about 720 ° C., and has a thickness of about 200 nm. As dry etching conditions, for example, the pressure is 33 Pa, the gas flow rate is CHF ₃ / CF ₄ / Ar = 20/20/400 ml / min, and the RF power is 395 W.

(Step 9A: see FIG. 27) After ion implantation of boron (B) using an ion implantation method, activation by heat treatment is performed to form a p ⁺ diffusion layer 12a1 that functions as an external base layer. At this time, the sidewall film 8c1 at the sidewall (opening boundary) of the silicon oxide film 4 becomes the p ⁺ diffusion layer 12b1. As the ion implantation conditions, for example, BF ₂ is implanted at an acceleration energy of 1 keV to 40 keV and an implantation amount of 1 × 10 ¹⁴ cm ⁻² to 5 × 10 ¹⁵ cm ⁻² . Under this implantation condition, since ions do not pass through the silicon nitride film 9a having a thickness of about 50 nm existing on the polycrystalline silicon film 8a1, boron is not implanted into the polycrystalline silicon film 8a1.

  (Step 10A: See FIG. 28) Heat treatment is performed to diffuse the n-type impurity of the polycrystalline silicon film 8a1 into the silicon film 7a1, thereby forming the n-type diffusion layer 13. As a result, an emitter-base junction is formed in the silicon film 7a1. The heat treatment is performed at about 1050 ° C. for about 5 seconds to 30 seconds using an RTA apparatus.

  Here, the emitter layer (n-type diffusion layer) 13 formed in the silicon film 7a1 is formed by diffusion of n-type impurities from the polycrystalline silicon film 8a1, but the diffusion is not only in the depth direction but also in the lateral direction. Therefore, the effective emitter width may be wider than the width of the polycrystalline silicon film 8a1. However, in the present embodiment, since the contact surface 50 between the emitter layer (n-type diffusion layer) 13 and the emitter electrode (polycrystalline silicon film) 8a1 is located above the lower surface 60 of the sidewall film 11, the sidewall film 11 Serves as a diffusion barrier and the lateral diffusion of the n-type diffusion layer 13 is suppressed. For this reason, the dimension width of the emitter layer is miniaturized.

  (Step 11A: see FIG. 29) After the heat treatment, the silicon nitride film 9a on the base electrode (not shown), the emitter electrode, and the collector electrode (not shown) is removed using dilute hydrofluoric acid and phosphoric acid. .

(Step 12A: See FIG. 30) After forming a silicon oxide film made of an insulating film by using the CVD method, a resist pattern (not shown) is provided by the lithography method, and unnecessary portions of the silicon oxide film are removed by dry etching. To do. Thus, a silicon oxide film 14a1 having an opening in a predetermined region and used as a salicide block is provided. By this dry etching, etching damage is further applied to the surface 80c1 of the silicon film 7a1, and a damaged layer is formed. The silicon oxide film is formed by, for example, heat-treating a TEOS / O ₂ mixed gas at about 720 ° C., and has a film thickness of about 50 nm. As dry etching conditions, for example, the pressure is 33 Pa, the gas flow rate is CHF ₃ / CF ₄ / Ar = 20/20/400 ml / min, and the RF power is 395 W.

(Step 13A: see FIG. 31) In order to remove the etching damage (damage layer) applied to the surfaces 80a1, 80b1, and 80c1 of the silicon film 7a1 in the steps 7A, 8A, and 12A described above, dry etching is performed. A part of the surface side of the p ⁺ diffusion layer 12a1 (silicon film 7a1) is removed. Here, the dry etching conditions are, for example, a pressure of 166 Pa, a gas flow rate: O ₂ / CF ₄ = 200/100 ml / min, and an RF power of 450 W, which are different from the dry etching conditions in the steps 7A, 8A, and 12A. P ⁺ diffusion layer 12a1 (silicon film 7a1) is performed under a condition that causes little damage. The film thickness of the p ⁺ diffusion layer 12a1 (silicon film 7a1) removed by this dry etching is, for example, about 10 nm. The timing for removing etching damage (damage layer) is the same as in the first embodiment.

(Step 14A: see FIG. 20) Cobalt (Co) is formed on the surface of the polycrystalline silicon 8a1 and the surface of the p ⁺ diffusion layer 12a1, and heat treatment is performed to form cobalt silicide films (silicide films) 15a1 and 15b1. The sheet resistance value of the silicide films 15a1 and 15b1 is about 7Ω / □, which is extremely low compared to the sheet resistance value of about 100Ω / □ of the conventional p ⁺ type SiGe layer (p ⁺ diffusion layer 12a1). . For this reason, the parasitic resistance which generate | occur | produces between an internal base layer and the base electrode (not shown) connected to an external base layer can be lowered | hung. In the silicidation process, the same effect can be obtained by forming titanium (Ti) instead of cobalt to form a titanium silicide film.

  Next, although not particularly shown, an interlayer insulating film such as a plasma TEOS film is deposited on the surface of the semiconductor substrate, and contact openings of the collector electrode part, the base electrode part, and the emitter electrode part of the NPN transistor are made and made of titanium or the like. A bipolar transistor having an NPN transistor can be manufactured by forming a barrier metal layer and a conductive layer made of aluminum or an aluminum alloy.

According to the semiconductor device manufacturing method of the third embodiment, in addition to the effects (1) to (3) and (6) of the first embodiment, the following effects can be obtained. .
(9) A part of the p ⁺ diffusion layer 12a1 and the silicide film 15b1 functioning as the external base layer is formed so as to extend from the inside of the opening A2 to the silicon oxide film (protective film) 4, so that the base electrode portion Design flexibility related to contact placement is improved.
(10) Since a part of the p ⁺ diffusion layer 12a1 extends over the silicon oxide film 4 from the inside of the opening A2, the thickness of the p ⁺ diffusion layer 12a1 on the silicon oxide film 4 is the opening A2. The silicon film 5a1 is formed thicker than the inner film. For this reason, when the contact of the base electrode portion is formed on the silicon oxide film 4, the penetration of the p ⁺ diffusion layer 12a1 of the contact due to the etching variation (excessive overetching) when opening the contact is suppressed. As a result, the manufacturing yield is improved and a bipolar transistor (semiconductor device) can be provided at low cost.

  Although the present invention has been described in detail with reference to the embodiments, the present invention is not limited to this, and can be applied to various bipolar transistors without departing from the spirit of the present invention.

In the third embodiment, an example of the p ⁺ diffusion layer 12a1 and the silicide film 15b1 extending over the silicon oxide film 4 on one side is shown. However, the present invention is not limited to this example. For example, in the step 4A, the silicon film 7a1 The SiGe alloy layer 6a1 may be processed into a straight line and both ends thereof may be formed on the silicon oxide film (protective film) 4. In this case, the same effect as that of the third embodiment can be obtained.

  In the third embodiment, the lower surface of the n-type diffusion layer 13 may be provided in the SiGe alloy layer 6a1. In this case, the effects (7) and (8) of the second embodiment can be further enjoyed.

It is sectional drawing for demonstrating the semiconductor device which concerns on 1st Embodiment of this invention. It is the elements on larger scale for explaining the semiconductor device concerning a 1st embodiment of the present invention. It is sectional drawing for demonstrating the manufacturing process of the semiconductor device which concerns on 1st Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing process of the semiconductor device which concerns on 1st Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing process of the semiconductor device which concerns on 1st Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing process of the semiconductor device which concerns on 1st Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing process of the semiconductor device which concerns on 1st Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing process of the semiconductor device which concerns on 1st Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing process of the semiconductor device which concerns on 1st Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing process of the semiconductor device which concerns on 1st Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing process of the semiconductor device which concerns on 1st Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing process of the semiconductor device which concerns on 1st Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing process of the semiconductor device which concerns on 1st Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing process of the semiconductor device which concerns on 1st Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing process of the semiconductor device which concerns on 1st Embodiment of this invention. It is sectional drawing for demonstrating the semiconductor device which concerns on 2nd Embodiment of this invention. It is sectional drawing for demonstrating the conventional SiGe base heterojunction bipolar transistor structure. It is the elements on larger scale for demonstrating the conventional SiGe base heterojunction bipolar transistor structure. FIG. 9 is a cross-sectional view for explaining a manufacturing process of a conventional semiconductor device corresponding to FIG. It is sectional drawing for demonstrating the semiconductor device which concerns on 3rd Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing process of the semiconductor device which concerns on 3rd Embodiment of this invention. FIG. 22 is a top view of the semiconductor device in the manufacturing process corresponding to FIG. 21; It is sectional drawing for demonstrating the manufacturing process of the semiconductor device which concerns on 3rd Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing process of the semiconductor device which concerns on 3rd Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing process of the semiconductor device which concerns on 3rd Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing process of the semiconductor device which concerns on 3rd Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing process of the semiconductor device which concerns on 3rd Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing process of the semiconductor device which concerns on 3rd Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing process of the semiconductor device which concerns on 3rd Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing process of the semiconductor device which concerns on 3rd Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing process of the semiconductor device which concerns on 3rd Embodiment of this invention.

Explanation of symbols

1 p-type silicon substrate 2 collector layer (epitaxial layer)
A1 Active region A2 Bipolar transistor formation region 3 Element isolation film (STI)
4 Protective film (silicon oxide film)
6a Silicon germanium (SiGe) alloy layer 7 Silicon film (second region)
8a Polycrystalline silicon film (emitter electrode)
11 Side wall film (side wall) made of silicon oxide film
12a, 12b p ⁺ diffusion layer 13 n-type diffusion layer (emitter layer)
14 Protective film (silicon oxide film)
15a, 15b Silicide film 50 Interface between n-type diffusion layer and polycrystalline silicon film 60 Bottom surface of sidewall film

Claims (3)

A first step of forming a protective film having an opening in a predetermined region including the active region on a semiconductor substrate on which an active region surrounded by an element isolation film is formed;
A second step of forming a conductive layer functioning as a base layer and a silicon film not including the n-type first impurity in the opening of the protective film;
A third step of forming an emitter electrode containing the n-type first impurity on the silicon film above the active region;
A fourth step of etching the silicon film using the emitter electrode as a mask;
A fifth step of forming a sidewall film covering the sidewall of the emitter electrode;
A sixth step of introducing a p-type second impurity so as to reach the surface of the active region, and forming an impurity region in the conductive layer and the silicon film;
Wherein said n-type first impurity is diffused into the surface of the silicon film included in the emitter electrode, in the silicon film, not including the n-type first impurity and the first region including the n-type first impurity A seventh step of forming a second region;
With
In the fourth step, the silicon film, the upper surface of the portion in contact with the front disappeared emitter electrode is processed into a convex shape as to be positioned above the upper surface of the portion not in contact with the emitter electrode,
In the fifth step, the side wall film is formed so as to cover the side wall of the emitter electrode and the side wall of the silicon film in contact with the emitter electrode.
In the seventh step, at least a part of the second region of the silicon film is located between the conductive layer and the sidewall film and is in contact with the conductive layer and the sidewall film. A method of manufacturing a semiconductor device.   The method of manufacturing a semiconductor device according to claim 1, wherein the conductive layer is a silicon germanium (SiGe) alloy layer, and a lower surface of the first region reaches the conductive layer.   3. The method of manufacturing a semiconductor device according to claim 1, wherein an upper surface of the protective film is located on a lower surface than a contact surface between the first region and the emitter electrode.

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