JP2007134375A - Laminated electronic component, electronic equipment, and electronic component series - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a laminated electronic component capable of reducing the fall of the electronic component in vertical packaging onto a circuit board, and chipping in the electronic component. <P>SOLUTION: The laminated electronic component has a nearly rectangular parallelepiped shape determined by length, width, and lamination directions L, W, and T. When a dimension viewed in the widthwise direction W and that viewed in the lamination direction T are set to W1 and T1, respectively, the inequality 1<W1/T1≤1.7 is met. An edge 51 between a surface 11 in parallel with the lengthwise and lamination directions L, T and a surface 13 in parallel with lengthwise and widthwise directions L, W is rounded, and the inequality 0.09≤(2×R/T1)≤0.33 is met when the radius of curvature is set to R. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a laminated electronic component.

  In general, a multilayer electronic component such as a multilayer ceramic capacitor is manufactured by the following process. First, a plurality of dielectric green sheets having internal electrodes are laminated and pressed to make a sheet laminate. Next, the sheet laminate is cut into a plurality of chip regions to obtain a laminated green chip. Then, the laminated green chip is barrel-polished to round off sharp edges generated by the cutting process. Thereafter, well-known processes such as binder removal, firing and terminal electrode formation are performed on the multilayer green chip to obtain a multilayer electronic component.

  The multilayer electronic component manufactured in this way has various shapes, and in particular, a low-profile multilayer electronic component in which the dimension in the stacking direction is smaller than the dimension in the width direction is known.

Further, for low-profile multilayer electronic components, a technique for performing so-called vertical mounting, in which the stacking direction is parallel to the circuit board surface and the width direction is perpendicular to the circuit board surface, is known. (See Patent Document 1).
JP-A-5-74444

  When vertically mounting a low-profile multilayer electronic component, it is an important issue to avoid the phenomenon that the multilayer electronic component falls on the circuit board. When the present applicant examined, when the curvature radius of the edge part of a multilayer electronic component is large, such electronic component fall may occur frequently.

  However, if the radius of curvature of the edge portion is small, the edge portion has a sharp shape. Therefore, when handling the laminated green chip in the manufacturing process, chipping or peeling of the laminate may occur. Such chip chipping or peeling of the laminate leads to chipping defects as an electronic component.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a laminated electronic component that can reduce electronic component collapse when vertically mounted on a circuit board and reduce chipping defects of the electronic component. And

  In order to solve the above-described problems, the multilayer electronic component according to the present invention has a substantially rectangular parallelepiped shape defined in the length direction, the width direction, and the stack direction, and the dimension seen in the width direction is W1, and is viewed in the stack direction. When the dimension is T1, 1 <W1 / T1 ≦ 1.7 is satisfied. Further, the edges of the surface parallel to the length direction and the laminating direction and the surface parallel to the length direction and the width direction are rounded, and when the radius of curvature is R, 0.09 ≦ (2 × R / T1) ≦ 0.33 is satisfied.

  As described above, the multilayer electronic component according to the present invention has a substantially rectangular parallelepiped shape defined by the length direction, the width direction, and the lamination direction. Further, regarding the dimension W1 in the width direction and the dimension T1 in the stacking direction, 1 <W1 / T1 is satisfied, that is, the dimension T1 in the stacking direction is smaller than the dimension W1 in the width direction. When such a low-profile multilayer electronic component is vertically mounted, it is an important issue to avoid the electronic component collapse.

  As a result of investigations by the inventors, when the stacked electronic component is vertically mounted, a surface parallel to the length direction and the stack direction is a mounting surface on the circuit board. Therefore, when the radius of curvature R is large with respect to the edge between the surface parallel to the length direction and the stacking direction and the surface parallel to the length direction and the width direction, electronic components may frequently collapse.

  However, as described above, when the radius of curvature R is small, there is a possibility that chipping defects of electronic components may increase.

  In the present invention, when the ratio W1 / T1 of the dimension W1 in the width direction and the dimension T1 in the stacking direction is in the range of 1 <W1 / T1 ≦ 1.7, the curvature radius R of the edge is 0.09. It is set to satisfy ≦ (2 × R / T1) ≦ 0.33. According to such conditions, it was found that the electronic component collapse during vertical mounting on the circuit board can be reduced and chipping defects of the electronic component can be reduced.

  More preferably, the radius of curvature R of the edge is set to satisfy 0.13 ≦ (2 × R / T1) ≦ 0.31.

  Furthermore, the present invention provides an electronic device. The electronic device according to the present invention includes a circuit board and a laminated electronic component. The multilayer electronic component is the multilayer electronic component according to the present invention described above, and is mounted on the circuit board in such a manner that a surface parallel to the length direction and the stack direction is a mounting surface.

  Furthermore, the present invention provides a series of electronic components. The electronic component series according to the present invention includes a belt-like body provided with a plurality of electronic component storage chambers, and a plurality of laminated electronic components respectively stored in the electronic component storage chambers. At least one of the multilayer electronic components is the multilayer electronic component according to the present invention described above.

  As described above, according to the present invention, it is possible to provide a laminated electronic component that can reduce the collapse of an electronic component when vertically mounted on a circuit board and can reduce chipping defects of the electronic component.

  FIG. 1 is a perspective view showing an example of a laminated electronic component according to the present invention, and FIG. 2 is a cross-sectional view taken along line 2-2 of FIG. The illustrated multilayer electronic component includes a multilayer electronic component body 10 and terminal electrodes 21 and 22. The illustrated multilayer electronic component is a multilayer ceramic capacitor, but may be another multilayer electronic component, for example, a multilayer inductor.

  The multilayer electronic component body 10 is made of a dielectric material whose main component is, for example, barium titanate. The multilayer electronic component body 10 has a substantially rectangular parallelepiped shape defined by a length direction L, a width direction W, and a thickness direction T, and terminal electrodes 21 and 22 are provided at both ends viewed in the length direction L. It has been.

  A plurality of internal electrodes 25 are stacked at intervals in the thickness direction T inside the multilayer electronic component body 10 (see FIG. 2). Hereinafter, the thickness direction T is referred to as a stacking direction. The internal electrodes 25 are alternately led to both end portions of the multilayer electronic component body 10 viewed in the length direction L, and are alternately connected to the terminal electrodes 21 and 22.

  The laminated electronic component described above has a substantially rectangular parallelepiped shape defined by the length direction L, the width direction W, and the lamination direction T when viewed as a whole, and has six surfaces 11 to 16. The surfaces 11 and 12 are surfaces parallel to the length direction L and the stacking direction T, and face each other in the width direction W. The surfaces 13 and 14 are surfaces parallel to the length direction L and the width direction W, and face each other in the stacking direction T. The surfaces 15 and 16 are surfaces parallel to the width direction W and the stacking direction T, and face each other in the length direction L.

Such a multilayered electronic component having a substantially rectangular parallelepiped shape has a dimension L1 measured in the length direction L, a dimension W1 measured in the width direction W, and a dimension T1 measured in the stacking direction T. The ratio W1 / T1 of the dimension W1 in the width direction W and the dimension T1 in the stacking direction T is given by
1 <W1 / T1 ≦ 1.7 (1)
It is set to a value that satisfies Furthermore, the dimension L1 in the length direction L is set to a value larger than the dimension W1 in the width direction W.

FIG. 3 is a partially enlarged end view taken along line 3-3 in FIG. 1 and 3, an edge 51 is formed at a position where the surface 11 and the surface 13 intersect. The edge 51 extends in the length direction L, and is rounded when viewed in a cross section (see FIG. 3) parallel to the width direction W and the stacking direction T. Then, the radius of curvature R is determined by the relationship between the dimension T1 in the stacking direction T and the following formula:
0.09 ≦ (2 × R / T1) ≦ 0.33 (2)
The range is set so as to satisfy.

  Further, an edge 52 is formed at a position where the surface 11 and the surface 14 intersect. The edge 52 has the same shape as the previous edge 51 and satisfies the expression (2). The edge 53 formed at the position where the surfaces 12 and 13 intersect and the edge 54 formed at the position where the surfaces 12 and 14 intersect also have the same shape and satisfy Expression (2).

  The following edges are formed: the edge 55 formed at the position where the surface 11 and the surface 15 intersect, the edge 56 formed at the position where the surface 11 and the surface 16 intersect, the position where the surface 12 and the surface 15 intersect. Formed at a position where the edge 57, the surface 12 and the surface 16 intersect with each other, and formed at a position where the edge 59, the surface 13 and the surface 16 formed at a position where the surface 13 and the surface 15 intersect with each other. The edge 61 formed at a position where the edge 60, the surface 14 and the surface 15 intersect, and the edge 62 formed at a position where the surface 14 and the surface 16 intersect are not necessarily limited, and are rounded. It can take any shape, including different shapes.

  The laminated electronic component shown in FIGS. 1 to 3 can be manufactured by the following process. First, a plurality of dielectric green sheets having internal electrodes are laminated and pressed to make a sheet laminate.

  Next, the sheet laminated body is cut into a plurality of chip regions to obtain a rectangular parallelepiped laminated green chip. As a method for cutting the sheet laminate, for example, a rotary blade cutting method in which a disk-shaped cutting blade is rotated to cut the sheet laminate.

  Then, the laminated green chip obtained by cutting is barrel-polished to round off sharp edges generated by the cutting process. As barrel polishing, either wet barrel polishing using a solvent or dry barrel polishing without using a solvent can be employed. As a specific example of wet barrel polishing, a laminated green chip and media are placed in a container (barrel) and filled with a solvent. Barrel polishing is performed by rotating the container in this state. Also, wet barrel polishing without using media is possible.

  Thereafter, well-known steps such as binder removal, firing and terminal electrode formation are performed on the laminated green chip subjected to barrel polishing to obtain the laminated electronic component shown in FIGS.

  FIG. 4 is a diagram for explaining a process of vertically mounting the multilayer electronic component shown in FIGS. When vertically mounting the laminated electronic components, first, as shown in the drawing, the laminated electronic component 1 is placed at a predetermined position on the circuit board 7, the lamination direction T is parallel to the surface 70 of the circuit board 7, and the width direction W Are arranged in a manner perpendicular to the surface 70 of the circuit board 7.

  Then, soldering is performed in this state, and the terminal electrodes 21 and 22 of the multilayer electronic component 1 are joined to the conductor patterns 71 and 72 of the circuit board 7 via solder. As a result, an electronic device in which the multilayer electronic component 1 is vertically mounted on the circuit board 7 is obtained.

  As described with reference to FIGS. 1 and 2, the laminated electronic component according to the present invention has a substantially rectangular parallelepiped shape defined by the length direction L, the width direction W, and the lamination direction T. When such a multilayer electronic component is vertically mounted as shown in FIG. 4, the multilayer electronic component is mounted on the circuit board 7 in such a manner that the dimension W1 in the width direction W is the height dimension of the multilayer electronic component. become. Therefore, the present invention is intended for a case where the dimension T1 in the stacking direction T is smaller than the dimension W1 in the width direction W, that is, 1 <W1 / T1 is satisfied.

  FIG. 5 is a partially enlarged end view taken along line 5-5 in FIG. Referring to FIG. 5, when the laminated electronic component 1 is vertically mounted, a surface 11 parallel to the length direction L and the lamination direction T becomes a mounting surface on the circuit board 4. Therefore, regarding the edge 51 between the surface 11 parallel to the length direction L and the stacking direction T and the edge 51 between the surface 13 parallel to the length direction L and the width direction W, if the radius of curvature R is large, the electronic component may frequently collapse. There is sex.

  On the other hand, if the radius of curvature R of the edge 51 is small, the edge 51 has a sharp shape. Therefore, when the laminated green chip is handled in the manufacturing process, chipping or peeling of the lamination may occur. Such chip chipping or peeling of the laminate leads to chipping defects as an electronic component.

  In the present invention, when the ratio W1 / T1 between the dimension W1 in the width direction W and the dimension T1 in the stacking direction T is in the range of 1 <W1 / T1 ≦ 1.7, the curvature radius R of the edge 51 is 0. 0.09 ≦ (2 × R / T1) ≦ 0.33. According to such conditions, it was found that the electronic component collapse during vertical mounting on the circuit board can be reduced and chipping defects of the electronic component can be reduced. Next, experimental results regarding the electronic component collapse failure and the electronic component chipping failure will be described.

  First, the experimental results when the ratio W1 / T1 is 1.4 are shown in Table 1 below.

  In the experiment, for each of Samples 1 to 8, the appearance of the laminated electronic component was confirmed, and the occurrence rate of defective electronic components was examined. The number of data N was 10,000. Regarding the determination result of electronic component chipping failure, if the occurrence rate of electronic component chipping failure is less than 0.1%, it is excellent (（), and the occurrence rate of electronic component chipping failure is 0.1% or more and less than 1.0%. In the case of (1), it was judged as good (◯), and when the occurrence rate of chipping defects in electronic parts was 1.0% or more, it was judged as impossible (×).

  Further, the stacked electronic components were vertically mounted on the circuit board, and the occurrence rate of the electronic component collapse failure was examined. The number of data N was 1,000. The judgment result of electronic component collapse failure is excellent (◎) when the occurrence rate of electronic component collapse failure is less than 0.1%, and the occurrence rate of electronic component collapse failure is not less than 0.1% and less than 0.5%. In this case, it was judged as good (◯), and when the occurrence rate of electronic component collapse failure was 0.5% or more, it was judged as impossible (×).

  As shown in Table 1, when the ratio W1 / T1 is 1.4, if the value (2 × R / T1) is 0.09 or more, the occurrence rate of chipping defects in electronic components is suppressed to a low value, The determination result of the component defect is good (◯) or excellent (◎) (Samples 2 to 8). On the other hand, if the value (2 × R / T1) is less than 0.09, the occurrence rate of electronic component chipping failure increases rapidly, and the determination result of electronic component chipping failure becomes impossible (×) (Sample 1).

  Further, when the value (2 × R / T1) is 0.33 or less, the occurrence rate of electronic component collapse failure is suppressed to a low value, and the determination result of the electronic component collapse failure is good (◯) or excellent (◎). (Samples 1 to 7). On the other hand, if the value (2 × R / T1) is larger than 0.33, the occurrence rate of the electronic component collapse failure increases rapidly, and the determination result of the electronic component collapse failure becomes impossible (×) (sample 8). .

  Therefore, when the ratio W1 / T1 is 1.4, by setting the value (2 × R / T1) to 0.09 or more and 0.33 or less, the electronic component collapse failure is reduced and the electronic component chipping failure is reduced. Can be reduced.

  Next, Table 2 below shows the experimental results when the ratio W1 / T1 is 1.7.

  For Samples 9 to 15 as well, as with Samples 1 to 8 shown in Table 1 above, the occurrence rate of chipping defects in electronic components was examined, and the determination of chipping defects in electronic components was performed. Furthermore, the occurrence rate of the electronic component collapse failure was examined, and the electronic component collapse failure was determined.

  As shown in Table 2, when the ratio W1 / T1 is 1.7, if the value (2 × R / T1) is 0.09 or more, the occurrence rate of chipping defects in electronic parts is suppressed to a low value, The determination result of the component defect is good (◯) or excellent (◎) (samples 10 to 15). On the other hand, if the value (2 × R / T1) is less than 0.09, the occurrence rate of chipping defects of electronic parts increases rapidly, and the determination result of chipping defects of electronic parts becomes impossible (×) (sample 9).

  Further, when the value (2 × R / T1) is 0.33 or less, the occurrence rate of electronic component collapse failure is suppressed to a low value, and the determination result of the electronic component collapse failure is good (◯) or excellent (◎). (Samples 9 to 14). On the other hand, if the value (2 × R / T1) is larger than 0.33, the occurrence rate of the electronic component collapse failure increases rapidly, and the determination result of the electronic component collapse failure is not possible (×) (sample 15). .

  Therefore, when the ratio W1 / T1 is 1.7, by setting the value (2 × R / T1) to 0.09 or more and 0.33 or less, the electronic component collapse failure is reduced and the electronic component chipping failure is prevented. Can be reduced.

  Finally, the experimental results when the ratio W1 / T1 is 2.2 are shown in Table 3 below.

  For Samples 16 to 20, as in Samples 1 to 8 shown in Table 1 above, the occurrence rate of chipping defects in electronic components was examined, and the determination of chipping defects in electronic components was performed. Furthermore, the occurrence rate of the electronic component collapse failure was examined, and the electronic component collapse failure was determined.

  As shown in Table 3, when the ratio W1 / T1 is 2.2, the value of the curvature radius R of the edge with respect to the dimension T1 in the stacking direction T (2 × R / T1) is less than 0.07. The occurrence rate of chipping defects becomes a high value, and the determination result of chipping defects of electronic parts is not possible (x) (sample 16). However, if the value (2 × R / T1) exceeds 0.07, the occurrence rate of the electronic component collapse failure becomes a high value, and the determination result of the electronic component collapse failure becomes impossible (×) (samples 18 to 18). 20).

  Therefore, when the ratio W1 / T1 is 2.2, it is difficult to achieve both the reduction of the electronic component collapse failure and the reduction of the electronic component chipping failure.

  From the above experimental results, when the ratio W1 / T1 is in the range of greater than 1 and 1.7 or less, the value (2 × R / T1) is set to 0.09 or more and 0.33 or less. It can be seen that it is possible to achieve both a reduction in electronic component collapse failure and a reduction in electronic component chipping failure.

  FIG. 6 is a partially cutaway perspective view showing an embodiment of the electronic component series according to the present invention, and FIG. 7 is a partial cross-sectional view taken along line 7-7 of FIG. The illustrated electronic component series includes a strip 3 and a plurality of laminated electronic components 1.

  The strip 3 has a strip shape defined by the longitudinal direction X, the strip width direction Y, and the strip thickness direction Z, and includes a lower strip 31 and an upper strip 32. First, the lower belt 31 will be described. A plurality of electronic component storage chambers 4 are provided in the lower belt 31 at intervals along the longitudinal direction X. Each electronic component storage chamber 4 has an opening in the upper surface 310 of the lower band 31 parallel to the longitudinal direction X and the band width direction Y, has a depth in the band thickness direction Z with respect to the upper surface 310, and the bottom is closed. ing.

  Next, the upper band 32 is attached to the upper surface 310 of the lower band 31 and covers the opening of the electronic component storage chamber 4.

  Each of the multilayer electronic components 1 is the multilayer electronic component shown in FIGS. 1 to 3 and is accommodated in the electronic component storage chamber 4 (see FIG. 7). In the case of the illustrated embodiment, the multilayer electronic component 1 stores the electronic component in such a manner that the stacking direction T is parallel to the longitudinal direction X of the strip 3 and the width direction W is parallel to the strip thickness direction Z of the strip 3. Although accommodated in the chamber 4, it is not limited to such a mode. For example, the multilayer electronic component 1 is stored in the electronic component storage chamber 4 in such a manner that the stacking direction T is parallel to the strip thickness direction Z of the strip 3 and the width direction W is parallel to the longitudinal direction X of the strip 3. May be.

  In the illustrated embodiment, all the multilayer electronic components 1 are the multilayer electronic components shown in FIGS. 1 to 3, but unlike such a configuration, only one of the multilayer electronic components 1 is illustrated in FIG. The structure which is not the laminated electronic component shown in FIGS.

It is a perspective view which shows an example of the laminated electronic component which concerns on this invention. FIG. 2 is a cross-sectional view taken along line 2-2 in FIG. FIG. 3 is a partially enlarged end view taken along line 3-3 in FIG. 1. It is a figure explaining the process of carrying out the vertical mounting of the multilayer electronic component shown in FIGS. FIG. 5 is a partially enlarged end view taken along line 5-5 in FIG. It is a partial fracture perspective view showing one embodiment of a series of electronic parts concerning the present invention. It is a fragmentary sectional view in alignment with line 7-7 in FIG.

Explanation of symbols

10 Stacked electronic component element body 21, 22 Terminal electrode 51, 52 Edge

Claims (4)

A laminated electronic component having a substantially rectangular parallelepiped shape defined by a length direction, a width direction and a lamination direction,
When the dimension seen in the width direction is W1 and the dimension seen in the stacking direction is T1, 1 <W1 / T1 ≦ 1.7 is satisfied,
Further, the edges of the surface parallel to the length direction and the stacking direction and the surface parallel to the length direction and the width direction are rounded, and when the radius of curvature is R, 0.09 ≦ (2 × R / T1) Multilayer electronic component satisfying ≦ 0.33. The multilayer electronic component according to claim 1,
A laminated electronic component satisfying 0.13 ≦ (2 × R / T1) ≦ 0.31. An electronic device including a circuit board and a laminated electronic component,
The multilayer electronic component is described in claim 1, and is mounted on the circuit board in a mode in which a surface parallel to the length direction and the stacking direction is a mounting surface.
Electronic equipment. An electronic component series including a belt-like body provided with a plurality of electronic component storage chambers and a plurality of laminated electronic components respectively stored in the electronic component storage chambers,
At least one of the multilayer electronic components is the one described in claim 1.
Electronic component series.

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