JP2007133085A - Laser exposure apparatus, image forming apparatus and copying machine - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To perform improvement of laser exposure accuracy, precise control of exposure dot position, and reduction in exposure deviation, and to provide a tandem full-color printer that does not have a no fθ lens. <P>SOLUTION: A laser exposure apparatus is equipped with means 21, 41 for generating a pulse signal VCLK of a frequency corresponding to frequency-designating data NLD; a means 46 for generating pixel clock PCLK of a phase specified by phase designating data DPHASE in the integer multiples of the period of the pulse signal; a memory 77 for holding the frequency designating data NLD and the phase-designating data DPHASE for the purpose of converting the constant angular velocity laser scanning of a polygon mirror to a constant velocity transfer along the line of the on-line exposure dot; means 72-76 for switching/reading data from the memory, corresponding to the on-line exposure scanning; and a laser drive circuit 23 for controlling the light emission of a laser light source, according to image DATA in synchronism with the pixel clock. When the frequency of the pixel clock is high, the light emission quantity of the laser light source is increased. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a laser exposure apparatus that scans a laser beam with a polygon mirror, and an image forming apparatus and a copying apparatus that use the laser exposure apparatus. The present invention can be applied to, for example, a printer, a copying machine, and a facsimile machine.

Japanese Patent No. 2691205 JP2003-98465A.

  In Japanese Patent Laid-Open No. 2004-228688, the constant-velocity scanning of the laser beam by the fθ lens is replaced with the constant-velocity scanning of the exposure dots on the line by using a variable frequency multiplication circuit composed of a PLL circuit in correspondence with the scanning position of the constant-velocity scanning. An optical scanning device that changes the pixel clock frequency is described. Patent Document 2 describes a pixel clock generation circuit that controls the phase of a pixel clock based on phase data and an image forming apparatus using the pixel clock generation circuit.

  The laser beam scan of a normal polygon scanner is a constant angular velocity scan, but the exposure dots on a straight line (line) must be a constant velocity scan. If the exposure dots are divided by a constant frequency pixel clock while scanning at a constant angular velocity, the exposure dots become dense near the image height 0, which is the central point of the entire length of the scanning line (straight line), and as the image height increases, that is, the line end There is a characteristic that dots are sparsely hit as they approach the portion. In an optical system of a normal laser printer or copying machine, an fθ lens is used to convert the equiangular speed scanning of the polygon scanner into the uniform speed scanning, but there is a problem that the cost is high. Therefore, Patent Document 1 proposes an optical scanning device that changes a pixel clock frequency in correspondence with a scanning position of constant speed scanning by using a variable frequency multiplication circuit formed of a PLL circuit instead of an fθ lens. In Patent Document 2, assuming that the configuration of the pixel clock control unit is complicated in the pixel clock frequency modulation method in which the fθ lens is omitted, two types of clocks are generated using phase data, a counter, and a comparator. A pixel clock generation circuit is provided that generates a pixel clock from the above clock and changes the cycle of the pixel clock by phase control.

  The first object of the present invention is to improve dot exposure accuracy of laser exposure in which laser beam scanning exposure of equiangular velocity scanning is changed to constant velocity scanning of dots on the line by frequency modulation of the pixel clock. The second object is to precisely control the dot position, the third object is to reduce the deviation of the exposure amount between dots on the same line, and the fourth object is to simplify the signal processing. . A fifth object is to provide a tandem full-color image forming apparatus in which the fθ lens is omitted.

(1) A rotary deflector (512) including a polygon mirror (34) and a laser light source (31) for projecting a laser beam onto the mirror surface;
Variable frequency pulse generating means (21, 41) for generating a pulse signal (VCLK) having a frequency specified by the frequency indication data (NLD);
Pixel clock generating means (46) for counting the pulse signal (VCLK) and generating a pixel clock (PCLK) having a phase designated by phase indication data (DPHASE), which is an integral multiple of the period of the pulse signal;
The frequency indicating data for converting the equiangular velocity scanning of the reflected laser beam by the rotation of the polygon mirror into the uniform velocity movement along a straight line (main scanning line) of dots divided in synchronization with the pixel clock (PCLK). A data memory (77) for holding (NLD) and phase indication data (DPHASE) in association with the dot positions on the straight line (on the line);
The pixel clock (PCLK) is counted to generate the movement position data of the dots on the straight line, and the frequency instruction data (NLD) and phase instruction data (DPHASE) corresponding to the movement position data from the data memory (77). Data reading means (72-76) to be read and supplied to the variable frequency pulse generating means (21, 41) and the pixel clock generating means (46); and
A laser driving circuit (23) for controlling light emission of the laser light source in response to an image signal in synchronization with the pixel clock (PCLK);
A laser exposure apparatus.

  In order to facilitate understanding, reference numerals of corresponding elements, corresponding elements or corresponding elements of the embodiments shown in the drawings and described later are added for reference in the parentheses. The same applies to the following.

  From the data memory (77), the frequency indication data for converting the equiangular velocity scanning of the reflected laser beam by the rotation of the polygon mirror into the uniform velocity movement along the straight line of dots divided in synchronization with the pixel clock (PCLK) ( NLD) and phase indication data (DPHASE) corresponding to the dot position on the line scan is read to determine the frequency and phase of the pixel clock (PCLK), and the laser light source is synchronized with the pixel clock (PCLK). Therefore, laser exposure with constant dot movement (equal density distribution on the exposure dot line) is possible without using an fθ lens. Further, since the pixel clock frequency changes little by little within the scanning period of one line, that is, the frequency is dispersed, EMI (harmonic noise), for example, a striped pattern is reduced by the pixel clock.

  Since the phase is also controlled by the phase indication data (DPHASE), it is possible to reduce the variation in the exposure dot distribution due to the stepwise switching of the pixel clock frequency in dot units or block units of a plurality of dots on the line. That is, the equal density distribution on the exposure dot line can be realized more precisely. A low-cost and simple laser exposure device that omits the fθ lens can be realized.

  (2) The laser drive circuit (23) increases the amount of light emitted from the laser light source when the frequency of the pixel clock (PCLK) is high, corresponding to the frequency instruction data (NLD) (FIGS. 7 and 13); The laser exposure apparatus according to (1) above. In the region where the frequency of the pixel clock is high, the one dot allocation time (clock cycle) is short, and the angle at which the laser beam strikes the exposure scanning surface (for example, the surface of the photosensitive member) becomes small, so the light density decreases. In some cases, the amount of emitted light of the laser light source is increased according to this embodiment, so that the amount of dot light in one line can be made equal.

  (3) The laser exposure apparatus further includes a memory (77a) for storing light emission amount instruction data (voltage instruction data / light amount compensation gain) for increasing the light emission amount of the laser light source when the frequency of the pixel clock (PCLK) is high. Provided (FIGS. 16 and 17); the laser drive circuit (23) increases the light emission quantity of the laser light source when the frequency of the pixel clock (PCLK) is high, corresponding to the emission quantity instruction data; ). According to this, the same effect as said (2) is acquired.

  (4) The laser drive circuit (23) is based on frequency multiplying means (61) for generating a PWM pulse generating clock obtained by multiplying the frequency of the pixel clock (PCLK) by an integral multiple, and the PWM pulse generating clock. PWM means (66) for converting an image signal into a PWM pulse in synchronization with the pixel clock (PCLK), and controlling the light emission of the laser light source by the PWM pulse; (1) to (3) The laser exposure apparatus according to any one of the above. According to this, the dot exposure amount can be controlled by PWM (Pulse Width Modulation).

  (5) The laser driving circuit (23) corrects the level of the image signal to a high level when the frequency of the pixel clock (PCLK) is high in correspondence with the frequency instruction data (NLD), and then sets the corrected level. Conversion to PWM pulses (FIG. 13); The laser exposure apparatus according to (4) above.

  (6) The data reading means (72 to 76) includes an up / down counter (76a) for generating movement position data of the dots on the straight line, and a center point of the movement range of the dots on the straight line. Including up / down control means (72, 82, 83) for designating the up / down counter as one of up-count and down-count at the previous time and designating the other as the other after the middle point; 77a) stores only the instruction data (NLD, DPHASE, voltage instruction data, light amount compensation gain) of the one count period; the laser exposure apparatus according to any one of (1) to (5) above . According to this, the amount of data to be held in the memory is halved.

  (7) The data reading means (72 to 76) counts the divided pulses of the pixel clock (76b in FIG. 15); the laser exposure apparatus according to any one of (1) to (6) above . According to this, the amount of data to be held in the memory is reduced corresponding to the frequency division ratio. For example, when the frequency division ratio is 1/2, the data amount is 1/2.

  (8) The pixel clock generating means (46) includes first and second counting means (51, 49) for counting a pulse signal (VCLK) generated by the variable frequency pulse generating means (21, 41), and A clock level holding means (52) for outputting the pixel clock, and when one count means (51) counts a set value, the holding level of the clock level holding means (52) is switched and the phase indication by the other counter Counting of the data (DPHASE) corresponding value is started, and when the corresponding value is counted, the holding level of the clock level holding means (52) is switched and the setting value is counted by the one counter; (1) The laser exposure apparatus as described in any one of thru | or (7).

(9) The laser exposure apparatus (512) according to any one of (1) to (8) above;
A photosensitive member (202) that is irradiated with the reflected laser beam of the laser exposure apparatus to thereby form an electrostatic latent image corresponding to an image signal;
A developer (204) that visualizes the electrostatic latent image into a toner image; and
An image forming apparatus comprising transfer means (205, 208, 213) for transferring the toner image directly or via an intermediate transfer member to a sheet.

  (10) There are a plurality of the photoreceptors (202) and developing units (204), respectively; the laser exposure device (512) includes the laser light source (31), pixel clock generation means (46), frequency indication data ( NLD), phase indication data (XDEPT), and a plurality of laser drive circuits (23), and each reflected laser beam is projected onto each photoconductor; each transfer unit (205, 208, 213) is developed by each developer (204). The image forming apparatus according to (9), wherein the imaged toner image is transferred onto the same sheet.

  (11) The image forming apparatus has an intermediate transfer belt (208); the plurality of photoconductors are distributed in tandem in the moving direction of the intermediate transfer belt (208); and the transfer means (205, 208, 213) The image forming apparatus according to (10), further comprising: means (205) for transferring the toner image to the intermediate transfer belt (208);

  According to this, it is possible to realize a tandem color image forming apparatus in which the fθ lens is omitted and a simple and low-cost EMI (harmonic noise), for example, a stripe pattern is reduced.

  (12) The photoconductor includes photoconductors for Bk, C, M, and Y color images; the developing unit (204) forms Bk, C, M, and Y color toner images on the photoconductors. The full-color image forming apparatus according to (10) or (11).

  (13) Further, a controller (501) that converts document information given from the outside into image data; and an image data processing device that converts the image data into an image signal suitable for image formation by the image forming apparatus (200). (510, IPP); The image forming apparatus (200) according to any one of (9) to (12).

  (14) The image forming apparatus (200) according to any one of (8) to (12); an image reading apparatus (300) that generates image data representing an image projected by an optical system; A copying apparatus comprising: an image data processing device (510, IPP) that converts image data into an image signal suitable for image formation by the image forming device (200) and supplies the image signal to the image forming device (200).

  (15) The copying apparatus according to (14), further comprising a controller (501) that converts document information provided from outside into image data and supplies the image data to the image data processing apparatus (510, IPP).

  Other objects and features of the present invention will become apparent from the following description of embodiments with reference to the drawings.

  FIG. 1 shows the appearance of a multi-function full-color digital copying machine MF1 according to an embodiment of the present invention. This full-color copying machine is roughly constituted by units of an automatic document feeder (ADF) 120, an operation board 10 (FIG. 4), a color scanner 300, a color printer 200, and a paper supply bank 400. . A LAN (Local Area Network) connected to the personal computer PC is connected to the system controller 501 (FIG. 4) in the apparatus. The facsimile controller 506 (FIG. 4) in the machine can perform facsimile communication via the exchange PBX and the public communication network PN.

  The printer 200 includes a transfer unit, and the transfer unit includes a transfer belt 208 that is an endless belt. The transfer belt 208 is wound around three support rollers and one tension roller, and is driven to rotate counterclockwise. Near the tension roller, there is a transfer body cleaning unit that removes residual toner remaining on the transfer belt 208 after image transfer.

  The transfer belt 208 between one support roller and another support roller has Bk (black), C (cyan), M (magenta), and Y (yellow) from the upstream side along the moving direction. An image forming unit for each color image is provided, and there is a transfer roller 205 facing each photoconductor drum 202 in the image forming unit with the transfer belt 208 interposed therebetween. Above the image forming apparatus is an optical writing unit 512 that irradiates each photosensitive drum of each color photosensitive unit with laser light for image formation. The photosensitive drum 202 is uniformly charged by the charging roller 203, and a laser whose optical writing unit 512 is modulated by an image signal is projected onto the charging surface. The electrostatic latent image generated thereby is developed by the developing device 204 into a toner image. This toner image is transferred to the transfer belt 208.

  A transfer belt 213 is below the transfer belt 208. The conveyor belt 213 transfers the toner image on the transfer belt 208 onto a sheet, that is, a sheet (transfer sheet). The sheet onto which the toner image has been transferred is sent out to the fixing unit 214 by the transport belt 213. Below the conveying belt 213 and the fixing unit 214, there is a double-sided drive unit 221 that is a sheet reversing unit that feeds a sheet immediately after an image is formed on the front surface and reverses the front and back to record an image on the back surface.

  When the start switch of the operation board 10 (FIG. 4) is pressed, if there is a document in the automatic document feeder (ADF) 120, it is transported onto the contact glass of the scanner 300 and then there is no document in the ADF 120. In order to read a manually placed document on the contact glass, the scanner 300 is immediately driven, and the first carriage and the second carriage in the scanner 300 are read and scanned. Then, light is emitted from the light source on the first carriage to the contact glass, and reflected light from the document surface is reflected by the first mirror on the first carriage and directed to the second carriage, and reflected by the mirror on the second carriage. Then, an image is formed on a CCD as a reading sensor through an imaging lens. Bk, C, M, and Y color recording data are generated based on the image signal obtained by the reading sensor.

  Further, when the start switch is pushed, the transfer belt 208 starts to rotate, the image forming preparation of each unit of the image forming apparatus is started, and the image forming sequence of each color image is started. Thus, an exposure laser modulated based on each color recording data is projected onto the photosensitive drum for each color, and each color toner image is superimposed and transferred as a single image on the transfer belt 208 by each color image forming process. When the leading edge of the toner image enters the conveying belt 213, the sheet is fed to the transfer belt 213 from the registration roller pair 212, that is, the feeding roller, at a timing so that the leading edge enters the conveying belt 213 at the same time. The toner image on the belt 208 is transferred to the paper. A voltage for transferring toner is applied to the transfer belt 208 by the transfer roller 205. The sheet on which the toner image has moved is sent to the fixing unit 214 where the toner image is fixed on the sheet.

  Note that the above-mentioned paper is selectively rotated by driving one of the paper feed rollers immediately above the paper feed trays (also referred to as paper feed trays or cassettes) 209 to 211 of the paper feed bank 400 so that the paper feed bank 400 has multiple stages. A sheet is fed out from one of the paper feed trays 209 to 211, separated by one by a separation roller, put into a vertically arranged transport roller unit, transported upward, and guided to a transport path in the printer 200. The transport roller 215 transports the registration roller pair 212 to the registration roller pair 212 to stop the leading end of the sheet against the registration roller pair 212, and then rotates the registration roller pair 212 and the transport roller 215 to the transport belt 213 at the timing described above. It will be sent out. It is also possible to feed paper by inserting paper on the right side manual feed tray. When the user is inserting paper onto the manual feed tray, the printer 200 rotates the paper feed roller of the manual feed tray to separate one sheet on the manual feed tray and pull it into the manual feed path. Stop against the pair 212.

  The paper discharged after receiving the fixing process by the fixing unit 214 is guided to the discharge roller by the switching claw and stacked on a paper discharge tray (not shown). Alternatively, it is guided to the double-sided drive unit by the switching claw, reversed there and led again to the transfer position, and the image is recorded also on the back surface, and then discharged onto the paper discharge tray by the discharge roller. On the other hand, residual toner remaining on the transfer belt 208 after image transfer is removed by a transfer body cleaning unit (not shown) to prepare for image formation again.

  FIG. 2 shows an enlarged outline of the optical writing unit 512, and FIG. 3 shows an outline of the arrangement of the laser light sources of the optical writing unit 512. As shown in FIG. 2 shows a front view of the polygon mirror, while FIG. 3 shows a plan view. LDB (Bk, C, M, Y) on FIG. 3 is an LD control plate (laser diode), and a laser drive circuit 23 (bk, c, m, y; FIG. 7) described later on the LD control plate An LD (laser diode) 31 (bk, c, m, y) is energized. The laser beam generated by the LD 31 is corrected to parallel light (laser beam) by the collimating lens 32 (bk, c, m, y), and the spot shape is corrected by the cylindrical lens 33 (bk, c, m, y). To the polygon mirrors 34ybk and 34mc. The laser deflector is in a two-stage polygon format. As the polygon mirror rotates in the clockwise direction (solid arrow) in FIG. 3 at a constant speed, the reflected laser beam is swung in the direction of the one-dot chain line arrow. This is an equiangular velocity scan. Since this embodiment does not include an fθ lens, the details will be described later, but in order to convert the equiangular velocity scan to the equal velocity scan, the pixel clock frequency is set to an image height of 0 (the scan line length) as shown in FIG. As the image height increases (as the scanning point on the line approaches the end of the line), the height increases stepwise.

  A laser beam (reflected laser beam: exposure scanning beam) reflected by the polygon mirror is projected onto the photosensitive drum 202 through a path indicated by a one-dot chain line in FIG. 2, and the surface of each drum is axially projected on the paper surface of FIG. Exposure scanning is performed in the vertical direction. This is the main scanning for optical writing. Reference numeral 38 (bk, c, m, y) denotes an optical sensor of the main scanning synchronization detection circuit. The half mirror 39 (bk, c, m, y) reflects a part of the reflected laser beam toward the optical sensor 38 (bk, c, m, y). The remaining laser beam passes through the half mirror 39 and irradiates the photosensitive drum. The main scanning synchronization detection circuit detects a laser beam based on a laser beam detection signal of each sensor 38 (bk, c, m, y) and a pixel clock PCLK (bk, c, m, y) described later. Then, the level is switched to a significant level (low level L in the present embodiment) in synchronization with the pixel clock generated first, and then to an insignificant level (high level H in the present embodiment) after the set number of pixel clocks are generated. The returning main scanning synchronization signal XDETP (bk, c, m, y) is generated. The repetition interval of the main scanning synchronization signal XDETP becomes the main scanning line period. Although details will be described later with reference to the main scanning synchronization signal XDETP, the pixel clock is counted and the count data represents the scanning position (dot exposure position) on the scanning line.

  FIG. 4 shows the system configuration of the electrical system of the multifunction copying machine MF1 shown in FIG. The electrical system communicates with the outside using a system controller 501 that performs overall control of the image forming apparatus, an operation board 10 of the image forming apparatus connected to the controller 501, an HDD 503 that stores image data, and an analog line. Communication control device interface board 504, LAN interface board 505, FAX control unit 506, IEEE1394 board, wireless LAN board, USB board, etc. 507 connected to general-purpose PIC bus, and engine control 510 connected to the controller via PCI bus An I / O board 513 for controlling I / O of the image forming apparatus, a scanner board (SBU: Sensor Board Unit) 511 for reading a copy original (image), and connected to the engine control 510 An optical writing unit 512 that projects (optically writes) image light represented by image data onto the photosensitive drum is formed.

  A reading unit 300 that optically reads an original scans the original with an original illumination light source and forms an original image on the CCD 520. An original image, that is, reflected light of light irradiation on the original is photoelectrically converted by the CCD 520 to generate R, G, B image signals.

  The communication control device interface board 504 immediately informs an external remote diagnosis device when a failure occurs in the device, and allows the service person to recognize the contents and situation of the failure part and repair them immediately. . In addition, it is also used for sending out the usage status of the device.

  The CCD 520 shown in FIG. 4 is a three-line color CCD, which generates R, G, and B image signals of EVENch (even-numbered pixel channel) / ODDch (odd-numbered pixel channel), and outputs it to an analog ASIC (Application Specific IC) on the SBU board. input. The SBU board 511 is provided with a circuit for generating an analog ASIC, CCD, and analog ASIC drive timing. The output of the CCD 520 is sampled and held by a sample and hold circuit inside the analog ASIC, then A / D converted, converted into R, G and B image data, and shading corrected, and an output I / F (interface) At 520, the data is sent to an image data processor IPP (Image Processing Processor; hereinafter simply referred to as IPP) via an image data bus.

  IPP is a programmable arithmetic processing means that performs image processing, separation generation (determination of whether an image is a character area or a photographic area: image area separation), background removal, scanner gamma conversion, filter, color correction, scaling, and image processing. , Perform printer gamma conversion and gradation processing. The image data transferred from the SBU to the IPP is corrected by the IPP for signal deterioration due to quantization of the optical system and the digital signal (signal deterioration of the scanner system) and written in the frame memory 521.

  The system controller 501 includes a ROM that controls the CPU and the system controller board, a RAM that is a working memory used by the CPU, a lithium battery, an NV-RAM that includes an SRAM backup and a clock, and a system controller board. The system bus control, frame memory control, FIFO, and other ASICs for controlling the CPU periphery and their interface circuits are mounted.

  A system controller 501 has functions of a plurality of applications such as a scanner application, a facsimile application, a printer application, and a copy application, and controls the entire system. The input of the operation board 10 is decoded, and the setting of the system and the state contents are displayed on the display unit of the operation board.

  Many units are connected to the PCI bus, and image data and control commands are transferred in a time division manner by the image data bus / control command bus.

  The communication control device interface board 504 is a communication interface board between the communication control device and the controller 501. Communication with the controller 501 is connected by full-duplex asynchronous serial communication. The communication control device 522 is multi-drop connected according to the RS-485 interface standard. Communication with the remote management system is performed via the communication controller device interface board 504.

  The LAN interface board 505 is connected to an in-house LAN. It is a communication interface board between the in-house LAN and the controller 501, and is equipped with a PHY chip. The LAN interface board 505 and the controller 501 are connected by standard communication interfaces of a PHY chip I / F and an I2C bus I / F. Communication with an external device is performed via the LAN interface board 505.

  The HDD 503 is used as an application database that stores system application programs and device activation information of printers and image forming process devices, and an image database that stores image data of read images and written images, that is, image data and document data. . Both the physical interface and the electrical interface are connected to the controller through an interface compliant with ATA / ATAPI-4.

  The operation board 10 is equipped with a CPU, ROM, RAM, LCD, and ASIC (LCDC) for controlling key input. In the ROM, a control program for the operation board 10 that controls input reading and display output of the operation board 10 is written. The RAM is a working memory used by the CPU. Through communication with the system controller 501, the panel is operated to perform input for the user to input system settings, and display and input control for displaying the setting contents and status of the system to the user.

  The Bk, C, M, and Y writing signals (image DATA) output from the work memory of the system controller 501 are input to the optical writing unit 512 (FIG. 5). The optical writing unit 512 (FIG. 5) performs LD current control (PWM control) based on the write signal, and each LD is energized (driven; energized) in response to the write signal.

  The engine control 510 mainly performs image formation control, that is, image formation control, and includes a CPU, an IPP that performs image processing, a ROM that contains programs necessary to control copying and printout, a RAM that is necessary for the control, and It is equipped with NV-RAM. The NV-RAM is equipped with an SRAM and a memory that detects power-off and stores it in the EEPROM. The I / O ASIC that also has a serial interface that transmits and receives signals to and from other CPUs that perform control is a nearby I / O (counter, fan, solenoid, motor, etc.) on which an engine control board is mounted. ASIC for controlling the). The I / O control board 513 and the engine control board 510 are connected via a synchronous serial interface.

  A sub CPU 517 is mounted on the I / O control board 513, and I / O of the image forming apparatus including analog control such as P sensor and T sensor, jam detection referring to a detection signal of a paper sensor, and paper conveyance control. Control is in progress. The interface circuit 515 is an interface circuit with various sensors and actuators (motors, clutches, solenoids).

  The power supply unit PSU 514 is a unit that supplies power to control the image forming apparatus. When the main SW is turned on (closed), commercial power is supplied. The commercial AC is supplied from the commercial power source to the AC control circuit 540, and the DC power supply PSU 514 is necessary for each control board using the AC control output controlled by the AC control circuit 540 such as rectification and smoothing. Supply DC voltage. The CPU of each control unit operates using a constant voltage generated by the DC power supply unit PSU. The AC control circuit 540 includes an AC energization circuit (heater driver) that performs energization control for energizing the fixing heater 214 and maintaining the fixing temperature constant. When the main SW is switched from OFF to ON, the AC control circuit 540 supplies commercial AC to the heater driver and DC voltage to the DC power supply 514. This is the standby mode. If there is a copy or print instruction in this state, the system controller 501 instructs the engine control 510 to copy or print, and the engine control 510 starts this. The state in which the engine control 510 is executing copying or printing is an operation mode, and power consumption is large.

  During the standby mode, the system controller 501 monitors whether a color misregistration correction start condition, which will be described later, is satisfied, and performs color misregistration correction when the start condition is satisfied. When the set time input to 10 has elapsed, the AC control circuit 540 and the DC power supply device 514 are switched to the energy saving mode. That is, the AC control circuit 540 cuts off the AC supply to the heater driver, and the DC power supply device 514 directly accesses the copying machine MF1 by the user (operation board 10 input or operation for copying or printing) or external (personal computer) DC receiving power supply circuit for DC output excluding a standby power supply circuit for supplying a voltage for recognition operation to a return electric circuit for performing power supply operation for recognizing an image request or a print request from a facsimile) and returning to an operation mode. Shut off from line. As a result, the operating voltage of the system controller 501 disappears. When the return electric circuit recognizes an access from the user or the outside in the energy saving mode, the AC control circuit 540 and the DC power supply device 514 are set in the standby mode. As a result, an operating voltage is applied to the system controller 501.

  In addition to the liquid crystal touch panel, the operation board 10 includes a numeric keypad, a clear / stop key, a start key, an initial setting key, a mode switching key, a test print key, a power key, and the like. On the left side of the liquid crystal touch panel, there is an alphabet keyboard with hiragana added for inputting, setting, and abbreviated registration for URL, mail text, file name, folder name, and the like.

  On the liquid crystal touch panel, various function keys and messages indicating the operation states of the engine 300 and the controller 501 are displayed. The LCD touch panel has functions for selecting and executing the “Copy” function, “Scanner” function, “Print” function, “Facsimile” function, “Store” function, “Edit” function, “Register” function and other functions. A function selection key is displayed. An input / output screen determined for the function specified by the function selection key is displayed. For example, when the “copy” function is specified, a message indicating the function key, the number of copies, and the state of the image forming apparatus is displayed. When the operator touches a key displayed on the liquid crystal touch panel, the operation board 10 reads it as an operator input, and highlights the key indicating the selected function in gray indicating designation. Further, when it is necessary to specify the details of a function (for example, the type of page printing), a detailed function setting screen is popped up by touching a key. Thus, since the liquid crystal touch panel 11 uses a dot display, it is possible to graphically perform an optimal display at that time. Among the function keys 12, the printing color designation keys “black (Bk)”, “full color”, “automatic color selection”, “blue (C)”, “red (M)” and “yellow (Y)” designation There is a key.

  FIG. 5 shows the configuration of the image writing control unit of the optical writing unit 512. The print image control units 25m, 25c, 25y and 25Bk addressed to the color image signals of magenta M, cyan C, yellow Y and black Bk control the entire image writing control unit according to the command of the CPU of the engine control 510, and The image signals M, C, Y, and Bk (images DATAm, c, y, bk) output from the I / OASIC of the control 510 are transferred to the laser drive circuits 23m, 23c, 23y, and 23Bk. In the following, in order to simplify the description, the color component division codes m, c, y, and bk are omitted and element codes are shown.

  The reference clock generation circuit 21 generates a reference clock FREF that is used to generate a pixel synchronization clock PCLK that is a clock signal having a period in units of main scanning pixels, and sends it to the phase synchronization circuit 22. The phase synchronization circuit 22 uses the main scanning synchronization signal XDETP for each color generated by the main scanning synchronization detection circuit based on the laser beam detection signal of the optical sensor 38 as a control signal, and a reference clock sent from the reference clock generation circuit 21. A pixel synchronization clock PCLK is generated based on FREF and supplied to the print image control unit 25 and the laser drive circuit 23.

  The print image control unit 25 holds the control data given by the engine control 510 and outputs it to each unit of the image writing control unit 512, and sets a trim area in the image data frame (paper surface), or the image frame (image Image processing such as overlaying an arbitrary frame line on the surface) according to the contents designated by the CPU in the engine control 510. That is, based on the paper size, trim area data, and boundary line writing provided by the engine control 510, the print position of the incoming image signal on the paper is determined based on the main scanning count (pixel synchronization pulse count) and the sub-scanning count (line). The output of the image signal assigned to the trim area is stopped or converted to a non-record signal, and if there is boundary writing, several pixels inside the edge of the trim area The image signal is converted into a line writing signal (writing of a trim boundary line).

  Further, in this embodiment, the print image control unit 25 mainly uses the frequency indication data NLD and the phase indication data DPHASE for pixel clock frequency modulation for converting the equiangular velocity scanning of the laser beam into the constant velocity scanning of the exposure dots. It is read out from the memory 77 (FIG. 8) corresponding to the scanning dot position (on-line exposure dot position) and given to the phase synchronization circuit 22. Further, the frequency instruction data NLD is also given to the laser drive circuit 23 in order to correct the laser beam quantity corresponding to the main scanning dot position.

  The laser drive circuit 23 converts the image signal (image DATA) sent from the print image control unit 25 into a PWM drive signal synchronized with the pixel clock PCLK (pixel synchronization pulse) coming from the phase synchronization circuit 22, and the drive signal Based on this, the LD 31 is energized. The polygon motor control circuit 24 performs PLL (Phase Locked Loop) control of the polygon motors 35ybk and 35mc to a predetermined rotational speed based on the reference clock FREF.

  FIG. 6 shows the configuration of the phase synchronization circuit 22 for one color. In this embodiment, the phase synchronization circuit 22 generates a frequency multiplication pulse VCLK having a frequency N (integer) times the reference clock FREF specified by the frequency instruction data NLD, and the frequency multiplication pulse VCLK. The phase control frequency divider 46 generates a pixel clock PCLK having a phase specified by the phase instruction data DPHASE.

  The PLL circuit 41 calculates a phase difference between the frequency-divided pulse obtained by dividing the frequency-multiplied pulse VCLK by the 1 / N frequency divider 45 and the reference clock FREF by the phase comparator 42, and outputs the phase difference by an LPF (low-pass filter) 43. The phase difference is integrated, and the frequency-multiplied pulse VCLK is controlled to the frequency and phase corresponding to the integrated value by the VCO (voltage controlled variable frequency oscillator) so that the phase difference becomes zero. In order to change the frequency of the frequency multiplication pulse VCLK, the value of NLD [12: 0] (N or 1 / N) may be changed.

  The phase control frequency divider 46 includes first and second counters 51 and 49 for defining the H period and the L period of the pixel clock PCLK. The first counter 51 is cleared by an L pulse obtained by inverting a main scanning synchronization signal XDETP (L pulse) that is a line synchronization signal indicating the head of a line and a count over signal (carry signal: H pulse) of the second counter 49. Then, when the frequency multiplied pulse VCLK is counted up by 4 pulses, a count over signal (carry signal: H pulse) is generated to reset the flip-flop 52 for outputting the pixel clock PCLK. The second counter 49 is cleared by the inverted signal of the carry signal H of the first counter 49, and at the falling edge point of the carry signal H, the addition value of the adder 48 is loaded into the count value, and the pixel is calculated from the value. When the number of arrivals of the clock PCLK is counted down and the remaining value becomes 0 (when the count up for the added value is completed), a count over signal (carry signal: H pulse) is generated and a flip-flop for outputting the pixel clock PCLK 52 is set and the counter 51 is cleared. The adder 48 has L period value 4 for dividing the frequency-multiplied pulse VCLK to the basic frequency division ratio 1/8 and phase indication data DPHASE [1: 0] designating a numerical value of 0 to 3. The addition operation is started at the falling edge of the carry signal H of the first counter 49, and the addition value is updated and latched (updated) in the output latch (flip-flop) in the adder 48. . The timing of this update latch is after the timing at which the second counter 49 loads the added value at the falling edge of the carry signal H of the first counter 49, so that the phase indication data DPHASE [1: 0] is updated. The phase change is delayed by one cycle of the pixel clock with respect to (one cycle of the pixel clock PCLK or a cycle that is an integral multiple, as will be described later).

  Due to the operations of the first and second counters 51 and 49 described above, the pixel clock PCLK is constant in four periods of the frequency multiplied pulse VCLK that is the count-up period of the first counter 51 during the H period. The L period is a period of 4 cycles + a value (0 to 3) represented by the phase instruction data, and the phase of the pixel clock PCLK is controlled by controlling the L period by the phase instruction data. The adder 48 may be omitted, and the phase instruction data DPHASE may be changed to one representing 4 + 0 to 3. Further, the adder 48 is used as an adder / subtracter, and the phase indication data DPHASE represents 0, +1, +2, −1, −2, or the adder 48 is omitted and the phase indication data DPHASE is set to 2, It may represent 3,4,5,6. In this case, the phase of the rising edge of the pixel clock PCLK can be advanced or delayed within the range of 4 periods (half period of PCLK) of the frequency multiplication pulse VCLK.

  Although the PLL circuit 41 is provided in each of the phase control circuits 22bk, 22c, 22m, and 22y, it can be a single one that is used in common. The phase control frequency divider 46 is provided in each of the phase control circuits 22bk, 22c, 22m, and 22y so that the phase of the pixel clock PCLK can be individually adjusted for each color of Bk, C, M, and Y. Is preferred. The phase control frequency divider 46 may change the connection so that the carry signal of the first counter 51 is applied to the set input terminal of the flip-flop 52 and the carry signal of the second counter 49 is applied to the reset input terminal. In this case, the L period of the pixel clock PCLK is constant in 4 cycles of the frequency multiplication pulse VCLK, and the H period is adjusted within the range of 4 cycles of the frequency multiplication pulse VCLK + 0 to 3 cycles by the phase indication data DPHASE. .

  FIG. 7 shows an outline of the configuration of the laser drive circuit 23 that supplies current to the LD 31. An LD 31 that exposes the photosensitive drum and a photodiode PD that detects a part of the output light (optical power) are incorporated in one package as a laser light emitter for driving an APC (Automatic Power Controller).

  In the present embodiment, a PWM pulse PWM having a duty corresponding to the image DATA [4: 0] (recording instruction density) synchronized with the pixel clock PCLK is supplied to the LD driver 71, and the PWM H period (or L period). During this period, the energization level of the LD 31 is controlled so that the level of the light amount detection signal of the photodiode PD matches the voltage instruction level VCONT corresponding to the light amount reference signal. The image DATA [4: 0] is a recording density gradation expression used for laser exposure in a normal case (conventional example using an fθ lens; the PWM cycle is constant). In this embodiment, the PWM cycle (the pixel clock PCLK) is used. Therefore, the PLL circuit 61 generates a count pulse for generating a PWM pulse M times the frequency of the pixel clock PCLK in order to prevent an error corresponding to the change in the cycle. Therefore, the frequency of the count clock for generating PWM pulses changes at the same rate as the change in the frequency of the pixel clock PCLK.

  The flip-flop 68 of the PWM pulse generator 66 is set at the rising point of the pixel clock PCLK from L to H, and its Q output (PWM pulse) becomes H. At the rising edge of H, the counter 67 of the PWM pulse generator 66 loads the image DATA [4: 0], and starts counting down the count clock for generating the PWM pulse from the value, and the image DATA [4: 0]. ], A count over signal (carry signal) H is generated. At the rising point to H, the flip-flop 68 is reset and its Q output (PWM pulse) is inverted to L. This L continues until the pixel clock PCLK rises to H again.

  By the way, at the center point (image height 0) of the total line scanning length, the cycle of the pixel clock PCLK (PWM pulse cycle) is long and becomes shorter as it approaches the line end, so 1 dot exposure is assigned as it approaches the line end. Time is reduced and the exposure of one dot is reduced. Further, since the fθ lens is not used, the laser beam reflected by the polygon mirror is orthogonal to the photoconductor surface at the center point of the total line scanning length, but as it approaches the end of the line (with an increase in the frequency of the pixel clock PCLK). The angle with respect to the photoreceptor surface becomes smaller than 90 degrees, reflection on the photoreceptor surface increases, and the amount of laser beam irradiation on the photoreceptor decreases. In order to compensate for the light quantity reduction, in this embodiment, the frequency indication data NLDM [12: 0] for determining the frequency of the pixel clock PCLK is converted by the data converter (amplifier; may be a lookup table) 69 to reduce the light quantity. Is converted into voltage instruction data corresponding to the light quantity reference signal, and the converted data is converted into an analog voltage VCONT by the D / A converter 70 and applied to the LD driver 71. The LD driver 71 controls the energization level of the LD 31 so that the level of the light amount detection signal of the photodiode PD matches the voltage instruction level VCONT corresponding to the light amount reference signal during the H period (or L period) of PWM. To do. As a result, the LD emits a light amount corresponding to the image DATA [4: 0].

  The frequency-multiplied pulse VCLK generated by the PLL circuit 41 of the phase synchronization circuit 22 is changed to a high frequency that does not cause shortage of the above-described PWM pulse generation, and is given as a count pulse to the counter 67 of the PWM pulse generator 66. The PLL circuit 61 of the drive circuit 23 can be omitted.

  FIG. 8 shows the above-described frequency instruction data NLD [12: 0] and phase instruction data DPHASE [1: 0] held by the print image control unit 25 at the on-line scanning position of the line scanning of the reflected laser beam. The circuit part which outputs each corresponding data to the phase-synchronization circuit 22 and the laser drive circuit 23 is shown. In the equiangular / constant velocity conversion table 77 using the semiconductor memory, the LD emission initial value data (frequency indication data NLD [12: 0] and phase indication data DPHASE [1] for generating the main scanning synchronization signal XDETP is stored. : 0]), and the beginning (main scanning x) of the effective scanning area (effective section) corresponding to the image forming effective area in the axial direction x of the photosensitive drum 202 in one line scanning section of the reflected laser beam of the polygon mirror. Frequency indication data NLD [12: 0] and phase indication data DPHASE [1: 0] addressed to each exposure dot position (including each end) between the effective start point and the end point (effective end point of the main scan x). Stored. In this embodiment, since the phase instruction data DPHASE [1: 0] is 2 bits and has a small number of bits, the data is stored in the equiangular / constant velocity conversion table 77 as it is. However, since the frequency instruction data NLD [12: 0] has a large number of bits of 13 bits, in order to reduce the number of stored bits, the data of the succeeding scanning dot of the adjacent scanning dot with respect to the data of the preceding scanning dot is reduced. The difference data of 6 bits or less representing the difference is compressed and stored. When this compressed data is read from the table 77, it is restored to the original 13-bit data NLD [12: 0] by the decoder 78 and output to the PLL circuit 41 and the data converter 69.

  The address counter 76 designates a data read address corresponding to the scanning dot position in the effective scanning area in the one-line scanning section of the table 77. Frequency instruction data NLD and phase instruction data DPHASE addressed to each exposure dot in the effective scanning area are stored at addresses on the table 77 corresponding to count data of count value 1 or more of the address counter 76. In the address on the table 77 corresponding to the count data of the count value 0, initial value data (frequency indication data NLD and phase indication data DPHASE) for LD emission for generating the main scanning synchronization signal XDETP is stored. ing.

  When the laser exposure scanning is started, the address counter 76 is initialized and the count data becomes 0 value data. Therefore, the LD light emission initial value data (frequency indication) for generating the main scanning synchronization signal XDETP from the table 77. Data NLD and phase indication data DPHASE) are read out. When the reference clock generation circuit 21 and the phase synchronization circuit 22 are energized, the counter 51 counts up from 0 to 4, and when it counts up to 4, a carry signal is generated, the flip-flop 52 is reset, and the counter 49 is cleared. Then, the count value of the counter 51 is set to 0 and recounting is started. When the carry signal of the counter 51 disappears, the counter 49 loads the addition value of the adder 48 and starts counting the addition value. When the counting of the addition value ends, the counter 49 generates a carry signal and sets the flip-flop 52. And the counter 51 is cleared. When the carry signal disappears, the counter 51 starts counting up from the count value 0. By such circulation, a pixel clock PCLK (Q output of the flip-flop 52) is generated. When the rotation speed of the polygon mirror rises and stabilizes, the print image control unit 25 sets the image DATA [4: 0] to the light emission instruction level. As a result, a reflected laser beam is generated and swings at an equal angular velocity. When the reflected laser beam reaches the sensor 38, a scanning synchronization signal XDETP (L pulse) is generated. When the counter 51 is cleared by this XDETP and the XDETP (L pulse) disappears (rises to H), the counter 51 starts counting up from 0, so that the pixel clock PCLK becomes the head of the line (position 38). Thus, the signal is synchronized with the scanning synchronization signal XDETP.

  When the main scanning counter 72 of the print image control unit 25m is cleared by the scanning synchronization signal XDETP and XDETP (L pulse) disappears (rises to H), the main scanning counter 72 starts counting up the pixel clock PCLK. . Therefore, the count data of the main scanning counter 72 represents the exposure dot position on one line with the sensor 38 as a base point. When the exposure dot position reaches the start point of the effective scanning area, the output of the first comparator 73 is switched from L to H. When the exposure dot position reaches the end point of the effective scanning area, the output of the second comparator 74 switches from H to L. Therefore, the outputs of the comparators 73 and 74 are output only while the exposure dot position is in the effective scanning area. Both are H, and the pixel clock PCLK is applied to the count pulse input terminal CK of the address counter 76 through the AND gate 75a while the reflected laser beam is scanned in this effective scanning region. At the clear input terminal CL of the address counter 76 (L level input is the clear operation level), the scanning synchronization signal XDETP (L pulse) and the outputs L of the comparators 73 and 74 (outside the effective scanning area) are cleared through the AND gate 75b. While being given as an instruction signal, the address counter 76 maintains a clear state while it is L, and the output count data represents a 0 value, whereby the table 77 is used to generate the main scanning synchronization signal XDETP. Initial value data (frequency indication data NLD and phase indication data DPHASE) for LD emission is output. While the AND gate 75a outputs the pixel clock PCLK, the print image control unit 25 outputs the printing image DATA to the laser drive circuit. However, when the AND gate 75a is turned off (output of the pixel clock PCLK is stopped). When the count data of the main scanning counter 72 comes to the position immediately before the sensor 38, the laser light is used to drive light emission data (image DATA) for LD light emission (for light detection of the sensor 38) for generating the scanning synchronization signal XDETP. Output to the circuit 23.

  FIG. 9 schematically shows changes in the frequency of the pixel clock PCLK during one-line exposure scanning of the reflected laser beam. The horizontal axis represents the scanning area of one line, and the vertical axis represents the pixel clock frequency controlled by the frequency instruction data NLD read from the table 77 corresponding to the exposure dot scanning position on one line. “Image height 0” on the horizontal axis corresponds to the center position of the photosensitive drum 202 in the axial direction x.

  FIG. 10 shows changes in the laser scanning area and the pixel clock frequency defined by the main scanning x and the sub-scanning y. In this embodiment, the sub-scanning y is the moving direction of the photosensitive member due to the rotation of the photosensitive drum 202. XDETP is a main scanning synchronization signal, XPSTA is a sub scanning start signal, and XFGATE is a sub scanning image effective area signal.

  FIG. 11 shows the relationship between the frequency multiplied pulse VCLK and phase instruction data generated by the PLL circuit 41 and the pixel clock PCLK. When the phase indication data DPHASE [1: 0] is 00b representing the numerical value 0 (both 2 bits are binary “0”), there is no phase correction, and the pixel clock PCLK is VCLK 4 cycles in both H and L periods. This is a pulse with a duty of 50% of the frequency of 1/8 of VCLK. In the case of 01b representing a decimal value of 1 (the lower bit is a binary “1” and the upper bit is a binary “0”), the rise of the pixel clock PCLK from L to H is determined by the frequency multiplied pulse VCLK. Delay one cycle. That is, the L period of the preceding image clock PCLK is lengthened by one cycle of the frequency multiplication pulse VCLK. In the case of 10b, the frequency multiplication pulse VCLK is delayed by two cycles. The phase indication data DPHASE [1: 0] is updated in synchronization with the pixel clock PCLK and is reflected on the next rising edge of PCLK. When the phase indication data is 00b, PCLK has a cycle eight times that of VCLK. However, when the correction data is 01b, the phase of the rising edge is delayed by one cycle of VCLK.

  The image DATA is 5-bit data in this embodiment, but any number of bits may be used. However, in this embodiment, since the recording density is expressed in multiple values by gradation control by PWM in the period of one pixel clock, the image DATA is set to 2 bits or more. When the recording density control by PWM is not performed, the image DATA may be 1 bit. On the other hand, when only the 1-bit image DATA is targeted, a laser drive circuit that omits the PLL circuit 61 and the PWM pulse generator 66 and inputs the 1-bit image DATA to the LD driver 71 as it is is used.

  The phase adjustment of the pixel clock PCLK results in fine adjustment of the cycle (frequency) of the pixel clock PLCK. A frequency adjustment of 1 dot or less is performed by DPHASE [1: 0]. That is, the coarse adjustment of the frequency is performed by NLD [12: 0], and the fine adjustment is performed by DPHASE [1: 0].

  As shown in FIG. 9, at an image height of 0, the pixel clock frequency is set to a low value, and the pixel clock frequency increases stepwise as exposure scanning proceeds to the end of the line (as the image height increases). As a result, the LD driving light quantity reference voltage VCONT given to the LD driver 71 is switched higher as the pixel clock frequency becomes higher, as shown in FIG. As described above, although the fθ lens is not used, the exposure dots by the line scanning of the laser beam reflected by the polygon mirror on the surface of the photosensitive drum are scanned at a constant speed (uniform width in the main scanning direction), and the same image DATA If it is a value, the light quantity of the exposure dot is substantially constant over the entire length of the line.

  FIG. 13 shows the configuration of the laser drive circuit 23 of the second embodiment. In the second embodiment, the LD driver 71 inserts a current control transistor and a switching transistor in series between the LD and the equipment ground, and gives the hold voltage of the sample hold circuit to the base of the current control transistor, thereby preventing non-printing. During a period (for example, outside the effective scanning region in which the AND gate 75a outputs the pixel clock PCLK), the LD emits light and energizes the received light amount signal of the phototransistor PD. The output voltage of the sample and hold circuit is adjusted so as to match the voltage), and the matched output voltage is held by the sample and hold circuit. In the effective scanning region, the switching transistor is turned on and the LD is lit only during the H period (or L period) of the PWM pulse. Since the effective scanning region (image printing period) is a constant value determined by the LD drive current determined by the output voltage of the sample and hold circuit, the data converter 80 uses the data converter 80 to compensate the light intensity of the frequency instruction data NLD [12: 0]. By converting to gain and multiplying the image DATA [4: 0] by the multiplier (amplifier) 81, that is, by correcting the amplification of the PWM pulse, the decrease of the exposure dot light amount due to the increase of the pixel clock frequency is compensated. Other configurations and functions of the second embodiment are the same as those of the first embodiment.

  FIG. 14 shows a partial configuration of the print image control unit 25 of the third embodiment. In the third embodiment, a third comparator 82 is provided to detect the position of the image height 0 on one-line exposure scanning, and the address counter 76a is an up / down counter, and moreover, equiangular / etc. The speed conversion table 77 stores only the frequency instruction data NLD (compressed data thereof) and the phase instruction data DPHASE from the start point of the effective scanning area to the image height 0. The up / down counter 76a counts up the pixel clock of the effective scanning area output from the AND gate 75b while H is applied to the up / down instruction input terminal U / D, and L is applied to the input terminal U / D. During this time, the pixel clock of the effective scanning area output from the AND gate 75b is counted down. Until the exposure dot scanning position reaches the image height 0 position (the center point of one line), the output of the comparator 82 is H and the AND gate 83 gives H to the counter 76a to instruct count up. When the dot scanning position passes the zero image height position (the center point of one line), the output of the comparator 82 turns to L, and the AND gate 83 gives L indicating the countdown to the counter 76a. As a result, when the count data of the address counter 76a is increased to the position data equivalent value at the image height 0 position (the center point of one line), it is decreased from the next. Therefore, also in the third embodiment, as shown in FIG. 9, the frequency of the pixel clock PCLK changes over the entire effective scanning area of one line. Other configurations and functions of the third embodiment are the same as those of the first embodiment. According to the third embodiment, the amount of data stored in the table 77 is half that in the first embodiment. In the third embodiment, the laser drive circuit 23 of the second embodiment may be used.

  FIG. 15 shows a partial configuration of the print image control unit 25 of the fourth embodiment. In the fourth embodiment, a frequency divider 76b is added to the print image control unit 25 of the third embodiment, and the pixel clock PCLK in the effective scanning region is divided by a frequency of 1 / K (K is an integer of 2 or more). The clock is divided and given to the count pulse input terminal CK of the up / down counter 76a, and a set of frequency instruction data and phase instruction data of the equiangular / constant speed conversion table 77a is K pieces continuous on one line. The data amount is reduced to 1 / K of the third embodiment and 1 / (2K) of the first embodiment. In the fourth embodiment, since the same frequency instruction data and phase instruction data are assigned to K exposure dots continuous on one line, the frequency and phase of the pixel clock are set to K consecutive on one line. It is the same for the exposed dots. Other configurations and functions of the fourth embodiment are the same as those of the third embodiment.

  FIG. 16 shows a partial configuration of the print image control unit 25 of the fifth embodiment. In the fifth embodiment, the voltage output from the data converter 69 of FIG. 7 is stored in the equiangular / constant velocity conversion table 77a of the print image control unit 25 of the third embodiment as frequency instruction data and phase instruction data. Data equivalent to the instruction data is added, the data converter 69 in the laser drive circuit 23 (FIG. 7) is omitted, and the voltage instruction data read from the table 77a is output to the D / A converter 70 (FIG. 7). Other configurations are the same as those of the third embodiment. The operation of the fifth embodiment is the same as that of the third embodiment.

  FIG. 17 shows a partial configuration of the print image control unit 25 of the sixth embodiment. In the sixth embodiment, the data stored in the equiangular / constant velocity conversion table 77a of the print image control unit 25 of the third embodiment is converted into frequency instruction data and phase instruction data, and the amount of light output by the data converter 80 in FIG. Data equivalent to the compensation gain is added, the data converter 80 in the laser drive circuit 23 (FIG. 13) is omitted, and the light amount compensation gain data read from the table 77a is output to the multiplier 81 (FIG. 13). Other configurations are the same as those of the third embodiment. The operation of the sixth embodiment is the same as that of the print image control unit 25 (FIG. 14) of the third embodiment and the laser drive circuit 23 (FIG. 13) of the second embodiment.

1 is a longitudinal sectional view of a multi-function full-color copying machine according to a first embodiment of the present invention. It is an enlarged front view which shows the laser beam path of the optical writing unit 512 shown in FIG. 1 with a dashed-dotted line. FIG. 3 is an enlarged plan view of the polygon mirror 34mc shown in FIG. FIG. 2 is a block diagram showing an outline of an image processing system of the copying machine shown in FIG. 1. FIG. 5 is a block diagram showing a configuration of an electric control system of the optical writing unit 512 shown in FIG. 4. FIG. 6 is a block diagram showing a configuration of a phase synchronization circuit 22m shown in FIG. It is a block diagram which shows the structure of the laser drive circuit 23m shown in FIG. FIG. 6 is a block diagram showing a configuration of a part of a print image control unit 25m shown in FIG. 7 is a graph schematically showing a frequency change (vertical axis) corresponding to a scanning position (horizontal axis) on one line scanning of the pixel clock PCLK output from the phase synchronization circuit 22m shown in FIG. 6; It is a top view which shows typically the relationship between the frequency change of pixel clock PCLK, and the exposure scanning area | region of a laser beam. 7 is a time chart showing waveforms of a frequency multiplication pulse VCLK and a pixel clock PCLK generated by the PLL circuit 41 and the phase control frequency divider 46 shown in FIG. It is a graph which shows typically the change corresponding to the scanning position (horizontal axis) on 1 line scanning of the light quantity reference voltage VCONT of LD driving given to the LD driver 71 shown in FIG. It is a block diagram which shows the structure of the laser drive circuit 23m used in 2nd Example of this invention. It is a block diagram which shows the structure of the printing image control part 25m used in 3rd Example of this invention. It is a block diagram which shows the structure of the printing image control part 25m used in 4th Example of this invention. It is a block diagram which shows the structure of the printing image control part 25m used in 5th Example of this invention. It is a block diagram which shows the structure of the printing image control part 25m used in 6th Example of this invention.

Explanation of symbols

10: Operation board 300: Color document scanner 120: Automatic document feeder 200: Color printer PC: Personal computer PBX: Exchanger PN: Communication line 204: Charging roller 205: Transfer roller 208: Transfer belts 209 to 211: Paper feed tray 212 : Registration roller pair 213: Conveying belt 214: Fixing unit 512: Optical writing unit 514: Power supply device

Claims (15)

A rotary deflector including a polygon mirror and a laser light source for projecting a laser beam onto the mirror surface;
Variable frequency pulse generating means for generating a pulse signal having a frequency specified by the frequency indication data;
Pixel clock generating means for counting the pulse signal and generating a pixel clock having an integer multiple of the period of the pulse signal and having a phase specified by phase indication data;
The frequency indication data and the phase indication data for converting the equiangular velocity scanning of the reflected laser beam by the rotation of the polygon mirror into the uniform velocity movement along the straight line of dots divided in synchronization with the pixel clock is the straight line. A data memory to store in association with the upper dot position;
The pixel clock is counted to generate movement position data of the dots on the straight line, and the frequency instruction data and phase instruction data corresponding to the movement position data are read from the data memory, and the variable frequency pulse generation means, Data reading means for supplying to the pixel clock generating means; and
A laser driving circuit for controlling light emission of the laser light source in response to an image signal in synchronization with the pixel clock;
A laser exposure apparatus.   2. The laser exposure apparatus according to claim 1, wherein the laser driving circuit increases the light emission amount of the laser light source when the frequency of the pixel clock is high corresponding to the frequency instruction data;   The laser exposure apparatus further includes a memory for storing light emission amount instruction data for increasing the light emission amount of the laser light source when the frequency of the pixel clock is high; the laser driving circuit corresponds to the light emission amount instruction data; 2. The laser exposure apparatus according to claim 1, wherein when the frequency of the pixel clock is high, the amount of light emitted from the laser light source is increased.   The laser drive circuit generates a PWM pulse generation clock that is an integer multiple of the frequency of the pixel clock, and an image signal in synchronization with the pixel clock based on the PWM pulse generation clock. 4. The laser exposure apparatus according to claim 1, further comprising: PWM means for converting into a PWM pulse, wherein the light emission of the laser light source is controlled by the PWM pulse. 5.   5. The laser drive circuit according to claim 4, wherein the laser drive circuit corrects the level of the image signal to be high when the pixel clock frequency is high, and then converts the corrected level into a PWM pulse corresponding to the frequency instruction data; Laser exposure device.   The data read-out means is an up / down counter for generating movement position data of the dot on the straight line, and up / down counter when the dot is before the center point of the movement range on the straight line. 2. An up / down control means that designates one of count and down count and designates the other after the center point; and the memory means stores only the instruction data of the one count period; The laser exposure apparatus according to any one of 1 to 5.   The laser exposure apparatus according to claim 1, wherein the data reading unit counts the frequency-divided pulses of the pixel clock.   The pixel clock generating means includes first and second counting means for counting pulse signals generated by the variable frequency pulse generating means, and clock level holding means for outputting the pixel clock, and one of the counting means is set When the value is counted, the holding level of the clock level holding unit is switched and the phase counter data corresponding value is started to be counted by the other counter. When the corresponding value is counted, the holding level of the clock level holding unit is switched and the one is The laser exposure apparatus according to any one of claims 1 to 7, wherein the setting value is counted by a counter. A laser exposure apparatus according to any one of claims 1 to 8;
A photoreceptor that irradiates the reflected laser beam of the laser exposure apparatus and thereby forms an electrostatic latent image corresponding to an image signal;
A developing unit that visualizes the electrostatic latent image into a toner image; and
An image forming apparatus comprising: a transfer unit that transfers the toner image to a sheet directly or via an intermediate transfer member.   The laser exposure apparatus has a plurality of systems of the laser light source, pixel clock generation means, frequency instruction data, phase instruction data, and laser drive circuit, and each of the reflected laser beams. The image forming apparatus according to claim 9, wherein the toner image is projected onto each photoconductor; and the transfer unit transfers the toner image visualized by each developer while being superimposed on the same sheet.   The image forming apparatus includes an intermediate transfer belt; the plurality of photosensitive members are distributed in tandem in a moving direction of the intermediate transfer belt; and the transfer unit is configured to transfer the toner image to the intermediate transfer belt and the intermediate transfer belt The image forming apparatus according to claim 10, further comprising means for transferring from a belt to a sheet.   11. The photoconductor includes respective photoconductors for Bk, C, M, and Y color images; and the developing unit forms Bk, C, M, and Y color toner images on the respective photoconductors. The full-color image forming apparatus according to 11.   13. A controller for converting document information provided from the outside into image data; and an image data processing device for converting the image data into an image signal suitable for image formation by the image forming apparatus. The image forming apparatus according to any one of the above.   The image forming apparatus according to claim 9; an image reading apparatus that generates image data representing an image projected by an optical system; and the image data adapted to image formation by the image forming apparatus. An image data processing apparatus that converts the image signal into an image signal to be supplied to the image forming apparatus. 15. The copying apparatus according to claim 14, further comprising a controller that converts document information given from outside into image data and gives the image data to the image data processing apparatus.

Images