JP2007129757A - Digital demodulation apparatus and method for detecting synchronization - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a digital demodulation apparatus and a synchronization detecting method, in which whether a synchronization error is generated in a DTV signal or not can be judged, and when the generation of the synchronization error is judged, a synchronizing position is corrected. <P>SOLUTION: A control part (4) receives a center tap coefficient from a waveform equalization part (2) and compares the center tap coefficient with a given center tap coefficient threshold. When the coefficient is smaller than the threshold, the synchronization detection part (1) judges the existence of the synchronization error and outputs a control signal. The synchronization detection part (1) inputs the control signal and redetects a synchronizing signal included in a received signal. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a digital signal synchronization detection technique, and more particularly to a synchronization signal detection technique included in a digital television signal (DTV signal) transmitted from a broadcasting station.

  Initially, digital broadcasting has been mainly performed by satellite broadcasting, but in recent years, the trend of digitization has also been rushing to terrestrial broadcasting. In terrestrial digital broadcasting, a distortion that a DTV (Digital TV) signal transmitted from a broadcasting station receives on a transmission path is larger than that in satellite broadcasting.

  FIG. 19 shows an example of typical multipath interference in terrestrial broadcasting, which is one of distortions received on the transmission path. In the figure, reference numeral 1901 denotes a broadcasting station that transmits a DTV signal, 1902 is an obstacle that reflects the DTV signal transmitted from the broadcasting station 1901, and 1903 is an antenna that receives the DTV signal transmitted from the broadcasting station 1901. 1904 is a DTV receiver.

  Of the DTV signals received by the antenna 1903, a DTV signal that arrives directly from the broadcasting station 1901 and has a good reception status is a desired wave, and for example, the DTV signal W1 corresponds to this. On the other hand, a DTV signal with poor reception conditions, such as reflected by an obstacle 1902 other than the desired wave, is a delayed wave, and corresponds to, for example, the DTV signal W2. The delayed wave is generally a signal whose phase is delayed from that of the desired wave because the transmission distance is longer than that of the desired wave, and a part of the energy is lost when reflected by the obstacle 1902 and the amplitude is increased. The antenna 1903 receives the desired wave W1 and the delayed wave W2. For this reason, the DTV signal input to the DTV receiver 1904 is a combination of the desired wave W1 and the delayed wave W2, and is distorted. As described above, receiving signals distorted by combining signals that arrive via a plurality of transmission paths is called multipath interference.

  FIG. 20 shows a received signal when receiving multipath interference. In the figure, W1 is a desired wave, W2 is a delayed wave, and DT1 is a received signal. The received signal DT1 is a distorted signal obtained by synthesizing the desired wave W1 and the delayed wave W2.

  The digital demodulator in the DTV receiver 1904 attempts to demodulate the DTV signal of the desired wave by reducing the distortion of the received signal. FIG. 21 shows the configuration of a conventional digital demodulator. In the figure, 101 is a synchronization detector that detects the synchronization of the received signal DT1, and 102 is a waveform equalization that reduces distortion of the received signal DT1 based on the synchronization timing signal DT2 output from the synchronization detector 101. 103 is an error correction unit for correcting a code error of the waveform-equalized DTV signal DT3. Note that the data DT4 that has been error-corrected by the error correction unit 103 is output to a circuit subsequent to the digital demodulator in the DTV receiver 1904, and processing for video display is performed.

  The DTV signal is composed of predetermined data units (segments) starting with a synchronization signal (portion indicated by A or A ′ in FIG. 20) indicating synchronization timing. The synchronization detection unit 101 detects a synchronization signal from the received signal DT1, and outputs a synchronization timing signal DT2 at the same timing as the synchronization signal.

  The synchronization detection is a particularly important function in determining the performance of the DTV receiver 1904, and at the present time when the performance competition of the DTV receiver 1904 is intense, further performance improvement is required.

  The synchronization detection unit 101 normally detects the synchronization by capturing the synchronization signal (A in FIG. 20) included in the desired wave W1 (2001 in FIG. 20). However, when the amplitude of the delay wave W2 synthesized with the reception signal DT1 is particularly large, the synchronization signal (A ′ in FIG. 20) included in the delay wave W2 may be captured instead of the desired wave W1. Yes (2002 in FIG. 20).

  When the synchronization detection unit 101 detects the synchronization signal of the delayed wave W2, that is, when there is a synchronization error, the synchronization timing signal DT2 is output at the timing of the synchronization signal included in the DTV signal of the delayed wave W2. The waveform equalizing unit 102 operates to remove the desired wave W1 from the received signal DT1 based on the synchronization timing signal DT2. However, since the energy of the desired wave W1 is larger than that of the delayed wave W2, it is difficult to completely remove the desired wave W1. For this reason, the waveform-equalized DTV signal DT3 includes an error that cannot be corrected by the error correction unit 103.

  In view of the above problems, the present invention provides a digital demodulator that detects a correct synchronization position for a received signal that is distorted due to multipath interference or the like, and synchronization detection for detecting the correct synchronization position. It is an object to provide a method.

  In order to solve the above problems, the means provided by the present invention is a digital demodulator that detects a synchronization signal included in a received signal and outputs a synchronization timing signal indicating the timing of the synchronization signal. A waveform equalization unit that has a transversal filter, sets the timing of the synchronization timing signal as a center tap position, and performs waveform equalization of the received signal by updating a coefficient of the tap of the transversal filter; And a control unit that inputs a coefficient of one of the taps and determines whether or not the synchronization detection unit has a synchronization error based on the coefficient of the tap.

  According to the present invention, the control unit determines whether or not the synchronization detection unit has a synchronization error based on the tap coefficient of the transversal filter. Therefore, the digital demodulator can know whether or not a synchronization error has occurred, and can perform processing for detecting a correct synchronization position.

  Preferably, when the control unit determines that the synchronization detection unit has a synchronization error, the control unit instructs the synchronization detection unit to re-detect the synchronization signal. In addition, the synchronization detection unit redetects the synchronization signal in response to an instruction from the control unit.

  According to the present invention, when the control unit determines that the synchronization detection unit has a synchronization error, the synchronization detection unit can re-detect the synchronization signal. Accordingly, it can be expected that a new synchronization signal is detected by the synchronization detection unit and a correct synchronization position is detected.

  Preferably, the digital demodulator includes a second synchronization detector that detects a synchronization signal included in the received signal and outputs a synchronization timing signal indicating the timing of the synchronization signal. And a synchronous detection part and a 2nd synchronous detection part shall respectively re-detect a synchronous signal according to the instruction | indication from the said control part. In addition, the control unit selects a synchronization timing signal output from one of the synchronization detection unit and the second synchronization detection unit as a signal indicating timing for the waveform equalization, and the selected signal Is determined to be a synchronization error, the other of the synchronization detection unit and the second synchronization detection unit is instructed to re-detect the synchronization signal, and the synchronization detection unit instructed to re-detect the synchronization signal or the second When the synchronization timing signal output by the synchronization detection unit is different in timing from the selected signal, the synchronization timing signal is newly selected as a signal indicating the timing for the waveform equalization. To do.

  According to the present invention, by providing two synchronization detection units, the synchronization signal can be re-detected while the other outputs the synchronization timing signal. As a result, the synchronization timing signal can be continuously output to the subsequent circuit even while the synchronization signal is being re-detected, and the TV output image can be prevented from being interrupted due to the synchronization signal re-detection. Can do.

  In addition, when the synchronization timing signal output as a result of the re-detection of the synchronization signal is different from the one selected as the signal indicating the timing of waveform equalization of the received signal, the synchronization timing signal is updated. As a result of the re-detection of the synchronization signal, a signal having the same synchronization error is not selected and a correct synchronization position can be detected.

  Preferably, the digital demodulator includes a second synchronization detection unit that detects a synchronization signal included in the received signal. When determining that the synchronization timing signal is a synchronization error, the control unit generates a signal indicating a new synchronization position and sends the signal to the synchronization detection unit and the second synchronization detection unit. The second synchronization detection unit redetects the synchronization signal so as to detect the synchronization signal at the new synchronization position based on the signal from the control unit, and outputs a signal indicating the success or failure of the redetection. It is generated and sent to the synchronization detector. Furthermore, when the signal from the second synchronization detection unit indicates that the synchronization signal has been successfully re-detected, the synchronization detection unit detects the synchronization signal at the new synchronization position based on the signal from the control unit. It is assumed that the synchronization signal is redetected so as to detect.

  According to the present invention, when the control unit determines that the synchronization timing signal output from the synchronization detection unit is a synchronization error, a signal indicating a new synchronization position is generated. Is this new synchronization position correct? Only after it is determined whether or not, the synchronization detection unit can re-detect the synchronization signal. Whether or not the new synchronization position is correct can be determined by the success or failure of the re-detection of the synchronization signal by the second synchronization detector. In other words, the synchronization detection unit assumes that the new synchronization position indicated by the control unit is correct when re-detection of the synchronization signal in the second synchronization detection unit is successful, and based on the signal indicating the new synchronization position. The correct synchronization position can be detected by re-detecting the synchronization signal.

  In addition, while the second synchronization detection unit performs redetection of the synchronization signal, the synchronization timing signal from the synchronization detection unit is continuously output to the subsequent circuit, and the output image of the TV accompanying the redetection of the synchronization signal is output. Interruption can be prevented.

  Next, the means taken by the present invention uses, as a synchronization detection method, a synchronization detection step for detecting a synchronization signal included in the received signal and generating a synchronization timing signal indicating the timing of the synchronization signal, and a transversal filter. A tap coefficient reading step of performing waveform equalization of the received signal by updating the coefficient of the tap of the transversal filter with the timing of the synchronization timing signal as the position of the center tap and reading the coefficient of at least one of the taps And a synchronization error determination step of determining whether or not a synchronization error has occurred in the synchronization detection step based on the tap coefficient read by the tap coefficient reading step.

  According to the present invention, the synchronization error determination step determines whether or not a synchronization error has occurred in the synchronization detection step based on the tap coefficient of the transversal filter. Therefore, it is possible to know whether or not the synchronization detection is wrong, and it is possible to take measures for detecting the correct synchronization position.

  Preferably, the synchronization detection method includes a synchronization position correction step for performing re-detection of the synchronization signal when the synchronization error determination step determines that a synchronization error has occurred in the synchronization detection step. To do.

  According to the present invention, when it is determined that a synchronization error has occurred in the synchronization detection step, the synchronization signal can be re-detected. By re-detecting the synchronization signal, it can be expected that a new synchronization signal is detected and a correct synchronization position is detected.

  As described above, according to the present invention, it is possible to determine whether or not a synchronization error has occurred in a digital demodulator that detects synchronization of a received signal such as a DTV signal. Furthermore, when it is determined that a synchronization error has occurred, the synchronization signal can be re-detected to correct the synchronization error. Further, when the synchronization signal is re-detected, it is possible to determine where the correct synchronization position is, and to correct the synchronization error based on the difference between the synchronization position and the correct synchronization position when the synchronization error occurs. As a result, it is possible to reliably detect a correct synchronization signal by re-detecting the synchronization signal, and to reduce the time required for re-detection of the synchronization signal.

  Furthermore, even if it is determined that a synchronization error has occurred, the synchronization signal is not re-detected unless a malfunction occurs in the TV output image, and the output image is not interrupted due to the re-detection of the synchronization signal. Can do.

  Embodiments of the digital demodulator according to the present invention will be described below with reference to the drawings.

(First embodiment)
FIG. 1 shows the configuration of a digital demodulator according to the first embodiment of the present invention. The digital demodulator according to this embodiment includes a synchronization detection unit 1, a waveform equalization unit 2, an error correction unit 3, and a control unit 4.

  The synchronization detector 1 receives the reception signal DT1, detects the synchronization signal included in the reception signal DT1, and outputs a synchronization timing signal DT2 indicating the timing of the synchronization signal. As a synchronization detection method in the synchronization detector 1, for example, there is a method used in an 8-value VSB (Vestigial Side Band) modulation method adopted in the United States.

  Hereinafter, synchronization detection by the 8-level VSB modulation method will be described with reference to the drawings.

  FIG. 2 shows a frame format configuration in the 8-level VSB modulation method. The format of the 8-level VSB modulation method includes an area including a segment synchronization signal 201, an area including a field synchronization signal 202, and a data signal randomized with a pseudo random signal in a modulation process at the time of transmission of a digital signal such as a video signal or audio. And a region including 203.

  FIG. 3 shows a segment structure in the 8-level VSB modulation method. The segment is composed of 832 symbols including a region including the segment synchronization signal 301 and a region including the data signal or the field synchronization signal 302. The numbers “+7”, “+5”, “+3”, “+1”, “−1”, “-3”, “-5”, “-7” shown on the left of the figure are 8 values. There are eight possible values that a symbol can take in the VSB modulation system.

  FIG. 4 shows a symbol configuration of the segment synchronization signal 301. The segment synchronization signal 301 is composed of four consecutive symbols at the beginning of the segment (symbols mapped with “+5”, “−5”, “−5”, and “+5” in order from the front).

  The value taken by the symbol changes as the received signal DT1 is distorted. In particular, at the time of multipath interference, the distortion of the received signal DT1 increases as the delay wave amplitude increases. Therefore, in order to correctly recognize the segment synchronization signal 301 whose symbol value has changed, the first threshold value 401 and the second threshold value 402 are set to determine whether or not the segment synchronization signal is a segment synchronization signal. Specifically, if the symbol value is equal to or greater than the first threshold value 401, it is determined as “+5”, and if it is equal to or less than the second threshold value 402, it is determined as “−5”. As a result, when a symbol pattern arranged in the order of “+5”, “−5”, “−5”, and “+5” is confirmed in the received signal DT1, a signal including the symbol pattern is converted into the segment synchronization signal 301. As captured.

  Next, the internal configuration and operation of the synchronization detection unit 1 will be described in detail with reference to the drawings.

  FIG. 5 shows an internal configuration of the synchronization detection unit 1. The synchronization detection unit 1 includes a synchronization acquisition circuit 11, a period counter 12, a backward protection circuit 13, a forward protection circuit 14, an SR flip-flop 15, and an AND gate 16.

  The synchronization acquisition circuit 11 acquires a segment synchronization signal (hereinafter referred to as synchronization signal) from the input reception signal DT1, and outputs the synchronization acquisition signal DT11 at the timing of the acquired synchronization signal.

  When receiving the synchronization acquisition signal DT11, the period counter 12 outputs a period timing signal DT12 for each period of one segment.

  The rear protection circuit 13 counts the number of times that the output timings of the synchronization acquisition signal DT11 and the cycle timing signal DT12 are continuously matched. If the synchronization acquisition circuit 11 has acquired the correct synchronization signal, the synchronization signal in the reception signal DT1 can be acquired for each segment period, so that the output timing of the synchronization acquisition signal DT11 and the period timing signal DT12 is continuous. And match. Then, if the number of consecutive matches is equal to or greater than the given number of rear protection stages, the rear protection circuit 13 outputs the rear determination signal DT13, assuming that the correct segment signal is captured.

  The SR flip-flop 15 is set by inputting the backward determination signal DT13, and outputs the synchronization detection signal DT15. Then, the AND gate 16 outputs a synchronization timing signal DT2 as a logical product of the synchronization detection signal DT15 and the cycle timing signal DT12.

  FIG. 6 shows an example of capturing the synchronization signal included in the reception signal DT1. In the figure, reference numeral 601 denotes a desired wave synchronization signal having a symbol pattern equal to the synchronization signal in the 8-level VSB modulation method. In the figure, reference numeral 602 denotes a signal that is similar to a synchronization signal in a delayed wave or a data signal, and is recognized as a synchronization signal using the first and second threshold values.

  In the figure, a synchronization acquisition pattern 603 indicates a case where acquisition of a continuous synchronization signal is successful. For example, when the number of rear protection stages is 3, in the case of the pattern 603, synchronization detection is successful and the synchronization timing signal DT2 is output.

  On the other hand, the synchronization acquisition pattern 604 in the figure shows a case where the synchronization signal cannot be captured continuously. Since the signal 602 is not a correct synchronization signal, it does not appear every segment period, and the synchronization acquisition fails for the second time. Therefore, the synchronization of the reception signal DT1 is not detected, and the synchronization timing signal DT2 is not output.

  Next, the forward protection circuit 14 counts the number of times that the output timings of the synchronization acquisition signal DT11 and the cycle timing signal DT12 are not consistent. If the synchronization acquisition circuit 11 has made a synchronization error, it is unlikely that a synchronization signal will appear for each segment period. Therefore, when the number of consecutive mismatches exceeds the given number of forward protection stages, it is determined that an erroneous synchronization signal has been captured, and the front protection circuit 14 outputs a forward determination signal DT14.

  The SR flip-flop 15 is reset by inputting the forward determination signal DT14 and does not output the synchronization detection signal DT15. As a result, the synchronization detection signal DT15 is not input to the AND gate 16, and the synchronization timing signal DT2 is not output.

  As described above, the synchronization detection unit 1 captures a correct synchronization signal and performs synchronization detection. However, in the case of the received signal as shown in FIG. 20, the synchronization detection unit 101 in the conventional digital demodulator shown in FIG. 21 continues to detect the synchronization of the delayed DTV signal when first synchronized with the delayed wave. Therefore, it is impossible to know whether or not there is a synchronization error.

  Therefore, the synchronization detection unit 1 detects the synchronization signal included in the reception signal DT1 by using the control signal DT5 from the control unit 4 as a reset input of the SR flip-flop 15.

  Next, the internal configuration and operation of the waveform equalization unit 2 will be described in detail with reference to the drawings.

  FIG. 7 shows the internal configuration of the waveform equalization unit 2. The waveform equalization unit 2 includes a transversal filter 21 and a tap coefficient calculation unit 22, and uses the timing of the synchronization timing signal DT2 as a zero-delay reference position (this reference position is the center tap position). The tap coefficient of the filter 21 is updated, and the waveform of the received signal DT1 is equalized.

  The transversal filter 21 performs a product-sum operation on the tap coefficient and the received signal DT1, and outputs a waveform-equalized signal DT3. This tap coefficient is calculated by the tap coefficient calculator 22.

  When the synchronization detection of the synchronization detection unit 1 is correct, “+5”, “−5”, “−5”, “+5” is added to the reception signal DT1 at the timing of the synchronization timing signal DT2 input to the tap coefficient calculation unit 22. The symbol pattern synchronization signal appears. Therefore, the tap coefficient calculation unit 22 calculates the tap coefficient so that the symbol pattern of the reception signal DT1 at the reference position with zero delay approaches “+5”, “−5”, “−5”, and “+5”. To do. By using the tap coefficient calculated in this way, the distortion of the reception signal DT1 can be reduced, that is, the waveform can be equalized.

  Next, calculation of the tap coefficient will be described with reference to the drawings.

  FIG. 8 is an example of tap coefficient calculation when the synchronization detection in the synchronization detection unit 1 is correct. In the figure, (a) is a received signal DT1 input to the transversal filter 21, (b) is a tap coefficient, and (c) is an output signal DT3 of the transversal filter 21.

  The received signal DT1 is composed of a desired wave with a delay of zero and a delayed wave having a delay of 1/3 times the amplitude of the desired wave with a delay of 1 μs ((a) in the figure). At this time, the tap coefficient calculation unit 22 sets the center tap coefficient to 1 time and the tap coefficient with a delay of 1 μs to −1/3 times ((b) in the figure). Then, as the output signal DT3, a signal obtained by combining the desired wave with zero delay and the delayed wave of 1/9 times the desired wave with a delay of 2 [mu] s is obtained ((c) in the figure). That is, the waveform equalization is performed, and the distortion existing in the delay 1 μs of the reception signal DT1 is reduced.

  On the other hand, FIG. 9 is an example of tap coefficient calculation when the synchronization detection unit 1 has a synchronization error. In the figure, (a) is a received signal DT1 input to the transversal filter 21, (b) is a tap coefficient, and (c) is an output signal DT3 of the transversal filter 21.

  The received signal DT1 is composed of a desired wave with a delay of −1 μs and a delayed wave with an amplitude of 1/3 times that of the desired wave with a delay of zero ((a) in the figure). The reason why the desired wave appears in the delay of −1 μs is that the synchronization detection unit 1 has made a synchronization error and is synchronized with the synchronization signal of the delayed wave delayed by 1 μs from the desired wave. In this case, the tap coefficient calculation unit 22 calculates the tap coefficient so that the synchronization signal appears at the zero-delay position indicated by the synchronization timing signal DT2 in the output signal DT3. For example, the tap coefficient with a delay of 1 μs is multiplied by 1, The tap coefficient with a delay of 2 μs is set to −1/3 times ((b) in the figure). Then, as the output signal DT3, a signal obtained by combining the desired wave with zero delay and the delayed wave of 1/9 times the desired wave with a delay of 2 [mu] s is obtained ((c) in the figure).

  In the example of FIG. 9, in the signal DT3, the tap coefficient is calculated so that the synchronization timing signal of the desired wave appears at the zero-delay position indicated by the synchronization timing signal DT2. It does not always converge to a correct value. Even if the signal converges, another distortion occurs in the output signal DT3 at the stage of the product-sum operation in the transversal filter 21. This occurs when the waveform equalizing unit 2 tries to remove the desired wave in the reception signal DT1 as noise based on the synchronization timing signal DT2 of the synchronization error. Originally, the desired wave has larger energy than the delayed wave, and it is difficult to completely remove the desired wave.

  Next, the error correction unit 3 corrects the code error of the signal DT3 waveform-equalized by the waveform equalization unit 2. Then, the signal DT4 after error correction is output to the subsequent circuit. Here, as the error correction unit 3, for example, a trellis decoder that performs trellis decoding is used.

  The control unit 4 determines whether or not the synchronization detection unit 1 has made a synchronization error, and when determining that it has made a synchronization error, a control signal for instructing the synchronization detection unit 1 to re-detect the synchronization signal DT5 is output. For this determination, the center tap coefficient DT6 is input from the waveform equalization unit 2 and compared with the center tap coefficient threshold value DT7 given from the outside. Further, in order to determine whether or not to output the control signal DT5, an error rate DT8 indicating how much code error has occurred in the code error correction processing is input from the error correction unit 3 and externally input. A comparison is made with the given error rate threshold DT9. The threshold values DT7 and DT9 are not given from the outside, but may be preset in the control unit 4.

  The operation of the digital demodulator according to the present embodiment configured as described above will be described with reference to the flowchart of FIG.

  First, in step S101 (synchronization detection step), the synchronization detection unit 1 detects a synchronization signal included in the received signal DT1. When the synchronization signal is successfully detected, the synchronization detection unit 1 outputs the synchronization timing signal DT2.

  In the subsequent step S102 (tap coefficient reading step), the center tap coefficient DT6 is read from the waveform equalizing unit 2 to the control unit 4. At this time, a waiting time of about 200 ms is provided after the synchronization signal is detected by the synchronization detection unit 1 until the tap coefficient in the waveform equalization unit 2 converges.

  In the subsequent step S103 (synchronization error determination step), it is determined whether or not the synchronization detection unit 1 has a synchronization error. Specifically, the control unit 4 compares the center tap coefficient DT6 with the center tap coefficient threshold value DT7, and when DT6 <DT7 (or DT6 ≦ DT7), the synchronization detection unit 1 has a synchronization error. Judge. If the synchronization detection unit 1 determines that a synchronization error has occurred, the process proceeds to step S104. On the other hand, if it is determined that the synchronization detection is correct, the process ends.

  Here, the center tap coefficient threshold value DT7 is preferably set to 0.7 times. This is because the center tap coefficient when the synchronization detection unit 1 makes a synchronization error is often smaller than 0.7 times.

  Next, in step S104 (error count step), the error correction unit 3 counts the degree of error when the code error correction of the waveform equalized signal DT3 is performed, and outputs it to the control unit 4 as an error rate DT8. Is done. At this time, the degree of error is counted after about 200 ms after the synchronization signal is detected by the synchronization detector 1. This is because the tap coefficients in the waveform equalizing unit 2 converge and the waveform equalized signal DT3 is output, and then the degree of error starts to be counted.

  Then, the control unit 4 compares the error rate DT8 and the error rate threshold value DT9. When DT8> DT9 (or DT8 ≧ DT9), the process proceeds to step S105. On the other hand, when DT8 ≦ DT9 (or DT8 <DT9), the process returns to step S104, and whether or not the error rate DT8 exceeds the error rate threshold DT9 (or whether or not the error rate threshold DT9 or more) is always set. Be monitored.

Here, the error rate threshold DT9 is preferably set to 5.0 × 10 ⁻² . This is because, when a DTV signal based on the 8-level VSB modulation system is subjected to multipath interference, generally, if the bit error rate (error rate) is 5.0 × 10 ⁻² or more during trellis decoding, the output video of the TV is blocked. This is because problems such as noise occur. In other words, even if a code error occurs in the signal DT3 waveform-equalized due to the synchronization error of the synchronization detector 1, as long as the error is corrected by the error corrector 3 and a normal output video is obtained. The synchronization signal is not re-detected. Thereby, it is possible to prevent the video output from being interrupted due to the re-detection of the synchronization signal.

  Next, in step S105 (synchronization position correction step), the control unit 4 outputs a control signal DT5 instructing the synchronization detection unit 1 to re-detect the synchronization signal. Accordingly, the process returns to step S101, and the synchronization detection unit 1 performs redetection of the synchronization signal. In many cases, the synchronization signal can be captured and the synchronization position can be corrected by redetecting the synchronization signal.

  As described above, according to the present embodiment, based on the center tap coefficient of the waveform equalization unit 2, it can be determined whether or not the synchronization detection unit 1 has made a synchronization error. Further, when it is determined that a synchronization error has occurred, the synchronization detection unit 1 can detect the synchronization signal again by detecting the synchronization signal again.

  Further, when the synchronization detection unit 1 makes a synchronization error but there is no malfunction in the output video of the TV, the synchronization detection unit 1 does not unnecessarily re-detect the synchronization signal, and the TV output The video can be kept from being interrupted frequently.

  Although the waiting time of about 200 ms is provided as the convergence time of the tap coefficient in the waveform equalization unit 2, the waiting time is not limited to this, and the optimum waiting time varies depending on the configuration of the waveform equalization unit 2. obtain. Although the error correction unit 3 uses a trellis decoder, any error correction unit may be used, for example, a Reed-Solomon decoder that performs error correction of Reed-Solomon encoded data. It may be. Further, the optimum value of the error rate threshold value DT9 may change depending on the decoder used for the error correction unit 3.

(Second Embodiment)
The digital demodulator according to the second embodiment of the present invention has the configuration shown in FIG. 1 as in the first embodiment. However, the digital demodulator according to the present embodiment includes a synchronization detection unit 1A and a control unit 4A having configurations different from those of the first embodiment. In this embodiment as well, the received signal DT1 is assumed to be based on 8-level VSB modulation.

  The synchronization detector 1A receives the reception signal DT1, detects a synchronization signal included in the reception signal DT1, and outputs a synchronization timing signal DT2. Further, it has a function of detecting a new synchronization signal at a new synchronization position indicated by the control signal DT5A when the synchronization signal is re-detected.

  FIG. 11 shows the internal configuration of the synchronization detector 1A. The synchronization detection unit 1A has substantially the same configuration as the synchronization detection unit 1 according to the first embodiment, but differs in that the control signal DT5A is input to the period counter 12.

  The period counter 12 receives the control signal DT5A and outputs the period timing signal DT12 with a shift by an amount indicated by the control signal DT5A. Then, the synchronization acquisition circuit 11 captures a new synchronization signal included in the reception signal DT1 so as to match the output timing of the periodic timing signal DT12. As a result, the synchronization timing signal DT2 synchronized with the new synchronization position indicated by the control signal DT5A is output.

  Next, the control unit 4A inputs from the waveform equalizing unit 2 the coefficients DT6A of the center tap and taps in the vicinity thereof, for example, the five taps before and after the center tap. Then, in the same manner as the control unit 4 according to the first embodiment, it is determined whether or not the synchronization detection unit 1A has made a synchronization error. Judgment is also made where. Then, the deviation between the zero-delay reference position indicated by the synchronization timing signal DT2 of the synchronization detection unit 1A and the position determined to be the correct synchronization position is estimated, and control indicating a new synchronization position based on this deviation. A signal DT5A is generated and output to the synchronization detector 1A.

  Next, determination of the correct synchronization position and calculation of deviation from the correct synchronization position by the control unit 4A will be described.

  As described with reference to FIG. 9, when the synchronization detection unit 1 </ b> A makes a synchronization error, the tap coefficient of the tap coefficient does not become the maximum value, but the tap coefficient in the vicinity thereof takes the maximum value. This is because, in the waveform equalization processing in the waveform equalization unit 2, the tap coefficient is calculated so that the synchronization signal of the desired wave having a large energy appears at the position of zero delay indicated by the synchronization timing signal DT2. Therefore, when it is determined that the synchronization detection unit 1A has made a synchronization error, the deviation between the zero-delay position indicated by the synchronization timing signal DT2 and the correct, that is, the synchronization timing position of the desired wave is from the center tap. It is determined that this is the delay amount up to the tap coefficient in the neighborhood (maximum value tap) that takes the maximum value.

  The delay amount can be calculated by multiplying the difference between the center tap and the maximum value tap by the delay time per tap. For example, in the case shown in FIG. 9, since the deviation between the center tap and the maximum value tap is −1 and the delay time per tap is 1 μs, the delay amount is calculated as −1 μs. That is, in the received signal, it can be expected that the synchronization signal of the desired wave exists at the position of delay-1 μs from the current synchronization position.

  The operation of the digital demodulator according to the present embodiment configured as described above will be described below with reference to the flowchart of FIG.

  First, in step S201 (synchronization detection step), the synchronization detection unit 1A detects a synchronization signal included in the reception signal DT1. When the synchronization signal is successfully detected, a synchronization timing signal DT2 is output from the synchronization detector 1A.

  In the subsequent step S202 (tap coefficient reading step), the coefficient DT6A of the center tap and the tap in the vicinity thereof is read from the waveform equalization unit 2 to the control unit 4. At this time, the waiting time until the tap coefficient converges in the waveform equalization unit 2 is as described in the first embodiment.

  In subsequent step S203 (synchronization error determination step), the control unit 4A determines whether or not the synchronization detection unit 1A has a synchronization error. This is as described in the first embodiment.

  In step S204 (synchronization error position determination step), a deviation to the correct synchronization position is estimated by the control unit 4A.

  In the subsequent step S205 (error count step), the degree of error in the error correction unit 3 is counted. This is as described in the first embodiment.

  In subsequent step S206 (synchronization position correction step), control signal DT5A instructing redetection of the synchronization signal is output from control unit 4A to synchronization detection unit 1A. Then, the process returns to step S201, and the synchronization detection unit 1A performs re-detection of the synchronization signal so as to detect a new synchronization signal at a new synchronization position indicated by the control signal DT5A.

  As described above, according to the present embodiment, when the control unit 4A determines that the synchronization detection unit 1A has a synchronization error, the synchronization detection unit 1A detects the synchronization signal at the new synchronization position indicated by the control signal DT5A. Can be detected. Further, in the redetection of the synchronization signal, the synchronization detection time can be shortened by indicating a new synchronization position to the synchronization detection unit 1A.

  The control signal DT5A uses a delay time as a delay amount indicating a new synchronization position. However, the control signal DT5A is not limited thereto, and may be a signal indicating the number of tap shifts, for example.

(Third embodiment)
FIG. 13 shows the configuration of a digital demodulator according to the third embodiment of the present invention. The digital demodulator according to the present embodiment omits the error correction unit 3 from the digital demodulators according to the first and second embodiments, and includes a synchronization detection unit 1B and a control unit 4B having different configurations. In this embodiment as well, the received signal DT1 is assumed to be based on 8-level VSB modulation.

  The synchronization detection unit 1B performs redetection of the synchronization signal by inputting the control signal DT5, but continues to output the synchronization timing signal DT2 having a synchronization error during the redetection of the synchronization signal. As a result, the waveform equalized signal DT3 can be continuously output from the waveform equalizing unit 2, and interruption of the output video of the TV can be prevented.

  When the control unit 4B determines that the synchronization detection unit 1B has a synchronization error, the control unit 4B outputs the control signal DT5 without considering the degree of error.

  The operation of the digital demodulator according to the present embodiment configured as described above will be described with reference to the flowchart of FIG.

  First, in step S301 (synchronization detection step), the synchronization detection unit 1B detects a synchronization signal included in the reception signal DT1. When the synchronization signal is successfully detected, a synchronization timing signal DT2 is output from the synchronization detector 1B.

  In the subsequent step S302 (tap coefficient reading step), the coefficient DT6A of the center tap and the tap in the vicinity thereof is read from the waveform equalization unit 2 to the control unit 4B. At this time, the waiting time until the tap coefficient converges in the waveform equalization unit 2 is as described in the first embodiment.

  In the subsequent step S303 (synchronization error determination step), the control unit 4B determines whether or not the synchronization detection unit 1B has a synchronization error. Specifically, the control unit 4B normalizes the center tap coefficient by converting the tap coefficient in the vicinity of the center tap into a dB value using the center tap coefficient as a reference value, and converts the converted value and the tap coefficient conversion threshold DT7A given from the outside. Compare. When there is a conversion value that is larger than the tap coefficient conversion threshold DT7A, the synchronization detection unit 1B determines that a synchronization error has occurred. If the synchronization detection unit 1B determines that a synchronization error has occurred, the process proceeds to step S304. On the other hand, if the synchronization detection is determined to be correct, the process ends.

  Here, preferably, 0 dB is set as the tap coefficient conversion threshold DT7A. This is because, when the synchronization detection unit 1B has a synchronization error, the tap coefficient corresponding to the position of the synchronization signal of the desired wave takes the maximum value that is equal to or greater than the center tap coefficient among the tap coefficients near the center tap. . Further, the threshold value DT7A is not given from the outside, but may be preset in the control unit 4B.

  Next, in step S304 (synchronization position correction step), a control signal DT5 is output from the control unit 4B to the synchronization detection unit 1B to instruct redetection of the synchronization signal. Then, returning to step S301, the synchronization detection unit 1B performs redetection of the synchronization signal. This is as described in the first embodiment.

  As described above, according to the present embodiment, it is possible to determine whether or not the synchronization detection unit 1B has a synchronization error from the value obtained by normalizing the tap coefficients near the center tap with the center tap coefficient. In addition, since the synchronization detection unit 1B continues to output the synchronization timing signal DT2 while performing the redetection of the synchronization signal, it is possible to prevent the TV output video from being interrupted due to the redetection of the synchronization signal.

  Although the dB value is used as the conversion value of the tap coefficient in the vicinity of the center tap, any conversion is possible as long as the conversion is to a value indicating the relative relationship between the center tap coefficient and the tap coefficient in the vicinity thereof.

  The output of the synchronization timing signal DT2 is continued until the synchronization detection unit 1B outputs a new synchronization timing signal DT2. However, the duration of the synchronization is set, for example, the control signal DT5 is input. It may be continued for a period of about 10 ms.

(Fourth embodiment)
FIG. 15 shows the configuration of a digital demodulator according to the fourth embodiment of the present invention. The digital demodulator according to this embodiment includes first and second synchronization detection units 1a and 1b, a waveform equalization unit 2, and a control unit 4C. Among these, the configurations and operations of the synchronization detection units 1a and 1b and the waveform equalization unit 2 are the same as described in the first embodiment, and thus the description thereof is omitted here. In this embodiment as well, the received signal DT1 is assumed to be based on 8-level VSB modulation.

  The control unit 4C selects one of the synchronization timing signals DT2a and DT2b output from the synchronization detection units 1a and 1b, respectively, that is correctly detected for synchronization, and outputs the selected signal as the synchronization timing signal DT2c. Then, the coefficient DT6A of the center tap and the tap in the vicinity of the center tap is input from the waveform equalization unit 2, and whether or not the synchronization detection unit 1a (or 1b) that is the output source of the synchronization timing signal DT2c has a synchronization error. Judging.

  When it is determined that a synchronization error has occurred, the control signal DT5a (or DT5b) is output to the synchronization detector 1a (or 1b) that is the output source of the synchronization timing signal DT2c. Also, the other synchronization timing signal DT2b (or DT2a) is newly selected as the synchronization timing signal DT2c.

  In order to avoid that the newly selected synchronization timing signal DT2b (or DT2a) has the same synchronization error, the control unit 4C compares the synchronization timing signals DT2a and DT2b before switching the selection. I do. As a result of the comparison, when the synchronization timing signal DT2a has the same timing as the synchronization timing signal DT2b, the synchronization detection unit 1b (or 1a) to be newly selected detects another new synchronization signal. In order to achieve this, the control signal DT5b (or DT5a) is output. Therefore, until it is determined that a synchronization error has occurred and the synchronization detection unit 1b (or 1a) detects a new synchronization timing signal, the synchronization detection unit 1a (or 1b) detects the synchronization error synchronization timing signal DT2a ( Alternatively, DT2b) is continuously output. Thereby, the signal DT3 waveform-equalized by the waveform equalization unit 2 is continuously output, and interruption of the output video of the TV can be prevented.

  The operation of the digital demodulator according to the present embodiment configured as described above will be described with reference to the flowchart of FIG.

  First, in step S401 (first synchronization detection step), the synchronization detection unit 1a (or 1b) detects a synchronization signal included in the reception signal DT1. When the synchronization signal is successfully detected, the synchronization detector 1a (or 1b) outputs the synchronization timing signal DT2a (or DT2b). The synchronization timing signal DT2a (or DT2b) is selected as the synchronization timing signal DT2c by the control unit 4C and output to the waveform equalization unit 2.

  In the subsequent step S402 (tap coefficient reading step), the coefficient DT6A of the center tap and its neighboring taps is read from the waveform equalizing unit 2 to the control unit 4C. At this time, the waiting time until the tap coefficient converges in the waveform equalization unit 2 is as described in the first embodiment.

  In the subsequent step S403 (synchronization error determination step), it is determined whether or not the synchronization detector 1a (or 1b) has a synchronization error. Specifically, the control unit 4C compares the center tap coefficient and the tap coefficient in the vicinity of the center tap, and if there is a tap coefficient in the vicinity of the center tap that is larger than the center tap coefficient, the synchronization detection is performed. It is determined that the unit 1a (or 1b) has a synchronization error. When the synchronization detector 1a (or 1b) determines that a synchronization error has occurred, the control signal DT5b (or DT5a) instructs the synchronization detector 1b (or 1a) to re-detect the synchronization signal from the controller 4C. ) Is output, and the process proceeds to step S404. On the other hand, if it is determined that the synchronization detection is correct, the process ends.

  In step S404 (second synchronization detection step), the synchronization signal is detected again by the synchronization detector 1b (or 1a), and the synchronization timing signal DT2b (or DT2a) is output. When the control unit compares the synchronization timing signals DT2a and DT2b and determines that both are signals indicating the same timing, the control signal DT5b (or DT5a) instructing the re-detection of the synchronization signal is output again. Step S404 is repeated. On the other hand, if it is determined that the synchronization timing signal DT2b (or DT2a) is different in timing from the synchronization timing signal DT2a (or DT2b), the process proceeds to step S405.

  In step S405 (synchronization position correction step), the synchronization timing signal DT2b (or DT2a) is selected as the synchronization timing signal DT2c. Then, returning to step S402, it is determined whether or not the synchronization detector 1b (or 1a) that is the output source of the newly selected synchronization timing signal DT2b (or DT2a) has a synchronization error.

  As described above, according to the present embodiment, it is determined whether or not the synchronization detection unit 1a or 1b has a synchronization error from the magnitude relation between the center tap coefficient and the coefficient of the tap in the vicinity thereof, and the correct synchronization position is detected. Can do.

  Further, by providing the two synchronization detectors 1a and 1b, it is possible to prevent selection of the synchronization timing signals having the same synchronization error by comparing the two synchronization timing signals. Furthermore, while one synchronization detection unit redetects the synchronization signal, the other synchronization detection unit can continue to output the synchronization timing signal, and the output image is not interrupted.

  Since there is no priority order between the two synchronization detectors 1a and 1b, the synchronization timing signal that has succeeded in detecting synchronization first is the synchronization timing signal when the digital demodulator according to the present embodiment starts up. What is necessary is just to make it select as DT2c.

  Further, the control unit 4C determines whether or not the synchronization detection unit 1a or 1b has a synchronization error from the coefficient DT6A of the center tap and its neighboring taps, but it is determined by another method. May be.

(Fifth embodiment)
FIG. 17 shows the configuration of a digital demodulator according to the fifth embodiment of the present invention. The digital demodulator according to this embodiment includes first and second synchronization detection units 1C and 1D, a waveform equalization unit 2, and a control unit 4D. Among these, since the configuration and operation of the waveform equalization unit 2 are as described in the first embodiment, description thereof is omitted here. In this embodiment as well, the received signal DT1 is assumed to be based on 8-level VSB modulation.

  The synchronization detector 1C receives the reception signal DT1, detects the synchronization signal included in the reception signal DT1, and outputs the synchronization timing signal DT2. Furthermore, it has a function of detecting a new synchronization signal at a new synchronization position indicated by the control signal DT5A when re-detecting the synchronization signal. Further, it is determined whether or not the synchronization signal is actually re-detected according to the contents indicated by the control signal DT5B.

  The synchronization detector 1D receives the reception signal DT1, and detects a synchronization signal included in the reception signal DT1. Further, by inputting the control signal DT5A, a new synchronization signal is detected at a new synchronization position indicated by the control signal DT5A. And the information which shows the success or failure of the re-detection of a synchronizing signal is output as control signal DT5B.

  The control unit 4D receives the coefficient DT6A of the center tap and its neighboring taps from the waveform equalization unit 2, determines whether or not the synchronization detection unit 1C has a synchronization error, and determines that a synchronization error has occurred. If so, it is determined where the correct synchronization position is. Then, the deviation between the zero-delay reference position indicated by the synchronization timing signal DT2 and the position determined to be the correct synchronization position is estimated, and a control signal DT5A indicating a new synchronization position is generated based on this deviation. And output to the synchronization detectors 1C and 1D.

  The operation of the digital demodulator according to the present embodiment configured as described above will be described with reference to the flowchart of FIG.

  First, in step S501 (first synchronization detection step), the synchronization detection unit 1C detects a synchronization signal included in the reception signal DT1. When the synchronization signal is successfully detected, a synchronization timing signal DT2 is output from the synchronization detector 1C.

  In the subsequent step S502 (tap coefficient reading step), the waveform equalizing unit 2 loads the center tap coefficient and the tap coefficient DT6A near the center tap into the control unit 4D. At this time, the waiting time until the tap coefficient converges in the waveform equalization unit 2 is as described in the first embodiment.

  In the subsequent step S503 (synchronization error determination step), it is determined whether or not the synchronization detector 1C has a synchronization error. This determination method is as described in the fourth embodiment. If it is determined that the synchronization detection unit 1C has a synchronization error, the process proceeds to step S504. On the other hand, if it is determined that the synchronization detection is correct, the process ends.

  In step S504 (synchronization error position determination step), the control unit 4D estimates the deviation to the correct synchronization position and outputs the control signal DT5A. The estimation of this deviation is as described in the second embodiment.

  In subsequent step S505 (second synchronization detection step), the synchronization detection unit 1D performs re-detection of the synchronization signal so as to detect a new synchronization signal at a new synchronization position indicated by the control signal DT5A. Then, a control signal DT5B indicating whether the synchronization detection unit 1D has successfully detected the synchronization signal again is output.

  In the subsequent step S506 (synchronization position correction step), the synchronization detection unit 1C corrects the synchronization error, and the process returns to step S502. Specifically, the synchronization detection unit 1C detects the synchronization signal at a new synchronization position indicated by the control signal DT5B when the synchronization detection unit 1D indicates that the synchronization signal is successfully detected again by the control signal DT5B. . On the other hand, when the control signal DT5B indicates that the synchronization detection unit 1D has not succeeded in redetecting the synchronization signal, the synchronization detection unit 1C detects the synchronization signal detected in step S501 without performing redetection of the synchronization signal. The synchronization timing signal DT2 is continuously output.

  As described above, according to the present embodiment, whether or not the new synchronization position indicated by the control signal DT5A from the control unit 4D indicates the correct synchronization position indicates whether the synchronization detection unit 1D has succeeded in redetecting the synchronization signal. Can know from. When it is determined that the control signal DT5A is correct, the synchronization detection unit 1C can detect the synchronization signal again based on the control signal DT5A for the first time. As a result, the correct synchronization position can be detected, and the synchronization detection unit 1C can avoid frequent re-detection of the synchronization signal, thereby preventing the output image from being interrupted.

  Note that the control unit 4D determines whether or not the synchronization detection unit 1C has a synchronization error from the coefficient DT6A of the center tap and its neighboring taps. Good. Similarly, the control unit 4D generates the signal DT5A indicating the new synchronization position based on the coefficient DT6A of the center tap and the taps in the vicinity thereof, but may be generated by another method.

  In each of the above embodiments, the received signal DT1 is a DTV signal modulated by the 8-level VSB modulation method, but may be a signal by another modulation method. The effect of the present invention is not limited to the modulation method of the received signal DT1, and any synchronization error may occur in the synchronization detectors 1, 1a, 1b, 1A, 1B, 1C, 1D. ,Obtainable.

It is a block diagram of the digital demodulator according to the first and second embodiments of the present invention. It is a frame structure diagram of an 8-value VSB modulation system. It is a segment structure diagram of an 8-value VSB modulation system. It is a block diagram of the segment signal of an 8-value VSB modulation system. It is an internal block diagram of the synchronous detection part in the digital demodulation apparatus which concerns on the 1st Embodiment of this invention. It is a figure which shows the mode of a detection of a segment synchronizing signal. It is an internal block diagram of a waveform equalization part. It is a figure which shows the mode of a tap coefficient calculation when synchronous detection is correct. It is a figure which shows the mode of the tap coefficient calculation when the synchronization error is made. It is a flowchart of the digital demodulation apparatus which concerns on the 1st Embodiment of this invention. It is an internal block diagram of the synchronous detection part in the digital demodulator which concerns on the 2nd Embodiment of this invention. It is a flowchart of the digital demodulation apparatus which concerns on the 2nd Embodiment of this invention. It is a block diagram of the digital demodulation apparatus which concerns on the 3rd Embodiment of this invention. It is a flowchart of the digital demodulation apparatus which concerns on the 3rd Embodiment of this invention. It is a block diagram of the digital demodulation apparatus which concerns on the 4th Embodiment of this invention. It is a flowchart of the digital demodulation apparatus which concerns on the 4th Embodiment of this invention. It is a block diagram of the digital demodulation apparatus which concerns on the 5th Embodiment of this invention. It is a flowchart of the digital demodulation apparatus which concerns on the 5th Embodiment of this invention. It is the figure which showed the mode of multipath interference. It is the figure which showed the synchronization error at the time of multipath interference. It is a block diagram of the conventional digital demodulator.

Explanation of symbols

1, 1a, 1b, 1A, 1B, 1C, 1D Synchronization detection unit 2 Waveform equalization unit 21 Transversal filter 22 Tap coefficient calculation unit 3 Error correction unit 4, 4A, 4B, 4C, 4D Control unit DT1 Received signal DT2, DT2a, DT2b, DT2c Synchronization timing signal DT3 Waveform equalized signal DT4 Error corrected signal DT5, DT5a, DT5b, DT5A, DT5B Control signal DT6 Center tap coefficient DT6A Center tap coefficient DT7 Center tap coefficient threshold DT7A Center tap coefficient conversion threshold DT8 Error rate (degree of error)
DT9 Error rate threshold 201, 301 Segment synchronization signal (synchronization signal)
S101, S201, S301 Synchronization detection steps S401, S501 First synchronization detection steps S102, S202, S302, S402, S502 Tap coefficient reading steps S103, S203, S303, S403, S503 Synchronization error determination steps S204, S504 Synchronization error position determination Step S104, S205 Error count step S404, S505 Second synchronization detection step S105, S206, S304, S405, S506 Synchronization position correction step

Claims (6)

A synchronization detection unit that detects a synchronization signal included in the received signal and outputs a synchronization timing signal indicating the timing of the synchronization signal;
A waveform equalization unit that has a transversal filter, sets the timing of the synchronization timing signal as a center tap position, and updates the coefficient of the tap of the transversal filter to equalize the waveform of the received signal;
A digital demodulator comprising: a control unit that inputs at least one coefficient of the tap and determines whether or not the synchronization detection unit has a synchronization error based on the tap coefficient. The digital demodulator according to claim 1, wherein
When the control unit determines that the synchronization detection unit has a synchronization error, the control unit instructs the synchronization detection unit to re-detect a synchronization signal;
The digital demodulator according to claim 1, wherein the synchronization detection unit redetects a synchronization signal in response to an instruction from the control unit. The digital demodulator according to claim 1, wherein
A second synchronization detector that detects a synchronization signal included in the received signal and outputs a synchronization timing signal indicating a timing of the synchronization signal;
The synchronization detection unit and the second synchronization detection unit each perform redetection of a synchronization signal in response to an instruction from the control unit,
The control unit selects a synchronization timing signal output from one of the synchronization detection unit and the second synchronization detection unit as a signal indicating timing for the waveform equalization, and the selected signal is When it is determined that a synchronization error has occurred, the synchronization detection unit or the second synchronization detection unit that instructs the other of the synchronization detection unit and the second synchronization detection unit to re-detect the synchronization signal and instructs the re-detection of the synchronization signal. When the synchronization timing signal output from the synchronization detector is different in timing from the selected signal, this synchronization timing signal is newly selected as a signal indicating the timing for waveform equalization. A digital demodulator characterized by the above. The digital demodulator according to claim 1, wherein
A second synchronization detector for detecting a synchronization signal included in the received signal;
When the control unit determines that the synchronization timing signal is a synchronization error, the control unit generates a signal indicating a new synchronization position, and sends the signal to the synchronization detection unit and the second synchronization detection unit,
The second synchronization detection unit redetects the synchronization signal so as to detect the synchronization signal at the new synchronization position based on the signal from the control unit, and generates a signal indicating the success or failure of the re-detection. And sent to the synchronization detection unit,
When the signal from the second synchronization detection unit indicates that the synchronization signal has been successfully re-detected, the synchronization detection unit sends a synchronization signal to the new synchronization position based on the signal from the control unit. A digital demodulator for redetecting a sync signal so as to detect it. A synchronization detection step of detecting a synchronization signal included in the received signal and generating a synchronization timing signal indicating a timing of the synchronization signal;
Using a transversal filter, the timing of the synchronization timing signal is set as the center tap position, and the waveform of the received signal is equalized by updating the coefficient of the tap of the transversal filter, and at least one coefficient of the tap is determined. A tap coefficient reading step to be read;
A synchronization detection method comprising: a synchronization error determination step of determining whether or not a synchronization error has occurred in the synchronization detection step based on the tap coefficient read in the tap coefficient reading step. The synchronization detection method according to claim 5, wherein
A synchronization detection method comprising: a synchronization position correction step for redetecting a synchronization signal when it is determined by the synchronization error determination step that a synchronization error has occurred in the synchronization detection step.

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