JP2005333301A - Device and method of reception, and program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent or minimize data errors due to replacement of a main wave with a delayed wave. <P>SOLUTION: A correlation means 1002 delays an input by one symbol each through a shift register, performs convolutional operation between the input and a reference symbol sequence, and outputs correlation values as operation results one after another. A maximum value position detection means 1003 detects the position of a maximum correlation value. A reliability measuring means 1004 judges that a synchronizing symbol position changes when a synchronization position is different from a current synchronization position and the same maximum value position is obtained successively for specified fields while synchronism is established, and then outputs synchronizing pulses according to the new synchronization position and also generates synchronization position shift information. A reset signal generating means 22 generates a reset signal just before a field where the timing of the synchronizing pulses is changed according to the synchronization position shift information and outputs the reset signal to a waveform equalization part. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a reception technique for dealing with switching of a main wave and a delayed wave through a multipath transmission line.

  In the terrestrial digital broadcasting in the United States, there is a problem that data error occurs or reception performance deteriorates when the main wave and the delayed wave are switched by the multipath transmission line.

  As a conventional receiving apparatus, a receiving apparatus including a synchronization detection circuit disclosed in the following patent document can be cited.

  FIG. 11 is a diagram illustrating a functional configuration of the synchronization detection circuit disclosed in the patent document.

  The synchronization detection circuit 1001 includes correlation means 1002, maximum value position detection means 1003, and reliability measurement means 1004.

Correlation means 1002 obtains a cross-correlation between an input signal that is a received signal and a known synchronization signal on the receiving side. Maximum value position detection means 1003 detects the position where the maximum value is obtained in the sequence of correlation values obtained as a result, and reliability measurement means 1004 synchronizes the position of the maximum value detected by maximum value position detection means 1003 with the correct value. In order to determine whether it is the position of the signal, its reliability is measured and, for example, a synchronization pulse signal indicating the synchronization position is output.
US Pat. No. 6,504,578

  As a receiving apparatus including the synchronization detection circuit 1001, FIGS. 12 and 13 are typical examples. 12 performs synchronization detection using a pre-equalization signal preceding the waveform equalization unit 1011, and FIG. 13 performs synchronization detection using the post-equalization signal output from the waveform equalization unit 1011. It is.

  FIG. 14 shows the configuration of the waveform equalization unit 1011. The waveform equalization unit 1011 is generally composed of an FIR filter 1012, an IIR filter 1013, and a delay adjustment unit 1014. The FIR filter 1012 and the IIR filter 1013 include a coefficient generation unit 1015, a delay unit 1016, a multiplier 1017, and an adder 1018.

  The delay adjustment unit 1014 delays and outputs the synchronization pulse by the same number as the number of delays of the data output as the equalized signal, that is, the number of delays until the center tap.

  Hereinafter, the overall operation of the waveform equalization unit 1011 will be described.

  FIG. 15A shows how the main wave and the delayed wave are switched in the multipath transmission path. The power of the main wave (D) and the delay wave (U) is almost the same in a severe transmission path environment, and the original delay wave (D ′) exceeds the power of the original main wave (U ′) over time. There is. FIG. 15A shows a case where a delayed wave (U) exists after two symbols of the main wave (D) as an example.

FIG. 15B shows changes in tap coefficients of the waveform equalization unit 1011. Before the switching of the main wave and the delayed wave, when the tap N in FIG. 14 is the center tap, ideally the coefficient of the tap N = 1
Coefficient of tap N + 2 = −α
Thus, the delayed wave (U) is removed.

When the switching speed of the main wave and the delayed wave is high, the waveform equalizing unit 1011 cannot follow, and returns to the initial state at the moment when the switching occurs, and then the original main wave (U ′) is changed. Remove. That is, ideally, the coefficient of tap N−2 = −β
Coefficient of tap N = 1
Thus, the original main wave (U ′) is removed.

  FIG. 15C shows a data delay relationship in the waveform equalization unit 1011. Before the main wave and the delayed wave are switched, the output of the waveform equalizing unit 1011 is an output obtained by delaying the main wave (D) by the center tap, that is, N symbols. On the other hand, after switching between the main wave and the delayed wave, the output of the waveform equalizing unit 1011 is an output obtained by delaying the original delayed wave (D ') by the center tap, that is, N symbols. The original delayed wave (D ′) is a signal received with a delay of 2 symbols due to multipath, and the output after the occurrence of the change is delayed by 2 symbols before the occurrence of the change, so the period of one field changes. As a result, the error correction unit in the subsequent stage cannot correct the error correctly.

  The above is a case where the waveform equalization unit 1011 after the occurrence of switching between the main wave and the delayed wave is operating ideally although there is a delay in the output data. If the operation is not ideal, the waveform equalization unit 1011 may fall into the wrong stable point due to the occurrence of switching, and the reception performance is deteriorated without leaving the state.

  In the configuration of FIG. 12, the synchronization detection circuit 1001 uses the equalized signal, and in the case of the above example, the synchronization pulse is also output with a delay of 2 symbols. It is impossible to prevent the period from changing, and when the waveform equalizing unit 1011 falls into the wrong stable point, no measures are taken to get out of that state.

  In the configuration of FIG. 13, since the synchronization detection circuit 1001 uses the pre-equalization signal, a change in the delay of the output data of the waveform equalization unit 1011 cannot be detected. Further, since both the synchronization detection circuit 1001 and the waveform equalization unit 1011 use a signal including transmission path distortion, the synchronization pulse signal generated by the synchronization detection circuit 1001 in a severe multipath environment in which the main wave and the delayed wave are switched. And the center tap position of the waveform equalization unit 1011 do not coincide with each other, and the error correction unit at the subsequent stage cannot correct the error correctly.

  The present invention has been made to solve the above-described problems, and provides a receiving apparatus, a receiving method, and a program that prevent or minimize data errors due to switching of a main wave and a delayed wave through a multipath transmission line. For the purpose.

  In order to achieve the above object, a receiving apparatus according to the present invention includes a synchronization detection circuit that generates and outputs a reset signal when a change in the synchronization timing period is detected, a waveform that equalizes transmission path distortion, and the like. And a coefficient in the waveform equalization circuit is reset by the reset signal.

  Further, the reception method that achieves the above object is a reception method used in a reception device that receives a signal, and the reception device detects a synchronization timing of a reception signal and detects a change in a synchronization timing period. Includes a synchronization detection step for generating a reset signal and a waveform equalization step for equalizing transmission path distortion, and the coefficient in the waveform equalization circuit is reset by the reset signal.

  A program that achieves the above-described object is a program that performs a synchronization detection process used in a synchronization detection circuit that performs synchronization timing detection. The reception process detects a synchronization timing of a received signal, and performs a synchronization timing cycle. Including a synchronization detection step for generating a reset signal when a change is detected, and a waveform equalization step for equalizing transmission path distortion, and resetting coefficients in the waveform equalization circuit by the reset signal It is characterized by.

  According to the configuration of the receiver of claim 1, which achieves the above object, a synchronization detection circuit that detects synchronization timing of a received signal and generates and outputs a reset signal when a change in synchronization timing period is detected; A waveform equalization circuit for equalizing the transmission path distortion is included, and the coefficient in the waveform equalization circuit is reset by the reset signal. As a result, in a situation where the main wave and the delayed wave are switched, the waveform equalization circuit can escape from the wrong stable point.

  According to the configuration of the receiving apparatus of claim 2, which achieves the above object, synchronization timing detection is performed using a signal before the channel distortion is waveform-equalized, and synchronization is detected when a change in the synchronization timing period is detected. A synchronization detection circuit that generates and outputs a position shift amount τ, and a waveform equalization circuit that equalizes transmission path distortion, and the waveform equalization circuit uses the synchronization position shift amount τ to generate a coefficient. Recalculate. As a result, in the situation where the main wave and the delay wave are switched, the coefficient of the waveform equalization circuit can be changed to one corresponding to the switch of the main wave and the delay wave, and the waveform equalization operation suitable for the synchronization timing detection result can be performed. It can be carried out.

  According to the configuration of the receiving device of claim 3, which achieves the above object, in claim 1, further comprising an error correction circuit for performing error correction of data, and at least a part of the error correction circuit by the reset signal. Reset the process. As a result, it is possible to prevent the error correction circuit from malfunctioning when the main wave and the delayed wave are switched.

  According to the configuration of the receiving device of claim 4, which achieves the above object, in claim 1 or 3, the synchronization detection circuit includes synchronization timing detection means for detecting the synchronization timing of the received signal, and changes in the synchronization timing period. Reset signal generating means for generating and outputting a reset signal when detected. As a result, in a situation where the main wave and the delayed wave are switched, the waveform equalization circuit can escape from the wrong stable point.

  According to the configuration of the receiving device of claim 5, which achieves the above object, in claim 1, 3 or 4, the synchronization detection circuit further outputs the reset signal as invalid when the synchronization timing position changes. As a result, the influence time due to the change in the synchronization timing position can be shortened, and the normal operation can be performed from the beginning of the next cycle when the synchronization timing position has changed.

  According to the configuration of the receiving apparatus of claim 6, which achieves the above object, in claim 2, the synchronization detection circuit detects synchronization timing detection means for detecting the synchronization timing of the received signal, and detects a change in the synchronization timing period. In this case, a synchronization position shift amount generating means for generating and outputting the synchronization position shift amount τ is provided. As a result, in the situation where the main wave and the delay wave are switched, the coefficient of the waveform equalization circuit can be changed to one corresponding to the switch of the main wave and the delay wave, and the waveform equalization operation suitable for the synchronization timing detection result can be performed. It can be carried out.

According to the configuration of the reception device of claim 7 that achieves the above object, in claim 2 or 6, the waveform equalization circuit sets the coefficient C _i of the tap number _i to C _i = A _i exp (jθ _i ).
When the tap number N is the center tap and k is an integer, and the synchronization position shift amount τ is not 0,
C _{N−τ + k} = C _N−k ^* exp {−j (θ _{N + τ} + π)}
Accordingly, the coefficient recalculation unit is configured to perform coefficient recalculation of the FIR filter when the synchronization timing position changes. As a result, in the situation where the main wave and the delay wave are switched, the coefficient of the waveform equalization circuit can be changed to one corresponding to the switch of the main wave and the delay wave, and the waveform equalization operation suitable for the synchronization timing detection result can be performed. It can be carried out.

According to the configuration of the receiving apparatus of claim 8 that achieves the above object, in claim 2 or 6, the waveform equalization circuit sets the coefficient C _i of the tap number _i to C _i = A _i exp (jθ _i ).
When the tap number N is the center tap and k is an integer, and the synchronization position shift amount τ is not 0,
C _{N−τ + k} = C _N−k ^*
Thus, the coefficient recalculation means for recalculating the coefficient of the FIR filter when the synchronization timing position changes and the phase rotation means for performing the phase rotation of exp {−j (θN + τ + π)} are included. As a result, in the situation where the switching of the main wave and the delayed wave occurs, the coefficient of the waveform equalization circuit can be changed to one corresponding to the switching of the main wave and the delayed wave with a small circuit scale, and the waveform suitable for the synchronization timing detection result An equalization operation can be performed.

  According to the configuration of the receiving device of claim 9 that achieves the above object, the coefficient in the IIR filter is reset when the synchronization position shift amount τ is not 0 in claim 7 or 8. As a result, in the situation where the main wave and the delayed wave are switched, the IIR filter can also start the operation from the initial state, and the waveform equalization circuit coefficient corresponds more precisely by the switching of the main wave and the delayed wave. The waveform equalization operation suitable for the synchronization timing detection result can be performed.

  According to the configuration of the receiving device of claim 10, which achieves the above object, in any one of claims 7 to 9, the synchronization detection circuit outputs a synchronization pulse indicating a synchronization timing position, and the waveform equalization The circuit further normally outputs the synchronization pulse by delaying the synchronization pulse by a predetermined amount, and outputs the synchronization pulse by changing the delay amount of the synchronization pulse by −τ when the synchronization position shift amount τ is not zero. The delay adjusting means is configured. As a result, in the situation where the main wave and the delay wave are switched, the coefficient of the waveform equalization circuit can be changed to one corresponding to the switch of the main wave and the delay wave, and the waveform equalization operation suitable for the synchronization timing detection result can be performed. It can be carried out. Furthermore, the synchronization pulse output from the waveform equalization circuit and the timing of the output data coincide with each other, and the error correction unit at the subsequent stage can correct the error correctly.

  According to the reception method of claim 11, which achieves the above object, the reception method is used in a reception apparatus that receives a signal, wherein the reception apparatus detects a synchronization timing of a reception signal and changes a synchronization timing period. Is detected, a synchronization detection step for generating a reset signal and a waveform equalization step for equalizing the transmission path distortion are performed, and the coefficient in the waveform equalization circuit is reset by the reset signal. As a result, in a situation where the main wave and the delayed wave are switched, the waveform equalization circuit can escape from the wrong stable point.

  According to the program of claim 12, which achieves the above object, it is a program for performing a reception process used in a receiving apparatus for receiving a signal, wherein the reception process detects a synchronization timing of a received signal, and performs a synchronization timing. A synchronization detection step for generating a reset signal when a change in the period is detected, and a waveform equalization step for equalizing the transmission path distortion, and the reset signal resets the coefficient in the waveform equalization circuit. Do. As a result, in a situation where the main wave and the delayed wave are switched, the waveform equalization circuit can escape from the wrong stable point.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(Embodiment 1)
<Functional configuration of broadcast receiver>
FIG. 1 is a diagram showing a functional configuration of a broadcast receiving apparatus including a receiving apparatus according to the present invention.

  The broadcast receiving apparatus 1 is a receiver compatible with a single-carrier 8-level VSB (Vestinal Side Band) modulation system called an ATSC (Advanced Television Systems Committee) system, which is a US terrestrial digital broadcasting system. Functionally, it is divided into a front end part 2 and a back end part 3.

  The front end unit 2 includes a tuner 11, a demodulation unit 12, a synchronization detection circuit 13, a waveform equalization unit 1011, and an error correction unit 14.

  The tuner 11 has a function of selecting a received VSB modulated broadcast wave.

  The demodulator 12 has a function of demodulating the selected VSB modulated broadcast wave and outputting a symbol string of the VSB signal. The data structure of the VSB signal will be described later.

  The synchronization detection circuit 13 has a function of detecting a segment synchronization signal and a field synchronization signal from a symbol string and calculating a delay profile.

  The waveform equalization unit 1011 has a function of removing a distortion component from a symbol string distorted by multipath or white noise.

  The error correction unit 14 has a function of correcting a code error of a signal generated on the transmission path and outputting a transport stream.

  The back-end unit 3 has a function of receiving the transport stream output from the front-end unit 2, converting it into a video signal or an audio signal, and outputting it.

<VSB data frame structure>
Here, an ATSC VSB data frame will be described.

  FIG. 2 shows the data structure of an ATSC VSB data frame.

  The VSB data frame is composed of two fields, a first field and a second field.

  One field is composed of 313 segments, and the first segment is a field synchronization segment. The difference between the first field and the second field can be identified by the fact that the polarity of the second PN63 symbol sequence is inverted among the three PN63 symbol sequences included in the field synchronization segment.

  One segment includes a segment synchronization symbol string (4 symbols) and a data symbol string (828 symbols). One symbol is 3 bits / symbol in the 8VSB mode.

  The field sync segment includes segment sync (4 symbols), a training signal (724 symbols), a reserved area, etc. (104 symbols).

  The training signal is a pseudo-noise signal that takes a pseudo-random value within the signal band. The training signal includes three PN511 symbol sequences (511 symbols), three PN63 symbol sequences (63 symbols) (total 189 symbols), VSB mode symbol sequences that identify five types of VSB modes: 2VSB, 4VSB, 8VSB, 16VSB, and TC8VSB. (24 symbols).

  In the 8VSB mode, each data symbol constituting the data segment is obtained by encoding information such as video, audio, and data, which is +7, +5, +3, +1, -1, -3, -5, -7. It is represented by a value of 8 levels.

  In the 8VSB mode, each symbol of the segment synchronization symbol sequence and the field synchronization symbol sequence is expressed by two-level values of +5 and -5 except for a part of the reserved symbol sequence.

  In the present embodiment, the target signal detected by the synchronization detection circuit 13 is the above-described segment synchronization or training signal.

<Functional Configuration of Synchronization Detection Circuit 13>
Next, the functional configuration of the synchronization detection circuit 13 of the first embodiment will be described in detail. Each functional unit other than the synchronization detection circuit 13 uses conventional technology, and a detailed description thereof is omitted.

  FIG. 3 is a diagram illustrating a functional configuration of the synchronization detection circuit 13.

  The synchronization detection circuit 13 has a configuration in which the reliability measurement unit 21 is replaced with the reset signal generation unit 22 in the synchronization detection circuit 1001 of FIG. However, the portion constituted by the correlation unit 1002, the maximum value position detection unit 1003, and the reliability measurement unit 21 is redefined as the synchronization timing detection unit 23.

  In the synchronization detection circuit 13 of FIG. 3, the correlator 1002 has a function of taking a cross-correlation between a sequentially input symbol string and a known symbol string (hereinafter simply referred to as a reference symbol string).

  FIG. 4 is a diagram illustrating an example of the configuration of the correlation unit 1002. Correlation means 1002 includes delay section 31 corresponding to the length to be correlated, reference symbol string input section 32, multiplier 33 corresponding to the length to be correlated, and adder 34.

  The correlation means 1002 shown in FIG. 4 delays the symbol sequence as an input signal one symbol at a time using a delay unit configured with a shift register or the like, so that the symbol sequence and the reference symbol sequence input unit are input. The convolution calculation is performed by shifting the collation position with the reference symbol string one by one, and the correlation value as the calculation result is sequentially output. The configuration shown in FIG. 4 is the same as that of a conventional correlator, and detailed description thereof is omitted.

  In this embodiment, a part of the training signal is used as a reference symbol string.

  Maximum value position detection means 1003 obtains the maximum value from a correlation value sequence (hereinafter simply referred to as a correlation value sequence) obtained as a result of cross-correlation between an input symbol sequence and a reference symbol sequence in correlation unit 1002. It has a function of detecting the position of the regarded correlation value on the correlation value sequence.

  FIG. 5 is a graph of an example of a correlation value sequence obtained as a result of cross-correlation between an input symbol sequence and a reference symbol sequence by the correlation unit 1002.

  In the case of FIG. 5, the maximum value position detecting means 1003 detects correlation value = 185 (S21) at T = 9 as the maximum value, and outputs T = 9 as the maximum value position.

  The reliability measuring means 21 outputs a synchronization pulse in synchronization with the input signal of the waveform equalizing unit, assuming that synchronization detection can be performed, for example, when the maximum value position is the same for a predetermined number of fields. This function is usually called back protection. The sync pulse indicates a field sync segment and a segment sync symbol. The reliability measuring means 21 usually has a function called forward protection in addition to backward protection. The forward protection is a function of stopping the output of the synchronization pulse when the synchronization is lost when the synchronization is established and the synchronization pulse is output and the maximum value position is different for a predetermined number of fields.

  The above operation is the same as that of the conventional synchronization detection circuit 1001. The synchronization detection circuit 13 of the present embodiment further performs the following operation.

  As an example, consider a situation in which a predetermined number of fields (b) are continuous, the maximum position is reached in S21 in FIG. 5, and the reliability measuring means 21 outputs a synchronization pulse. Under this circumstance, if the c symbol continues and reaches the maximum value position in S22 in FIG. 5, the synchronization symbol position is shifted and a synchronization pulse is output in accordance with S22. Here, a predetermined number of fields in forward protection is f, and c ≦ f. At the same time, synchronization position deviation information is generated and output.

  The reset signal generation unit 22 generates a reset signal immediately before the field in which the timing of the synchronization pulse is changed according to the synchronization position deviation information, and outputs the reset signal to the waveform equalization unit 1011 (see FIG. 2).

  The waveform equalizing unit 1011 initializes the tap coefficient by this reset signal, and starts updating the tap coefficient from the timing when the reset is released, that is, from the beginning of the field.

  With the above configuration, the synchronization detection circuit 13 can detect the occurrence of the switching between the main wave and the delayed wave as shown in FIG. 15 as the correlation maximum value position shift. As a result, a reset signal is generated, and the waveform equalization unit 1011 can escape from the wrong stable point. In particular, since the field head is a binary data section as shown in FIG. 2, when the waveform equalizer 1011 starts operating from the field head, the probability that the tap coefficient update direction is correct increases. Furthermore, if the reset signal period is shortened, the length of error data can be shortened.

  Further, the error correction unit 14 in FIG. 1 may reset at least a part of the processing using the reset signal. Thereby, it is possible to prevent the error correction unit 14 from malfunctioning with respect to the interchange of the main wave and the delayed wave.

  Further, the synchronization detection circuit 13 may perform the same processing using the output of the demodulator 12 which is a pre-equalization signal instead of using the output of the waveform equalization unit 1011 which is a post-equalization signal. As a result, the synchronization pulse signal from the synchronization detection circuit 13 and the center tap position of the waveform equalization unit 1011 do not match, and it is possible to quickly get out of the situation where the error correction unit in the subsequent stage cannot correctly correct the error.

(Embodiment 2)
Hereinafter, the receiving apparatus according to the second embodiment will be described.

  FIG. 6 is a diagram illustrating a functional configuration of the broadcast receiving apparatus 41 according to the second embodiment.

  The broadcast receiving device 41 has a configuration in which the synchronization detection circuit 42 and the waveform equalization unit 43 are replaced with those of the broadcast reception device 1 of FIG. It has changed.

  FIG. 7 shows the configuration of the synchronization detection circuit 42. The synchronization detection circuit 42 has a configuration in which the reset signal generation unit 22 is replaced with a synchronization position shift amount generation unit 51 in the synchronization detection circuit 13 of FIG.

  Only the operation difference from the synchronization detection circuit 13 of FIG. 3 will be described below. In the first embodiment, the reset signal generation unit 22 generates a reset signal and outputs it to the waveform equalization unit 1011 when the synchronization symbol position is shifted. The synchronization position shift amount generation means 51 generates a synchronization position shift amount τ instead of the reset signal and outputs it to the waveform equalization unit 1011. When the synchronization pulse is changed in accordance with S21 to S22 in FIG. 5, “+2” is output. Conversely, when the synchronization pulse is changed in accordance with S22 to S21 in FIG. 5, "-2" is output.

  FIG. 8 shows the configuration of the waveform equalization unit 43. The waveform equalizing unit 43 is configured by adding a coefficient recalculating unit 61 and replacing the delay adjusting unit 62 in the waveform equalizing unit 1011 of FIG. The waveform equalizing unit 43 performs the conventional operation when the synchronization position shift amount τ is “0” at the field start position indicated by the synchronization pulse.

  If it is not “0”, the coefficient recalculator 61 reads the tap coefficient group from the coefficient generator 1015 of the FIR filter 1012 and recalculates the tap coefficient group when the synchronization timing position changes according to the synchronization position shift amount τ. Output to the coefficient generation unit 1015 of the FIR filter 1012.

<Coefficient recalculation formula>
FIG. 9 shows the concept of coefficient recalculation in the coefficient recalculation unit 61. In FIG. 9, tap coefficients and multipath estimation are represented by vectors, and the vertical direction is set to 0 degree in the upper direction.

FIG. 9A shows an example of the original tap coefficient in a situation where τ ≠ 0 is detected. The coefficient C _i of the tap number i is
C _i = A _i exp (jθ _i ) (Equation 1)
And The center tap is N, the tap number N is the original main wave D, and the tap number N + τ is the original maximum delay wave U.

FIG. 9B shows the result of estimating the original multipath from FIG. The main wave D is a complex conjugate of the original tap coefficient, and the others including the original maximum delay wave U are rotated by 180 degrees for each of the original tap coefficients. Operation regarding the main wave D is because the original tap coefficients C _N of the main wave D indicates the direction to adjust the phase of the main wave D to 0 °. This is because the operation related to others removes the delayed wave corresponding to the leak by the original tap coefficient.

FIG. 9C shows the result of estimating the latest multipath in consideration of the fact that the main wave D and the maximum delay wave U are switched from FIG. 9B. The center tap N is replaced with a mirror image relationship, and all complex conjugates are taken. As a result, the latest maximum delay wave U ′ is present by τ before the latest main wave D ′. This is because the operation for switching to the mirror image relationship assumes that the power of the main wave D and the maximum delay wave U are switched. Furthermore, the maximum delay wave U exists behind the main wave D in time, and the influence of the tap coefficient C _{N + τ} of the maximum delay wave U is exerted behind in time, whereas the latest maximum delay wave U ′. This is because the time is present before the latest main wave D ′, and the influence of the tap coefficient of the latest maximum delay wave U ′ is exerted before time.

  FIG. 9 (d) shows the result of estimating the latest tap coefficient from FIG. 9 (c). Similarly to FIGS. 9A to 9B, the tap coefficient of the latest main wave D ′ is rotated by 180 degrees for the complex conjugate of the main wave D ′ and the others including the latest maximum delay wave U ′. Become a thing.

The result of recalculating the tap coefficients from FIG. 9D is shown in FIG. All tap coefficients are phase-rotated by − (θ _{N + τ} + π) and time-shifted by −τ. The phase rotation operation is performed to output the original maximum delay wave U at a phase of 0 degree by the tap coefficient of the latest main wave D ′. The time shift operation is a process for preventing the data delay in the waveform equalization unit 43 from changing before and after the tap coefficient is recalculated.

  From the above, the tap coefficient after recalculation is expressed by the following equation.

C _{N−τ + k} = C _N−k ^* exp {−j (θ _{N + τ} + π)} (Expression 2)
That is, the tap coefficient of the latest main wave D ′ is the tap number N−τ, and the tap coefficient of the latest maximum delay wave U ′ is the tap number N−2τ.

<Output of Waveform Equalizer 43>
The output of the waveform equalization unit 43 will be described with reference to the problem described in FIG. The synchronization detection circuit 42 detects the occurrence of switching between the main wave and the delayed wave using the pre-equalization signal, and generates and outputs a synchronization position shift amount τ. When τ ≠ 0, the waveform equalizing unit 43 uses (Equation 2) to recalculate the tap coefficient when the synchronization timing position changes. The latest main wave D ′ is a signal received with a delay of τ symbols from the original main wave D, and the center tap is changed from tap number N to N−τ. Therefore, the delay of the output data of the waveform equalizing unit 43 does not change before and after the switching of the main wave and the delayed wave.

  With the above configuration, the period of one field in the output data of the waveform equalization unit can be maintained before and after the switching of the main wave and the delayed wave.

  If τ ≠ 0, the coefficient recalculator 61 may generate a reset signal and output it to the IIR filter 1013 to reset the tap coefficient of the IIR filter.

  Further, the synchronization pulse output from the synchronization detection circuit 42 is delayed by τ symbols from before the occurrence after the switching of the main wave and the delayed wave. In this regard, the delay adjustment unit 62 of the waveform equalization unit 43 may reduce the delay amount by τ. This includes the meaning that the delay amount is increased by the absolute value of τ when τ is negative. As a result, the timing of the synchronization pulse output from the waveform equalization unit 43 and the output data coincide before and after the occurrence of switching between the main wave and the delayed wave, and the error correction unit at the subsequent stage can correct the error correctly.

<Modification 1>
In the second embodiment, the following operation may be performed.

  FIG. 10 shows the configuration of the waveform equalization unit 71. The waveform equalization unit 71 is configured by adding a phase rotation unit 73 and replacing the coefficient recalculation unit 72 in the waveform equalization unit 43 of FIG.

  Only the differences from the second embodiment will be described below. When the synchronization position shift amount τ is not “0”, the coefficient recalculation unit 72 reads the tap coefficient group from the coefficient generation unit 1015 of the FIR filter 1012 and the next time when the synchronization timing position changes according to the synchronization position shift amount τ. The tap coefficient group is recalculated by the equation and output to the coefficient generation unit 1015 of the FIR filter 1012.

C _{N−τ + k} = C _N−k ^* (Formula 3)
The coefficient recalculator 72 generates and outputs the phase rotation information exp {−j (θ _{N + τ} + π)}. The phase rotation unit 73 rotates the phase of the pre-equalization signal input to the waveform equalization unit 71 by exp {−j (θ _{N + τ} + π)}.

With the above configuration, the same effect as in the second embodiment is obtained. Furthermore, since the phase rotation calculation of exp {−j (θ _{N + τ} + π)} is concentrated in one place, the circuit scale can be reduced.

<Supplement>
Needless to say, the present invention is not limited to the contents described in the above embodiments. That is,
(1) Not only when receiving signals of the ATSC standard, but also when detecting synchronization before the error correction unit, preventing or minimizing data errors due to switching of the main wave and delay wave through the multipath transmission path Can be limited.

  (2) In the above example, correlation is used as a configuration for performing synchronization detection. However, it is not necessary to use correlation, and other configurations may be used as long as the shift of the synchronization timing position can be detected.

  (3) In the second embodiment, the waveform equalization unit includes the FIR filter and the IIR filter. However, the waveform equalization unit may include only the FIR filter or only the IIR filter.

  (4) In the second embodiment, the coefficient recalculation formula of the waveform equalization unit is (Formula 2) or (Formula 3), but other formulas may be used.

  The receiving apparatus according to the present invention can be applied to a terrestrial digital broadcast receiving apparatus, a wireless receiver, or the like.

FIG. 3 is a diagram illustrating an example of a functional configuration of a broadcast receiving device in the first embodiment The figure which shows the data structure of the VSB data frame of an ATSC system FIG. 5 is a diagram illustrating an example of a configuration of a synchronization detection circuit in Embodiment 1 The figure which showed an example of the structure of the correlation means in Embodiment 1 A graph of an example of a correlation value sequence obtained as a result of cross-correlation between an input symbol sequence and a reference symbol sequence The figure which shows an example of a function structure of the broadcast receiver in Embodiment 2. FIG. 5 shows an example of the configuration of a synchronization detection circuit in Embodiment 2. The figure which shows an example of a function structure of the waveform equalization part in Embodiment 2. The figure which shows an example of the concept of the coefficient recalculation in Embodiment 2 The figure which shows an example of a function structure of the waveform equalization part in the modification 1 of Embodiment 2. The figure which showed the composition of the conventional synchronous detection circuit The figure which shows an example of a function structure of the conventional broadcast receiver The figure which shows another example of a function structure of the conventional broadcast receiving apparatus. The figure which shows an example of a function structure of the conventional waveform equalization part The figure which shows the delay relation of the appearance of the delay profile, the appearance of the tap coefficient, and the waveform equalizer output data when the main wave and the delayed wave are switched by the multipath transmission line

Explanation of symbols

DESCRIPTION OF SYMBOLS 1,41 Broadcast receiving apparatus 2,44 Front end part 3 Back end part 11 Tuner 12 Demodulation part 13,42,1001 Synchronization detection circuit 14 Error correction part 21,1004 Reliability measurement means 22 Reset signal generation means 23 Synchronization timing detection means 31, 1016 Delay unit 32 Reference symbol string input unit 33, 1017 Multiplier 34, 1018 Adder 43, 71, 1011 Waveform equalization unit 51 Synchronous position shift amount generation means 61, 72 Coefficient recalculation unit 62, 1014 Delay adjustment unit 73 Phase Rotating Means 1012 FIR Filter 1013 IIR Filter 1015 Coefficient Generation Unit

Claims (12)

A synchronization detection circuit that detects the synchronization timing of the received signal and generates and outputs a reset signal when a change in the synchronization timing period is detected;
Consists of a waveform equalization circuit that equalizes the transmission path distortion,
A receiving apparatus, wherein a coefficient in the waveform equalization circuit is reset by the reset signal. A synchronization detection circuit that performs synchronization timing detection using a signal before waveform equalization of transmission path distortion, and generates and outputs a synchronization position shift amount τ when a change in synchronization timing period is detected;
Consists of a waveform equalization circuit that equalizes the transmission path distortion,
The receiving apparatus according to claim 1, wherein the waveform equalization circuit recalculates a coefficient using a synchronization position shift amount τ. The receiving device further includes:
Equipped with an error correction circuit that performs error correction of data,
4. The receiving apparatus according to claim 1, wherein at least a part of processing in the error correction circuit is reset by the reset signal. The synchronization detection circuit includes:
Synchronization timing detection means for detecting the synchronization timing of the received signal;
4. The receiving apparatus according to claim 1, further comprising reset signal generation means for generating and outputting a reset signal when a change in the synchronization timing period is detected. 5. The receiving apparatus according to claim 1, wherein the synchronization detection circuit further outputs the reset signal as invalid when a synchronization timing position changes. The synchronization detection circuit includes:
Synchronization timing detection means for detecting the synchronization timing of the received signal;
3. The receiving apparatus according to claim 2, further comprising: a synchronization position shift amount generation unit that generates and outputs a synchronization position shift amount τ when a change in the synchronization timing period is detected. The waveform equalization circuit converts the coefficient C _i of the tap number _i to C _i = A _i exp (jθ _i )
When the tap number N is the center tap and k is an integer, and the synchronization position shift amount τ is not 0,
C _{N−τ + k} = C _N−k ^* exp {−j (θ _{N + τ} + π)}
7. The receiving apparatus according to claim 2, further comprising: coefficient recalculating means for performing coefficient recalculation of the FIR filter when the synchronization timing position changes. The waveform equalization circuit converts the coefficient C _i of the tap number _i to C _i = A _i exp (jθ _i )
When the tap number N is the center tap and k is an integer, and the synchronization position shift amount τ is not 0,
C _{N−τ + k} = C _N−k ^*
, The coefficient recalculation means for performing the coefficient recalculation of the FIR filter when the synchronization timing position changes, and the phase rotation means for performing the phase rotation of exp {−j (θ _{N + τ} + π)}. The receiving apparatus according to claim 2 or 6, characterized in that: The waveform equalization circuit further includes:
9. The receiving apparatus according to claim 7, wherein the coefficient in the IIR filter is reset when the synchronization position shift amount [tau] is not zero. The synchronization detection circuit outputs a synchronization pulse indicating a synchronization timing position,
Further, the waveform equalization circuit normally outputs the synchronization pulse by delaying the synchronization pulse by a certain amount, and when the synchronization position shift amount τ is not 0, the delay amount of the synchronization pulse is changed by −τ. The receiving apparatus according to claim 7, comprising delay adjusting means for outputting a synchronization pulse. A receiving method used in a receiving apparatus for receiving a signal,
The receiver performs a synchronization timing detection of a received signal, and a synchronization detection step of generating a reset signal when a change in the synchronization timing period is detected;
A waveform equalization step for equalizing the transmission path distortion,
A receiving method comprising: resetting a coefficient in the waveform equalization circuit by the reset signal. A program for performing reception processing used in a reception device that receives a signal,
The reception process performs synchronization timing detection of a received signal, and generates a reset signal when a change in the synchronization timing period is detected, and a synchronization detection step,
A waveform equalization step for equalizing the transmission path distortion,
A program for resetting a coefficient in the waveform equalization circuit by the reset signal.

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