JP2007129619A - Equalizer circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an equalizer circuit which has a simple configuration and less noise and has parameter easily adjusted. <P>SOLUTION: The equalizer circuit includes a first amplification circuit 50 for amplifying an input signal and then outputting it, a filter circuit 51 having the input signal applied thereto, a second amplification circuit 52 having an output signal of the filter circuit 51 input thereto, and an addition circuit 53 for adding an output signal of the first amplification circuit 50 and that of the second amplification circuit 52 in opposite phases. A plurality of pairs of filter circuits 51 and second amplification circuits 52 may be included. Furthermore, the equalizer circuit includes an equalization characteristic setting circuit 54 for controlling gains of amplification circuits and characteristics of filter circuits. The equalizer circuit does not require components and elements of high precision or low noise and has a simple circuit configuration. Since the equalizer circuit is not made sensitive to a high band, noise reduction is achieved. Furthermore, characteristics of the equalizer circuit can be continuously changed. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an equalizer circuit, and more particularly to an equalizer circuit having a simple configuration, low noise, and easy parameter adjustment.

In the field of wired data transmission, an equalizer circuit is conventionally provided in a receiving circuit in order to compensate for reception waveform deterioration due to frequency characteristics of a transmission path. Since the frequency characteristics of the transmission line are similar to those of the low-pass filter, a high-pass filter circuit has been used as the equalizer circuit. The following Patent Document 1 discloses an example of an equalizer circuit using a high-pass filter circuit.
Japanese Patent Laid-Open No. 06-152340

  In the conventional circuit as described above, for example, when trying to change the frequency characteristics of the equalizer circuit, it is necessary to switch the value of the element through which the signal passes, such as a resistor, a capacitor, and a coil, by the switching element. There was a problem that the circuit scale and area of the circuit of this would become large. In addition, since a high-pass filter circuit is used, the circuit characteristics are likely to transmit high-frequency signal components, and noise is likely to be mixed into the signal from a switching element for switching the element value. There was also a point.

  Furthermore, in order to continuously change the frequency characteristics of the equalizer circuit, many elements are required to increase the switching resolution, and there is a problem that it is more difficult to reduce the noise. An object of the present invention is to solve the above-described problems of the prior art, and to provide an equalizer circuit that is particularly simple in structure, has low noise, and can easily adjust frequency characteristics.

  The equalizer circuit of the present invention includes a first amplifier circuit that amplifies and outputs an input signal, a filter circuit to which the input signal is applied, a second amplifier circuit to which the output signal of the filter circuit is input, The main feature is that an addition circuit for adding the output signal of the first amplifier circuit and the output signal of the second amplifier circuit in opposite phases is provided.

  In the equalizer circuit described above, the first and second amplifier circuits are each a differential amplifier circuit, and the filter circuit is an integration circuit.

  In the equalizer circuit described above, the differential amplifier circuit includes a current source circuit for adjusting a bias current of two amplifier elements, and further includes a current adjusting unit for adjusting a current value of the current source circuit. There is also a feature in the point.

  In the equalizer circuit described above, the filter circuit includes a filter characteristic changing circuit that changes a frequency characteristic of the filter circuit. Further, the equalizer circuit described above is characterized in that a plurality of sets of the filter circuit and the second amplifier circuit are provided.

  The equalizer circuit of the present invention does not require high-precision or low-noise parts or elements, has a simple circuit configuration, and can be easily manufactured. Further, since the filter circuit is composed of a low-pass filter, it is not sensitive to a high-frequency signal, so that there is an effect that noise can be reduced. Further, there is also an effect that the frequency characteristic of the equalizer circuit can be continuously changed by continuously adjusting the bias current value of the differential amplifier circuit. Further, even when a circuit for switching the characteristics of the filter is employed, there is an effect that noise can be further reduced as compared with the conventional case. Therefore, the equalizer circuit of the present invention is suitable for an ultrahigh-speed transmission circuit that uses a high frequency.

  Embodiments of the present invention will be described below in detail with reference to the drawings.

  The equalizer circuit according to the first embodiment of the present invention will be described below. FIG. 1 is a block diagram showing the configuration of the equalizer circuit of the present invention. For example, a known differential amplifier IC can be used as the first differential amplifier circuit 50 which is a first amplifier circuit that amplifies and outputs an input signal.

  The filter circuit 51 to which the input signal is applied is, for example, a low-pass filter circuit having the same frequency characteristics as the transmission path. As the second differential amplifier circuit 52 that is the second amplifier circuit to which the output signal of the filter circuit 51 is input, a known differential amplifier IC that is the same as the first differential amplifier circuit 50 can be used. .

  The adder circuit 53 that adds the output signal of the first amplifier circuit and the output signal of the second amplifier circuit in reverse phase is a circuit in which the respective output terminals are simply connected. However, the positive (+) output signal terminal of the first differential amplifier circuit 50 and the negative (−) output signal terminal of the second differential amplifier circuit 52 are the negative electrodes of the first differential amplifier circuit 50. The negative (−) output signal terminal and the positive (+) output signal terminal of the second differential amplifier circuit 52 are connected to each other.

  As a result, a signal obtained by subtracting the output signal of the second differential amplifier circuit 52 that has passed through the filter circuit 51 from the output signal of the first differential amplifier circuit 50 is generated at the load resistance of the adder circuit 53 and output. Is done. Here, when the filter circuit has low-pass characteristics, a signal in which the high-frequency component of the input signal is more emphasized is obtained as the output signal of the equalizer circuit.

  The equalization characteristic setting circuit 54 controls and adjusts the filter circuit 51, the first differential amplifier circuit 50, and the second differential amplifier circuit 52 by a method described later based on parameters set from an external adjustment device. Note that any known adjustment method can be adopted as the equalizer circuit adjustment method, but the description thereof is omitted because it is not the gist of the present invention.

  FIG. 2 is a circuit diagram showing the configuration of the equalizer circuit of the present invention. The first differential amplifier circuit 50 and the second differential amplifier circuit 52 are respectively composed of, for example, a differential amplifier circuit 80, 82 composed of two FETs and a known current mirror circuit 81, 83 which is a kind of current source circuit. Become.

  The filter circuit 51 is, for example, a low-pass filter circuit (integration circuit) composed of a resistor and capacitor network. In the adder circuit 53, the output terminals of the differential amplifier circuits 80 and 82 are connected in reverse phase and connected to a load resistor.

  The equalization characteristic setting circuit 54 is a parameter register 84 that holds control parameters for each differential amplifier set from an external adjustment device, and a known current output that generates an analog control current based on the set value of the parameter register. It comprises a type D / A converter 85.

  The current mirror circuits 81 and 83 supply a bias current proportional to the current input to the current mirror circuit to the differential amplifier circuits 80 and 82. Therefore, by controlling the input current to the current mirror circuit, the bias current flowing through the differential amplifier circuits 80 and 82 can be controlled, and the amplitude of the output signal of the differential amplifier circuit can be controlled.

  For example, when a value for outputting a large current from the current output type D / A converter 85 is set in the parameter register 84 corresponding to the differential amplifier circuit 80, a large bias current flows through the differential amplifier circuit 80. As a result, the amplitude of the signal output from the differential amplifier circuit 80 increases.

  Therefore, the frequency characteristics of the equalizer circuit can be changed by controlling the bias current of only the differential amplifier circuit 80 or both of the two differential amplifier circuits 80 and 82. For example, if the current flowing through the current mirror circuit 83 is set to 0, the characteristics of the equalizer circuit become flat. If the current flowing through the current mirror circuit 83 is increased, the high-pass characteristics are increased according to the current value. Since the current flowing through the current mirror circuits 81 and 83 can be changed almost continuously if the accuracy of the D / A converter 85 is increased, the characteristics of the equalizer circuit can also be changed continuously.

  FIG. 3 is a block diagram showing the configuration of the entire transmission circuit including the equalizer circuit of the present invention. The equalizer circuit of the present invention is developed on the assumption that it is used for an ultrahigh-speed digital data transmission apparatus (LAN) of several gigabps or more using a balanced cable or a coaxial cable represented by a twisted pair cable. However, the equalizer circuit of the present invention is not limited to this, and can be applied to equalization of an arbitrary signal.

  This embodiment consists of a full-duplex data transmitter / receiver of the same configuration connected to both ends of the transmission cable 21. For example, in 10 Gigabit Ethernet (registered trademark), four sets of the transmission apparatus of FIG. 3 are used.

  The transmission circuit 10 includes a code converter 11, a PN signal generation circuit 12, a switch 13, a precoder 14, a D / A converter 15, an amplifier 16, and a transmission side training control circuit 17. The code converter 11 divides the transmission data into predetermined bits and outputs one of a plurality of signal levels (voltage values) corresponding to the value of the bit string.

  The precoder 14 includes, for example, an FIR filter processing circuit, and performs a known pre-emphasis process on the signal. The output of the precoder 14 is converted into an analog signal by the DAC 15 and transmitted through the amplifier 16 and the hybrid circuit 20.

  The transmission-side training control circuit 17 switches the switch 13 to the PN signal generation circuit 12 when the apparatus is turned on, for example, sends a training signal to the transmission line, and performs a training process for the equalizer circuit 32 on the reception side. Alternatively, the precoder 14 may be controlled by feeding back a signal from the receiving circuit to the transmitting training control circuit 17. Further, even during signal transmission, the coefficients of the equalizer circuit 32 and the precoder 14 may be adjusted based on the signal evaluation result on the receiving circuit side.

  Next, the receiving circuit will be described. The reception circuit 30 includes a variable gain amplifier 31, an equalizer circuit 32 according to the present invention, a symbol synchronization circuit 33, an A / D converter 34, a level determination circuit 35, a sign reverse conversion circuit 37, a reception side training control circuit 38, and the like.

  The variable gain amplifier 31 amplifies the received signal to a desired level. The equalizer circuit 32 of the present invention equalizes the transmission path. The symbol synchronization circuit 33 reproduces a synchronization signal from the received signal, and the A / D converter 34 A / D converts the received signal. A digital equalizer circuit may be provided after the A / D converter 34 to share the equalization function with the equalizer circuit 32 of the present invention.

  The level determination circuit 35 is a circuit that determines in which multi-valued region the received signal is, and the sign reverse converter 37 reversely converts the output of the level determination circuit 35 into the original bit information. The reception side training control circuit 38 cooperates with the transmission side training control circuit 17 to adjust the equalizer circuit 32 and the like using the training signal. Also, during data communication, obtain more detailed signal evaluation information such as how much the signal is deviated from the central level of the signal arrangement, and adjust the equalizer circuit 32 and the like to improve the evaluation value To do.

  FIG. 4 is a circuit diagram showing a configuration example of the filter circuit 51 of the present invention. FIG. 4A shows an example of a filter circuit including an integrating circuit 60 including a resistor and a capacitor and a resistor 61 for adjusting the gain. FIG. 4B shows an example of a filter circuit in which integrating circuits 63 and 64 composed of resistors and capacitors are cascaded in two stages.

  4C includes capacitors 67 and 68 and a switching circuit 69 in addition to the integration circuit 66 composed of a resistor and a capacitor. By controlling the switching circuit 69, the time constant (filter characteristic) of the integration circuit can be changed. It is what I did. Also, the gain adjustment resistor can be changed by the resistors 72 and 73 and the switching circuit 74. For example, an FET can be used as the switching element.

  In this configuration, the switching circuits 69 and 74 are not directly connected to the signal path connecting the input terminal and the output terminal, and the characteristics of the network itself are low-pass types and are not sensitive to high frequencies. For example, it is difficult for noise generated from a switching circuit or the like to be mixed in a signal, and noise can be reduced.

  FIG. 4D shows an example of a band-pass filter circuit in which a differentiation circuit (high-pass filter circuit) 76 composed of a resistor and a capacitor is provided before an integration circuit 77 composed of a resistor and a capacitor. In addition, a coil may be used as an element, and any known circuit can be adopted as a filter circuit as necessary.

  FIG. 5 is a circuit diagram showing a configuration of an embodiment 2 of the equalizer circuit of the present invention. This circuit includes a plurality of sets (two sets in the embodiment) of the filter circuit 51 and the second differential amplifier circuit 52 of the first embodiment. The first filter circuit 94 constitutes a low-pass filter and is connected to the differential amplifier circuit 90. The second filter circuit 95 constitutes a band-pass filter and is connected to the differential amplifier circuit 92.

  Therefore, by controlling the current mirror circuit 91 connected to the differential amplifier circuit 90, the high frequency characteristics of the equalizer circuit can be controlled. Further, by controlling the current mirror circuit 93 connected to the differential amplifier circuit 92, it is possible to control the mid-range characteristics of the equalizer circuit.

  In this embodiment, a known current output type A / D converter 97 is connected to the output of the control register 96, and a current proportional to the value set in the control register 96 is output to the current mirror circuit. Is done.

  Note that the number of sets of the filter circuit and the second differential amplifier circuit may be three or more, and the configuration and characteristics of the filter circuit are also arbitrary. In the second embodiment, with the above configuration, the equalizer circuit can be controlled to an arbitrary characteristic with a simple configuration.

Although the embodiments have been described above, the following modifications may be considered in the present invention. In the embodiment, an example in which an FET is used as an amplifying element has been disclosed. However, a bipolar transistor can also be used as an amplifying element.
During training or data transmission, the reception-side training control circuit 38 and the transmission-side training control circuit 17 may simultaneously adjust the equalizer circuit 32 and other circuits using a genetic algorithm. In this case, the chromosome information includes a plurality of control parameters of the equalizer circuit, and the evaluation function value of the genetic algorithm is the voltage distribution of the received signal waveform, the jitter amount of the received signal, or the bit error of the received data. It can be calculated from the rate.

It is a block diagram which shows the structure of the equalizer circuit of this invention. It is a circuit diagram which shows the structure of the equalizer circuit of this invention. It is a block diagram which shows the structure of the whole transmission circuit containing the equalizer circuit of this invention. It is a circuit diagram which shows the structural example of the filter circuit 51 of this invention. It is a circuit diagram which shows the structure of Example 2 of the equalizer circuit of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 50 Differential amplifier 51 Filter circuit 52 Differential amplifier 53 Reverse phase addition circuit 54 Equalization characteristic setting circuit

Claims (5)

A first amplifier circuit for amplifying and outputting an input signal;
A filter circuit to which the input signal is applied;
A second amplifier circuit to which an output signal of the filter circuit is input;
An equalizer circuit comprising: an adder circuit that adds an output signal of the first amplifier circuit and an output signal of the second amplifier circuit in opposite phases. Each of the first and second amplifier circuits is a differential amplifier circuit;
The equalizer circuit according to claim 1, wherein the filter circuit is an integration circuit. The differential amplifier circuit includes a current source circuit for adjusting bias currents of two amplifier elements,
2. The equalizer circuit according to claim 1, further comprising a current adjusting means for adjusting a current value of the current source circuit.   The equalizer circuit according to claim 1, wherein the filter circuit includes a filter characteristic changing circuit that changes a frequency characteristic of the filter circuit. 2. The equalizer circuit according to claim 1, comprising a plurality of sets of the filter circuit and the second amplifier circuit.

Images