JP2007129490A - Digital broadcast adaptive software radio equipment and image signal processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide technology which is adaptive to a digital broadcast, with respect to software radio equipment capable of being connected to a plurality of communication systems. <P>SOLUTION: The software radio equipment 1 comprises a central control signal processor 10, a programmable signal processor 20, and a radio communication board 30, wherein the central control signal processor 10 includes a plurality of CPUs 11 and 12 and the programmable signal processor 20 includes a plurality of FPGA groups 21 and 22. Further, an image processor 60 is connected to the programmable signal processor 20. While one CPU performs radio communication by the FPGAs, the other makes a connection with a different radio communication system so as to be able to receive a digital broadcast. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a software defined radio and an image signal processing apparatus compatible with digital broadcasting, and more particularly to a technique corresponding to digital broadcasting in a software defined radio compatible with a plurality of wireless communications and a technique related to a programmable image signal processing apparatus. is there.

  Currently, standardization regarding wireless consumer communication is actively performed by IEEE, ETSI, ARIB, and the like, and users can use many wireless access systems. In addition to wireless access systems, users can enjoy services such as terrestrial / satellite analog broadcasting and terrestrial / satellite digital broadcasting through mobile phones, creating new business models that integrate communications and broadcasting. Has been done.

  Wireless access systems other than cellular mobile communications include wireless LAN wireless access systems using 2.4 GHz, 5 GHz, and 25 GHz bands, and FWA (Fixed Wireless Access using 22 GHz, 26 GHz, and 38 GHz bands with a communication speed of 100 Mbps or higher. There are fixed wireless access systems typified by

However, it is currently difficult for users to carry radio devices that can use all of these wireless access systems and broadcast systems. In addition, communication between different wireless access systems and communication using a plurality of radio communication systems, radio communication systems, and broadcast systems have not been made yet.
As a well-known technique, there is a mobile phone terminal disclosed in Patent Document 1 having a reception function for terrestrial broadcasting. However, this is merely a combination of both functions, and is used in a plurality of systems. It is not flexible.

JP 2003-101812 A

In addition, software wireless technology is attracting attention as an indispensable technology for realizing new generation mobile communication.
As disclosed in Non-Patent Document 2, software radio technology has been proposed as a technology for quickly dealing with bugs, upgrades, and the like that have occurred in communication devices.
In addition, as disclosed in Non-Patent Documents 3 and 4 by the present inventors, the effectiveness is shown as means for realizing the functions of a plurality of wireless devices in a space-saving environment such as a car. I came.

J. Mitra, IEEE Communications Magazine, vol.33, no.5, pp.26-38, 1995 Harada et al., IEICE Technical Report, SR99-12, pp. 81-88, 1999 H. Harada et.al., IEICE Trans. Commun., Vol. E85-B, No. 12, pp. 2703-2715, 2002

Further, Patent Literature 5 proposed by the present applicant is patent literature relating to software radio technology.
In the technique of Patent Document 5, the control unit manages the function of the software information set in the signal processing unit and the function of each of the plurality of software information stored in the information storage unit. On the other hand, the signal processing unit reads the software information corresponding to the other service function from the information storage unit and sets it in the signal processing unit in response to the request of the other service function in the state of executing the service function, The signal processing unit is configured to execute a plurality of service functions in parallel.
The present technology enables a plurality of available service functions to be used at the same time, and is a technology that improves user convenience.

This technology assumes switching between different communication systems, for example, switching and executing any one of ETC (Electric Toll Collection), FM Radio, AM Radio, and GPS (Global Positioning System) functions. ing. Therefore, when switching to another communication system in the middle of one access like Internet access, there is a problem that switching takes time in the present technology.
As described above, when performing seamless communication between various wireless access systems, it cannot be applied as it is.

Japanese Patent Laid-Open No. 2004-153662

In addition, the technique of Patent Document 6 by the present applicants has also been proposed. The present technology includes one control unit, a plurality of digital signal processing units, and a plurality of transmission units. The control unit controls the plurality of digital signal processing units by one or both of the parameter and the program read from the information recording medium.
Each of the plurality of digital signal processing units receives a digital signal, processes the digital signal, and outputs the digital signal.
Each of the plurality of transmission units is associated with one of the plurality of digital signal processing units, converts the digital signal output from the associated digital signal processing unit into an analog signal, and transmits the analog signal.
This provides a plurality of services simultaneously.

  However, this technology can handle multi-mode and multi-service. However, as mentioned above, interference occurs due to the same frequency band, and many services are used simultaneously. Cannot be fully satisfied.

Japanese Patent No. 35251181

  As a technique capable of supporting a plurality of wireless access systems, a technique of Non-Patent Document 7 by the present applicants is also known.

"Development of software defined radio terminal for new generation mobile communication system-overview and system configuration-", IEICE Technical Report, RCS, Vol, June 2004

  According to the present technology, it is possible to efficiently cope with a plurality of wireless access systems, but it is not compatible with digital broadcasting, and it has not been possible to receive the broadcasting by the wireless device described at the beginning.

  The present invention was created in view of the above-described problems of the prior art, and is a software defined radio that can be connected to a plurality of communication systems, and an object thereof is to provide a technology that also supports digital broadcasting. To do.

In order to solve the above-described problems, the present invention provides the following configuration of a digital radio compatible software defined radio.
The invention described in claim 1 is a digital broadcast-compatible software defined radio including a central control signal processing device, a programmable signal processing device, a wireless communication board, and an image signal processing device.
A central control signal processing apparatus of the radio includes a plurality of CPUs (Central Processing Units), a system bus corresponding to each CPU, a memory connected to the system bus, and a network adapter connected to the system bus. , An audio codec processing unit, a data transmission bus unit, a connection interface unit connected to the programmable signal processing device, and a DPRAM (Dual Port RAM) shared by the plurality of CPUs.

Moreover, the programmable signal processing apparatus of this radio | wireless machine is equipped with two or more electronic element groups comprised by the programmable electronic element categorized using the programmable electronic element which can program an electronic circuit structure.
And for every said electronic element group, the RF interface part which communicates the control signal with the radio | wireless communication board which manages radio | wireless communication, the AD conversion process part which digitally converts the signal from a radio | wireless communication board, and inputs it into a programmable electronic element, or At least one of a DA conversion processing unit that analog-converts and outputs a signal to the wireless communication board, a digital signal output unit that transmits a digital signal to at least an image signal processing device that performs image signal decoding processing, and each programmable electronic element A program interface unit for externally programming, a clock input interface unit for inputting a clock from the outside, a clock distribution unit for dividing the input clock into a predetermined multiple of clocks and inputting the divided clocks to each electronic element group, OSI At least the data link layer in the hierarchical model And a connection interface with the central control signal processing unit which controls the signal processing of the network layer.

In this configuration, wireless communication of a predetermined communication method including at least a digital broadcasting method is performed on the wireless communication board by the control of the central control signal processing device and the programmable signal processing device.
Further, the image signal processing apparatus includes a digital signal input unit that inputs a signal from the digital signal output unit, and one or more programmable electronic elements that can program the electronic circuit configuration. An image signal decoding process is performed on the programmable electronic element.

  According to a second aspect of the present invention, in the configuration in which the image signal processing apparatus includes a central processing element, the central processing element performs at least signal processing related to the sound included in the digital signal. Is.

  According to a third aspect of the present invention, the image signal processing apparatus includes a small storage medium reading unit that reads data from a small storage medium using a semiconductor storage element. Then, the image decoding process is performed by reading and programming at least one of the programmable electronic element and the central processing element stored in the small storage medium.

  According to a fourth aspect of the present invention, the image signal processing apparatus includes two programmable electronic elements, and the first programmable electronic element relates to at least digital signal communication with the programmable signal processing apparatus. While performing the signal processing, each of the second programmable electronic elements performs a program operation so as to perform at least an image signal decoding process.

  According to a fifth aspect of the present invention, in the above programmable signal processing apparatus, the first programmable electronic element is a process related to the codec in a predetermined communication system in a configuration including two programmable electronic elements for one electronic element group. On the other hand, each of the second programmable electronic elements performs a program operation so as to perform processing related to modulation / demodulation in a predetermined communication method.

  According to a sixth aspect of the present invention, there is provided a digital broadcasting-compatible software defined radio wherein the digital signal is a transport stream (TS) signal.

  According to a seventh aspect of the present invention, in the configuration in which the image signal processing device according to the fifth aspect processes a transport stream signal (TS signal), the first programmable electronic element is configured to generate a PCR (Program Clock) from the TS signal. Each of the programs is performed so that at least one of the Reference (Preference) signal and AUDIO PES (Audio Packetized Elementary Stream) signal is separated (DEMUX) while the second programmable electronic element performs at least MPEG2 (Moving Pictures Experts Group 2) decoding. It is characterized by operation.

  According to an eighth aspect of the present invention, the image signal processing apparatus includes a plurality of digital signal input units, and the first programmable electronic element multiplexes and separates a plurality of input digital signals. A program operation is performed so as to perform the above.

  According to a ninth aspect of the present invention, in the image signal processing apparatus according to the ninth aspect, the plurality of digital signal input units inputs digital signals from each electronic element group in the programmable signal processing apparatus according to the fifth aspect. It is characterized by doing.

  According to the tenth aspect of the present invention, in the above image signal processing apparatus, a first digital signal input unit that inputs a scrambled signal or an encrypted signal and a digital signal that outputs the input signal without signal processing. A signal external output unit and at least a second digital signal input unit for inputting a signal descrambled or decrypted by a descrambler or encryption / decryption device connected to the digital signal external output unit .

The present invention can be provided as a single image signal processing apparatus separately from the digital broadcast compatible software defined radio.
That is, the invention described in claim 11 is an image signal processing apparatus capable of decoding an image signal related to digital broadcasting, and at least a digital signal input unit for inputting a digital signal and a single unit capable of programming an electronic circuit configuration. Alternatively, a plurality of programmable electronic elements are provided, and an image signal decoding process is performed on the input digital signal on the programmable electronic elements.

  According to a twelfth aspect of the present invention, in the image signal processing apparatus having the central processing element, the central processing element performs at least signal processing related to sound included in the digital signal. .

  According to a thirteenth aspect of the present invention, the image signal processing apparatus includes a small storage medium reading unit that reads data from a small storage medium using a semiconductor storage element. Then, the image decoding process is performed by reading and programming at least one of the programmable electronic element and the central processing element stored in the small storage medium.

  According to a fourteenth aspect of the present invention, the image signal processing apparatus includes two programmable electronic elements, and the first programmable electronic element is digitally connected to at least an external digital signal output apparatus such as a digital tuner. While performing signal processing related to signal communication, each of the second programmable electronic elements performs a program operation so as to perform at least image signal decoding processing.

  According to a fifteenth aspect of the present invention, there is provided an image signal processing apparatus, wherein the digital signal is a transport stream (TS) signal.

  According to a sixteenth aspect of the present invention, in the configuration in which the image signal processing device according to the fourteenth aspect processes a transport stream signal (TS signal), the first programmable electronic element is changed from the TS signal to a PCR (Program Clock Reference). At least one of the signal and the AUDIO PES (Audio Packetized Elementary Stream) signal is separated (DEMUX). On the other hand, each of the second programmable electronic elements performs a program operation so as to perform at least MPEG2 (Moving Pictures Experts Group 2) decoding processing.

  According to a seventeenth aspect of the present invention, the image signal processing apparatus includes a plurality of digital signal input units, and the first programmable electronic element performs multiplexing processing and separation processing on the plurality of input digital signals. A program operation is performed so as to perform the above.

  According to an eighteenth aspect of the present invention, in the above image signal processing apparatus, a first digital signal input unit that inputs a scrambled signal or an encrypted signal and the input signal is output without signal processing. It comprises at least a digital signal external output section and a second digital signal input section for inputting a signal descrambled or decrypted by a descrambler or encryption / decryption device connected to the digital signal external output section. To do.

  By providing the above configuration, the present invention can support reception of a plurality of communication systems and digital broadcasts by simply rewriting a program with one terminal device. And since it has two or more signal processing means at the time of communication, the continuous communication without a joint is possible.

Hereinafter, embodiments of the present invention will be described based on examples shown in the drawings. The embodiment is not limited to the following.
As shown in FIG. 1, a digital broadcast-compatible software defined radio (hereinafter referred to as a single software defined radio) (1) according to the present invention includes a CPU board (10) that is a central control signal processor and programmable signal processing. The device includes an FPGA board (20), a wireless communication board (30), and an image signal processing device (60) according to the present invention.

In the wireless communication board (30), the received signal power from the antenna (7), the bit error rate (BER), and the packet error rate (PER) are measured by the communication state measurement unit (6). These measuring methods are known.
The wireless communication board (30) includes a plurality of wireless communication systems and operates in conjunction with switching of the wireless communication systems of the central control signal processing device (10) and the programmable signal processing device (20) according to the present invention.

  Further, the wireless communication board (30) receives the digital broadcast and converts it into a frequency band that can be processed by the programmable signal processing device (20). For example, in this embodiment, processing for converting from the frequency band of terrestrial digital broadcasting to 8.143 MHz or 4.0715 MHz is performed.

The communication protocol used in the apparatus of the present invention is arbitrary. For example, the signal received by the wireless communication board (30) is subjected to signal processing such as decoding by the FPGA board (20), and converted into a TCP / IP packet by the CPU board (10). It can be converted and output from the connected personal computer in the form of a moving still image or sound.
During wireless transmission, the captured moving / still image or audio signal is input to the FPGA board (20) in the form of a TCP / IP packet by the CPU board (10).

As shown in FIG. 2, the CPU board (10) has two CPUs, a main CPU (11) and a sub CPU (12), and has a system bus (13) (14) corresponding to each of them. .
The CPU board (10) and the FPGA board (20) are connected by connectors (15) and (16). In the present invention, each board is provided separately and can be easily connected by connectors (15) and (16).

  For the FPGA board (20), an FPGA which is a programmable electronic element capable of programming an electronic circuit configuration is used. As a feature of the present invention, two categorized FPGA groups (referred to as right and left channels for convenience) (21) (22) are formed, and two FPGAs (23) (24) are provided for each channel. Is placed.

  The main CPU (11) and the sub CPU (12) of the CPU board (10) are configured to be able to control any of the left and right channel FPGA groups. The operation of the both is as follows. While the main CPU (11) performs wireless communication using the FPGA group of one channel, the sub CPU (12) sets the FPGA group of the other channel as the switching destination communication method. To wait for communication.

  Signal processing is switched from the main CPU (11) to the sub CPU (12) when switching from the user to a switching instruction or a communication method waiting at a predetermined switching trigger. This switching is simply a switching of the signal path on the circuit in a state where communication has already been established, so that the communication system can be switched instantaneously without interruption. For example, when the BER falls below a threshold set in advance by the user in the threshold comparison unit (2), the wireless communication system is compared with another wireless communication system searched for by the next candidate wireless communication system search unit (3). The switching unit (4) acts so as to perform a switching operation.

The present invention implements a digital broadcast receiving function by using these resources by using a CPU board having a plurality of CPUs and a FPGA board having a plurality of FPGAs as a platform.
Further, each component will be described in detail below.

FIG. 3 shows a detailed configuration of the FPGA board (20).
The FPGA group of each channel includes a serial interface (40) that controls the wireless communication board (30), a digital output interface (41) that is an output unit that outputs a digital signal to the image signal processing device according to the present invention, and wireless communication. A plurality of AD / DA converters (42) for inputting and outputting signals transmitted and received by the board, an interface (43) for programming an electronic circuit configuration in the FPGA, and the like are provided.

  The serial interface (40) includes a digital output, an analog input, an AD / DA converter for analog output, and a buffer.

As a feature of the present invention, an operation clock is input from the wireless communication board (30). As shown in FIG. 2, one system of input clocks is divided into a predetermined multiple of clocks and distributed to each FPGA group for input. FIG. 3 shows the clock input interface (44) after distribution.
Thus, by dividing and using one input clock, it is possible not only to supply clocks having a plurality of types of frequencies to the FPGA group, but also to operate the two channels in a completely synchronized state.

The FPGA board mainly performs processing that requires high-speed processing among processing of the first layer (physical layer) and processing of the second layer and higher in the OSI reference model. That is, it is high-speed processing in the case of performing electrical conversion, mechanical processing, and communication adjustment between users for sending data to a communication line.
As shown in the figure, two FPGA groups constitute one system, and this FPGA board has four FPGAs. Therefore, at least two communication systems can be operated simultaneously.

  The number of CPUs and the number of FPGA groups of the present invention can be arbitrarily configured by a plurality. That is, when selecting an optimum system at high speed from a large number of communication systems, two or more standby systems may be operated together with one active system, in which case there are three CPUs and FPGA groups. The above configuration may be used.

The specification of the FPGA board used in this embodiment is that the AD converter has 2 channels and the conversion rate is 170 Msps and 12 bits, and the DA converter has 2 channels and the conversion rate is 500 Msps and 12 bits.
As the FPGA, XC2V4000, XC2V6000, and XC2V8000 (product names) of Xilinx (registered trademark) are used.

FIG. 4 shows a detailed configuration of the CPU board (10).
An RS232C interface (50), which is a serial interface, is connected to each CPU (11) (12).
Further, SDRAM (51) and flash ROM (52) are connected to the system buses (13) and (14), and software for signal processing is stored in the flash ROM (52).

A network adapter (53) such as Ethernet (registered trademark), an audio codec processing circuit (54), and a data transmission bus (55) such as USB are connected to the system bus. Any one of these may be provided or a plurality of these may be provided according to the system requirements. Other interfaces may also be included.
In addition to the FPGA board, an FPGA (56) is provided on the system bus.

Then, a program defining the CPU processing from the outside is written into the flash ROM (52) using the interface (57). Thereafter, the programs required for the CPU (11) (12) are expanded from the flash ROM into the SDRAM (51) for those required for the CPU (11), and the programs required for the CPU (12) are expanded to the SDRAM (52). , Drive the program. The DPRAM is used for exchanging information shared between the CPUs (11) and (12).
A program for realizing various communication systems is written in the flash ROM (52) and the FPGA (56), and performs signal processing to be described later.

Note that the CPU board of this embodiment is composed of two CPUs that operate on a 430 MIPS μ-ITRON that operates at 240 MHz so that it can also be used in a portable terminal.
In this embodiment, the functions below the IP layer of W-CDMA and IEEE802.11a wireless LAN are softwareized on the above platform. These software can be changed freely according to user's wishes, propagation path information, etc.

In the present invention, an image signal processing device (hereinafter referred to as a decoder board) is manufactured in the same size as the FPGA board (20) in order to cope with the reception of broadcasting signals in addition to the common platform. Both devices can be stacked and connected.
FIG. 5 shows a configuration diagram of the decoder board (60). In the present invention, the decoder board (60) is also provided with two programmable electronic elements, FPGA (61) (62), and a central processing element (CPU) that performs processing such as rewriting the program.

  Various signal processing for decoding can be changed by changing the software for the FPGA (61) (62). Also, a DSUB 25-pin connector for inputting a digital signal such as a digital signal output from the digital output interface (41) of the FPGA board (20) or an external digital tuner is an input connector (63) (64) (65 ).

  The signal from the digital output interface (41) of the system A in the FPGA board (20) of FIG. 3 is input to the input connector CN4 (64), and the same signal from the system B is input to the input connector CN6 (65). Is input to the input connector CN8 (63).

This board is provided with the following five output terminals as terminals for outputting an image (in the present invention, video and audio are collectively referred to as an image, but only one of them may be used) to a television monitor or the like. Yes.
(1) HDTV video signal (Y, Pr, Pb) output (D terminal) (600)
(2) SDTV video signal (Y, C) output (S terminal) (601)
(3) NTSC composite video signal (RCA pin jack) (602)
(4) Audio (5.1CH compatible) signal output (RCA pin jack) (603)
(5) TS signal (DVB-SPI) output (25P DSUB connector) (604)

  In the processing of digital broadcasting, processing is basically performed by each FPGA group on the FPGA board (20). Here, Table 1 shows an outline of terrestrial digital broadcasting targeted by the present embodiment.

A basic block diagram of software incorporated in the FPGA board (20) at this time is shown in FIG.
As the input signal to the FPGA board (20), the signal converted by the wireless communication board (30) as described above is input. As an output, a parallel MPEG2 signal is output from the digital output interface (41).

  Table 2 shows the number of FPGA slices used in each block of the FPGA board. This numerical value is an optimization of the algorithm for mounting on the platform according to the present invention.

  In the FPGA 1 (23), in addition to the channel estimator and the equalizer (231), each circuit such as a deinterleaver (232) and a Viterbi decoder (233) is configured, and finally a parallel MPEG2 from the RS decoder (234). The signal is output.

  As shown in FIG. 6, in the present invention, the FPGA 2 (24) in one of the channels of the FPGA board (20) inputs a received signal from the wireless communication board (30) and also receives a sin wave and a cos wave mixer ( 241), a Fourier transform processing unit (242), an automatic gain control (243), and other processing circuits are configured.

Then, an MPEG2 transport stream (TS) signal is input on the FPGA (61) (62) of the decoder board (60), and software for converting it into an HDTV or SDTV video signal and audio signal is inserted.
7 and 8 show basic block diagrams of software incorporated in the decoder board (60). Table 3 shows the number of logic elements (4818 out of 41250, 10705 out of 25660), the capacity of the MPU software, and Table 4 shows the basic functions of each FPGA (61) (62).

FIG. 7 is a block diagram of the FPGA 1 (61). The TS signals input from the input connectors CN4 (64) and CN6 (65) are multiplexed by the MUX (610) and separated by the Demux (611).
Here, as separation processing, the signal is separated into a PCR (Program Clock Reference) signal and an Audio PES (Audio Packetized Elementary Stream) signal.

The separated signal is sent to the SDRAM (67) in addition to the AAC decoder processing unit (66), which is the processing unit of the CPU, and the FPGA 2 (62), via the MPU1 interface (612). The MPU2 interface (613) controls reception of signals from the FPGA2 (62).
The signal sent to the AAC decoder processing unit (66) is output from the audio terminal (603) as audio.

On the other hand, the FPGA 2 (62) functions as a video decoder in the SD / HD format of MPEG2. That is, the decoder processing circuit (620) is configured by a program and outputs data (621) to the video encoder.
The video encoder circuit is mounted on the decoder board (60) and is realized by the CPU described above. Since this circuit is well known, it will be omitted.

  Using this software, it is also possible to specify a channel to be received from the CPU board (10) to the tuner via the serial bus interface (40) in the FPGA 2 (24).

In addition to the above embodiment, the TS signal input from the input connector CN4 (64) or the input connector CN6 (65) may be output from the TS signal external output (604) without performing signal processing.
In this case, the scrambled or encrypted TS signal is input to the input connector CN4 (64) or the input connector CN6 (65), and is output from the TS signal external output (604). A descrambler or an encryption / decryption device (not shown) is connected to the external output (604). These external devices are known devices and have a descrambler function or an encryption / decryption function.

  Then, the TS signal descrambled or decoded by these external devices is input to the input connector CN8 (63), and an image of a desired signal is output by the decoding circuit programmed in the FPGA1 (61) and FPGA2 (62). Decrypt.

The decoder board (60) of the present invention includes a flash memory slot (68). By inserting the flash memory into the slot (68), the programs of FPGA1 (61) and FPGA2 (62) can be installed. The CPU may be configured so that the program can be changed in the same manner. As the flash memory, any memory such as a compact flash (registered trademark) can be used.
In this way, the decoder board can perform various image decoding processes and can cope with different broadcasting systems.

  The decoder board described above can be provided separately from the software defined radio of the present invention. As described above, by using a programmable FPGA in the decoder circuit, it is possible to provide an image signal processing apparatus that supports various broadcasting systems.

Next, an example in which the above-described different communication system is introduced into the FPGA board and the CPU board in the software defined radio will be described.
First, in the W-CDMA software, a physical layer is installed on the FPGA board. Further, a codec processing unit is installed in the FPGA 1 (23), and a modulation / demodulation processing unit is installed in the FPGA 2 (24).

  The electronic circuit configuration at this time is shown in FIGS. FIG. 9 shows an electronic circuit composed of the FPGA 1 (23), and the function indicated by each block name in the figure is as shown in Table 5 below. Table 5 shows the number of slices necessary for the function.

  FIG. 10 shows an electronic circuit composed of the FPGA 2 (24), and the function indicated by each block name in the figure is as shown in Table 6 below. Table 6 shows the number of slices necessary for the function.

  As can be seen from the table, the capacity of the turbo decoder is large as the capacity of the physical layer because this software is compatible with HSDPA. From the above results, it can be seen that FPGA1 (23) requires an 8 million gate class FPGA and FPGA2 (24) requires a 6 million gate class FPGA.

On the other hand, a signal processing program related to the data link layer (second layer) and the network layer (third layer) is installed on the CPU board. Thereby, for example, input / output by the IP protocol becomes possible.
After being converted to the IP protocol, it can be connected to a personal computer or the like by an Ethernet (registered trademark) adapter provided in the apparatus, and can perform IP communication. The CPU board of the apparatus has second and third layers. It is a requirement to perform at least layer processing, and a processing circuit for processing more layers may be provided.

  The present invention is capable of switching between different communication systems. For example, when the W-CDMA is installed in the left-channel FPGA group, the IEEE802.11a wireless LAN system can be installed in the right-channel FPGA group. .

Specifically, as in the case of W-CDMA, a physical layer (a codec in FPGA1 and a modem in FPGA2) is installed in the FPGA, and a data link layer and a network layer are installed in the CPU. Since IEEE802.11a does not require codec processing, the FPGA 1 actually has only an interface with the CPU board.
FIG. 12 shows the configuration of software entering the FPGA 1 and FPGA 2 for IEEE802.11a, and Table 7 shows the contents of each block name and the number of FPGA slices to be used.

According to Table 7, FPGA2 requires 20000 slices, that is, 6 million gate class FPGAs, but FPGA1 has only 700 CPU slices because of the CPU interface only.
That is, it can be built with one 6 million gate class FPGA. In addition, common to W-CDMA and IEEE802.11a, quadrature modulation / demodulation is performed by digital signal processing.

  As the wireless communication board (30) connected to the FPGA board (20), for example, a board for 5 GHz band and a board for 2 GHz band are provided. The wireless communication board holds information such as a corresponding frequency band in advance, and notifies the type of the connected wireless communication board (30) through the serial interface (40). Also, information about the reception status such as the received signal level and the bit error rate can be notified through the interface (40).

The wireless communication board includes a frequency conversion circuit that performs frequency conversion between a radio frequency signal and an intermediate frequency signal or a baseband signal. The frequency conversion circuit performs frequency conversion by mixing with the local oscillation signal output from the frequency synthesizer. This technique is well known. Of course, an antenna (not shown) is attached to the wireless communication board.
The frequency of the local oscillation signal generated from the frequency synthesizer is instructed by a control signal from the FPGA board.

The intermediate frequency signal or baseband signal that is an analog signal is output by the DA converter (42) of the FPGA board at the time of transmission, and is transmitted from the wireless communication board to the AD converter (42) of the FPGA board at the time of reception. Is.
The FPGA board (20) associates a wireless communication system with the wireless communication board (30), and the CPU board (10), the FPGA board (20), and the wireless communication board (30) cooperate to perform wireless communication. I do.

The capacity comparison between the above-mentioned FPGA software for terrestrial digital broadcasting and the physical layer portion using W-CDMA and wireless LAN software, especially FPGA is performed. In both communication systems, the physical layer is composed of two FPGAs.
When the comparative evaluation is performed, the number of slices is W-CDMA> terrestrial digital> IEEE802.11a (wireless LAN).
This is because the turbo decoder used on the receiving side of W-CDMA is designed so as to be compatible with HSDPA and the like, and therefore a considerable number of slices are used.
If it is possible to process with the same capacity as the Viterbi decoder shown in Table 3, W-CDMA processing can be performed with almost the same amount of processing as software for receiving terrestrial digital broadcasts.

  In conclusion, if the size of the FPGA has a capacity that can be accommodated by the physical layer of W-CDMA (about 75000 slices), terrestrial digital broadcasting, IEEE802.11a wireless LAN, etc. can be accommodated. It is.

1 is an overall configuration diagram of a digital radio compatible software defined radio according to the present invention. 1 is a configuration diagram of a platform including a CPU board, an FPGA board, and a wireless communication board according to the present invention. It is a block diagram of the programmable signal processing apparatus of this invention. It is a block diagram of the central control signal processing apparatus of this invention. It is a block diagram of the image signal processing apparatus of this invention. It is a block diagram of the electronic circuit programmed in FPGA1 and 2 of a programmable signal processing apparatus at the time of digital broadcast reception. It is a block diagram of the electronic circuit programmed in FPGA1 of an image signal processing apparatus at the time of digital broadcast reception. It is a block diagram of the electronic circuit programmed in FPGA2 of an image signal processing apparatus at the time of digital broadcast reception. It is a block diagram of the electronic circuit programmed to FPGA1 at the time of W-CDMA communication. It is a block diagram of the electronic circuit programmed to FPGA2 at the time of W-CDMA communication. It is a block diagram of the electronic circuit programmed to the FPGA group at the time of IEEE802.11a communication.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Digital broadcasting-compatible software defined radio 2 Threshold comparison unit 3 Secondary candidate radio communication search unit 4 Wireless communication system switching unit 5 FPGA group 10 CPU board 11 Main CPU
12 Sub CPU
13 System bus 14 System bus 15 Connector 16 Connector 20 FPGA board 21 Left channel FPGA group 22 Right channel FPGA group 23 FPGA
24 FPGA
30 Wireless communication board 60 Decoder board

Claims (18)

A digital broadcast-compatible software defined radio comprising a central control signal processing device, a programmable signal processing device, a wireless communication board, and an image signal processing device,
The central control signal processor is
A system bus corresponding to each CPU together with a plurality of CPUs (Central Processing Units),
A memory connected to the system bus;
At least one of a network adapter unit, an audio codec processing unit, and a data transmission bus unit connected to the system bus,
A connection interface unit connected to the programmable signal processing device;
DPRAM (Dual Port RAM) shared by the plurality of CPUs,
The programmable signal processing device uses a programmable electronic element that can program an electronic circuit configuration,
Provided with two or more electronic element groups composed of a plurality of categorized programmable electronic elements, for each electronic element group,
An RF interface unit for communicating a control signal with a wireless communication board for managing wireless communication;
At least one of an AD conversion processing unit that digitally converts a signal from the wireless communication board and inputs the signal to the programmable electronic element or a DA conversion processing unit that converts the signal to the wireless communication board and outputs the analog signal;
A digital signal output unit for transmitting a digital signal to at least an image signal processing apparatus that performs image signal decoding processing;
A program interface unit for programming each programmable electronic element from the outside;
A clock input interface for inputting a clock from the outside;
A clock distribution unit that divides the input clock into clocks of a predetermined multiple and inputs the divided clocks to each electronic element group;
A connection interface unit with the central control signal processing device that controls at least the data link layer and network layer signal processing in the OSI hierarchical model,
While performing wireless communication of a predetermined communication system including at least a digital broadcasting system on a wireless communication board under the control of the central control signal processing device and the programmable signal processing device,
The image signal processing apparatus includes a digital signal input unit for inputting a signal from the digital signal output unit, and one or a plurality of programmable electronic elements capable of programming an electronic circuit configuration. Software broadcasting radio compatible with digital broadcasting, characterized in that image signal decoding processing is performed on an electronic element. In the configuration comprising a central processing element in the image signal processing device in the digital broadcast-compatible software defined radio,
The digital broadcasting-compatible software defined radio according to claim 1, wherein the central processing element performs at least signal processing related to sound included in the digital signal. The image signal processing apparatus in the digital broadcasting-compatible software defined radio,
A small storage medium reading unit for reading data from a small storage medium using a semiconductor storage element;
The digital broadcast compatible type according to claim 1 or 2, wherein the image decoding process is performed by reading and programming at least one of the program of the programmable electronic element or the central processing element stored in the small storage medium. Software defined radio. The image signal processing apparatus in the digital broadcasting-compatible software defined radio,
A configuration comprising two programmable electronic elements,
While the first programmable electronic element performs at least signal processing related to digital signal communication with the programmable signal processing device,
In order for the second programmable electronic element to perform at least the image signal decoding process,
The digital broadcast-compatible software defined radio according to any one of claims 1 to 3, wherein each program operates. In the programmable signal processing apparatus in the digital broadcast compatible software defined radio,
In the configuration including two programmable electronic elements for one electronic element group,
While the first programmable electronic element performs processing related to the codec in the predetermined communication method,
In order for the second programmable electronic element to perform processing related to modulation / demodulation in a predetermined communication method,
The digital broadcast-compatible software defined radio according to any one of claims 1 to 4, wherein each program operates. 6. The digital broadcast-compatible software defined radio according to claim 1, wherein the digital signal is a transport stream (TS) signal. In the configuration in which the image signal processing device according to claim 5 in the digital broadcasting-compatible software defined radio processes a transport stream signal (TS signal),
While the first programmable electronic element performs a process of separating (DEMUX) at least one of a PCR (Program Clock Reference) signal or an AUDIO PES (Audio Packetized Elementary Stream) signal from the TS signal,
The second programmable electronic element performs at least MPEG2 (Moving Pictures Experts Group 2) decoding processing.
The digital broadcasting-compatible software defined radio according to claim 5, wherein each program operates. In the image signal processing apparatus in the digital broadcast-compatible software defined radio,
With a plurality of digital signal input units,
The digital broadcast-compatible software defined radio according to any one of claims 1 to 7, wherein the first programmable electronic element performs a program operation so as to perform a multiplexing process and a separating process on a plurality of input digital signals. In the image signal processing apparatus in the digital broadcast-compatible software defined radio,
The plurality of digital signal input units are:
The digital broadcasting-compatible software defined radio according to claim 8, wherein digital signals from each electronic element group in the programmable signal processing apparatus according to claim 5 are input. In the image signal processing apparatus in the digital broadcast-compatible software defined radio,
A first digital signal input unit for inputting a scrambled signal or an encrypted signal;
A digital signal external output unit for outputting the input signal without signal processing;
10. A second digital signal input unit for inputting a signal descrambled or decrypted by a descrambler or an encryption / decryption device connected to the digital signal external output unit. Digital broadcast compatible software radio. An image signal processing apparatus capable of image signal decoding processing related to digital broadcasting, wherein at least a digital signal input unit for inputting a digital signal;
With one or more programmable electronic elements that can program the electronic circuit configuration,
An image signal processing apparatus characterized in that an image signal decoding process is performed on an input digital signal on the programmable electronic element. In the configuration including a central processing element in the image signal processing device,
The image signal processing apparatus according to claim 11, wherein the central processing element performs signal processing relating to at least sound included in the digital signal. The image signal processing device comprises:
A small storage medium reading unit for reading data from a small storage medium using a semiconductor storage element;
The image signal processing apparatus according to claim 11 or 12, wherein the image decoding process is performed by reading and programming at least one of the programmable electronic element and the central processing element stored in the small storage medium. . The image signal processing device comprises:
A configuration comprising two programmable electronic elements,
While the first programmable electronic element performs at least signal processing related to digital signal communication with an external digital signal output device such as a digital tuner,
In order for the second programmable electronic element to perform at least the image signal decoding process,
The image signal processing apparatus according to claim 11, wherein each program operates. The image signal processing apparatus according to claim 11, wherein the digital signal is a transport stream signal (TS signal). In the configuration in which the image signal processing device according to claim 14 processes a transport stream signal (TS signal),
While the first programmable electronic element performs a process of separating (DEMUX) at least one of a PCR (Program Clock Reference) signal or an AUDIO PES (Audio Packetized Elementary Stream) signal from the TS signal,
The second programmable electronic element performs at least MPEG2 (Moving Pictures Experts Group 2) decoding processing.
The image signal processing apparatus according to claim 14, wherein each program operation is performed. In the image signal processing apparatus,
With a plurality of digital signal input units,
The image signal processing apparatus according to claim 11, wherein the first programmable electronic element performs a program operation so as to perform a multiplexing process and a separating process on a plurality of input digital signals. In the image signal processing apparatus,
A first digital signal input unit for inputting a scrambled signal or an encrypted signal;
A digital signal external output unit for outputting the input signal without signal processing;
The digital signal input unit according to any one of claims 11 to 17, further comprising: a second digital signal input unit that inputs a signal descrambled or decrypted by a descrambler or an encryption / decryption device connected to the digital signal external output unit. Image signal processing apparatus.