JP2007128973A - Wiring structure of substrate - Google Patents

Wiring structure of substrate Download PDF

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JP2007128973A
JP2007128973A JP2005318572A JP2005318572A JP2007128973A JP 2007128973 A JP2007128973 A JP 2007128973A JP 2005318572 A JP2005318572 A JP 2005318572A JP 2005318572 A JP2005318572 A JP 2005318572A JP 2007128973 A JP2007128973 A JP 2007128973A
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wiring
power supply
substrate
supply layer
return path
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Shigemasa Oyamada
成聖 小山田
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Technology Alliance Group Inc
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Technology Alliance Group Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H01L2224/48228—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item the bond pad being disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15192—Resurf arrangement of the internal vias

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  • Parts Printed On Printed Circuit Boards (AREA)
  • Structure Of Printed Boards (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a wiring structure of a substrate that can ensure the transmission quality of a high-frequency signal in a substrate without multilayer structure. <P>SOLUTION: The wiring structure 100 wherein a plurality of integrated circuits can be mounted, includes a signal wiring 150 to connect integrated circuits each other, a first power supply layer 130 and a second power supply layer 140 which are arranged opposite to each other, and two sets of wiring 130a and 140a for a return path that are arranged nearly parallel to the signal wiring 150. Both terminals of the wiring 130a for a return path are connected to the first power supply layer (Vcc layer) 130, and both terminals of the wiring 140a for a return path are connected to the second power supply layer (Gnd layer) 140. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、基板の配線構造に関し、詳細には、高周波信号（高速信号）の伝送品質を確保することが可能な基板の配線構造に関する。   The present invention relates to a wiring structure of a substrate, and more particularly to a wiring structure of a substrate capable of ensuring transmission quality of a high-frequency signal (high-speed signal).

高周波信号を伝送する配線基板では、高周波信号の伝送品質を確保するために、特性インピーダンスやＥＭＩ（Ｅｌｅｃｔｒｏ Ｍａｇｎｅｔｉｃ Ｉｎｔｅｒｆｅｒｅｎｃｅ：電磁障害）の対策が行われている（例えば、特許文献１参照）。   In a wiring board that transmits a high-frequency signal, measures against characteristic impedance and EMI (Electro Magnetic Interference) are taken in order to ensure the transmission quality of the high-frequency signal (see, for example, Patent Document 1).

図４は、集積回路を搭載する有機基板の構造を示す部分断面斜視図である。同図に示す基板は、複数の層構造を有するビルト基板となっている。同図において、５０１は第１信号配線、５０２は第２信号配線を示しており、第１信号配線間５０１、５０２間には、第１絶縁層５０３、第１電源層（Ｇｎｄ層）５０４、第２絶縁層５０５、第２電源層（Ｖｃｃ層）５０６、および第３絶縁層５０７が順に積層されている。   FIG. 4 is a partial cross-sectional perspective view showing the structure of the organic substrate on which the integrated circuit is mounted. The substrate shown in the figure is a built substrate having a plurality of layer structures. In the figure, reference numeral 501 denotes a first signal wiring, and 502 denotes a second signal wiring. Between the first signal wirings 501 and 502, a first insulating layer 503, a first power supply layer (Gnd layer) 504, A second insulating layer 505, a second power supply layer (Vcc layer) 506, and a third insulating layer 507 are sequentially stacked.

同図に示すようなビルト基板では、電源層に絶縁層を介して信号配線を並走する構成とすることによって、信号配線の連続した特性インピーダンスを確保して、高周波信号伝送時の伝送品質を確保することができる。   In the built board as shown in the figure, the signal wiring runs parallel to the power supply layer through the insulating layer, so that the continuous characteristic impedance of the signal wiring is secured and the transmission quality at the time of high-frequency signal transmission is improved. Can be secured.

また、かかるビルト基板では、半導体回路中に存在するトランジスタをスイッチングする際に必要となるシンク電流、ソース電流、および貫通電流を、第１、第２電源層５０４、５０５および第１、第２電源層５０４、５０５間に形成された第２絶縁層５０５とで形成される寄生容量や外付けのバイパスキャパシタによって確保することができる。   Further, in such a built-in board, the sink current, the source current, and the through current required for switching the transistor existing in the semiconductor circuit are converted into the first and second power supply layers 504 and 505 and the first and second power supplies. It can be ensured by a parasitic capacitance formed by the second insulating layer 505 formed between the layers 504 and 505 or an external bypass capacitor.

また、かかるビルト基板では、信号配線５０１の高周波電流のリターン電流は第２電源層５０６に流れ、また、信号配線５０２の高周波電流のリターン電流は第１電源層５０４に流れるため、リターン電流の帰路を確保することができる。   In such a built-in board, the return current of the high-frequency current of the signal wiring 501 flows to the second power supply layer 506, and the return current of the high-frequency current of the signal wiring 502 flows to the first power supply layer 504. Can be secured.

しかしながら、小型・薄型化した半導体基板および１〜２層の有機基板は、多層構造をもつことができないため、以下のような問題がある。   However, since the semiconductor substrate reduced in size and thickness and the organic substrate having one or two layers cannot have a multilayer structure, there are the following problems.

図５は、単層構成の有機基板の構造を示す部分断面斜視図である。同図において、６０１は第１信号配線、６０２は絶縁層、６０３は第２信号配線を示している。多層構造をもつことができない基板の場合には、（１）信号配線の特性インピーダンスの連続性を確保することが難しい、（２）リターン電流の帰路を確保することが難しい、（３）電源ラインの低インピーダンス化が難しい等の問題があるため、高周波信号の伝送品質を確保することが困難であるという問題がある。   FIG. 5 is a partial cross-sectional perspective view showing the structure of a single layer organic substrate. In the figure, reference numeral 601 denotes a first signal wiring, 602 denotes an insulating layer, and 603 denotes a second signal wiring. In the case of a substrate that cannot have a multilayer structure, (1) it is difficult to ensure the continuity of the characteristic impedance of the signal wiring, (2) it is difficult to ensure the return path of the return current, (3) the power line Therefore, there is a problem that it is difficult to ensure the transmission quality of the high frequency signal.

特開２００２−３４４１４９号公報JP 2002-344149 A

本発明は、上記に鑑みてなされたものであって、多層構造を持たない基板において、高周波信号の伝送品質を確保することが可能な基板の配線構造を提供することを目的とする。   The present invention has been made in view of the above, and an object of the present invention is to provide a wiring structure of a substrate that can ensure the transmission quality of a high-frequency signal in a substrate that does not have a multilayer structure.

上述した課題を解決し、目的を達成するために、本発明は、複数の集積回路を搭載する基板の配線構造において、集積回路間を接続するための信号配線と、対向配置される第１電源層および第２電源層と、前記信号配線に略並行に配されたリターン・パス用配線と、を備え、前記リターン・パス用配線は、前記第１および第２電源層の少なくとも一方の電源層にその両終端が接続されており、前記信号配線と、前記リターン・パス用配線と、前記信号配線および前記リターン・パス用配線間に狭持される絶縁膜とで第１容量を形成し、前記第１電源層と、前記第２電源層と、前記第１電源層および前記第２電源層間に狭持される絶縁膜とで第２容量を形成したことを特徴とする。   In order to solve the above-described problems and achieve the object, the present invention provides a wiring structure of a substrate on which a plurality of integrated circuits are mounted, and a first power supply disposed opposite to the signal wiring for connecting the integrated circuits. And a return path wiring disposed substantially in parallel with the signal wiring, wherein the return path wiring is at least one power supply layer of the first and second power supply layers. Both ends thereof are connected to each other, and a first capacitor is formed by the signal wiring, the return path wiring, and an insulating film sandwiched between the signal wiring and the return path wiring, A second capacitor is formed by the first power supply layer, the second power supply layer, and an insulating film sandwiched between the first power supply layer and the second power supply layer.

また、本発明の好ましい態様によれば、前記リターン・パス用配線は、前記信号配線を挟んで一対に形成されており、一方のリターン・パス用配線の両終端は、前記第１電源層に接続されており、他方のリターン・パス用配線の両終端は、前記第２電源層に接続されていることが望ましい。   According to a preferred aspect of the present invention, the return path wiring is formed in a pair with the signal wiring interposed therebetween, and both ends of one return path wiring are connected to the first power supply layer. It is desirable that both ends of the other return path wiring are connected to the second power supply layer.

また、本発明の好ましい態様によれば、前記第１電源層は、Ｖｃｃ層であり、前記第２電源層は、Ｇｎｄ層であることが望ましい。   According to a preferred aspect of the present invention, it is preferable that the first power supply layer is a Vcc layer and the second power supply layer is a Gnd layer.

また、本発明の好ましい態様によれば、前記信号配線は高周波信号用の信号配線であることが望ましい。   According to a preferred aspect of the present invention, it is desirable that the signal wiring is a signal wiring for high frequency signals.

また、本発明の好ましい態様によれば、前記基板は、単層構造であることが望ましい。   According to a preferred aspect of the present invention, it is desirable that the substrate has a single layer structure.

また、本発明の好ましい態様によれば、前記基板は、有機基板、半導体基板、またはセラミック基板であることが望ましい。   According to a preferred aspect of the present invention, the substrate is preferably an organic substrate, a semiconductor substrate, or a ceramic substrate.

本発明によれば、複数の集積回路を搭載する基板の配線構造において、集積回路間を接続するための信号配線と、対向配置される第１電源層および第２電源層と、前記信号配線に略並行に配されたリターン・パス用配線と、を備え、前記リターン・パス用配線は、前記第１および第２電源層の少なくとも一方の電源層にその両終端が接続されており、前記信号配線と、前記リターン・パス用配線と、前記信号配線および前記リターン・パス用配線間に狭持される絶縁膜とで第１容量を形成し、前記第１電源層と、前記第２電源層と、前記第１電源層および前記第２電源層間に狭持される絶縁膜とで第２容量を形成することとしたので、多層構造を持たない基板の配線構造において、高周波信号の伝送品質を確保することが可能となる。   According to the present invention, in a wiring structure of a substrate on which a plurality of integrated circuits are mounted, the signal wiring for connecting the integrated circuits, the first power supply layer and the second power supply layer arranged opposite to each other, and the signal wiring Return path wiring arranged substantially in parallel, the return path wiring having both ends connected to at least one power supply layer of the first and second power supply layers, and the signal The wiring, the return path wiring, and the insulating film sandwiched between the signal wiring and the return path wiring form a first capacitor, and the first power supply layer and the second power supply layer And the insulating film sandwiched between the first power supply layer and the second power supply layer, the second capacitor is formed, so that the transmission quality of the high-frequency signal is improved in the wiring structure of the substrate having no multilayer structure. It can be secured.

以下に、この発明の最良の形態につき図面を参照しつつ詳細に説明する。なお、この実施例によりこの発明が限定されるものではない。また、下記実施例における構成要素には、当業者が容易に想定できるものまたは実質的に同一のものが含まれる。   Hereinafter, the best mode of the present invention will be described in detail with reference to the drawings. Note that the present invention is not limited to the embodiments. In addition, constituent elements in the following embodiments include those that can be easily assumed by those skilled in the art or those that are substantially the same.

図１を参照して、実施例に係る基板の配線構造を説明する。本実施例に係る基板は、各種の集積回路を搭載する場合に適用可能である。集積回路としては、例えば、メモリ、マイクロプロセッサ、ＤＳＰ等である。   With reference to FIG. 1, the wiring structure of the board | substrate which concerns on an Example is demonstrated. The substrate according to the present embodiment is applicable when various types of integrated circuits are mounted. Examples of the integrated circuit include a memory, a microprocessor, and a DSP.

図１−１は、本発明に係る基板の配線構造を説明するための模式図である。図１−２は、図１−１のＡ−Ａ断面構成を示す図、図１−３は、図１−２のＢ−Ｂ断面構成を示す図、図１−４は、図１−１のＣ−Ｃ断面構成を示す図、図１−５は、図１−１の基板の配線構造において、第１電源層、第２電源層、信号配線、およびリターン・パス用配線の平面構成を示す模式図である。   FIG. 1-1 is a schematic view for explaining a wiring structure of a substrate according to the present invention. 1-2 is a diagram showing a cross-sectional configuration along line AA in FIG. 1-1, FIG. 1-3 is a diagram showing a cross-sectional configuration along line BB in FIG. 1-2, and FIG. FIG. 1-5 is a diagram showing a cross-sectional configuration along the line C-C of FIG. 1A, and FIG. It is a schematic diagram shown.

図１−１〜図１−５において、１００は、実施例に係る基板の配線構造を示している。同図に示す基板は、単層構造となっている。同図において、１０１は基板を示しており、この基板１０１は、本実施例では半導体シリコン基板である。本発明は、半導体シリコン基板に限られるものではなく、絶縁膜を形成した有機基板やセラミック基板にも適用可能である。１１０、１２０は、基板１０１に実装されたＩＣチップの一部を示している。ＩＣチップ１１０は、ワイヤボンディング用のパット１１１ａ、１１１ｂ、１１１ｃを備えている。また、ＩＣチップ１２０は、半田ボール用のパット１２１ａ、１２１ｂ、１２１ｃを備えている。   1-1 to 1-5, reference numeral 100 denotes a wiring structure of a substrate according to the embodiment. The substrate shown in the figure has a single layer structure. In the figure, reference numeral 101 denotes a substrate, and this substrate 101 is a semiconductor silicon substrate in this embodiment. The present invention is not limited to a semiconductor silicon substrate, but can also be applied to an organic substrate or a ceramic substrate on which an insulating film is formed. Reference numerals 110 and 120 denote part of the IC chip mounted on the substrate 101. The IC chip 110 includes pads 111a, 111b, and 111c for wire bonding. In addition, the IC chip 120 includes solder ball pads 121a, 121b, and 121c.

基板１０１には、絶縁膜１０２が形成されている。また、基板１０１には、絶縁膜１０２を挟んで、第１電源層（Ｖｃｃ層）１３０および第２電源層（Ｇｎｄ層）１４０が対向して配置されている。ＩＣチップ１１０のパット１１１ａ、１１１ｃは、第１電源層１３０のパット１３１ａ、第２電源層１４０のパット１４１ｃとそれぞれボンディングワイヤＢＷで接続されている。また、ＩＣチップ１２０のパット１２１ａ、１２１ｃは、第１電源層１３０のパット１３２ａ、第２電源層１４０のパット１４２ｃとそれぞれ半田ボールＨＢで接続されている。   An insulating film 102 is formed on the substrate 101. A first power supply layer (Vcc layer) 130 and a second power supply layer (Gnd layer) 140 are disposed on the substrate 101 so as to face each other with the insulating film 102 interposed therebetween. The pads 111a and 111c of the IC chip 110 are connected to the pad 131a of the first power supply layer 130 and the pad 141c of the second power supply layer 140 respectively by bonding wires BW. The pads 121a and 121c of the IC chip 120 are connected to the pads 132a of the first power supply layer 130 and the pads 142c of the second power supply layer 140 by solder balls HB, respectively.

また、図１−２〜図１−５に示すように、ＩＣチップ１１０、１２０間には、第２電源層１４０と略同一面上に、ＩＣチップ１１０、１２０間で高周波信号を伝送するための複数の信号配線１５０が形成されている。この信号配線１５０の両端は、第１および第２電源層１３０、１４０に挟まれる位置に形成されている。信号配線１５０の両端には、それぞれワイヤボンディング用のパット１５１ｂ、半田ボール用のパット１５２ｂが形成されている。ＩＣチップ１１０のパット１１１ｂは、信号配線１５０のパット１５１ｂとボンディングワイヤＢＷで接続されている。また、ＩＣチップ１２０のパット１２１ｂは、信号配線１５０のパット１５２ｂと半田ボールＨＢで接続されている。   Also, as shown in FIGS. 1-2 to 1-5, a high-frequency signal is transmitted between the IC chips 110 and 120 between the IC chips 110 and 120 on the substantially same plane as the second power supply layer 140. A plurality of signal wirings 150 are formed. Both ends of the signal wiring 150 are formed at positions sandwiched between the first and second power supply layers 130 and 140. At both ends of the signal wiring 150, a wire bonding pad 151b and a solder ball pad 152b are formed, respectively. The pad 111b of the IC chip 110 is connected to the pad 151b of the signal wiring 150 by a bonding wire BW. The pad 121b of the IC chip 120 is connected to the pad 152b of the signal wiring 150 by the solder ball HB.

図１−５に示すように、信号配線１５０の連続した特性インピーダンスを確保するために、各信号配線１５０を挟んで、信号配線１５０に対して略並行（略等間隔）に一対のリターン・パス用配線１３０ａ、１４０ｂが形成されている。リターン・パス用配線１３０ｂの両終端は第１電源層１３０に接続されている。また、リターン・パス用配線１４０ｂの両終端は第２電源層１４０に接続されている。   As shown in FIG. 1-5, in order to ensure continuous characteristic impedance of the signal wiring 150, a pair of return paths are provided substantially parallel (substantially equidistantly) to the signal wiring 150 with each signal wiring 150 interposed therebetween. Wiring lines 130a and 140b are formed. Both ends of the return path wiring 130 b are connected to the first power supply layer 130. Further, both ends of the return path wiring 140 b are connected to the second power supply layer 140.

図２は、図１−５の基板の配線構造の等価回路を示す図である。同図において、Ｃ0は、第１電源層（Ｖｃｃ層）１３０と、第２電源層（Ｇｎｄ層）１４０と、および第１電源層１３０と第２電源層１４０間に狭持される絶縁膜１０２とで形成される寄生容量（第２容量）を示している。Ｃ1は、信号配線１５０、リターン・パス用配線１３０ａ、および信号配線１５０とリターン・パス用配線１３０ａ間に狭持される絶縁膜１０２とで形成される容量（第１容量）を示している。Ｃ2は、信号配線１５０、リターン・パス用配線１４０ａ、および信号配線１５０とリターン・パス用配線１４０ａ間に狭持される絶縁膜１０２で形成される容量（第１容量）を示している。Ｌ0は、信号配線１５０のインピーダンス成分、Ｌ1は、リターン・パス用配線１３０ａのインピーダンス成分、Ｌ2はリターン・パス用配線１４０ａのインピーダンス成分を示している。   FIG. 2 is a diagram showing an equivalent circuit of the wiring structure of the substrate of FIGS. 1-5. In the figure, C0 is a first power supply layer (Vcc layer) 130, a second power supply layer (Gnd layer) 140, and an insulating film 102 sandwiched between the first power supply layer 130 and the second power supply layer 140. The parasitic capacitance (second capacitance) formed by C1 indicates a capacitance (first capacitance) formed by the signal wiring 150, the return path wiring 130a, and the insulating film 102 sandwiched between the signal wiring 150 and the return path wiring 130a. C2 indicates a capacitance (first capacitance) formed by the signal wiring 150, the return path wiring 140a, and the insulating film 102 sandwiched between the signal wiring 150 and the return path wiring 140a. L0 represents the impedance component of the signal wiring 150, L1 represents the impedance component of the return path wiring 130a, and L2 represents the impedance component of the return path wiring 140a.

同図に示すように、パット１５１ｂ、１５２ｂで閉じられた信号配線１５０は、等間隔で絶縁膜１０２を挟んで配置されたリターン・パス用配線１３０ａ、１４０ａにより形成される容量Ｃ1、Ｃ2によって、特性インピーダンスの連続性を確保することができる。また、大きな面積を有する第１電源層１３０および第２電源層１４０間には、大きな寄生容量Ｃ0が形成されるため、第１電源層１３０と第２電源層１４０間を低インピーダンスとすることができる。これにより、リターン・パス用配線１３０ａ、１４０ａの両終端においても、特性インピーダンスの連続性を確保することができる。また、ＩＣチップ１１０、１２０に搭載されるトランジスタには、第１、第２電源層１３０、１４０から低周波数から高周波数動作に亘って低インピーダンスの電源が供給されるため、入力信号がローレベルからハイレベルに変化する瞬間のソース−ドレイン電流による電源ノイズを防止することができる。   As shown in the figure, the signal wiring 150 closed by the pads 151b and 152b is constituted by capacitors C1 and C2 formed by return path wirings 130a and 140a arranged with the insulating film 102 sandwiched at equal intervals. The continuity of characteristic impedance can be ensured. In addition, since a large parasitic capacitance C0 is formed between the first power supply layer 130 and the second power supply layer 140 having a large area, the impedance between the first power supply layer 130 and the second power supply layer 140 may be reduced. it can. Thereby, the continuity of the characteristic impedance can be ensured at both ends of the return path wirings 130a and 140a. In addition, since the low impedance power is supplied from the first and second power supply layers 130 and 140 to the high frequency operation from the first and second power supply layers 130 and 140 to the transistors mounted on the IC chips 110 and 120, the input signal is low level. It is possible to prevent power supply noise due to the source-drain current at the moment when the current level changes from high to low.

このように、パット１３１ａ、１３２ａ、１４１ｃ、１４２ｃで閉じられた領域（第１電源層１３０、第２電源層１４０、信号配線１５０、およびリターン・パス用配線１３０ａ、１４０ａで形成されるループ）を、低インピーダンスの閉ループとすることができるため、シンク電流およびソース電流の流れと、信号配線１５０に流れる高周波電流のリターン電流の帰路をこの閉ループ上に形成できるため、電源ノイズやリターン電流を輻射源とするＥＭＩの発生を防止することができる。   In this way, the region closed by the pads 131a, 132a, 141c, and 142c (the loop formed by the first power supply layer 130, the second power supply layer 140, the signal wiring 150, and the return path wirings 130a and 140a). Since the low impedance closed loop can be used, the sink current and the source current flow and the return path of the high frequency current flowing through the signal wiring 150 can be formed on the closed loop. EMI can be prevented.

上記実施例によれば、複数の集積回路を搭載可能な基板の配線構造において、集積回路間を接続するための信号配線１５０と、対向配置される第１電源層１３０および第２電源層１４０と、信号配線１５０に略並行に配されたリターン・パス用配線１３０ａ、１４０ａとを備え、リターン・パス用配線１３０ａの両終端を第１電源層（Ｖｃｃ層）１３０に接続し、リターン・パス用配線１４０ａの両終端を第２電源層（Ｇｎｄ層）１４０に接続し、また、信号配線１５０と、リターン・パス用配線１３０ａと、信号配線１５０およびリターン・パス用配線１３０ａ間に狭持される絶縁膜１０２とで容量Ｃ1、（第１容量）を形成し、また、信号配線１５０と、リターン・パス用配線１４０ａと、信号配線１５０およびリターン・パス用配線１４０ａ間に狭持される絶縁膜１０２とで容量Ｃ2（第１容量）を形成し、また、第１電源層１３０と、第２電源層１４０と、第１電源層１３０および第２電源層１４０間に狭持される絶縁膜１０２とで寄生容量Ｃ0（第２容量）を形成することとしたので、第１電源層１３０、第２電源層１４０、信号配線１５０、およびリターン・パス用配線１３０ａ、１４０ａにより、低インピーダンスの狭いループを構成することができ、信号配線の特性インピーダンスの連続性の確保・リターン電流の帰路の確保・電源ノイズの防止が可能となり、多層構造を持たない基板の配線構造において、高周波信号の伝送品質を確保することが可能となる。   According to the above embodiment, in the wiring structure of the substrate on which a plurality of integrated circuits can be mounted, the signal wiring 150 for connecting the integrated circuits, the first power supply layer 130 and the second power supply layer 140 that are arranged to face each other, Return path wirings 130a and 140a arranged substantially in parallel with the signal wiring 150, both ends of the return path wiring 130a are connected to the first power supply layer (Vcc layer) 130, and the return path wiring Both ends of the wiring 140a are connected to the second power supply layer (Gnd layer) 140, and are sandwiched between the signal wiring 150, the return path wiring 130a, the signal wiring 150, and the return path wiring 130a. A capacitance C1, (first capacitance) is formed with the insulating film 102, and the signal wiring 150, the return path wiring 140a, the signal wiring 150, and the return path wiring 14 are formed. A capacitor C2 (first capacitor) is formed by the insulating film 102 sandwiched between 0a, and the first power supply layer 130, the second power supply layer 140, the first power supply layer 130, and the second power supply layer 140 are formed. Since the parasitic capacitance C0 (second capacitance) is formed with the insulating film 102 sandwiched therebetween, the first power supply layer 130, the second power supply layer 140, the signal wiring 150, and the return path wiring 130a. 140a can form a low-impedance narrow loop, ensuring the continuity of the characteristic impedance of the signal wiring, ensuring the return path of the return current, and preventing power supply noise, and wiring the board without a multilayer structure In the structure, it is possible to ensure the transmission quality of the high frequency signal.

（変形例）
図３を参照して、変形例に係る基板の配線構造を説明する。上記実施例では、信号配線１５０に対して、一対のリターン・パス用配線１３０ａ、１４０ａを略並行に配置する構成としたが、各信号配線１５０に対して配置するリターン・パス用配線は、必ずしも複数本必要ではなく、１本としても同様の作用効果を得ることができる。変形例に係る基板の実装構造は、各信号配線１５０に対して、一本のリターン・パス用配線を配置する構成である。 (Modification)
With reference to FIG. 3, the wiring structure of the board | substrate which concerns on a modification is demonstrated. In the above embodiment, the pair of return path wirings 130a and 140a are arranged substantially in parallel with the signal wiring 150. However, the return path wiring to be arranged with respect to each signal wiring 150 is not necessarily limited. A plurality of lines are not necessary, and the same function and effect can be obtained with a single line. The substrate mounting structure according to the modification is configured such that one return path wiring is arranged for each signal wiring 150.

図３−１は、変形例１に係る基板の配線構造を示す図である。図３−１において、図１−５と同等機能を有する部分には同一符号を付してある。変形例１に係る基板の配線構造３００は、図３−１に示すように、信号配線１５０に対して、リターン・パス用配線１４０ａのみを略並行に配置した構成である。リターン・パス用配線１４０ａの両終端は、第２電源層（Ｇｎｄ層）１４０に接続されている。   FIG. 3A is a diagram illustrating a wiring structure of the substrate according to the first modification. 3A, parts having the same functions as those in FIG. As shown in FIG. 3A, the board wiring structure 300 according to the first modification has a configuration in which only the return path wiring 140 a is arranged substantially in parallel with the signal wiring 150. Both ends of the return path wiring 140 a are connected to the second power supply layer (Gnd layer) 140.

図３−２は、変形例２に係る基板の配線構造を示す図である。図３−２において、図１−５と同等機能を有する部分には同一符号を付してある。変形例２に係る基板の配線構造４００は、図３−２に示すように、信号配線１５０に対して、リターン・パス用配線１３０ａのみを略並行に配置した構成である。リターン・パス用配線１３０ａの両終端は、第１電源層（Ｖｃｃ層）１３０に接続されている。   FIG. 3B is a diagram illustrating a wiring structure of the substrate according to the second modification. 3B, parts having the same functions as those in FIG. As shown in FIG. 3B, the wiring structure 400 of the substrate according to the modification 2 has a configuration in which only the return path wiring 130a is arranged substantially in parallel with the signal wiring 150. Both ends of the return path wiring 130 a are connected to the first power supply layer (Vcc layer) 130.

変形例に係る基板の配線構造によれば、各信号配線１５０に対して１本のリターン・パス用配線１３０ａまたは１４０ａを配置しているので、配線エリアを省スペース化でき、基板のレイアウトの自由度を向上させることができる。   According to the wiring structure of the substrate according to the modification, since one return path wiring 130a or 140a is arranged for each signal wiring 150, the wiring area can be saved and the layout of the substrate can be freely set. The degree can be improved.

本発明に係る基板の配線構造は、高周波信号の伝送路として使用する場合に特に有用である。   The wiring structure of the substrate according to the present invention is particularly useful when used as a transmission path for high-frequency signals.

本発明の実施例に係る基板の配線構造を説明するための模式図である。It is a schematic diagram for demonstrating the wiring structure of the board | substrate which concerns on the Example of this invention. 図１−１のＡ−Ａ断面構成を示す図である。It is a figure which shows the AA cross-section structure of FIGS. 1-1. 図１−１のＢ−Ｂ断面構成を示す図である。It is a figure which shows the BB cross-section structure of FIGS. 1-1. 図１−１のＣ−Ｃ断面構成を示す図である。It is a figure which shows CC cross-section structure of FIGS. 1-1. 図１−１の基板の配線構造において、第１電源層、第２電源層、信号配線、およびリターン・パス用配線の平面構成を示す模式図である。FIG. 1B is a schematic diagram illustrating a planar configuration of a first power supply layer, a second power supply layer, a signal wiring, and a return path wiring in the wiring structure of the substrate of FIG. 1-1. 図１−５の基板の配線構造の等価回路を示す図である。It is a figure which shows the equivalent circuit of the wiring structure of the board | substrate of FIGS. 1-5. 変形例１に係る基板の配線構造を説明するための模式図である。10 is a schematic diagram for explaining a wiring structure of a substrate according to Modification 1. FIG. 変形例２に係る基板の配線構造を説明するための模式図である。10 is a schematic diagram for explaining a wiring structure of a substrate according to Modification 2. FIG. 集積回路を搭載する有機基板の構造を示す部分断面斜視図である。It is a fragmentary sectional perspective view which shows the structure of the organic substrate which mounts an integrated circuit. 単層構成の有機基板の構造を示す部分断面斜視図である。It is a fragmentary sectional perspective view which shows the structure of the organic substrate of a single layer structure.

符号の説明Explanation of symbols

１００ 基板の配線構造
１０１ 基板
１０２ 絶縁層
１１０ ＩＣチップ
１１１ａ、１１１ｂ、１１１ｃ パット
１２０ ＩＣチップ
１２１ａ、１２１ｂ、１２１ｃ パット
１３０ 第１電源層（Ｖｃｃ層）
１３０ａ リターン・パス用配線
１３１ａ、１３２ａ パット
１４０ 第２電源層（Ｇｎｄ層）
１４１ｃ、１４２ｃ パット
１５０ 信号配線
１５１ｂ、１５２ｂ パット
３００、４００ 基板の配線構造
５０１ 第１信号配線
５０２ 第２信号配線
５０３ 第１絶縁層
５０４ 第１電源層（Ｇｎｄ層）
５０５ 第２絶縁層
５０６ 第２電源層（Ｖｃｃ層）
５０７ 第３絶縁層
６０１ 第１信号配線
６０２ 絶縁層
６０３ 第２信号配線 DESCRIPTION OF SYMBOLS 100 Substrate wiring structure 101 Substrate 102 Insulating layer 110 IC chip 111a, 111b, 111c pad 120 IC chip 121a, 121b, 121c pad 130 First power supply layer (Vcc layer)
130a Return path wiring 131a, 132a pad 140 Second power supply layer (Gnd layer)
141c, 142c pad 150 signal wiring 151b, 152b pad 300, 400 substrate wiring structure 501 first signal wiring 502 second signal wiring 503 first insulating layer 504 first power supply layer (Gnd layer)
505 Second insulating layer 506 Second power supply layer (Vcc layer)
507 Third insulating layer 601 First signal wiring 602 Insulating layer 603 Second signal wiring

Claims (6)

複数の集積回路を搭載可能な基板の配線構造において、
集積回路間を接続するための信号配線と、
対向配置される第１電源層および第２電源層と、
前記信号配線に略並行に配されたリターン・パス用配線と、
を備え、
前記リターン・パス用配線は、前記第１および第２電源層の少なくとも一方の電源層にその両終端が接続されており、
前記信号配線と、前記リターン・パス用配線と、前記信号配線および前記リターン・パス用配線間に狭持される絶縁膜とで第１容量を形成し、
前記第１電源層と、前記第２電源層と、前記第１電源層および前記第２電源層間に狭持される絶縁膜とで第２容量を形成することを特徴とする基板の配線構造。 In the wiring structure of the substrate that can mount multiple integrated circuits,
Signal wiring for connecting the integrated circuits;
A first power supply layer and a second power supply layer disposed opposite to each other;
A return path wiring arranged substantially parallel to the signal wiring;
With
The return path wiring has both ends connected to at least one of the first and second power supply layers,
A first capacitor is formed by the signal wiring, the return path wiring, and the insulating film sandwiched between the signal wiring and the return path wiring,
A wiring structure of a substrate, wherein a second capacitor is formed by the first power supply layer, the second power supply layer, and an insulating film sandwiched between the first power supply layer and the second power supply layer. 前記リターン・パス用配線は、前記信号配線を挟んで一対に形成されており、
一方のリターン・パス用配線の両終端は、前記第１電源層に接続されており、他方のリターン・パス用配線の両終端は、前記第２電源層に接続されていることを特徴とする請求項１に記載の基板の配線構造。 The return path wiring is formed in a pair across the signal wiring,
Both ends of one return path wiring are connected to the first power supply layer, and both ends of the other return path wiring are connected to the second power supply layer. The wiring structure of the board according to claim 1. 前記第１電源層は、Ｖｃｃ層であり、前記第２電源層は、Ｇｎｄ層であることを特徴とする請求項１に記載の基板の配線構造。   2. The wiring structure of a substrate according to claim 1, wherein the first power supply layer is a Vcc layer and the second power supply layer is a Gnd layer. 前記信号配線は高周波信号用の信号配線であることを特徴とする請求項１〜請求項３のいずれか１つに記載の基板の配線構造。   4. The wiring structure for a substrate according to claim 1, wherein the signal wiring is a signal wiring for high-frequency signals. 前記基板は、単層構造であることを特徴とする請求項１〜請求項４のいずれか１つに記載の基板の配線構造。   The wiring structure of a substrate according to any one of claims 1 to 4, wherein the substrate has a single layer structure. 前記基板は、有機基板、半導体基板、またはセラミック基板であることを特徴とする請求項１〜請求項５のいずれか１つに記載の基板の配線構造。   The substrate wiring structure according to claim 1, wherein the substrate is an organic substrate, a semiconductor substrate, or a ceramic substrate.
JP2005318572A 2005-11-01 2005-11-01 Wiring structure of substrate Pending JP2007128973A (en)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11298150A (en) * 1998-04-16 1999-10-29 Sony Corp Multilayered printed board
JP2000223799A (en) * 1999-02-02 2000-08-11 Toshiba Corp Wiring board and its manufacture
JP2003133747A (en) * 2001-10-22 2003-05-09 Nec Corp Multilayered printed wiring board
JP2003347693A (en) * 2002-05-24 2003-12-05 Toshiba Corp Interface substrate and display device
JP2005236268A (en) * 2004-01-19 2005-09-02 Matsushita Electric Ind Co Ltd Multilayer printed board

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11298150A (en) * 1998-04-16 1999-10-29 Sony Corp Multilayered printed board
JP2000223799A (en) * 1999-02-02 2000-08-11 Toshiba Corp Wiring board and its manufacture
JP2003133747A (en) * 2001-10-22 2003-05-09 Nec Corp Multilayered printed wiring board
JP2003347693A (en) * 2002-05-24 2003-12-05 Toshiba Corp Interface substrate and display device
JP2005236268A (en) * 2004-01-19 2005-09-02 Matsushita Electric Ind Co Ltd Multilayer printed board

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