JP2007126748A - METHOD FOR PRODUCING HIGH-PURITY Ta MATERIAL FOR SEMICONDUCTOR DEVICE - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for producing a high-purity Ta material for semiconductor devices, which can enhance in-plane uniformity of thickness of a TaN film formed by a reactive sputtering process. <P>SOLUTION: The method for producing the high-purity Ta material for semiconductor devices comprises a step of forging a high-purity Ta ingot from two or more directions, a step of subjecting the ingot to vacuum heat treatment at least twice in the course of the forging step, a step of cold-rolling the Ta material having been subjected to the forging step and the vacuum heat treatment step, and a step of subjecting the cold-rolled Ta material to a recrystallization heat treatment. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a method for producing a high-purity Ta material for a semiconductor device suitable for forming a barrier layer of a Cu wiring used for a semiconductor element or the like.

  In recent years, the semiconductor industry represented by LSI has been progressing rapidly. In semiconductor devices such as DRAMs of 256 Mbit or more, high-speed logic, and system LSIs, the precision required for microfabrication technology is increasing more and more as high integration, high reliability, and high functionality progress. With the increase in the density and speed of such integrated circuits, the width of metal wiring formed mainly of Al or Cu is becoming 0.13 μm or less.

  In order to operate an integrated circuit at high speed, it is essential to reduce the resistance of Al wiring and Cu wiring. In the conventional wiring structure, it is common to reduce the wiring resistance by increasing the thickness of the wiring. However, in semiconductor devices that are further highly integrated and densified, the coverage of the insulating film formed on the wiring when using the conventional laminated structure deteriorates, and naturally the yield of the device also decreases. There is a need to improve the wiring technology itself.

  Therefore, dual damascene (DD) wiring technology, which is different from the conventional wiring technology, has been applied. In the DD technology, a metal mainly composed of Al or Cu as a wiring material is formed on a wiring groove formed in advance in a base film using a sputtering method, a CVD method, or the like, and poured into the groove by heat treatment (reflow). In this technique, excess wiring metal is removed by a CMP (Chemical Mechanical Polishing) method or the like.

As a wiring material used in the semiconductor device as described above, Cu having a resistivity lower than that of Al is becoming mainstream. Since Cu wiring is superior in electromigration resistance compared to Al wiring, Cu wiring will be essential in future high-speed devices. When such Cu wiring is applied, it is necessary to provide a barrier metal layer for the purpose of preventing diffusion of Cu into Si. Although TiN has generally been used as a barrier metal for semiconductor devices, TaN obtained by reactive sputtering in a mixed gas of Ar and N ₂ using a Ta target as a barrier material for Cu wiring. Membranes are drawing attention. The TaN film is thermally stable and is an effective barrier material for preventing diffusion of Cu into Si.

  On the other hand, the shape of wiring grooves, holes, and the like has an aspect ratio of more than 4, for example, as the wiring density increases and the design rules become finer. In order to cope with a semiconductor device having such a wiring groove or the like, it is necessary to improve the accuracy when forming a TaN film as a barrier metal layer by reactive sputtering. For this reason, collimation sputtering, long-distance sputtering, low-pressure sputtering, and recently, bias sputtering, etc. have been incorporated to improve the TaN film formation accuracy.

  However, in the reactive sputtering using the conventional Ta target, there is a problem that it is difficult to control the in-plane uniformity of the TaN film thickness to 5% or less with an 8-inch Si wafer. Si wafers are becoming larger, and if 12-inch Si wafers become more common in the future, the in-plane uniformity of the TaN film thickness is likely to be further reduced. For this reason, the Ta target is required to further improve the in-plane uniformity of the film thickness.

Conventionally, regarding the in-plane uniformity of the TaN film thickness, for example, sputtering target made of high-purity Ta containing nitrogen (see Patent Document 1), sputtering in which the crystal orientation of the target made of high-purity TaN and variations thereof are controlled. Targets (see Patent Documents 2 and 3) have been proposed, but sufficient results are not always obtained with these targets. As described above, there are cases where the in-plane uniformity of the TaN film thickness cannot be sufficiently increased even with an 8-inch Si wafer.
JP 2000-323432 A JP 2000-323433 A JP 2000-323434 A

  An object of the present invention is to produce a high-purity Ta material for a semiconductor device that can further improve the in-plane uniformity of the film thickness when a TaN film or the like as a barrier layer is formed by reactive sputtering. It is to provide a method.

  The method for producing a high-purity Ta material for semiconductor devices according to the present invention includes a step of producing a high-purity Ta ingot, a step of forging the high-purity Ta ingot from two or more directions, and a midway of the forging step. A step of performing vacuum heat treatment twice or more, a step of cold rolling the Ta material that has undergone the forging step and the vacuum heat treatment step, and a step of subjecting the Ta material that has undergone the cold rolling step to a recrystallization heat treatment. It is characterized by comprising.

  According to the manufacturing method of the present invention, it is possible to obtain a high-purity Ta material for a semiconductor device capable of obtaining a sputtered film (TaN film or the like) excellent in in-plane film thickness uniformity with good reproducibility. Therefore, by using such a sputtering target made of a high-purity Ta material for semiconductor devices, for example, a TaN film effective as a barrier layer of a Cu wiring film can be stably formed with a high yield.

  Hereinafter, modes for carrying out the present invention will be described. The method for producing a high-purity Ta material for semiconductor devices according to the present invention is a method for producing a high-purity Ta material used for forming a sputtering target, and the high-purity Ta material comprises a barrier layer of a semiconductor device, particularly Cu or a Cu alloy. It is suitably used for forming a TaN film useful as a barrier layer for a wiring film. Here, the high-purity Ta material constituting the sputtering target preferably has a purity of 99.99% or more, for example, in consideration of the intended use of a barrier layer of a semiconductor device.

  The purity of Ta mentioned here is a value obtained by subtracting the total content of Fe, Ni, Cr, W, Mo, Nb, Si, Al, Na and K as impurity elements from 100%, that is, [100% − ( Fe% + Ni% + Cr% + W% + Mo% + Nb% + Si% + Al% + Na% + K%)]. When the total content of the impurity elements exceeds 100 ppm, the specific resistance of the obtained film becomes too high, and the characteristics as a wiring film, for example, deteriorate. The purity of the high-purity Ta material constituting the sputtering target is more preferably 99.995% or more.

  In the sputtering target (Ta target) made of the high-purity Ta material as described above, the variation in Vickers hardness over the entire sputtering surface of the target is controlled to 20% or less. Based on such hardness variation control of the Ta target, it is possible to improve the in-plane uniformity of the thickness of the TaN film reactively sputtered using the Ta target.

That is, reactive sputtering using a Ta target is performed in, for example, a mixed gas atmosphere of Ar and N ₂ , and a rare gas ion such as Ar is collided with the Ta target, and Ta and its cluster that are constituent atoms of the target are used. A TaN film is formed by pulverizing and nitriding in plasma. At this time, if the Vickers hardness of the Ta target surface varies, there is a difference in the amount of implantation of Ar ions or the like between the hard part and the soft part, and as a result, Ta sputtered by the Ta target part. Variations occur in the amount of atoms and their clusters. Based on such a difference in the amount of sputtering, in-plane uniformity of the film thickness of the TaN film to be formed is lowered.

  Based on finding such a phenomenon, the variation in the Vickers hardness of the entire sputtering surface of the high purity Ta target is controlled to 20% or less. By making the hardness of the entire Ta target uniform, it is possible to suppress variations in the amount of Ta atoms sputtered, and thus it is possible to significantly increase the in-plane uniformity of the TaN film thickness to be formed. . The variation in Vickers hardness over the entire surface of the Ta target is more preferably 15% or less, and even more preferably 10% or less, in order to further uniformize the sputtering phenomenon at each portion of the Ta target.

The hardness of the high-purity Ta target varies depending on the crystal grain size and the like, but after suppressing the occurrence of variations in Vickers hardness, for example, a range in which a good sputter rate, sound spatter discharge, etc. can be obtained, that is, Hv70 in the Vickers hardness It is preferable to be in the range of ~ 150. When the hardness of the Ta target exceeds Vvs hardness of Hv150, the Ta target itself is too hard against the impact of Ar ions, so even if Ar ions collide, the efficiency of ejecting constituent atoms, clusters, etc. of the Ta target Will fall. As a result, not only the sputtering rate is lowered, but also the Ar ⁺ ions whose kinetic energy could not be exchanged are charged on the surface of the Ta target, which may cause abnormal discharge. Abnormal discharge may cause device troubles such as discharge stop.

On the other hand, if the hardness of the Ta target is less than Hv70 in terms of Vickers hardness, Ar ions are implanted into the surface when colliding with the Ta target, and the portion is positively charged by Ar ⁺ ions. As a result, abnormal discharge is caused in the sputter deposition process. Here, the degree of impact by Ar ions, the sputtering rate, and the like vary depending on various substances. The above hardness is defined based on the relationship with the sputtering rate and abnormal discharge in the case of a Ta target.

  As described above, even if the hardness of the Ta target is too high or too low, a charging phenomenon occurs, which may cause abnormal discharge and accompanying discharge stoppage. For this reason, it is preferable to control the Vickers hardness of the Ta target within a range of Hv 70 to 150. A Ta target having such hardness is excellent in sputter rate and can prevent abnormal discharge with good reproducibility. The hardness of the Ta target is more preferably in the range of Hv 80 to 130 in terms of Vickers hardness.

  In addition, the Vickers hardness of the Ta target prescribed | regulated by this invention shall show the value measured as follows. That is, for example, if the target is a disk shape, each position at a distance of 50% from the central part of the target and four straight lines that divide the circumference evenly through the central part (total of 8 places), and Test specimens were collected from a total of 17 locations at a distance of 90% from the center (total of 8 locations), the Vickers hardness of each of these 17 test samples was measured, and the average value of these measurements was calculated. The Vickers hardness of the Ta target. Furthermore, the variation in the Vickers hardness as a whole Ta target is determined from {(maximum value−minimum value) / (maximum value + minimum value)} from the maximum value and minimum value of the Vickers hardness (each measured value) of each test piece. Value)} × 100 (%).

  The Vickers hardness of each test piece is measured by first polishing the surface of each test piece cut out from the Ta target to # 1000, further buffing the surface to make it a mirror surface, and using this as a sample for measuring Vickers hardness use. The Vickers hardness of this measurement sample is measured using a Vickers hardness tester under the conditions of a load of 200 g and a load application time of 10 seconds. Vickers hardness of each measurement sample is measured 10 times or more, and the average value is taken as the Vickers hardness of each test piece.

  The method for producing a high-purity Ta material for semiconductor devices of the present invention is not particularly limited except that specific processing conditions, heat treatment conditions, and the like are satisfied, and can be produced by applying a known method. However, the hardness of the high-purity Ta material for semiconductor devices is basically based on the specific hardness of the constituent material. For example, the processing conditions (for example, processing rate) when processing from the ingot to the target, and further processing The heat treatment conditions to be applied during and finally have a great influence. The same applies to the variation in hardness of the high-purity Ta material as a whole. Therefore, in order to control the Vickers hardness of the high-purity Ta material (Ta target) within a predetermined range and reduce the variation of the entire high-purity Ta material, the following processing conditions and heat treatment conditions can be applied. It becomes important.

First, a high-purity Ta material that is a raw material for forming a Ta target is prepared. For example, a Ta ingot is produced by applying an alkali melting method, a fractional crystallization method, an electron beam melting method or the like to Ta ₂ O ₅ ore. At this time, it is preferable to set the purification conditions for the Ta raw material so that the purity of the Ta ingot falls within the above-described range. The Ta ingot thus obtained is subjected to plastic working by forging and rolling.

  At this time, the forging process is performed from two or more axes. First, tightening forging is performed in which the Ta ingot is plastically processed in the radial direction, and then upsetting forging is performed in the thickness direction. Thus, by forging the Ta ingot from two or more directions, it is possible to reduce variations in hardness when a high-purity Ta material for semiconductor devices is produced.

  That is, coarse grains are present in the raw Ta ingot, but the coarse grains cannot be sufficiently destroyed by plastic processing only in the uniaxial direction, and a high-purity Ta material for semiconductor devices is produced. Coarse grains are partially present on the surface of the high-purity Ta material for semiconductor devices. Since the hardness is different between the part where the coarse particles are present and the part where the coarse particles are not present, the hardness of the surface of the high-purity Ta material for semiconductor devices varies. On the other hand, forging a Ta ingot from two or more directions can break coarse grains more reliably, and it is possible to improve the hardness uniformity of high-purity Ta material for semiconductor devices. Become.

  The processing rate in the forging process described above is preferably in the range of 10 to 98% in total. When the processing rate is less than 10%, there is a possibility that coarse grains that contribute to hardness variation cannot be sufficiently broken. Even if the forging process is performed with a processing rate exceeding 98%, no further effect can be obtained.

  In addition, two or more vacuum heat treatments are performed during the forging process described above. This vacuum heat treatment is preferably performed for 5 hours or more at a temperature of 1000 to 1600 ° C. in a vacuum atmosphere of 0.1 Pa or less. In addition, the rate of temperature increase during the heat treatment is preferably 10 ° C./min or more. By such heat treatment, the mother crystal of the Ta ingot is completely removed, and the strain applied by forging can be recovered. The processing strain causes an increase in hardness and variation. If the heat treatment temperature during plastic working is less than 1000 ° C. or if the heat treatment time is less than 5 hours, the strain cannot be sufficiently recovered, and thus the variation in hardness increases.

  Next, cold rolling is performed on the Ta material that has undergone the above steps. Depending on the processing rate at the time of cold rolling, the strain applied to the high-purity Ta material (target material) for semiconductor devices becomes non-uniform for each part, which may cause variations in hardness. Therefore, it is important to uniformly apply a predetermined strain to each part of the high-purity Ta material (target material) for semiconductor devices by controlling the processing rate (rolling rate) during cold rolling. It becomes possible to suppress variations in hardness of the high-purity Ta material for devices. Specifically, the processing rate during cold rolling is preferably in the range of 10 to 98%.

  Thereafter, the cold-rolled material is subjected to a recrystallization heat treatment at a temperature of 1000 to 1500 ° C. for 5 to 10 hours in a vacuum atmosphere of 0.1 Pa or less. High-purity Ta material for semiconductor devices (Ta target material) with the desired Vickers hardness and reduced variation by applying such recrystallization heat treatment to recover the strain caused by cold rolling Can be obtained. If the heat treatment temperature at this time is less than 1000 ° C., strain recovery is insufficient, and the Vickers hardness of the high-purity Ta material for semiconductor devices may be too high. On the other hand, when the heat treatment temperature exceeds 1500 ° C., the Vickers hardness of the high-purity Ta material for semiconductor devices may be too soft. In such a case, the variation in hardness tends to increase.

  By processing a high-purity Ta material (target material) for semiconductor devices under the processing conditions and heat treatment conditions as described above, the variation in Vickers hardness when used as a target can be controlled to 20% or less with good reproducibility. . Further, the specific Vickers hardness of the Ta target can be controlled in the range of Hv 70 to 150. The sputtering target is obtained by machining the high-purity Ta material for semiconductor devices (Ta target material) thus obtained into a predetermined shape and then joining it to a backing plate made of, for example, Al or Cu. General diffusion bonding or solder bonding can be applied to the backing plate. When applying solder joint, it joins with a backing plate via the well-known In type or Sn type joining material. The temperature of diffusion bonding is preferably 600 ° C. or less.

  The high-purity Ta material for semiconductor devices obtained by the production method of the present invention can be used for forming wiring films for various electronic devices, and forms a TaN film as a barrier layer for wiring films made of Cu films or Cu alloy films. Is preferably used. In particular, when the TaN film is formed by the reactive sputtering method, the variation in the amount of sputtered particles (the amount of Ta atoms and clusters to be sputtered) from each part of the Ta target is suppressed. The internal uniformity can be greatly increased. Specifically, it becomes possible to achieve film thickness uniformity of 4% or less, which was difficult to achieve with a conventional Ta target. A TaN film having excellent in-plane uniformity of film thickness is useful as a barrier material for highly integrated semiconductor devices.

As a specific wiring structure in which a high-purity Ta material for semiconductor devices obtained by the manufacturing method of the present invention is used, for example, a TaN film is formed on a SiO ₂ insulating film, and a Cu wiring film is further formed thereon. An example is a Cu wiring structure in which (Cu film or Cu alloy film) is formed. According to such a Cu wiring structure, for example, it is possible to provide a wiring film structure suitable when applying the DD wiring technology, and it is possible to obtain high-density wiring with high reproducibility with high reliability. . This greatly contributes to improving the manufacturing yield of ultra-highly integrated semiconductor devices. Furthermore, such a Cu wiring structure can be applied not only to semiconductor devices such as VLSI but also to various electronic components such as SAW devices, TPH, and LCD devices.

  Next, specific examples of the present invention and evaluation results thereof will be described.

Example 1
First, prepare an EB melting Ta ingot (diameter 250mm x 30mm) with a purity of 99.99%, and cold-draw forging (diameter processing rate: 54%) to this Ta ingot to obtain a diameter of 115mm x 140mm Ta material was produced. This Ta material was heat-treated in a vacuum atmosphere of 1 × 10 ⁻³ Pa under the conditions of 1300 ° C. × 5 hr. The heating rate at this time was 15 ° C./min. Next, the heat-treated Ta material was cold-forged to a diameter of 250 mm x 30 mm (working rate in the thickness direction: 79%), and further 1300 ° C x 5 hr in a vacuum atmosphere of 1 x 10 ^-3 Pa Heat treatment was performed under the conditions (temperature increase rate: 10 ° C./min).

Next, the Ta material obtained by the forging process and the heat treatment described above was cold-rolled to a diameter of 350 mm × 15 mm (rolling ratio: 50%) and then 1300 ° C. × 3 hr in a vacuum atmosphere of 1 × 10 ⁻³ Pa. A Ta material for a target was produced by performing recrystallization heat treatment under the conditions. The target Ta material was machined into a shape having a diameter of 330 mm × 12 mm, and then bonded to an Al backing plate using a diffusion bonding method to produce a target Ta sputtering target.

  The Vickers hardness of the Ta sputtering target thus obtained was measured according to the method described above (measuring device: HMV-2000 manufactured by Shimadzu Corporation). As a result, the Vickers hardness (average value) was Hv82, and the variation in Vickers hardness was 11%. This Ta sputtering target was subjected to the characteristic evaluation described later. Table 1 shows the manufacturing conditions of the target (heat treatment conditions during plastic working), and Table 2 shows the Vickers hardness and variations of the Ta target.

Examples 2-4
In Example 1 described above, the heat treatment conditions after heat-forging and after forging (heat treatment conditions during plastic working) are 1300 ° C. × 6 hr (Example 2), 1300 ° C. × 8 hr (Example 3), 1300, respectively. A Ta material for a target was produced under the same conditions as in Example 1 except that the temperature was changed to ° C. × 10 hr (Example 4). Using these target Ta materials, Ta sputtering targets were produced in the same manner as in Example 1. The Vickers hardness of each Ta sputtering target and its variation were measured according to the method described above. The results are shown in Table 2. Such a Ta sputtering target was subjected to the characteristic evaluation described later.

Comparative Example 1
By cold rolling a EB melting Ta ingot similar to that in Example 1 to a diameter of 350 mm × 15 mm, a recrystallization heat treatment is performed in a vacuum atmosphere of 1 × 10 ⁻³ Pa at 1300 ° C. × 3 hr. A Ta material for the target was prepared. A Ta sputtering target was produced in the same manner as in Example 1 using this target Ta material. The Vickers hardness and variation of this Ta sputtering target were measured according to the method described above. The results are shown in Table 2. This Ta sputtering target was subjected to the characteristic evaluation described later.

Comparative Examples 2-7
In Example 1 described above, the heat treatment conditions after heat-forging and after forging (heat treatment conditions during plastic working) are 1300 ° C. × 1 hr (Comparative Example 2), 1300 ° C. × 2 hr (Comparative Example 3), 1300, respectively. Same conditions as in Example 1 except for changing to ℃ × 4hr (Comparative Example 4), 900 ° C × 10hr (Comparative Example 5), 800 ° C × 10hr (Comparative Example 6), 700 ° C × 10hr (Comparative Example 7) Thus, a Ta material for a target was produced. Using these target Ta materials, Ta sputtering targets were produced in the same manner as in Example 1. The Vickers hardness of each Ta sputtering target and its variation were measured according to the method described above. The results are shown in Table 2. Such a Ta sputtering target was subjected to the characteristic evaluation described later.

Using the Ta sputtering targets of Examples 1 to 4 and Comparative Examples 1 to 7 described above, sputtering method: DC sputtering, output DC: 18 kW, substrate bias: -100 V, back pressure: 1 × 10 ⁻⁵ Pa, Reactive sputtering was performed under the conditions of substrate-target distance: 300 mm, Ar: 5 sccm, N: 20 sccm, sputtering time: 5 min, and a TaN film (target film thickness: 0.2 μm) was formed on an 8-inch Si wafer. Filmed. The film thickness of each TaN film thus obtained was measured at 9 points on the Si wafer (1 point at the center, 4 points at each position 50 mm from the center, 4 points at each position 90 mm from the center), and these The film thickness uniformity (%) was determined based on {(maximum value−minimum value) / (maximum value + minimum value)} × 100 (%) from the maximum value and the minimum value of the film thickness. This value is shown in Table 2.

  As can be seen from Table 2, according to each Ta sputtering target of Examples 1 to 4, a TaN film having excellent in-plane uniformity of film thickness can be obtained. In particular, it can be seen that a film thickness uniformity of 4% or less, which was difficult to achieve with a conventional Ta target, can be achieved with good reproducibility. On the other hand, it can be seen that the Ta sputtering targets of Comparative Examples 1 to 7 having large variations in Vickers hardness are inferior in the in-plane uniformity of the film thickness of the obtained TaN film.

Claims (6)

Producing a high purity Ta ingot;
Forging from the direction of two or more axes to the high-purity Ta ingot;
A step of performing vacuum heat treatment twice or more during the forging step;
Cold rolling the Ta material that has undergone the forging step and the vacuum heat treatment step;
And a step of subjecting the Ta material that has undergone the cold rolling step to a recrystallization heat treatment. In the manufacturing method of the high purity Ta material for semiconductor devices of Claim 1,
A method for producing a high-purity Ta material for semiconductor devices, wherein the high-purity Ta ingot is produced by applying an alkali melting method, a fractional crystallization method, or an electron beam melting method to Ta ₂ O ₃ ore. In the manufacturing method of the high purity Ta material for semiconductor devices of Claim 1 or Claim 2,
A method for producing a high-purity Ta material for a semiconductor device, characterized in that the processing rate in the forging step is in the range of 10 to 98% in total. In the manufacturing method of the high purity Ta material for semiconductor devices of any one of Claim 1 thru | or 3,
A method for producing a high-purity Ta material for semiconductor devices, wherein the vacuum heat treatment step is performed in a vacuum atmosphere of 0.1 P or less at a temperature of 1000 to 1600 ° C. for 5 hours or more. In the manufacturing method of the high purity Ta material for semiconductor devices of any one of Claim 1 thru | or 4,
A method for producing a high-purity Ta material for a semiconductor device, wherein the cold rolling step is performed so that a processing rate is 10 to 98%. In the manufacturing method of the high purity Ta material for semiconductor devices of any one of Claims 1 thru | or 5,
A method for producing a high-purity Ta material for a semiconductor device, wherein the recrystallization heat treatment step is performed at a temperature of 1000 to 1500 ° C. for 5 to 10 hours.