JP2007124768A - Pack battery - Google Patents

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JP2007124768A
JP2007124768A JP2005311928A JP2005311928A JP2007124768A JP 2007124768 A JP2007124768 A JP 2007124768A JP 2005311928 A JP2005311928 A JP 2005311928A JP 2005311928 A JP2005311928 A JP 2005311928A JP 2007124768 A JP2007124768 A JP 2007124768A
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voltage
gate
fet element
battery
discharging
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JP4511445B2 (en
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Masayuki Kobayashi
雅幸 小林
Shinichi Itagaki
真一 板垣
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Sanyo Electric Co Ltd
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Sanyo Electric Co Ltd
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    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02EREDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E60/00Enabling technologies; Technologies with a potential or indirect contribution to GHG emissions mitigation
    • Y02E60/10Energy storage using batteries

Abstract

<P>PROBLEM TO BE SOLVED: To provide a pack battery including an electric circuit capable of, when an overcurrent is passed due to short-circuiting or the like, quickly causing an FET element for charging in the pack battery to transition from on state to off state. <P>SOLUTION: The pack battery includes: a battery 1; an n-type semiconductor FET element 92 for discharging disposed on the high voltage side of a charging/discharging path; controlling means; and a boosting circuit 11 that controls turn-on/off of the FET element 92 for discharging at a gate voltage corresponding to a boosted on signal based on an on/off signal from the controlling means. When the FET element 92 for discharging is turned on, the boosting circuit 11 applies a battery voltage through a battery voltage application path 21 and supplies a voltage boosted higher than the battery voltage to its gate. When the FET element 92 for discharging is turned off, the boosting circuit 11 applies the battery voltage to its gate through the battery voltage application path 21 with the boosting circuit 11 bypassed. A switching element 30 is placed between the source and the gate of the FET element 92 for discharging. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、パック電池に関する。   The present invention relates to a battery pack.

従来のパック電池について、以下の特許文献に、充放電経路の高電圧側に配置されたn型半導体の放電用FET素子の記載がある。パック電池と、これを電源とするノート型パソコンにおいては、相互にデータをやりとりするために通信する必要があり、通信信号は、パック電池とパソコンとの共通のグランド(=充放電経路の低電圧側経路)を利用するので、仮に低電圧側経路にFET素子を配置すると、該素子のオンオフでグランド電圧が変動することになるので、低電圧側経路にFET素子を配置することはできなかった。   Regarding conventional battery packs, the following patent document describes an n-type semiconductor discharging FET element arranged on the high voltage side of a charge / discharge path. The battery pack and the notebook computer that uses it as a power source need to communicate with each other in order to exchange data. The communication signal is the common ground between the battery pack and the computer (= low voltage on the charge / discharge path). Since the ground voltage fluctuates when the device is turned on and off, the FET device could not be placed on the low voltage side path. .

よって、従来においては、安価でオン抵抗が低いn型半導体の放電用FET素子を利用するときは、充放電経路の高電圧側に配置し、昇圧回路を利用して昇圧した電圧を、該素子のゲートに印加して、素子をオン状態としていた。
特開平11-178224号公報
Therefore, in the past, when using an n-type semiconductor discharge FET element that is inexpensive and has low on-resistance, it is arranged on the high voltage side of the charge / discharge path, and the voltage boosted using a booster circuit is supplied to the element. The device was turned on by applying the voltage to the gate.
Japanese Patent Laid-Open No. 11-178224

上記の従来のパック電池において、放電用FET素子をオン状態から、オフ状態とするときは、昇圧回路からの昇圧した電圧の供給を遮断して、オフ状態とする。このとき、放電用FET素子をオン状態から、オフ状態とするときは、ゲートに溜まった電荷を放電し、ソースとゲートが略同電位となってオフ状態となるには、ある程度の時間を必要とする。特に、過電流を検出したときは、放電用FET素子をオン状態から、オフ状態と素早く切り替える必要がある。   In the above-described conventional battery pack, when the discharging FET element is changed from the on state to the off state, the supply of the boosted voltage from the booster circuit is cut off to be in the off state. At this time, when the discharging FET element is changed from the on state to the off state, a certain amount of time is required for the electric charge accumulated in the gate to be discharged and the source and the gate to become substantially the same potential to be in the off state. . In particular, when an overcurrent is detected, it is necessary to quickly switch the discharging FET element from the on state to the off state.

本発明は、このような問題点を解決するために成されたものであり、出力端子間の短絡事故等で過電流が流れるとき、パック電池内の充電用FET素子をオン状態からオフ状態に、素早く移行できる電気回路を有するパック電池を提供することを目的とする。   The present invention has been made to solve such problems, and when an overcurrent flows due to a short circuit accident between output terminals, the charging FET element in the battery pack is changed from an on state to an off state. An object of the present invention is to provide a battery pack having an electric circuit that can be shifted quickly.

本発明は、パック電池内に、電池と、充放電経路の高電圧側に配置されたn型半導体の放電用FET素子と、制御手段と、該制御手段からのオンオフ信号に基づき、昇圧されたオン信号に対応したゲート電圧にて放電用FET素子をオンオフ制御する昇圧回路とを備え、前記昇圧回路においては、電池電圧を電池電圧印加経路を介して印加して、該電池電圧より昇圧した電圧をゲートに供給して前記放電用FET素子をオン状態とし、前記昇圧回路をバイパスして前記電池電圧印加経路にて前記電池電圧を前記ゲートに印加して前記放電用FET素子をオフとし、 前記放電用FET素子のソースと前記ゲート間にスイッチング素子を挿入したことを特徴とする。   The present invention boosts a battery pack based on a battery, an n-type semiconductor discharge FET element disposed on the high voltage side of the charge / discharge path, a control means, and an on / off signal from the control means. A booster circuit that controls on / off of the discharging FET element with a gate voltage corresponding to an on signal, wherein the booster circuit applies a battery voltage via a battery voltage application path, and boosts the battery voltage from the battery voltage. To the gate to turn on the discharge FET element, bypass the boost circuit and apply the battery voltage to the gate in the battery voltage application path to turn off the discharge FET element, A switching element is inserted between the source of the discharging FET element and the gate.

また、前記スイッチング素子は、FET素子であって、そのゲート電圧は前記電池電圧より定電圧が供給され、 前記放電用FET素子の前記ソースと、前記ゲート間に、前記スイッチング素子のソースとドレインが接続されることを特徴とする。
ことを特徴とする。
Further, the switching element is an FET element, and a gate voltage of the switching element is supplied from the battery voltage, and a source and a drain of the switching element are provided between the source of the discharging FET element and the gate. It is connected.
It is characterized by that.

本発明においては、出力端子間の短絡事故等で過電流が流れるとき、前記放電用FET素子のソースと前記ゲート間にスイッチング素子を挿入したことにより、放電用FET素子をオン状態から、オフ状態と素早く切り替えることができる。   In the present invention, when an overcurrent flows due to a short circuit accident between the output terminals or the like, by inserting a switching element between the source and the gate of the discharging FET element, the discharging FET element is turned off from the on state. You can switch quickly.

放電用FET素子のゲート電圧を、オン状態のHighレベルから、ソースとゲートが略同電位となったオフ状態のLowレベルにするとき、前記昇圧回路をバイパスして前記電池電圧印加経路にて前記電池電圧を前記ゲートに印加して前記放電用FET素子をオフ状態とするので、ゲートに溜まった電荷は電池電圧印加経路にて放電するから、ある程度の時間を必要とする。   When the gate voltage of the discharging FET element is changed from the high level in the on state to the low level in the off state in which the source and the gate are substantially at the same potential, the booster circuit is bypassed and the battery voltage application path is Since the battery voltage is applied to the gate and the discharging FET element is turned off, the charge accumulated in the gate is discharged through the battery voltage application path, so that a certain amount of time is required.

本発明においては、前記放電用FET素子のソースと前記ゲート間にスイッチング素子を挿入し、前記スイッチング素子は、FET素子であって、そのゲート電圧は前記電池電圧より定電圧が供給され、前記放電用FET素子の前記ソースと、前記ゲート間に、前記スイッチング素子のソースとドレインが接続される。   In the present invention, a switching element is inserted between the source of the discharging FET element and the gate, the switching element is an FET element, and the gate voltage is supplied with a constant voltage from the battery voltage. The source and drain of the switching element are connected between the source of the FET element for use and the gate.

このスイッチング素子により、放電用FET素子のゲート電圧を、オン状態のHighレベルから、ソースとゲートが略同電位となったオフ状態のLowレベルに素早くできることを、以下に説明する。   It will be described below that this switching element can quickly change the gate voltage of the discharging FET element from the high level in the on state to the low level in the off state in which the source and the gate have substantially the same potential.

例えば、ネックレス等の金属製異物が出力端子間に誤って配置され短絡事故が発生したり、電子機器に装着された状態で、電子機器側の放電回路に短絡事故が発生した等の理由により、過電流を検出したとき、前記昇圧回路をバイパスして前記電池電圧印加経路にて前記電池電圧を前記ゲートに印加しゲートに溜まった電荷をソースに放電し、ソースとゲートが略同電位となってオフ状態となるには、スイッチング素子がないなら、上述のように、ある程度の時間を必要とする。   For example, a metal foreign object such as a necklace is accidentally placed between the output terminals and a short-circuit accident occurs, or a short-circuit accident occurs in the discharge circuit on the electronic device side while attached to the electronic device, etc. When an overcurrent is detected, the battery voltage is applied to the gate in the battery voltage application path by bypassing the booster circuit, and the charge accumulated in the gate is discharged to the source, so that the source and the gate are substantially at the same potential. If there is no switching element, a certain amount of time is required to enter the OFF state as described above.

ここで、ゲートに溜まった電荷を放電するとき、ゲート電位が、ソース電位に近づくと、放電用FET素子のソース、ドレイン間抵抗が増大し、過電流の電流値が絞られて、電流値が小さくなる。出力端子が短絡された状態で、電流値が小さくなると、異物の電気抵抗は略一定であるので、電流値が小さくなることで出力端子間の電圧も、小さくなる。出力端子間の電圧が低下することで、スイッチング素子のソース電位が低下して、ゲート・ソース間電圧が閾値電圧以上になり、スイッチング素子がオンされて、このスイッチング素子を介して放電用FET素子のゲートに溜まった電荷を素早く、瞬時に、放電し、前記放電用FET素子のソースと前記ゲート間が同電位となり、素早く、瞬時に、放電用FET素子をオフ状態とすることができる。   Here, when the charge accumulated in the gate is discharged, when the gate potential approaches the source potential, the resistance between the source and drain of the discharging FET element increases, the current value of the overcurrent is reduced, and the current value is reduced. Get smaller. When the current value is reduced in a state where the output terminal is short-circuited, the electric resistance of the foreign matter is substantially constant. Therefore, the voltage between the output terminals is reduced as the current value is reduced. When the voltage between the output terminals decreases, the source potential of the switching element decreases, the gate-source voltage becomes equal to or higher than the threshold voltage, the switching element is turned on, and the discharging FET element is passed through this switching element. The electric charge accumulated in the gate of the discharge FET is quickly and instantaneously discharged, the potential between the source of the discharging FET element and the gate becomes the same potential, and the discharging FET element can be quickly and instantaneously turned off.

特に、上述のように、過電流検出の後、放電用FET素子のゲートに溜まった電荷を放電するとき、ゲート電位が、ソース電位に近づくと、放電用FET素子のソース、ドレイン間抵抗が増大するので、このとき、大電流である過電流を流し続けると、放電用FET素子が熱破壊をきたすことがある。よって、本発明においては、放電用FET素子のソース、ドレイン間抵抗が増大するとき、スイッチング素子により、素早く、瞬時に、放電用FET素子をオフ状態とすることで、このような放電用FET素子の熱破壊を防止することができる。   In particular, as described above, when discharging the charge accumulated at the gate of the discharging FET element after overcurrent detection, the resistance between the source and drain of the discharging FET element increases as the gate potential approaches the source potential. Therefore, at this time, if an overcurrent that is a large current is kept flowing, the discharging FET element may be thermally destroyed. Therefore, in the present invention, when the resistance between the source and the drain of the discharge FET element increases, the discharge FET element is turned off quickly and instantaneously by the switching element, thereby Can be prevented from thermal destruction.

本発明の実施例を、図を用いて詳細に説明する。まず、実施例のパック電池Aの全体構成を説明し、次に、実施例の特徴点であるスイッチング素子について、説明する。   Embodiments of the present invention will be described in detail with reference to the drawings. First, the overall configuration of the battery pack A of the embodiment will be described, and then the switching element that is a characteristic point of the embodiment will be described.

図1に示すように、本実施例の電池パックAにおいては、リチウムイオン等の4セルの二次電池1と、電池1の充放電時の電流を検出する電流検出抵抗2(電流検出部に相当する)と、電池1の充放電を監視、制御するマイクロプロセッサーユニット(以下、MPU(=Micro Processing Unit)と言う)とを備えている。そして、電子機器であるパーソナルコンピューター(以下、PCという)等に、内蔵して電池パックAが取り付けられたとき、電池1からの出力を、+端子及びGND端子よりPCに供給し、PCとの通信は、通信ラインSCL、SDAを介して行われる。一方、PCからは、充電器として、充電電力が、最大電流、最大電圧が規制された定電流・定電圧充電方法にて、供給される。   As shown in FIG. 1, in the battery pack A of the present embodiment, a 4-cell secondary battery 1 such as lithium ion, and a current detection resistor 2 (in the current detection unit) that detects current when the battery 1 is charged and discharged. And a microprocessor unit (hereinafter referred to as MPU (= Micro Processing Unit)) that monitors and controls charging / discharging of the battery 1. When the battery pack A is installed in a personal computer (hereinafter referred to as a PC), which is an electronic device, the output from the battery 1 is supplied to the PC from the + terminal and the GND terminal. Communication is performed via communication lines SCL and SDA. On the other hand, as a charger, charging power is supplied from the PC by a constant current / constant voltage charging method in which the maximum current and the maximum voltage are regulated.

MPUにおいては、測定点dの電池電圧や電流検出抵抗2両端のアナログ電圧をデジタル変換し、実電圧[mV]や実電流値[mA]に換算するA/D変換部3と、充放電電流を積算して残容量を演算処理する残容量処理部4と、電池1の満充電を検出したり、異常電流、別途設けられる感温素子(図示せず)から検出される電池の異常温度、異常電圧の検出時等に、充放電電流を遮断して制御する制御部5を備えている。   In the MPU, the battery voltage at the measurement point d and the analog voltage at both ends of the current detection resistor 2 are digitally converted and converted into an actual voltage [mV] or an actual current value [mA], and a charge / discharge current. And the remaining capacity processing unit 4 for calculating the remaining capacity, and detecting the full charge of the battery 1, the abnormal current, the abnormal temperature of the battery detected from a separately provided temperature sensing element (not shown), When detecting an abnormal voltage, a control unit 5 is provided which controls the charge / discharge current by cutting it off.

ここで、制御部5は、充電電流、放電電流を遮断するために、充放電経路の高電圧側に配置されたnチャネル型MOSFETである充電用FET素子91、放電用FET素子92に対して、オンオフ制御するために、オン、オフ信号を、昇圧回路を含む制御回路10に発する。   Here, in order to cut off the charging current and the discharging current, the control unit 5 performs the charging FET element 91 and the discharging FET element 92 which are n-channel MOSFETs arranged on the high voltage side of the charging / discharging path. In order to perform on / off control, an on / off signal is issued to a control circuit 10 including a booster circuit.

制御部5においては、電池1の電圧が、過充電電圧以上(例えば、4.2V/Cell以上)になると、充電用FET素子91をオフ制御するために、オフ信号を、ポートであるCHGより発する。また、電池1の電圧が、過放電電圧以下(例えば、2.7V/Cell以下)になると、放電用FET素子92をオフ制御するために、オフ信号を、ポートであるDSGより発する。   In the control unit 5, when the voltage of the battery 1 becomes equal to or higher than the overcharge voltage (eg, 4.2 V / Cell or higher), an off signal is sent from the port CHG in order to turn off the charging FET element 91. To emit. Further, when the voltage of the battery 1 becomes equal to or lower than the overdischarge voltage (for example, 2.7 V / Cell or lower), an off signal is generated from the DSG as a port in order to turn off the discharging FET element 92.

一方、MPUの残容量処理部4においては、A/D変換部3によって変換された充放電電流に測定単位時間(例えば、250msec)を掛け算した値を積算し、放電時においては満充電から積算値を引き算し、或いは、充電時においては充電開始時の残容量より積算値を加算する。このような演算により、電池1の残容量を算出している。   On the other hand, in the remaining capacity processing unit 4 of the MPU, a value obtained by multiplying the charging / discharging current converted by the A / D conversion unit 3 by a measurement unit time (for example, 250 msec) is integrated. The value is subtracted or, at the time of charging, the integrated value is added from the remaining capacity at the start of charging. The remaining capacity of the battery 1 is calculated by such calculation.

更には、制御部5においては、A/D変換部3により変換された電池電圧と充電電流から満充電(電流、電圧を規制した定電流・定電圧充電においては、電圧が所定値以上、電流が所定値以下の条件のとき、満充電とする)を検出し、残容量を100%とする情報を出力する。   Further, the control unit 5 is fully charged from the battery voltage and charging current converted by the A / D conversion unit 3 (in constant current / constant voltage charging in which the current and voltage are regulated, the voltage is a predetermined value or more. When the condition is less than or equal to a predetermined value, it is detected that the battery is fully charged), and information indicating that the remaining capacity is 100% is output.

電子機器であるPC(=パーソナルコンピュータ)、充電器等に対して、電池電圧、残容量、充放電電流値等の各種の電池情報を、電子機器が受信できる信号データに作成する通信データ作成部6と、PCや充電器と実際に通信を行うためのドライバ部7と、残容量を算出するための各種パラメータの記憶や諸々のデータを記憶する為のメモリ8を備えている。また、電子機器からバッテリパックの各種情報の送信要求をドライバ部7にて受け、通信データ作成部6にて作成されたデータをドライバ部から電子機器に送信する。このような通信データ作成部6、ドライブ部7、メモリ8は、電子機器等との通信を行う通信部COMである。   A communication data creation unit that creates various types of battery information such as battery voltage, remaining capacity, charge / discharge current value, etc., in signal data that can be received by the electronic device for a PC (= personal computer), a charger, etc. 6, a driver unit 7 for actually communicating with a PC or a charger, and a memory 8 for storing various parameters for calculating the remaining capacity and various data. In addition, the driver unit 7 receives a request for transmission of various information of the battery pack from the electronic device, and transmits the data created by the communication data creation unit 6 from the driver unit to the electronic device. The communication data creating unit 6, the drive unit 7, and the memory 8 are a communication unit COM that performs communication with an electronic device or the like.

更に、残容量処理部4においては、以下の機能を備えている。リチウムイオン等の二次電池1は、満充電電圧付近で充電を繰り返すと、電池自体の劣化が促進されたり、電池セル内における安全部品である過充電防止回路又は素子が頻繁に動作することになり、このような回路又は素子のサイクル寿命を縮める悪影響が発生する。このような問題を回避するために、本実施例においては、残容量処理部4において、所定の残容量(例えば95%以下)或いはこれに対応する所定の電圧(例えば4V/cell)に低下するまでは、充電を禁止する指示情報を、通信データ作成処理部6を介して、PC、充電器側に出力している。   Further, the remaining capacity processing unit 4 has the following functions. When the secondary battery 1 such as lithium ion is repeatedly charged in the vicinity of the full charge voltage, deterioration of the battery itself is promoted, or an overcharge prevention circuit or element that is a safety component in the battery cell frequently operates. Thus, an adverse effect of shortening the cycle life of such a circuit or element occurs. In order to avoid such a problem, in the present embodiment, the remaining capacity processing unit 4 drops to a predetermined remaining capacity (for example, 95% or less) or a predetermined voltage (for example, 4 V / cell) corresponding thereto. Until then, the instruction information for prohibiting charging is output to the PC and the charger side via the communication data creation processing unit 6.

次に、昇圧回路を含む制御回路10について、説明をする。制御回路10においては、MPUのDSG、CHGからのオンオフ信号に基づいて、充電用FET素子91、放電用FET素子92のゲートに、オンオフ信号を供給して、オンオフ制御を行う。素子のゲートには、オン状態とするために、電池電圧よりも高い電圧を供給する必要があるために、昇圧回路11Cと昇圧回路11Dとからなる昇圧回路11を備えている。充電用FET素子91のゲートには、制御回路10のポートであるCHGから、オンオフ信号は印加され、放電用FET素子92のゲートには、制御回路10のポートであるDSGから、オンオフ信号が印加される。   Next, the control circuit 10 including the booster circuit will be described. In the control circuit 10, on / off control is performed by supplying on / off signals to the gates of the charging FET element 91 and the discharging FET element 92 based on the on / off signals from the DSG and CHG of the MPU. The gate of the element is provided with a booster circuit 11 composed of a booster circuit 11C and a booster circuit 11D because it is necessary to supply a voltage higher than the battery voltage in order to turn it on. An on / off signal is applied to the gate of the charging FET element 91 from CHG which is a port of the control circuit 10, and an on / off signal is applied to the gate of the discharging FET element 92 from DSG which is a port of the control circuit 10. Is done.

以下に、昇圧回路11D、ポートDSGからの信号について、詳細に説明し、昇圧回路11C、ポートCHGからの信号も同様の構成、動作であるので、昇圧回路11Dと同じ符号を付し、説明を省略する。   In the following, the signals from the booster circuit 11D and the port DSG will be described in detail. Since the signals from the booster circuit 11C and the port CHG have the same configuration and operation, the same reference numerals as those of the booster circuit 11D are attached and the description will be given. Omitted.

昇圧回路11のDSGには、ポートPACKより、充放電経路の高電圧側の電池電圧が、抵抗R4(10KΩ程度)を含む電池電圧印加経路21を介して、入力され、ポートDSGからのオンオフ信号を、放電用FET素子92のゲートに、抵抗R2(10KΩ程度)を介して、供給している。このような抵抗R2、R4は、高電圧側の充放電経路より、ノイズが制御回路10に入るのを、防止したり、制御回路10内に短絡事故が発生したときに電池から電流が急激に流れ込むのを防止する等の目的で、設けられる。また、放電用FET素子92のゲート、ソース間に取り付けられた抵抗R1は、FETをOFFする際、完全にGS間の電圧を同じにし、OFFするために設けられている。   The battery voltage on the high voltage side of the charge / discharge path is input from the port PACK to the DSG of the booster circuit 11 via the battery voltage application path 21 including the resistor R4 (about 10 KΩ), and an on / off signal from the port DSG. Is supplied to the gate of the discharging FET element 92 via a resistor R2 (about 10 KΩ). Such resistors R2 and R4 prevent noise from entering the control circuit 10 from the charging / discharging path on the high voltage side, or when the short circuit accident occurs in the control circuit 10, the current suddenly flows from the battery. It is provided for the purpose of preventing inflow. A resistor R1 attached between the gate and source of the discharging FET element 92 is provided to completely turn off the voltage between GS when the FET is turned off.

昇圧回路11Dは、チャージポンプと呼ばれるもので、その構成は、数十kHz程度に発振するオシレータOSCと、MPUのDSG出力のオン、オフ信号に基づいてオン、オフ制御される供給スイッチ12と、供給スイッチ12がオンのとき、オシレータOSCからの出力が入力されるバッファ回路13を備えている。また、バッファ回路13には、電池電圧印加経路21を介して、電池電圧が電源電圧として供給される。また、供給スイッチ12を省略して、MPUのDSG出力のオンオフ信号に基づいて、バッファ回路13をオンオフしても良い。   The step-up circuit 11D is called a charge pump, and has a configuration in which an oscillator OSC that oscillates at several tens of kHz, a supply switch 12 that is on / off controlled based on an on / off signal of the MPG DSG output, When the supply switch 12 is on, a buffer circuit 13 is provided to which an output from the oscillator OSC is input. Further, the battery voltage is supplied to the buffer circuit 13 as a power supply voltage via the battery voltage application path 21. Further, the supply switch 12 may be omitted, and the buffer circuit 13 may be turned on / off based on the on / off signal of the MPU DSG output.

バッファ回路13からの出力を、電荷として溜めて電圧を発生させるコンデンサー14Cと、電池電圧より電流が流れる方向に設けられたダイオード14D1、ダイオード14D2を備え、ダイオード14D1、14D2間に、コンデンサー14Cの降圧側一端が、分岐点T接続されている。また、直列接続した2つのダイオード14D1、14D2の両端に、MPUのDSG出力のオン、オフ信号に基づいてオフ、オン制御されるスイッチSWが設けられている(DSG出力のオン信号のとき、スイッチSWはオフ状態、DSG出力のオフ信号のとき、スイッチSWはオン状態となる)。   A capacitor 14C for generating a voltage by accumulating the output from the buffer circuit 13 as an electric charge, and a diode 14D1 and a diode 14D2 provided in a direction in which a current flows from the battery voltage are provided. One end of the side is connected to the branch point T. Also, a switch SW that is turned off and on based on the on / off signal of the MPU DSG output is provided at both ends of the two diodes 14D1 and 14D2 connected in series (when the DSG output is on, the switch When SW is in the off state and the DSG output is off, the switch SW is in the on state).

以上の構成の昇圧回路11Dは、概略、以下のように動作をする。FET素子をオン状態とするときは、MPUの端子DSG出力のオン信号により、スイッチSWをオフ状態とし、供給スイッチ12がオンされ、オシレータOSC出力を入力したバッファ回路13からは、略電池電圧と最低電圧(=電池電圧−12V)程度の間で発振する電圧が出力される(概略の出力波形例を図1内に示す)。なお、供給スイッチ12がオンオフに代えて、供給スイッチをなくして、オシレータOSCの発振をオン、オフしても良い。   The booster circuit 11D having the above configuration generally operates as follows. When the FET element is turned on, the switch SW is turned off by the on signal of the MPG terminal DSG output, the supply switch 12 is turned on, and the buffer circuit 13 to which the oscillator OSC output is input receives the substantially battery voltage. A voltage that oscillates between the lowest voltage (= battery voltage−12 V) is output (a schematic output waveform example is shown in FIG. 1). The supply switch 12 may be turned on / off, and the supply switch 12 may be omitted to turn on / off the oscillation of the oscillator OSC.

バッファ回路13から最低電圧が出力されるとき、コンデンサー14Cの両端電圧は、略電池電圧となる。   When the lowest voltage is output from the buffer circuit 13, the voltage across the capacitor 14C is substantially a battery voltage.

次に、バッファ回路13から、略電池電圧が出力されるとき、ダイオード14DCのため、先程の略電池電圧となったコンデンサー14Cの電荷が電池側に流れることなく保持された状態なので、分岐点Tには、先程溜まった電荷が、コンデンサー14Cの負極側の電池電圧の上に、蓄積されたことになる。そして、このような電荷は、FET素子92のゲートソース間の寄生容量に電荷が溜まり、ゲートには、FET素子92をオン状態とすることが可能な、電池電圧より高い電圧を供給することができる。なお、ゲートソース間の寄生容量に加えて、端子DSG、ゲート間に、別途、コンデンサーを設けても良い。但し、このようなコンデンサーについては、FET素子92を、オンからオフ状態とするとき、電荷を放電するのに、時間を要することがある。   Next, when a substantially battery voltage is output from the buffer circuit 13, the charge of the capacitor 14C that has become the substantially battery voltage is held without flowing to the battery side because of the diode 14DC. In this case, the electric charge accumulated in the previous step is accumulated on the battery voltage on the negative electrode side of the capacitor 14C. Such charges are accumulated in the parasitic capacitance between the gate and the source of the FET element 92, and a voltage higher than the battery voltage capable of turning the FET element 92 on can be supplied to the gate. it can. In addition to the parasitic capacitance between the gate and the source, a capacitor may be separately provided between the terminal DSG and the gate. However, for such a capacitor, when the FET element 92 is turned from the on state to the off state, it may take time to discharge the charge.

また、FET素子をオフ状態とするときは、MPUの端子DSG出力のオフ信号により、スイッチSWをオン状態とし、供給スイッチ12をオフとする。このとき、オシレータOSCの発振を停止しても良い。スイッチSWをオン状態としたことにより、前記昇圧回路11をバイパスして前記電池電圧印加経路にて前記電池電圧を前記ゲートに印加したことになるので、寄生容量として、ソース、ゲート間に溜まった電荷を電池電圧印加経路にて放電する。   When the FET element is turned off, the switch SW is turned on and the supply switch 12 is turned off by an off signal of the MPS terminal DSG output. At this time, the oscillation of the oscillator OSC may be stopped. Since the switch SW is turned on, the battery voltage is applied to the gate via the battery voltage application path, bypassing the booster circuit 11, and therefore, the parasitic capacitance is accumulated between the source and the gate. The electric charge is discharged through the battery voltage application path.

そして、ここで、後述するスイッチング素子30がないなら、出力端子が短絡される等の過電流を検出したとき、ゲートに溜まった電荷を放電し、ソースとゲートが略同電位となってオフ状態となるには、ある程度の時間を必要とする。   Here, if there is no switching element 30 to be described later, when an overcurrent such as a short circuit of the output terminal is detected, the charge accumulated in the gate is discharged, and the source and the gate become substantially the same potential and are in the off state. It takes a certain amount of time to become.

本実施例には、出力端子が短絡される等の過電流を検出したとき、ゲートに溜まった電荷を放電するために、スイッチング素子30を、設けている。この素子30は、nチャネル型MOSFET素子であって、前記放電用FET素子92のソースと前記ゲート間にスイッチング素子30を挿入し、そのゲート電圧は前記電池電圧より定電圧が供給され、前記放電用FET素子の前記ソースと、前記ゲート間に、前記スイッチング素子のソースとドレインが接続される。抵抗R3を介して、ゲートに印加される定電圧は、パック電池A内で、電池電圧よりレギュレータ回路(図示せず)にて供給される2.5Vの電圧である。   In this embodiment, the switching element 30 is provided in order to discharge the charge accumulated in the gate when an overcurrent such as a short circuit of the output terminal is detected. The element 30 is an n-channel MOSFET element, and the switching element 30 is inserted between the source and the gate of the discharging FET element 92, and the gate voltage is supplied with a constant voltage from the battery voltage. The source and drain of the switching element are connected between the source of the FET element for use and the gate. The constant voltage applied to the gate via the resistor R3 is a voltage of 2.5 V supplied from the battery voltage by a regulator circuit (not shown) in the battery pack A.

また、上述のように、過電流である異常電流については、MPU内の制御部5のプログラム実行処理により充電用FET素子91、放電用FET素子92をオフ状態としているが、プログラム実行処理により、実際に過電流が流れて素子をオフするまでに、時間を要する(約1.0S以下程度)。本実施例においては、パック電池Aの短絡等により、非常に大きな過電流が流れたとき、MPUより充電用FET素子91、放電用FET素子92をオフ状態とするには時間がかかるので、MPUのプログラム実行処理より先に、制御回路10の機能にて、放電用FET素子92をオフ状態としている。制御回路10内には、電流検出抵抗2の両端電圧を検出する電圧検出回路19を備えている。この電圧検出回路19においては、所定電圧より大きい、過電流に相当する電圧が入力されるとき、この電圧検出回路19より、昇圧回路11Dに、放電用FET素子92をオフとするため、上述のMPUからと同様に、オフ信号を発して、スイッチSWをオン状態とし、供給スイッチ12をオフとする。このように、制御回路10は保護回路機能を備えている。なお、制御回路10のこのような保護回路機能をなくして、上述のように、MPU内の制御部5のプログラム実行処理により、充電用FET素子91、放電用FET素子92をオフ状態とする保護回路機能だけとしても良い。本発明においては、保護回路機能として、充電用FET素子91、放電用FET素子92をオフ状態とする制御手段としては、制御回路10又は制御部5を利用している。   As described above, for the abnormal current that is an overcurrent, the charging FET element 91 and the discharging FET element 92 are turned off by the program execution process of the control unit 5 in the MPU. It takes time (about 1.0 S or less) until an overcurrent actually flows and the device is turned off. In this embodiment, when a very large overcurrent flows due to a short circuit of the battery pack A or the like, it takes time to turn off the charging FET element 91 and the discharging FET element 92 from the MPU. Prior to the program execution process, the discharging FET element 92 is turned off by the function of the control circuit 10. The control circuit 10 includes a voltage detection circuit 19 that detects the voltage across the current detection resistor 2. In this voltage detection circuit 19, when a voltage larger than a predetermined voltage and corresponding to an overcurrent is input, the voltage detection circuit 19 turns off the discharging FET element 92 from the voltage detection circuit 19 to the booster circuit 11D. Similarly to the MPU, an off signal is issued to turn on the switch SW and turn off the supply switch 12. Thus, the control circuit 10 has a protection circuit function. In addition, the protection circuit function of the control circuit 10 is eliminated, and the charge FET element 91 and the discharge FET element 92 are turned off by the program execution process of the control unit 5 in the MPU as described above. Only the circuit function may be used. In the present invention, the control circuit 10 or the control unit 5 is used as a control means for turning off the charging FET element 91 and the discharging FET element 92 as a protection circuit function.

以下に、本実施例の特徴であるスイッチング素子30の動作について、詳細に説明する。   Hereinafter, the operation of the switching element 30 which is a feature of the present embodiment will be described in detail.

例えば、ネックレス等の金属製異物が出力端子間に誤って配置され短絡事故が発生したり、電子機器に装着された状態で、電子機器側の放電回路に短絡事故が発生した等の理由により、出力端子が短絡される等の過電流を検出したとき、制御回路10の電圧検出回路19が検出して、放電用FET素子92をオフとするため、オフ信号を発して、スイッチSWをオン状態とし、供給スイッチ12をオフとする。これにより、前記昇圧回路11Dをバイパスして前記電池電圧印加経路にて前記電池電圧を前記ゲートに印加しゲートに溜まった電荷をソース等に放電し、ソースとゲートが略同電位となってオフ状態となるには、スイッチング素子がないなら、上述のように、ある程度の時間を必要とする。特に、ノイズ、短絡防止のために、抵抗R2、R4が設けられているので、時間を必要とする。   For example, a metal foreign object such as a necklace is accidentally placed between the output terminals and a short-circuit accident occurs, or a short-circuit accident occurs in the discharge circuit on the electronic device side while attached to the electronic device, etc. When an overcurrent such as an output terminal is short-circuited is detected, the voltage detection circuit 19 of the control circuit 10 detects it, and in order to turn off the discharging FET element 92, an off signal is issued and the switch SW is turned on. And the supply switch 12 is turned off. Thereby, the battery voltage is applied to the gate in the battery voltage application path by bypassing the booster circuit 11D, and the charge accumulated in the gate is discharged to the source or the like, and the source and the gate become substantially the same potential and are turned off. To enter the state, if there is no switching element, a certain amount of time is required as described above. In particular, the resistors R2 and R4 are provided in order to prevent noise and short circuit, so that time is required.

スイッチング素子30がないとした場合、このときの時間(T)経過に伴う、放電電流(チャンネルCH3)、放電用FET素子92のゲート−ソース間の電圧(ソースを基準としてゲートの電圧)(チャンネルCH1)を、図2(a)に示す。図2(a)のCH3は、電流検出抵抗2の両端電圧を示し、このグラフに示されるように、短絡等により大きな電流が流れ始める。そして、電流発生より、約370μsec(100μsec/div)経過して、上述の電圧検出回路19がオフ信号を発して、スイッチSWをオフ状態とし、供給スイッチ12がオンにすることで、ゲートに溜まった電荷を放電し、図2(a)のCH1のGS間電圧が徐々に低下する。約680μsec(t1)経過して、GS間電圧が約2.0V以下となったとき、放電用FET素子92がオフ状態となり、電流がほぼゼロとなっている。   If the switching element 30 is not provided, the discharge current (channel CH3), the voltage between the gate and the source of the discharge FET element 92 (the gate voltage with reference to the source) (channel) with the passage of time (T) at this time CH1) is shown in FIG. CH3 in FIG. 2A indicates a voltage across the current detection resistor 2, and as shown in this graph, a large current starts to flow due to a short circuit or the like. Then, after about 370 μsec (100 μsec / div) has elapsed from the current generation, the voltage detection circuit 19 emits an off signal, the switch SW is turned off, and the supply switch 12 is turned on, so that the gate is accumulated at the gate. The discharged electric charge is discharged, and the GS voltage of CH1 in FIG. When about 680 μsec (t1) elapses and the GS voltage becomes about 2.0 V or less, the discharging FET element 92 is turned off and the current is almost zero.

図2(b)には、本実施例において、時間(T)経過に伴う、放電電流(CH3)(電流検出抵抗2の両端電圧を示す)、放電用FET素子92のゲート−ソース間の電圧(ソースを基準としてゲートの電圧)(CH1)、スイッチング素子30のゲート−ソース間の電圧(CH2)を示す。図2(b)においては、上述と同様に、過電流が発生し、電流発生より、約370μsec(100μsec/div)経過して、上述の電圧検出回路19がオフ信号を発して、スイッチSWをオフ状態とし、供給スイッチ12がオンにすることで、ゲートに溜まった電荷を放電し、図2(b)のCH1のGS間電圧が徐々に低下する。   FIG. 2B shows the discharge current (CH3) (showing the voltage across the current detection resistor 2) and the voltage between the gate and source of the discharge FET element 92 over time (T) in this embodiment. (Gate voltage with reference to the source) (CH1) and gate-source voltage (CH2) of the switching element 30 are shown. In FIG. 2B, as described above, an overcurrent is generated, and about 370 μsec (100 μsec / div) has elapsed from the occurrence of the current, and then the voltage detection circuit 19 generates an OFF signal, and the switch SW is turned on. When the supply switch 12 is turned on in the off state, the charge accumulated in the gate is discharged, and the voltage between GS of CH1 in FIG. 2B gradually decreases.

また、スイッチング素子30のGS間電圧(CH2)の経時変化について、以下に説明する。放電用FET素子92のゲートに溜まった電荷を放電するとき、ゲート電位が、ソース電位に近づくと、放電用FET素子92のソース、ドレイン間抵抗が増大し、過電流の電流値が絞られて、電流値が小さくなる。出力端子が短絡された状態で、電流値が小さくなると、異物の電気抵抗は略一定であるので、電流値が小さくなることで出力端子間の電圧も、小さくなる。出力端子間の電圧が低下することで、スイッチング素子30のソース電位が低下して、ゲート・ソース間電圧がゲート閾値電位以下となり、スイッチング素子がオン30される。つまり、スイッチング素子30のゲートには、レギュレータ回路より定電圧(約2.5V)が供給されているので、ソース電位が低下してゼロVに近い約0.5Vになると、経過時間約640msec(t2)にてスイッチング素子30のGS間電圧(CH2)が約2.0Vとなり、ゲート電圧がオン信号状態となるので、スイッチング素子30はオン状態となる。このオン状態のスイッチング素子30を介して放電用FET素子92のゲートに溜まった電荷を素早く、瞬時に、放電し、前記放電用FET素子92のソースと前記ゲート間が同電位となり、素早く、瞬時に、放電用FET素子をオフ状態とし、電流を遮断することができる。   Further, the change with time of the GS voltage (CH2) of the switching element 30 will be described below. When discharging the charge accumulated at the gate of the discharging FET element 92, when the gate potential approaches the source potential, the resistance between the source and drain of the discharging FET element 92 increases, and the current value of the overcurrent is reduced. The current value becomes small. When the current value is reduced in a state where the output terminal is short-circuited, the electric resistance of the foreign matter is substantially constant. Therefore, the voltage between the output terminals is reduced as the current value is reduced. As the voltage between the output terminals decreases, the source potential of the switching element 30 decreases, the gate-source voltage becomes equal to or lower than the gate threshold potential, and the switching element is turned on 30. That is, since a constant voltage (about 2.5 V) is supplied from the regulator circuit to the gate of the switching element 30, when the source potential decreases to about 0.5 V, which is close to zero V, an elapsed time of about 640 msec ( At t2), the GS voltage (CH2) of the switching element 30 becomes approximately 2.0 V, and the gate voltage is turned on, so that the switching element 30 is turned on. The charges accumulated in the gate of the discharging FET element 92 are quickly and instantaneously discharged through the switching element 30 in the on state, and the potential between the source and the gate of the discharging FET element 92 becomes the same potential. In addition, the discharging FET element can be turned off to interrupt the current.

特に、上述のように、過電流検出の後、放電用FET素子のゲートに溜まった電荷を放電するとき、ゲート電位が、ソース電位に近づくと、放電用FET素子92のソース、ドレイン間抵抗が増大するので、このとき、大電流である過電流を流し続けると、放電用FET素子92が熱破壊をきたすことがある。よって、本実施例においては、放電用FET素子92のソース、ドレイン間抵抗が増大するとき、スイッチング素30子により、素早く、瞬時に、放電用FET素子92をオフ状態とすることで、このような放電用FET素子92の熱破壊を防止することができる。図2(a)、(b)にて確認できるように、本実施例において、スイッチング素子30を利用することで、過電流開始より、放電用FET素子92をオフ状態として、電流を遮断するのに、約40μsec(t1−t2)程度、改善されている。   In particular, as described above, when discharging the charge accumulated in the gate of the discharging FET element after the overcurrent detection, when the gate potential approaches the source potential, the resistance between the source and drain of the discharging FET element 92 is increased. At this time, if an overcurrent that is a large current continues to flow, the discharging FET element 92 may be thermally destroyed. Therefore, in the present embodiment, when the resistance between the source and drain of the discharging FET element 92 increases, the switching FET element 92 quickly and instantaneously turns off the discharging FET element 92 as described above. It is possible to prevent thermal destruction of the discharge FET element 92. As can be seen in FIGS. 2A and 2B, in this embodiment, by using the switching element 30, the discharge FET element 92 is turned off from the start of the overcurrent, thereby interrupting the current. In addition, it is improved by about 40 μsec (t1-t2).

本発明の電池パックの回路ブロック図である。It is a circuit block diagram of the battery pack of the present invention. 本発明の実施例等の電気特性を示すグラフである。It is a graph which shows the electrical property of the Example of this invention.

符号の説明Explanation of symbols

A 電池パック
PC 電子機器
MPU マイクロプロセッサユニット
1 電池
2 電流検出抵抗(電流検出部)
4 残容量積算処理部
5 制御部
91 充電用FET素子
92 放電用FET素子
10 制御回路
11 昇圧回路

A Battery pack PC Electronic device MPU Microprocessor unit 1 Battery 2 Current detection resistor (current detection unit)
4 remaining capacity integration processing unit 5 control unit 91 charging FET element 92 discharging FET element 10 control circuit 11 boosting circuit

Claims (2)

パック電池内に、電池と、充放電経路の高電圧側に配置されたn型半導体の放電用FET素子と、制御手段と、該制御手段からのオンオフ信号に基づき、昇圧されたオン信号に対応したゲート電圧にて放電用FET素子をオンオフ制御する昇圧回路とを備え、
前記昇圧回路においては、電池電圧を電池電圧印加経路を介して印加して、該電池電圧より昇圧した電圧をゲートに供給して前記放電用FET素子をオン状態とし、前記昇圧回路をバイパスして前記電池電圧印加経路にて前記電池電圧を前記ゲートに印加して前記放電用FET素子をオフとし、
前記放電用FET素子のソースと前記ゲート間にスイッチング素子を挿入したことを特徴とするパック電池。
In the battery pack, the battery, the n-type semiconductor discharge FET element arranged on the high voltage side of the charge / discharge path, the control means, and the boosted on signal based on the on / off signal from the control means And a booster circuit that controls on / off of the discharging FET element with the gate voltage,
In the booster circuit, a battery voltage is applied via a battery voltage application path, a voltage boosted from the battery voltage is supplied to the gate to turn on the discharging FET element, and the booster circuit is bypassed. Applying the battery voltage to the gate in the battery voltage application path to turn off the discharging FET element,
A battery pack, wherein a switching element is inserted between a source of the discharging FET element and the gate.
前記スイッチング素子は、FET素子であって、そのゲート電圧は前記電池電圧より定電圧が供給され、
前記放電用FET素子の前記ソースと、前記ゲート間に、前記スイッチング素子のソースとドレインが接続されることを特徴とする請求項1のパック電池。


The switching element is an FET element, and the gate voltage is supplied with a constant voltage from the battery voltage,
2. The battery pack according to claim 1, wherein a source and a drain of the switching element are connected between the source of the discharging FET element and the gate.


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WO2010035431A1 (en) * 2008-09-25 2010-04-01 Necトーキン株式会社 Multiple series/multiple parallel battery pack
CN102376991A (en) * 2010-08-04 2012-03-14 三洋电机株式会社 Battery pack for practical low-power mode current detection and method of detecting excessive current
US9063200B2 (en) 2011-04-28 2015-06-23 Sanyo Electric Co., Ltd. Battery pack, method of determining malfunction, and a malfunction decision circuit
JP2013150139A (en) * 2012-01-19 2013-08-01 Asahi Kasei Electronics Co Ltd Power supply connection device
JP2014110731A (en) * 2012-12-04 2014-06-12 Sanyo Electric Co Ltd Battery pack
CN103943798A (en) * 2014-05-09 2014-07-23 廖建勋 Conversion bracket for converting AAA battery to 6F22 battery
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