JP7461253B2 - Step-up switching regulator - Google Patents

Description

The present invention relates to a step-up switching regulator having a circuit that protects switching elements from short-circuits to power supply.

Today, there is an increasing demand for switching regulators as small, lightweight, and highly efficient power sources for devices that operate on DC voltage, particularly as DC-DC converters for mobile and portable devices that use batteries or storage batteries. At the same time, the requirements for safety and reliability in switching regulators are also becoming higher.

Most switching regulators are equipped with a protection circuit to protect the power supply and load from overcurrent, short circuits, etc. Generally, this type of protection circuit detects the current flowing through the switching element, and when the current detection value exceeds a predetermined monitoring value or threshold, it determines that an undesirably large current, i.e. an overcurrent, is flowing. When such an overcurrent is detected, the protection circuit is of the overcurrent limiting type (pulse-by-pulse method), which limits the on-time of each cycle of the pulse-width modulated signal to continue to pass current to the load, and of the cut-off type, which stops the on/off operation of the switching element to cut off the current supply to the load, and it is also possible to combine both types.

Although the overcurrent limiting type can prevent malfunctions in the event of a temporary overload, if the overcurrent continues to flow near the limit value even after limiting the overcurrent, the device may eventually generate a large amount of heat or be destroyed. Therefore, when overcurrent detection continues for a long period of time over many consecutive cycles, a conventional technique is to count the number of detections, and when the number of detections reaches a set number, to completely stop the switching operation using a cutoff type method and cut off the output current.

However, if the overcurrent cannot be limited while counting the number of overcurrent detections over a large number of consecutive cycles, there is a risk that the device circuit will break down before the set number is reached. Therefore, while counting the number of overcurrent detections and continuing current limitation using the pulse-by-pulse method, if the overcurrent increases further and exceeds a high second threshold for short circuit detection, the switching operation is stopped at that point and the output current is cut off, even if the number of detections has not yet reached the set number.

Japanese Patent Application Publication No. 2014-3850

The basic configuration of a boost switching regulator is to provide a choke coil and a diode in series between the input terminal and the output terminal, a switching element between a first node between the choke coil and the diode and ground potential, and a capacitor between a second node between the diode and the output terminal and ground potential. In such a boost switching regulator, if a short circuit or layer short occurs in the choke coil for some reason, the first node is shorted to the power supply, causing an abnormal overcurrent to flow in the switching element, which can lead to the destruction of the switching element.

In this regard, in conventional switching regulators, an overcurrent limiting type protection circuit always operates preferentially to limit any overcurrent to near the lower first threshold value. Therefore, even if there is an abnormal overcurrent that is likely to exceed the second threshold, which is high from the beginning, the current is limited by pulse-by-pulse, and the time until it exceeds the second threshold is extended, and during that time, The switching element may generate a large amount of heat and be destroyed. In particular, when an abnormal overcurrent flows through the switching element due to a not-so-low impedance, such as a rare short circuit, the pulse-by-pulse current limiting works moderately, so the above-mentioned elongation time is prolonged, and a large amount of current flows through the switching element. Heat generation and thermal destruction are likely to occur.

The present invention solves the problems of the conventional technology and provides a step-up switching regulator that can safely and accurately protect switching elements from short circuits to the power supply.

A step-up switching regulator according to a first aspect of the present invention is a step-up switching regulator that converts a DC input voltage into a DC output voltage higher than the input voltage via a coil and a switching element, A load switch connected in series with the switching element, a switching control unit that turns on and off the switching element at a constant frequency and a variable duty ratio, and a current that generates a current detection signal representing the current flowing through the switching element. a detection circuit; and a blanking circuit that inserts a blanking period with a variable or switchable time width immediately after the start of the on-time in each switching cycle, and the current detection signal is detected after the end of the blanking period. a first protection circuit that turns off the switching element midway through the switching control unit when the current detection signal exceeds the first monitoring value during the ON time in each switching cycle; and a second protection circuit that turns off the load switch when the second higher monitoring value is exceeded.

In the step-up switching regulator having the above configuration, in each switching cycle, during the blanking period immediately after the start of the on-time, if the current detection signal corresponding to the current flowing through the switching element exceeds the lower first monitoring value, neither the load switch nor the switching element is turned off, but when it exceeds the higher second monitoring value, the load switch is turned off to cut off the power supply line. Then, if the current detection signal does not exceed the second monitoring value during the blanking period but exceeds the first monitoring value during the blanking period or after the end of the blanking period, the switching element is turned off to end the on-time of the cycle midway. In this way, by inserting a blanking period that brings about the above-mentioned action immediately after the start of the on-time, it is possible to cut off the power supply line early without extending the abnormal overcurrent caused by a power short by pulse-by-pulse current limiting, thereby preventing the destruction of the switching element. Moreover, by varying the time width of the blanking period or switching between multiple set time widths, it is possible to quickly and accurately cut off the power supply line without extending the abnormal overcurrent state even if a power short with a not-so-low impedance such as a layer short occurs, and it is possible to prevent the switching element from generating a large amount of heat or being destroyed.

A step-up switching regulator according to a second aspect of the present invention is a step-up switching regulator that converts a DC input voltage into a DC output voltage higher than the input voltage via a switching element and a coil, and wherein the switching element and a load switch connected in series with the coil; a switching controller that turns on and off the switching element at a constant frequency and a variable duty ratio; Monitoring is performed using the monitored value and a second monitored value higher than the monitored value, and a blanking period is conditionally inserted immediately after the start of the on time depending on the presence or absence of a predetermined event or the situation, and during the blanking period. When the current exceeds the second monitoring value, the load switch is turned off, and when the current exceeds the first monitoring value after the end of the blanking period, the switching control is turned off. and a protection part that turns off the switching element midway through the part.

In the step-up switching regulator configured as described above, blanking is performed immediately after the start of the on-time in a specific cycle of switching (for example, limited to one or several cycles immediately after an abnormal drop in the output voltage is detected). When a period is inserted, neither the load switch nor the switching element is turned off even if the current detection signal corresponding to the current flowing through the switching element exceeds the lower first monitoring value during the blanking period. , the load switch is turned off to cut off the power supply line when the second higher monitored value is exceeded. If the current detection signal does not exceed the second monitoring value during the blanking period and exceeds the first monitoring value after the blanking period ends, the switching element is turned off and the on-time of the cycle is Ends midway. In this way, when an abnormal drop in the output voltage is detected, a blanking period that produces the above effect is inserted immediately after the start of the on-time to prevent abnormal overcurrent caused by a short-circuit. Pulse-by-pulse current limiting allows the power supply line to be cut off early without being extended, thereby preventing heat generation or destruction of the switching element.

A step-up switching regulator according to a third aspect of the present invention is a step-up switching regulator that converts a DC input voltage into a DC output voltage higher than the input voltage via a switching element and a coil, and wherein the switching element and a load switch connected in series with the coil; a switching controller that turns on and off the switching element at a constant frequency and a variable duty ratio; Monitoring is performed using the monitored value and a second monitored value higher than the monitored value, and a first partial monitoring period whose time width is variable or switchable is provided immediately after the start of the on-time in each switching cycle, and the first partial monitoring period is provided with a variable or switchable time width. When the current exceeds the second monitoring value during the partial monitoring period, the load switch is turned off, and during the second partial monitoring period remaining after the end of the first partial monitoring period, The device further includes a protection unit that turns off the switching element midway through the switching control unit when the current exceeds the first monitoring value.

In the step-up switching regulator having the above configuration, in each switching cycle, during the first partial monitoring period immediately after the start of the on-time, if the current detection signal corresponding to the current flowing through the switching element exceeds the lower first monitoring value, neither the load switch nor the switching element is turned off, but when it exceeds the higher second monitoring value, the load switch is turned off and the power supply line is cut off. Then, when the current detection signal does not exceed the second monitoring value during the first partial monitoring period but exceeds the first monitoring value during the second partial monitoring period, the switching element is turned off and the on-time of the cycle is terminated midway. In this way, by setting the first and second partial monitoring periods that have the above-mentioned effect on the on-time of each switching cycle, the power supply line can be cut off early without extending the abnormal overcurrent by pulse-by-pulse current limiting, thereby preventing the switching element from heating up or breaking down. Moreover, by varying the time width of the first partial monitoring period or switching between multiple set time widths, even if a power short occurs with a relatively low impedance, such as a layer short, it is possible to quickly and accurately cut off the power supply line without prolonging the abnormal overcurrent state, and it is possible to prevent the switching element from generating a large amount of heat or being destroyed.

A boost switching regulator in a fourth aspect of the present invention is a boost switching regulator that converts a DC input voltage into a DC output voltage higher than the input voltage via a switching element and a coil, and includes a load switch connected in series with the switching element and the coil, a switching control unit that turns the switching element on and off at a constant frequency and a variable duty ratio, and a protection unit that monitors the current flowing through the switching element in each switching cycle using a first monitoring value and a second monitoring value that is higher than the first monitoring value, provides a first partial monitoring period immediately after the start of the on time in each switching cycle, turns off the load switch when the current exceeds the second monitoring value during the first partial monitoring period, and turns off the switching element midway through the switching control unit when the current exceeds the first monitoring value during the remaining second partial monitoring period after the end of the first partial monitoring period.

In the step-up switching regulator having the above configuration, in each switching cycle, during the first partial monitoring period immediately after the start of the on-time, if the current detection signal corresponding to the current flowing through the switching element exceeds the lower first monitoring value, neither the load switch nor the switching element is turned off, but when it exceeds the higher second monitoring value, the load switch is turned off and the power supply line is cut off. Then, when the current detection signal does not exceed the second monitoring value during the first partial monitoring period but exceeds the first monitoring value during the second partial monitoring period, the switching element is turned off and the on-time of the cycle is terminated midway. In this way, by setting the first and second partial monitoring periods that have the above-mentioned effect on the on-time of each switching cycle, the power supply line can be cut off early without extending the abnormal overcurrent by pulse-by-pulse current limiting, thereby preventing the switching element from heating up or being destroyed.

In a preferred embodiment of the present invention, when the load switch is turned off, the on/off operation of the switching element is stopped via the switching control unit. In this way, when a short circuit to the power supply occurs, the switching element itself is kept in the off state in addition to cutting off the power supply line, thereby more safely and reliably protecting the switching element and allowing the switching control unit to operate more stably.

According to the step-up switching regulator of the present invention, due to the above-described configuration and operation, the switching element can be safely and accurately protected from short-circuits to the power supply, and furthermore, it can prevent abnormal overcurrents due to not-so-low impedance such as layer shorts. Even if this occurs, it can be properly protected.

FIG. 1 is a block diagram showing the overall configuration of a step-up switching regulator in an embodiment of the present invention. FIG. 4 is a circuit diagram showing a more specific configuration example of the step-up switching regulator in the embodiment. 3 is a circuit diagram showing a specific configuration example of a blanking circuit included in the step-up switching regulator of FIG. 2. 4 is a diagram showing waveforms or states of various parts for explaining the operation of an SST status determination circuit included in the blanking circuit of FIG. 3. FIG. 5 is a diagram showing waveforms or states of various parts for explaining the operation of the FB status determination circuit included in the blanking circuit of FIG. 4; FIG. 5 is a diagram showing waveforms or states of each part for explaining the operation regarding the OCP1 status determination circuit included in the blanking circuit of FIG. 4. FIG. FIG. 3 is a diagram showing waveforms or states of various parts in the step-up switching regulator shown in FIG. 2 to explain the effect when a short-circuit with very low impedance suddenly occurs during a certain switching cycle. 3 is a diagram showing waveforms or states of various parts to explain the operation when a short circuit to power, the impedance of which is not so low, suddenly occurs in a certain switching cycle in the step-up switching regulator of FIG. 2. FIG.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.
[Overall configuration of switching regulator]

Figure 1 shows the overall configuration of a step-up switching regulator in one embodiment of the present invention. This step-up switching regulator is configured as a DC-DC converter that converts a DC voltage VDD input from an input terminal 10 into a DC voltage VOUT that is controlled to a higher constant voltage value and supplies it to a load from an output terminal 12. Typically, the load is connected between the output terminal 12 and a ground potential terminal. The input terminal 10 is connected to, for example, a battery or a storage battery (not shown).

This step-up switching regulator has, as its basic components, a step-up chopper circuit 16 and a switching control section 18. The step-up chopper circuit 16 has a choke coil 11 and a diode 13 connected in series between an input terminal 10 and an output terminal 12, a switching element 14 connected between a node _NA between the choke coil 11 and the diode 13 and ground potential, and a capacitor 15 connected between a node _NB between the diode 13 and the output terminal 12 and ground potential. The switching element 14 is preferably a semiconductor switching element that can be turned on and off at high speed, and may be, for example, a switching transistor made of a MOSFET.

The switching control unit 18 includes a voltage detection circuit 22, an error amplifier 24, a reference voltage circuit 26, and a switching circuit 28.

The voltage detection circuit 22 detects the output voltage VOUT obtained at the output terminal side of the boost chopper circuit 16 and provides a voltage detection signal FB representing this to the error amplifier 24. The error amplifier 24 is also provided with two types of reference voltages VREF3 and SST from the reference voltage circuit 26. One of the reference voltages, VREF3, has a constant voltage level corresponding to the set value of the output voltage VOUT. The other reference voltage, SST, is for soft starting, which gradually raises the output voltage VOUT at the time of start-up or restart, and has a variable voltage level. More specifically, the reference voltage SST gradually rises from a ground potential lower than the fixed level of the reference voltage VREF3 to the input voltage VDD level higher than VREF3 at the time of start-up or restart. Then, when the switching operation is stopped and the device is shut down, the reference voltage SST instantly drops from the previous VDD level to the ground potential.

The error amplifier 24 is configured to compare the voltage detection signal FB from the voltage detection circuit 22 with the lower of the reference voltages VREF3 and SST from the reference voltage circuit 26 to generate an error signal ER representing a comparison error. ing. In the steady state, SST>VREF3, and the error amplifier 24 provides the switching circuit 28 with an error signal ER obtained by comparing the voltage detection signal FB with the lower reference voltage VREF3.

The switching circuit 28 includes an oscillator circuit that generates a ramp signal such as a sawtooth signal or a triangular wave signal at a switching frequency, and an error signal ER from the error amplifier 24, which compares the ramp signal with the magnitude relationship between the two and converts it into a binary voltage. It includes a comparator that outputs a pulse width modulation signal represented by a level (H level/L level), and a driver circuit that drives the switching element 14 on and off using a drive signal DRV corresponding to the pulse width modulation signal.

With the above-described configuration, the switching control section 18 turns on and off the switching element 14 at a constant switching frequency and a variable duty ratio. Here, while the switching element 14 is on, a current flows from the input terminal 10 to the ground potential terminal through the choke coil 11 and the switching element 14, and electromagnetic energy is accumulated in the choke coil 11. At this time, an induced electromotive force is generated in the choke coil 11 that opposes the input voltage VDD. During the period when the switching element 14 is off, electromagnetic energy is released (supplied) from the choke coil 11 to the capacitor 15 or the load via the diode 13, and at this time, the input voltage is set so that the current continues to flow through the choke coil 11. An induced electromotive force is generated in the same direction as VDD. In this way, an output voltage VOUT higher than the input voltage VDD is obtained at the output terminal 12. The switching control unit 18 supplies a temporally continuous output current IL to the load while maintaining the output voltage VOUT near a set value through feedback control.

In addition to the boost chopper circuit 16 and switching control unit 18 described above, this boost switching regulator also has a load switch 200, a load switch drive circuit 202, and a protection unit 20.

Load switch 200 is preferably made of a MOSFET, and is connected in series with choke coil 11 and switching element 14 on the power supply line. More specifically, the load switch 200 is provided between the input terminal 10 and the choke coil 11 (or between the choke coil 11 and the node _NA ) on the power supply line. The load switch drive circuit 202 keeps the load switch 200 in the on state under normal conditions, and when it receives a cutoff instruction signal OCP2, which will be described later, from the protection unit 20, it turns the load switch 200 in the off state in response. There is.

The protection unit 20 in this embodiment includes a current detection circuit 30, a small overcurrent monitoring circuit (first overcurrent monitoring circuit) 32, a blanking circuit 34, a gate circuit 36, and a large overcurrent monitoring circuit (second overcurrent monitoring circuit). (monitoring circuit) 38 and a cutoff/return circuit 40. Among these, the small overcurrent monitoring circuit 32, the blanking circuit 34, and the gate circuit 36 constitute an overcurrent limiting circuit (first protection circuit) 42. On the other hand, the large overcurrent monitoring circuit 38 and the cutoff/recovery circuit 40 constitute a short circuit protection circuit (second protection circuit) 44 .

As will be described later, the protection unit 20 divides the current IS flowing through the switching element 14 in each switching cycle into a predetermined first monitoring value (low monitoring value) and a predetermined second monitoring value (high monitoring value) higher than that. ), and a first partial monitoring period (blanking period BT) with a variable or switchable time width is provided immediately after the start of the on-time in each switching cycle, and the first partial monitoring period (BT ), when the current IS exceeds the second monitoring value, the load switch 200 is turned off through the load switch drive circuit 202, and at the same time, the on/off operation of the switching element 14 is stopped through the switching control section 18, When the current IS exceeds the first monitoring value during the second partial monitoring period remaining after the end of the first partial monitoring period (BT), the switching element 14 is stopped midway through the switching control section 18. It's supposed to be turned off.

The signal DRV output from the switching circuit 28 of the switching control section 18 is not only given as a drive signal to the switching element 14 as described above, but also is applied to the blanking circuit 34 of the protection section 20, the current detection circuit 30, and both It is also given to the overcurrent monitoring circuits 32 and 38 as a timing control signal indicating the on/off status of the switching element 14.

The current detection circuit 30 responds to the timing control signal DRV from the switching circuit 28, detects the current IS flowing through the switching element 14 via the current sensor 46 for each switching cycle CYi, and represents the waveform of the current IS. It is configured to generate a current detection signal VOCP. This current detection signal VOCP is applied to both overcurrent monitoring circuits 32 and 38.

The small overcurrent monitoring circuit 32 of the overcurrent limiting circuit 42 monitors the current detection signal VOCP during the on time of each switching cycle CYi in response to the timing control signal DRV from the switching circuit 28, and outputs the current detection signal VOCP. When exceeds the lower monitoring value (first monitoring value) VREF1 for pulse-by-pulse, a small overcurrent detection signal EXD1 (first overcurrent detection signal) is generated. This small overcurrent detection signal EXD1 is input to the gate circuit 36.

A pulse signal or blanking signal BLK from the blanking circuit 34 is also input to the gate circuit 36. This blanking signal BLK is for inserting a blanking period BT immediately after the start of the on-time T _ON of each switching cycle CYi, and its pulse width defines the time width TW of the blanking period BT.

The blanking circuit 34 not only inputs the timing control signal DRV from the switching circuit 28 but also inputs the voltage detection signal FB from the voltage detection circuit 22, the variable reference voltage SST from the reference voltage circuit 26, and the gate circuit 36. A current limit instruction signal OCP1, which will be described later, is input as an event information signal indicating the presence or absence or status of each event.

The blanking circuit 34 controls or selects the generation conditions and characteristics of the blanking signal BLK based on the event information signals FB, SST, and OCP1, and particularly varies the time width TW of the blanking period BT, or It is configured to switch between set time widths (for example, a normal time width TW _S and an extended time width TW _L to be described later). The detailed configuration and operation of the blanking circuit 34 will be explained in detail later.

While the pulse of the blanking signal BLK continues, that is, during the blanking period BT, the gate circuit 36 invalidates the small overcurrent detection signal EXD1 even if it is generated by the small overcurrent monitoring circuit 32. However, after the duration of the blanking signal BLK (the blanking period BT) ends, when the small overcurrent detection signal EXD1 is generated by the small overcurrent monitoring circuit 32, the gate circuit 36 responds by outputting a current limit instruction signal OCP1 to the switching circuit 28. Upon receiving the current limit instruction signal OCP1 from the gate circuit 36, the switching circuit 28 immediately turns off the switching element 14 and ends the on-time T _ON of the cycle CYi in the middle.

In this way, the overcurrent limiting circuit 42 includes a blanking circuit 34 that inserts a variable or switchable blanking period BT with a time width TW immediately after the start of _{the on} -time TON in each switching cycle CYi. . In each switching cycle CYi, the overcurrent limiting circuit 42 monitors the current detection signal VOCP given by the current detection circuit 30 using the pulse-by-pulse low monitoring value VREF1, and during the blanking period BT, the Even if the detection signal VOCP exceeds the low monitoring value VREF1, no action is taken on the switching circuit 28, and when the current detection signal VOCP exceeds the low monitoring value VREF1 after the end of the blanking period BT, the current detection signal VOCP immediately A current limit instruction signal OCP1 for turning off the switching element 14 is applied to the switching circuit 28.

On the other hand, the large overcurrent monitoring circuit 38 of the short circuit protection circuit 44 responds to the timing control signal DRV from the switching circuit 28 to monitor the current detection signal VOCP provided by the current detection circuit 30 during the on-time T _ON of each switching cycle _CYi , and when the current detection signal VOCP exceeds a high monitoring value (second monitoring value) VREF2 for cut-off (where VREF1<VREF2), generates a large overcurrent detection signal (second overcurrent detection signal) EXD2 at that timing. This large overcurrent detection signal EXD2 is provided to the cut-off and recovery circuit 40.

When the shutoff/recovery circuit 40 receives the large overcurrent detection signal EXD2 from the large overcurrent monitoring circuit 38, it responds by outputting a shutoff instruction signal OCP2. This shutoff instruction signal OCP2 turns off the load switch 200 via the load switch drive circuit 202, and at the same time stops the on/off operation of the switching element 14 via the switching circuit 28. As a result, the current IS does not flow through the switching element 14. Furthermore, as the power supply line is shut off by the load switch 200, the output current IL disappears and the output voltage VOUT drops to ground potential.

When shutting down as described above, the cutoff/return circuit 40 cancels the cutoff instruction signal OCP2 to the load switch drive circuit 202 and the switching circuit 28 and turns on the load switch 200 after a predetermined period of time has elapsed. The state is restored, and a soft start is restarted through the switching control unit 18. In the soft start restart, the variable reference voltage SST in the variable reference voltage generation circuit 68 (FIG. 2) gradually rises from the ground potential up to that point to the VDD level. The error amplifier 24 uses SST as a comparison reference voltage for the voltage detection signal FB until SST exceeds VREF3. As the comparison reference voltage SST gradually increases, the duty ratio of the pulse width modulation signal PWM gradually increases, and as long as the short-circuit condition is resolved, the output voltage VOUT gradually rises.

Furthermore, when the gate circuit 36 of the overcurrent limiting circuit 42 generates a current limiting instruction signal OCP1, the shutoff/recovery circuit 40 takes it in. When the number of occurrences of the current limiting instruction signal OCP1 reaches a set value within a predetermined time or within a predetermined number of cycles, an active shutoff instruction signal OCP2 is provided to the load switch driving circuit 202 and the switching control unit 18. In this case, too, the load switch driving circuit 202 turns off the load switch 200, and the switching control unit 18 stops the on/off operation of the switching element 14. Then, after a certain time has passed, the shutoff/recovery circuit 40 releases the shutoff instruction signal OCP2 in the same manner as above, and the load switch 200 returns to the on state, and the switching control unit 18 restarts with a soft start.

In this way, the short circuit protection circuit 44 monitors the current detection signal VOCP given by the current detection circuit 30 using the high monitoring value VREF2 for cutoff in each switching cycle CYi, and performs the blanking given by the blanking signal BLK. Regardless of the period BT, whenever the current detection signal VOCP exceeds the high monitoring value VREF2 during the on-time, a cutoff instruction is issued to turn off the load switch 200 and stop the on/off operation of the switching element 14. A signal OCP2 is applied to the load switch drive circuit 202 and the switching control unit 18, and after a certain period of time, the load switch 200 is returned to the on state and the on/off operation of the switching element 14 is restarted by soft start. .

[Specific configuration example of switching regulator]

FIG. 2 shows a more specific example of the configuration of the step-up switching regulator in this embodiment.

The load switch 200 is composed of a PMOS transistor, the source of which is connected to the input terminal 10, the drain of which is connected to the input terminal of the choke coil 11, and the gate of which is connected to the output terminal of the load switch drive circuit 202.

Load switch drive circuit 202 includes a drive transistor 204 . This drive transistor 204 is made of an NMOS transistor, and its source is connected to a ground potential terminal, and its drain is connected to a control terminal (gate) of a load switch (PMOS transistor) 200, and is also connected to an input terminal 10 via a resistor 206. The gate is connected to the output terminal of the cutoff/return circuit 44 of the protection circuit 20 via the inverter 208.

The switching element 14 of the step-up chopper circuit 16 is composed of an NMOS transistor, the source of which is connected to the ground potential terminal via a sense resistor 82, the drain of which is connected to a node _NA , and the gate of which is connected to the output terminal of a driver circuit 56 of the switching circuit 28. The switching element (NMOS transistor) 14 is turned on/off in accordance with the binary voltage level (H level/L level) of a drive signal DRV given as a pulse signal by the driver circuit 56, and is turned on when DRV is at the H level and turned off when DRV is at the L level.

The switching circuit 28 includes an oscillator circuit 58 and a comparator 60 in addition to the driver circuit 56. The oscillator circuit 58 generates a ramp signal OSC, such as a sawtooth wave signal or a triangular wave signal, at the switching frequency. The comparator 60 compares the error signal ER from the error amplifier 24 with the ramp signal OSC, and outputs a pulse signal that indicates the magnitude relationship between the two with a binary voltage level (H level/L level) as a pulse width modulation signal PWM.

The driver circuit 56 receives not only the pulse width modulation signal PWM from the comparator 60, but also the current limit instruction signal OCP1 from the gate circuit 36 of the overcurrent limit circuit 42 and the cutoff instruction signal OCP2 from the cutoff/recovery circuit 40 of the short circuit protection circuit 44. The driver circuit 56 has a latch circuit, for example an RS flip-flop, and in each switching cycle, sets the drive signal DRV to an active H level in response to the start of the cycle (change from L level to H level) of the pulse width modulation signal PWM. After this, when neither the instruction signals OCP1 nor OCP2 are input, the driver circuit 56 resets the drive signal DRV to an inactive L level at the timing of the level change (H level to L level) of the pulse width modulation signal PWM determined by the current duty ratio. However, when the drive signal DRV is at an active H level, if either the instruction signal OCP1 or OCP2 is input, the driver circuit 56 latches it and resets the drive signal DRV to an inactive L level. In this case, the switching element 14 will turn off midway through its original on-time, which is determined by the current duty ratio.

The voltage detection circuit 22 includes two resistors 62 and 64 connected in series between the output end of the boost chopper circuit 16 and a ground potential terminal, and outputs a voltage detection signal FB from a node N1 between the two resistors. This voltage detection signal FB is not only given to the error amplifier 24 as a feedback signal for constant voltage control, but also given to the blanking circuit 34 as an event information signal indicating the presence or absence of the output voltage VOUT.

The reference voltage circuit 26 has a reference voltage source 66 that outputs a constant-level reference voltage VREF3 corresponding to the set value of the output voltage VOUT, and a variable reference voltage generation circuit 68 that outputs a variable reference voltage SST for soft start. The variable reference voltage generation circuit 68 has a constant current source 70 and a capacitor 72 connected in series between the VDD voltage supply terminal (input terminal 10) and the ground potential terminal, and generates a variable reference voltage SST on a node N2 between the two. An NMOS transistor 80 of the cutoff/return circuit 40 is provided as a switch between the node N2 and the ground potential terminal.

During normal operation, the NMOS transistor 80 is kept in an off state. As a result, capacitor 72 remains fully charged, and its charging voltage, that is, reference voltage SST on node N2, is maintained at the VDD level higher than fixed reference voltage VREF3. However, when the cutoff/recovery circuit 40 in the short circuit protection circuit 44 generates the cutoff instruction signal OCP2 for shutdown, the NMOS transistor 80 is turned on in response. As a result, the reference voltage SST on the node N2 is instantaneously discharged and drops from the VDD level to the ground potential. At this time, within the switching control unit 18, the reference voltage SST is used as a reference value for comparison with the voltage detection signal FB, so that the duty ratio of the pulse width modulation signal PWM quickly decreases toward zero.

When restarting, the shutoff/restart circuit 40 switches the NMOS transistor 80 from the on state to the off state. Then, the capacitor 72 is charged by the constant current IREF1 supplied from the constant current source 70, and the rising charging voltage is output from the node N2 as the reference voltage SST. This charging speed determines the speed of the soft start, and is determined by the amount of the charging current IREF1 and the capacity of the capacitor 72. The reference voltage SST obtained on the node N2 is not only provided to the error amplifier 24 of the switching control unit 18, but is also provided to the blanking circuit 34 as an event information signal indicating the presence or absence (on/off) of the soft start or its status.

The current sensor 46 used to detect the current IS flowing through the switching element (NMOS transistor) 14 has a sense resistor 82 connected between the source of the switching element (NMOS transistor) 14 and the ground potential terminal, and has a sense resistor 82 connected between the source of the switching element (NMOS transistor) 14 and the ground potential terminal. The voltage drop across the resistor 82 is taken out as the current sense voltage SNS. The resistance value of the sense resistor 82 is very low (for example, about several mΩ) and does not affect the current IS flowing through the switching element 14.

In this embodiment, the current detection circuit 30 includes a current sensor 46 and an error amplifier 86. The current sense voltage SNS obtained from the current sensor 46 is amplified by the error amplifier 86 to generate a voltage signal representing the waveform of the current IS, i.e., the current detection signal VOCP.

Node N4, which is the output terminal of current detection circuit 30, is connected to the inverting input terminal (-) of comparator 94 that constitutes small overcurrent monitoring circuit 32, and is connected to the non-inverting input terminal (-) of comparator 96 that constitutes large overcurrent monitoring circuit 38. Connected to the inverting input terminal (+). An NMOS transistor 98 is provided as a switch between the node N4 and the ground potential terminal.

The drive signal DRV from the driver circuit 56 of the switching circuit 28 is input to the gate of the NMOS transistor 98 via an inverter 99 as a timing control signal indicating the on/off state of the switching element 14 for each switching cycle CYi.

When the timing control signal DRV is at L level (when the switching element 14 is off), the NMOS transistor 98 is turned on and the node N4 is clamped to the ground potential. When timing control signal DRV is at H level (when switching element 14 is on), NMOS transistor 98 is turned off, and current detection signal VOCP is generated on node N4.

In the small overcurrent monitoring circuit 32, the reference voltage VREF1 is always input from the reference voltage source 100 to the non-inverting input terminal (+) of the comparator 94 as a low monitoring value. When the timing control signal DRV is at L level (when the switching element 14 is off), the node N4 is clamped to the ground potential via the NMOS transistor 98 in the ON state as described above, so the output of the comparator 94 is held at an inactive H level. When the timing control signal DRV is at H level (when the switching element 14 is on), the logic level of the output of the comparator 94 is determined by the voltage value of the current detection signal VOCP output from the current detection circuit 30 to the node N4, and the output of the comparator 94 changes to L level only when the current detection signal VOCP exceeds the low monitoring value VREF1, and this L level pulse becomes the small overcurrent detection signal EXD1.

The output of the comparator 94 is input to one input terminal of a NOR circuit that constitutes the gate circuit 36 of the short circuit limiter 42 . The output of the blanking circuit 34 is input to the other input terminal of the NOR circuit 36 . The blanking circuit 34 responds to the timing control signal DRV and outputs a blanking signal BLK as an H-level pulse signal immediately after the start of the on-time in each switching cycle.

While the blanking signal BLK at the H level, which is one input signal, is maintained (during the blanking period BT), the NOR circuit 36 is not concerned with the value or state of the output of the comparator 94, which is the other input signal. It generates an L level output that is uniquely inactive. As a result, even if the small overcurrent detection signal EXD1 of L level is received from the comparator 94 during the blanking period BT, the NOR circuit 36 invalidates it.

When the duration of the blanking signal BLK (blanking period BT) ends and the output of the blanking circuit 34 goes to L level, the output of the NOR circuit 36 is determined by the output of the comparator 94. That is, when the current detection signal VOCP on the node N4 is lower than the low monitoring value VREF1 and the output of the comparator 94 is at H level, the NOR circuit 36 maintains an inactive L level output. However, when the current detection signal VOCP exceeds the low monitoring value VREF1, the output of the comparator 94 changes from H level to L level (the small overcurrent detection signal EXD1 is generated), and in response to this, the output of the NOR circuit 36 changes from L level to H level (the current limit instruction signal OCP1 is generated).

Current limit instruction signal OCP1 generated by NOR circuit 36 is applied to driver circuit 56 of switching circuit 28 to turn off switching element 14. On the other hand, the current limit instruction signal OCP1 is also given to the blanking circuit 34 as an event information signal indicating that the current IS flowing through the switching element 14 has unexpectedly become an overcurrent that exceeds the low monitoring value VREF1. is also applied to the cutoff/return circuit 40 of the short circuit protection circuit 44.

As described above, node N4, which is the output terminal of the current detection circuit 30, is also connected to the non-inverting input terminal (+) of the comparator 96 that constitutes the large overcurrent monitoring circuit 38 of the short circuit protection circuit 44. The inverting input terminal (-) of the comparator 96 is constantly input with the reference voltage VREF2 as a high monitoring value from the reference voltage source 102.

When the timing control signal DRV is at the L level (when the switching element 14 is off), the node N4 is clamped to the ground potential via the NMOS transistor 98 in the on state as described above, and the voltage of the comparator 96 is The output is held at an inactive L level. During the period in which the timing control signal DRV is at the H level (during the period in which the switching element 14 is on), the voltage value of the current detection signal VOCP output from the current detection circuit 30 to the node N4 causes the voltage of the comparator 96 to change. The level or logical value of the output is determined. That is, while the current detection signal VOCP is lower than the high monitoring value VREF2, the output of the comparator 96 is at the L level, and when the current detection signal VOCP exceeds the high monitoring value VREF2, the output of the comparator 96 is at the H level, and the output of the comparator 96 is at the H level. The pulse becomes the large overcurrent detection signal EXD2.

When the comparator 96 of the large overcurrent monitoring circuit 38 outputs a large overcurrent detection signal EXD2 at an H level, this large overcurrent detection signal EXD2 is provided to the shutdown/recovery circuit 40 and input to the set input terminal S of the RS flip-flop 76 via the OR gate 74. In response to this, the RS flip-flop 76 sets the Q output to an H level, which becomes the shutdown instruction signal OCP2.

When the active H-level cutoff instruction signal OCP2 is output from the cutoff/return circuit 40, the drive transistor (NMOS transistor) 204 of the load switch drive circuit 202 is turned off, and the load switch that had been kept in the on state until then is turned off. Turn off 200. On the other hand, in response to the H-level cutoff instruction signal OCP2, the driver circuit 56 of the switching circuit 28 turns off the switching element 14 and stops the on/off operation. Further, the cutoff instruction signal OCP2 is also applied to the gate of the NMOS transistor 80 in order to lower the reference voltage SST of the variable reference voltage generation circuit 68 from the VDD level to the ground potential as described above.

The cutoff/return circuit 40 includes a timer circuit 78 and a counter 104 in addition to an NMOS transistor 80, an OR gate 74, and an RS flip-flop 76. When the Q output of the RS flip-flop 76 is set to H level, the timer circuit 78 starts measuring time in response to this, and resets the RS flip-flop 76 by sending an H level pulse when a preset time has elapsed. Give it to input terminal R. As a result, the Q output of the RS flip-flop 76 is reset to L level, and the duration of the cutoff instruction signal OCP2 ends.

When the cutoff instruction signal OCP2 changes from the active H level to the inactive L level, the load switch 200 returns from the off state (power cutoff state) to the on state (power supply state), and at the same time, the switching control unit 18 The on/off operation of the element 14 is restarted. That is, the variable reference voltage SST that gradually rises from the ground potential in the variable reference voltage generation circuit 68 is used as a comparison reference voltage in the error amplifier 24, and the duty ratio of the pulse width modulation signal PWM gradually increases. The driver circuit 56 outputs the drive signal DRV in response to the pulse width modulation signal PWM.

The counter 104 of the shutoff/recovery circuit 40 takes in and counts the current limiting instruction signal OCP1 generated by the NOR circuit 36 of the overcurrent limiting circuit 42. When the count value reaches a set value within a predetermined time or within a predetermined number of cycles, the counter 104 generates an H-level pulse signal. This H-level pulse signal indicates that the number of consecutive current limiting operations by the pulse-by-pulse method has exceeded an allowable limit value, and is provided as a shutoff request signal ARM to the set input terminal S of the RS flip-flop 76 via the OR gate 74. As a result, the shutoff instruction signal OCP2 is output from the RS flip-flop 76 in the same manner as above, and a shutdown or the like is performed.

[Example of a blanking circuit]

FIG. 3 shows a specific configuration example of the blanking circuit 34 included in the step-up switching regulator of FIG. 2. The blanking circuit 34 includes a blanking signal generation circuit 110 and a blanking period selection circuit 112.

The blanking signal generation circuit 110 includes constant current sources 114 and 116, a PMOS transistor 118, an NMOS transistor 120, a capacitor 122, inverters (inverting circuits) 124 and 126, and a NOR gate 128.

As illustrated, a constant current source 114 and a capacitor 122 are connected in series between the VDD voltage supply terminal and the ground potential terminal via a node N5, and a constant current source 116, a PMOS transistor 118, and an NMOS transistor 120 are connected in series. are connected in series via node N5.

More specifically, the capacitor 122 is connected to the output terminal of the constant current source 114 via node N5. On the other hand, the source of the PMOS transistor 118 is connected to the output terminal of the constant current source 116, the source of the NMOS transistor 120 is connected to the ground potential terminal, and the drains of both transistors are connected to each other via node N5.

Node N5 is connected to one input terminal of NOR gate 128 via inverters 124 and 126. The other input terminal of NOR gate 128 receives a timing control signal DRV from driver circuit 56 (FIG. 2) of switching circuit 28 via inverter 119. The timing control signal DRV is also provided to the gate of NMOS transistor 120 via inverter 119. The output of OR gate 142 of blanking signal selection circuit 112 is provided to the gate of PMOS transistor 118.

As described above, when the switching element 14 is off, the timing control signal DRV is at L level. At this time, in the blanking signal generating circuit 110, the NMOS transistor 120 is on, the capacitor 122 is in an uncharged state, and the potential VN5 of the node N5 is held at ground potential, that is, L level. In addition, the NOR gate 128 receives the inverted level (H level) of the timing control signal DRV via the inverter 119, so it holds an L level output regardless of the state of the output of the inverter 126. However, since the potential VN5 of the node N5 is at L level, the output of the inverter 126 is at L level.

When the switching element 14 is turned on, the timing control signal DRV changes from L level to H level. Then, in the blanking signal generating circuit 110, both inputs of the NOR gate 128 become L level, so the output changes from the previous L level to H level, and the blanking signal BLK pulse rises (the blanking period BT starts). On the other hand, the NMOS transistor 120 turns off and electrically cuts off the node N5 from the ground, so the constant current IREF3 from the constant current source 114 always flows into the capacitor 122 and contributes to charging. At this time, when the PMOS transistor 118 is on, the constant current IREF4 from the constant current source 116 also flows into the capacitor 122 and contributes to charging. However, when the PMOS transistor 118 is off, the constant current IREF4 is cut off and does not contribute to charging the capacitor 122.

In this way, a single constant current IREF3 or a composite constant current (IREF3+IREF4) flows into the capacitor 122, so that the charging voltage of the capacitor 122, that is, the potential VN5 of the node N5 increases at two rates. No matter which constant current is used for charging, when the potential VN5 of the node N5 exceeds the threshold voltage TH ₁₂₄ of the inverter 124, the output of the NOR gate 128 changes from the H level to the L level, and blanking is performed. The duration of the signal BLK or the blanking period BT ends.

In this manner, in the blanking signal generating circuit 110, if the capacitance of the capacitor 122 is _C122 , then the time width TW of the blanking period BT can be selected by turning on/off the PMOS transistor 118 to be either a shorter normal time width (first time width) TW _S determined by TH ₁₂₄ × C ₁₂₂ ÷ (IREF3 + IREF4) or a longer extended time width (second time width) TW _L determined by TH ₁₂₄ × C ₁₂₂ ÷ IREF3.

The blanking period selection circuit 112 has three event status determination circuits 130, 132, and 134 that correspond to the three types of event information signals SST, FB, and OCP1, respectively. Figures 4 to 6 show the waveforms or states of each part to explain the function of these event status determination circuits 130, 132, and 134.

The SST status determination circuit 130 has a comparator 138 and a reference voltage source 140, and is configured as a monitoring circuit that monitors whether the variable reference voltage SST in the variable reference voltage generation circuit 68 (Figure 2) is higher or lower than a predetermined threshold voltage VREF4.

More specifically, the comparator 138 inputs the reference voltage SST from the variable reference voltage generating circuit 68 to one input terminal (inverting input terminal (-)) and inputs the threshold voltage VREF4 from the constant voltage source 140 to the other input terminal (non-inverting input terminal (+)). The comparator 138 then compares the voltage levels of both input signals, and outputs an H level when SST<VREF4, and outputs an L level when SST>VREF4. The output of the comparator 138 is provided to the gate of the PMOS transistor 118 in the blanking signal generating circuit 110 via an OR gate 142.

According to this SST status determination circuit 130, when SST<VREF4, the PMOS transistor 118 in the blanking signal generation circuit 110 is turned off to select the single charging current IREF3 and thus the extended time duration _TWL , and when SST>VREF4, the PMOS transistor 118 in the blanking signal generation circuit 110 is turned on to select the composite charging current (IREF3+IREF4) and thus the normal time duration _TWS .

More specifically, as shown in FIG. 4, at startup or restart, the variable reference voltage SST linearly rises from the ground potential to the VDD level in order to perform a soft start. In this case, from the time (t ₀ ) when the cutoff/return circuit 40 turns off the NMOS transistor 80 (FIG. 2) until the time (t _S ) when the SST exceeds the threshold voltage VREF4, the comparator 138 of the SST status determination circuit 130 The output is at H level, the PMOS transistor 118 is turned off in the blanking signal generation circuit 110, and the single charging current IREF3 is selected. As a result, the blanking signal BLK is output as an H-level pulse having a duration of the extended time width _TWL .

Then, when SST exceeds VREF4 (t _S ), the output of the comparator 138 changes to L level, and the PMOS transistor 118 turns on in the blanking signal generating circuit 110 to select the composite charging current (IREF3+IREF4). As a result, after SST exceeds VREF4, the blanking signal BLK is output as an H level pulse having a duration of the normal time width TW _S.

Referring again to FIG. 3, the FB status determination circuit 132 includes a comparator 144 and a constant voltage source 146, and determines whether the voltage level of the voltage detection signal FB output from the voltage detection circuit 22 is higher or lower than a predetermined threshold voltage VREF5. It is configured as a voltage monitoring circuit that monitors.

More specifically, comparator 144 inputs voltage detection signal FB from voltage detection circuit 22 (Figure 2) to one input terminal (inverting input terminal (-)), and inputs threshold voltage VREF5 from reference voltage source 146 to the other input terminal (non-inverting input terminal (+)). Comparator 144 inputs variable reference voltage SST as an enable signal, and operates after startup or restart by soft start is substantially completed. It then compares the voltage levels of both input signals, and outputs an L level when FB>VREF5, and outputs an H level when FB<VREF5.

As shown in FIG. 5, while the voltage level of the voltage detection signal FB is higher than the threshold voltage VREF5, the output of the comparator 144 is at the L level, and within the blanking signal generation circuit 110, the gate voltage of the PMOS transistor 118 is at the L level. Yes, the PMOS transistor 118 is on. As a result, the composite charging current (IREF3+IREF4) is selected, and the blanking signal BLK is output as an H-level pulse having a duration of the normal time width _TWS .

However, when the voltage level of the voltage detection signal FB decreases and cuts off the threshold voltage VREF5 at time _tM , the output of the comparator 144 changes from L level to H level. Then, the one-shot pulse PLS with a short pulse width output from the one-shot circuit 162 in response to the H level output of the comparator 144 is input to the set input terminal S of the RS flip-flop 164, and the Q output of the RS flip-flop 164 is input to the set input terminal S of the RS flip-flop 164. is set to H level. The H level Q output of the RS flip-flop 164 is applied to the gate of the PMOS transistor 118 of the blanking signal generation circuit 110 via the OR gate 142. As a result, the PMOS transistor 118 is turned off, and the time width TW of the blanking period BT is switched from the normal time width TW _S to the extended time width TW _L.

However, due to the action of the reset circuit 180 described later, the Q output of the RS flip-flop 164 (and thus the gate voltage of the PMOS transistor 118) is reset to the L level immediately (after a certain time TJ) even if it changes from the L level to the H level as described above. As a result, the blanking period BT is output with the extended time width TW _L only for a limited certain time TJ immediately after the state changes from FB>VREF5 to FB<VREF5.

3 again, the OCP1 status determination circuit 134 has a comparator 148, a reference voltage source 150, a constant current source 152, a capacitor 154, and an NMOS transistor 156. The constant current source 152 and the capacitor 154 are connected in series between the VDD voltage supply terminal and the ground potential via a node N6. The NMOS transistor 156 has a source connected to the ground potential terminal, a drain connected to the node N6, and a gate input of the current limit instruction signal OCP1 from the overcurrent limit circuit 42 (FIG. 2). The comparator 148 inputs the potential VN6 of the node N6 to one input terminal (inverting input terminal (-)) and inputs a predetermined threshold voltage VREF6 from the reference voltage source 150 to the other input terminal (non-inverting input terminal (+)). The comparator 148 compares the voltage levels of both input signals, and outputs an L level when VN6>VREF6, and outputs an H level when VN6<VREF6. The output of the comparator 148 is provided to the input terminal of the one-shot circuit 162 via the OR gate 160. This causes the output of the comparator 148 to have the same effect on the subsequent circuits (the one-shot circuit 162, the RS flip-flop 164, etc.) as the output of the comparator 144 of the FB status determination circuit 132 described above.

6, in a stable state where the overcurrent limiting circuit 42 does not generate the current limiting instruction signal OCP1, the NMOS transistor 156 is off, the capacitor 154 is fully charged, and the potential VN6 of the node N6 is held at the VDD level, i.e., the H level. Therefore, the state is VN6>VREF6, and the output of the comparator 148 is at the L level. As a result, in the blanking signal generating circuit 110, the PMOS transistor 118 is turned on to select the combined charging current (IREF3+IREF4), and the blanking signal BLK is output with the normal time width TW _S.

However, if the current limit instruction signal OCP1 is suddenly output from the overcurrent limit circuit 42 under such a stable condition, the NMOS transistor 156 is turned on in response, and the capacitor 154 is instantly discharged. In an instant, the previous state of VN6>VREF6 changes to the state of VN6<VREF6, and the output of the comparator 148 changes from L level to H level. As a result, in the blanking signal generation circuit 110, the PMOS transistor 118 is turned off and a single charging current (IREF3) is selected, and the pulse duration (blanking period BT) of the blanking signal BLK is extended to the extended time width TW. Switch to _L. Then, after the predetermined time TJ has elapsed, the blanking period BT returns to the normal time width _TWS .

In the OCP1 status determination circuit 134, the NMOS transistor 156 is turned off immediately after the current limit instruction signal OCP1 unexpectedly (initially) generated by the overcurrent limiter circuit 42 is input. As a result, the capacitor 154 is charged by the constant current IREF2 from the constant current source 152, and the potential VN6 (charging voltage) of the node N6 increases at a constant rate. In this case, when the current limit instruction signal OCP1 is generated in the next cycle, the NMOS transistor 156 is turned on in response to the current limit instruction signal OCP1, and the potential VN6 on the node N6 rises to the threshold voltage VREF6. VN6 stops before reaching the ground potential, and VN6 drops to the ground potential. The same holds true when the current limit instruction signal OCP1 is generated in the next cycle. As a result, the extended time width TW _L is selected for a predetermined time TJ immediately after the current limit instruction signal OCP1 is suddenly (first) generated by the overcurrent limit circuit 42.

Reset circuit 180 includes a comparator 166, a reference voltage source 168, a constant current source 170, a capacitor 172, a PMOS transistor 174, and an NMOS transistor 176. Constant current source 170 and capacitor 172 are connected in series via PMOS transistor 174 and node N7 between the VDD voltage supply terminal and ground potential. The PMOS transistor 174 and the NMOS transistor 176 have their respective sources connected to the output terminal and the ground potential terminal of the constant current source 170, their respective drains connected to each other via the node N7, and their respective gates connected to the RS flip-flop 164. is connected to the Q_output (inverted output) of The comparator 166 inputs the potential VN7 of the node N7 to one input terminal (non-inverting input terminal (+)), and receives a predetermined threshold voltage VREF7 from the reference voltage source 168 to the other input terminal (inverting input terminal (-)). Enter. Comparator 166 compares the voltage levels of both input signals, and outputs L level when VN7<VREF7, and outputs H level when VN7>VREF7. The output of the comparator 166 is applied to the reset input terminal R of the RS flip-flop 164.

When the FB status determination circuit 132 or the OCP1 status determination circuit 134 sets the Q output of the RS flip-flop 164 to L level, the Q_output (inverted output) is at H level. At this time, the blanking signal generation circuit 110 outputs a blanking signal BLK having a pulse duration of the normal time width _TWS . On the other hand, in the reset circuit 180, the PMOS transistor 174 is off, the NMOS transistor 176 is on, the potential VN7 of the node N7 is clamped to the ground potential, and the output of the comparator 166 is at L level.

As described above, when the one-shot pulse PLS is generated from the one-shot circuit 162 in response to the H-level output from the FB status determination circuit 132 or the OCP1 status determination circuit 134, the Q output of the RS flip-flop 164 goes to the H level. In the blanking signal generation circuit 110, the pulse duration of the blanking signal BLK (the time width TW of the blanking period BT) is switched to the extended time width _TWL . In the reset circuit 180, in response to a change in the Q_output (inverted output) of the RS flip-flop 164 from H level to L level, the NMOS transistor 176 is turned off, the PMOS transistor 174 is turned on, and the capacitor 172 is turned on as a constant current source. It is charged by constant current IREF5 from node N7, and voltage VN7 (charging voltage) of node N7 increases at a constant rate. Then, when a certain period of time TJ has elapsed since the generation of the one-shot pulse PLS, that is, when the voltage VN7 reaches the threshold voltage VREF7, the output of the comparator 166 changes from the L level to the H level, and in response, the RS flip-flop 164 is reset, changing the Q output from H level to L level. As a result, the time width TW of the blanking period BT is switched to the normal time width _TWS . In the reset circuit 180, the PMOS transistor 174 is turned off, the NMOS transistor 176 is turned on, the voltage VN7 at the node N7 falls to the ground potential, and the output of the comparator 166 returns to the L level.

[Switching regulator action]

The main functions of the step-up switching regulators shown in FIGS. 2 and 3 will be explained with reference to FIGS. 7 to 9.

7 shows an example of a case where a short circuit with a very low impedance suddenly occurs at node N _A in boost chopper circuit 16 in the middle of a certain switching cycle CY _n-1 due to a short circuit in choke coil 11, for example. In this case, during the ON period of switching element 14, input voltage VDD is applied almost directly to switching element 14, so that a very large current IS flows through switching element 14, while almost no electromagnetic energy is stored in choke coil 11. Therefore, during the OFF period of switching element 14, the release of electromagnetic energy from choke coil 11 is very small, and the current supplied to capacitor 15 or the load side is reduced. This causes output voltage VOUT to drop, and the level of error signal ER in switching control unit 18 becomes high. In this way, as soon as the on-time T _ON starts in the next cycle CYn and the switching element 14 is turned on, the current IS flowing through the switching element 14 increases sharply, and the current detection signal VOCP exceeds not only the low monitoring value VREF1 but also the high monitoring value VREF2 during the blanking period BT (normal time width TW _S ).

In this case, in the overcurrent limiting circuit 42, when the current detection signal VOCP exceeds the low monitoring value VREF1, the small overcurrent monitoring circuit 32 generates the small overcurrent detection signal EXD1, but the gate circuit (NOR gate) 36 Since this is disabled, the current limit instruction signal OCP1 is not output. On the other hand, in the short circuit protection circuit 44, the comparator 96 of the large overcurrent monitoring circuit 38 generates a large overcurrent detection signal EXD2, and the cutoff/recovery circuit 40 generates an active H level H cutoff instruction signal OCP2. The load switch drive circuit 202 turns off the load switch 200 in response to the cutoff instruction signal OCP2. Further, the switching circuit 28 also stops the on/off operation of the switching element 14 in response to the cutoff instruction signal OCP2.

Note that when the output signal DRV of the driver circuit 56 of the switching circuit 28 changes from H level to L level in response to the cutoff instruction signal OCP2, the switching element 14 is turned off, while the NMOS transistor 98 is turned on, and the node N4 is turned off. The potential VN4 instantly drops to the ground potential. As a result, the output of the comparator 94 becomes H level within the overcurrent limiting circuit 42 (the pulse duration of the small overcurrent detection signal EXD1 ends), and the output of the comparator 96 becomes L level within the short circuit protection circuit 44. (The pulse duration of the large overcurrent detection signal EXD2 ends).

In this way, when the normal time width TW _S is continuously or steadily selected as the time width TW of the blanking period BT in each switching cycle CY _i , the blanking period BT is set in a certain switching cycle CY _n . If the current detection signal VOCP exceeds the high monitoring value VREF2 during the cycle CY _n , the short circuit protection circuit 44 generates the cutoff instruction signal OCP2 to turn off the load switch 200 and the switching element 14, and The on/off operations of cycles CY _n+1 , CY _n+2 , . . . are stopped. When load switch 200 is turned off, the power supply line is cut off between input terminal 10 and node _NA . Further, since the on/off operation of the switching element 14 is stopped and the switching element 14 is held in the off state, no current flows through the switching element 14.

In this way, even if an abnormally large overcurrent suddenly flows through the switching element 14 due to a power fault with a very low impedance caused by a short circuit in the choke coil 11, etc., the load switch 200 immediately cuts off the power supply line and stops the on/off operation of the switching element 14, so the switching element 14 can be safely and accurately protected.

8 shows an example of a case where a short circuit to power with a not-so-low impedance suddenly occurs at the node N _A of the boost chopper circuit 16 in a certain switching cycle CY _n-2 due to, for example, a layer short circuit of the choke coil 11. In this case as well, the output voltage VOUT drops and the error signal ER rises in the switching control unit 18 due to the same action as above, although not as abruptly as in the case of a short circuit. Then, when the on-time T _ON starts in the next cycle CY _n-1 and the switching element 14 is turned on, the rising speed of the current IS flowing through the switching element 14 is high but not as steep as in the case of a short circuit, and the current detection signal VOCP does not reach the high monitoring value VREF2 during the blanking period BT even if it exceeds the low monitoring value VREF1.

In cycle CY _n-1 , in the short-circuit protection circuit 44, the large overcurrent detection signal EXD2 is not generated from the large overcurrent monitoring circuit 38 during the blanking period BT (normal time width TW _S ). On the other hand, in the overcurrent limiting circuit 42, the current detection signal VOCP exceeds the low monitoring value VREF1, so the small overcurrent detection signal EXD1 goes low, but the current limiting instruction signal OCP1 is not generated from the gate circuit 36 during the blanking period BT (normal time width TW _S ), and is generated after the blanking period BT ends. In response to this current limiting instruction signal OCP1, the switching circuit 28 turns off the switching element 14, and ends the on-time T _ON midway.

In this way, when the normal time width TW _S is continuously or steadily selected as the time width TW of the blanking period BT in each switching cycle CY _i , blanking is performed in a certain switching cycle CY _n-1. If the current detection signal VOCP exceeds the low monitoring value VREF1 during the period BT but does not reach the high monitoring value VREF2, the overcurrent limiting circuit 42 generates the current limiting instruction signal OCP1 at the end of the blanking period BT. , the switching element 14 is turned off, and the on time of the cycle CY _n-1 is ended midway. In other words, current is limited using a pulse-by-pulse method. Then, only in the next cycle CY _n , the extended time width TW _L is selected as the time width TW of the blanking period BT, and when the current detection signal VOCP exceeds the high monitoring value VREF2 within this extended time width TW _L. In this case, the short-circuit protection circuit 44 generates the cutoff instruction signal OCP2 and turns off the load switch 200 to cut off the power supply line and turns off the switching element 14 within the cycle CY _n , and the subsequent cycles CY _n+1 and CY _n+2 , . . ., the on/off operation of the switching element 14 is stopped.

In this way, even if the rise of the overcurrent immediately after the start of the on-time is not as steep as in the case of an output short circuit, if it exceeds the high monitoring value VREF2 within the extended time width _TWL of the blanking period BT, it is an abnormal overcurrent. At that point, the load switch 200 is turned off. As a result, even if a short circuit with a not-so-low impedance occurs due to a layer short circuit in the choke coil 11, etc., the shutdown can be quickly and accurately performed without prolonging the state in which abnormal overcurrent flows through the switching element 14. This makes it possible to prevent heat generation or destruction of the switching element 14.

Furthermore, in this embodiment, immediately after the start of the soft start, the extended time width TW _L is selected for the time width TW of the blanking period BT as shown in Fig. 4. As a result, if the above-mentioned short-to-power state has already occurred or continues before start-up or restart, it is possible to properly detect an abnormal overcurrent state during start-up or restart and perform a shutdown similar to the above at an early stage, thereby preventing the switching element 14 from heating up or being destroyed.

[Other embodiments or modifications]

The above describes preferred embodiments of the present invention, but the present invention is not limited to the above-mentioned embodiments. Those skilled in the art can make various modifications and changes to specific embodiments without departing from the technical concept and scope of the present invention.

For example, in the embodiment described above, the protection unit 20 supplies the same cutoff instruction signal OCP2 to the load switch drive circuit 202 and the switching circuit 28 to turn off the load switch 200 and the switching element 14 at the same time. However, it is also possible to provide a certain time difference between the turn-off timings of both.

As in the above-described embodiment, when the load switch 200 is turned off, the on/off operation of the switching element 14 is stopped in conjunction with the load switch 200, thereby most reliably protecting the switching element 14 and allowing the switching control unit 18 to operate stably. However, it is also possible to configure the protection unit 20 to send separate cutoff instruction signals to the load switch drive circuit 202 and the switching circuit 28, or to send a cutoff instruction signal only to the load switch drive circuit 202.

In the embodiment described above, when the instruction signals OCP1, OCP2 are generated from the overcurrent limiting circuit 42 or the short circuit protection circuit 44, the limited time period is set such that the time width TW of the blanking period BT is extended to the extended time width _TWL only immediately after that. is defined as one cycle of switching. However, it is also possible to set such a limited time to several cycles.

Further, in the above embodiment, the time width TW of the blanking period BT is switched between the normal time width TW _S and the extended time width TW _L. However, depending on the characteristics of various event information signals, it is also possible to switch the time width TW of the blanking period BT between three or more set time widths, and in that case, the blanking signal generation circuit 110 The number of sources 116 and PMOS transistors 118 may be increased. Further, by using a constant current source whose current amount is variable, it is also possible to arbitrarily variably control the time width TW of the blanking period BT.

In the embodiment described above, the three types of event information signals SST, FB, and OCP1 taken in by the blanking circuit 34 are examples. It is also possible to apply other types of event information signals to the blanking circuit 34 according to the type and configuration of the switching regulator to appropriately vary the time width TW of the blanking period BT or to switch between a plurality of set time widths. It is.

As one embodiment of the present invention, depending on the method and characteristics of the step-up switching regulator, the current flowing through the switching element in each switching cycle is monitored using a first monitoring value and a higher second monitoring value, and a blanking period is inserted immediately after the start of the on-time only in certain cycles depending on the presence or absence of a specified event or situation (for example, limited to one or several cycles immediately after an abnormal drop in the output voltage is detected), and if the instantaneous value of the current during the blanking period exceeds the second monitoring value, the load switch is turned off, and if the instantaneous value of the current exceeds the first monitoring value after the end of the blanking period, the switching element is turned off midway through via the switching control unit.

Furthermore, according to the present invention, as can be seen from FIG. 7, even if the time width TW of the blanking period BT is always fixed, it is difficult to achieve the same comprehensive short circuit protection as in the above-mentioned embodiment, but it is possible to solve the problems of the conventional technology to a certain extent.

14 Switching element 16 Boost chopper circuit 18 Switching control section 20 Protection section 22 Voltage detection circuit 24 Error amplifier 26 Reference voltage circuit 28 Switching circuit 30 Current detection circuit 32 Small overcurrent monitoring circuit (first overcurrent monitoring circuit)
34 Blanking circuit 36 NOR gate (gate circuit)
38 Large overcurrent monitoring circuit (second overcurrent monitoring circuit)
40: cutoff/recovery circuit 42: overcurrent limiting circuit (first protection circuit)
44 Short circuit protection circuit (second protection circuit)
46 Current sensor 200 Load switch 202 Load switch drive circuit

Claims (14)

A step-up switching regulator that converts a DC input voltage to a DC output voltage higher than the input voltage through a coil and a switching element,
a load switch connected in series with the coil and the switching element;
a switching control unit that turns on and off the switching element at a constant frequency and a variable duty ratio;
a current detection circuit that generates a current detection signal representing the current flowing through the switching element;
The current detection signal includes a blanking circuit that inserts a blanking period with a variable or switchable time width immediately after the start of the on-time in each switching cycle, and the current detection signal is set to a first monitoring value after the end of the blanking period. a first protection circuit that turns off the switching element midway through the switching control section when the
a second protection circuit that turns off the load switch when the current detection signal exceeds a second monitoring value higher than the first monitoring value during the on-time in each switching cycle;
A step-up switching regulator with The step-up switching regulator according to claim 1, wherein the blanking circuit is capable of switching the duration of the blanking period between a first duration and a second duration greater than the first duration, and selects either the first duration or the second duration depending on the presence or absence of a predetermined event or the situation. a voltage monitoring circuit is provided for monitoring whether an output voltage applied to the load is higher or lower than a predetermined threshold;
the blanking circuit selects the first time duration while the output voltage is higher than the threshold, and selects the second time duration when the output voltage becomes lower than the threshold, based on an output signal of the voltage monitoring circuit.
3. The step-up switching regulator according to claim 2. The boost switching regulator according to claim 3, wherein the blanking circuit selects the second time duration only in one or several switching cycles immediately after the output voltage becomes lower than the threshold value, and selects the first time duration in other cycles. The first protection circuit includes:
a first overcurrent monitoring circuit that monitors the current detection signal in each switching cycle and generates a first overcurrent detection signal when the current detection signal exceeds the first monitoring value;
During the blanking period, even if the first overcurrent detection signal is generated by the first overcurrent monitoring circuit, it is invalidated, and after the end of the blanking period, the first overcurrent monitoring circuit a gate circuit that responds to the generation of the first overcurrent detection signal and provides the switching control unit with a current limit instruction signal to turn off the switching element;
has
The blanking circuit selects the first time width while the current limit instruction signal is not generated by the gate circuit, and selects the first time width when the current limit instruction signal is unexpectedly generated by the gate circuit. Select a second time range,
The step-up switching regulator according to claim 2. The switching regulator according to claim 5, wherein the blanking circuit selects the second time width only in one or several switching cycles immediately after the current limit instruction signal is unexpectedly generated by the gate circuit. The second protection circuit includes:
a second overcurrent monitoring circuit that monitors the current detection signal in each switching cycle and generates a second overcurrent detection signal when the current detection signal exceeds the second monitoring value;
a cutoff/return circuit that generates a cutoff instruction signal to turn off the load switch in response to the second overcurrent detection signal generated by the second overcurrent monitoring circuit;
The step-up switching regulator according to any one of claims 2 to 6, comprising: The switching control unit gradually increases the duty ratio with a soft start at startup or restart,
The blanking circuit initially selects the second time width at startup or restart, and selects the first time width after startup or restart is substantially completed.
The step-up switching regulator according to claim 2. The step-up switching regulator according to any one of claims 1 to 8, wherein the second protection circuit stops the on/off operation of the switching element through the switching control unit when the load switch is turned off. A step-up switching regulator that converts a DC input voltage to a DC output voltage higher than the input voltage through a coil and a switching element,
a load switch connected in series with the coil and the switching element;
a switching control unit that turns on and off the switching element at a constant frequency and a variable duty ratio;
Monitoring the current flowing through the switching element in each switching cycle using a first monitored value and a second higher monitored value, and conditionally starting the on-time depending on the presence or absence of a predetermined event or situation. Immediately afterward, a blanking period is inserted, and when the current exceeds the second monitoring value during the blanking period, the load switch is turned off, and the current increases after the end of the blanking period. a protection unit that turns off the switching element midway through the switching control unit when the first monitoring value is exceeded;
A step-up switching regulator with The boost switching regulator according to claim 10, wherein the protection unit varies the time width of the blanking period or switches between a plurality of set time widths depending on the type or content of the event. 1. A step-up switching regulator that converts a DC input voltage into a DC output voltage higher than the input voltage through a coil and a switching element,
A load switch connected in series with the coil and the switching element;
a switching control unit that turns on and off the switching element at a constant frequency and a variable duty ratio;
a protection unit that monitors a current flowing through the switching element in each switching cycle by using a first monitor value and a second monitor value that is higher than the first monitor value, provides a first partial monitoring period having a variable or switchable time width immediately after the start of an on-time in each switching cycle, turns off the load switch when the current exceeds the second monitor value in the first partial monitoring period, and turns off the switching element midway through via the switching control unit when the current exceeds the first monitor value in a remaining second partial monitoring period after the end of the first partial monitoring period;
A step-up switching regulator having a 1. A step-up switching regulator that converts a DC input voltage into a DC output voltage higher than the input voltage through a coil and a switching element,
A load switch connected in series with the coil and the switching element;
a switching control unit that turns on and off the switching element at a constant frequency and a variable duty ratio;
a protection unit that monitors a current flowing through the switching element in each switching cycle by using a first monitor value and a second monitor value that is higher than the first monitor value, provides a first partial monitoring period immediately after the start of an ON time in each switching cycle, turns off the load switch when the current exceeds the second monitor value in the first partial monitoring period, and turns off the switching element midway through via the switching control unit when the current exceeds the first monitor value in a remaining second partial monitoring period after the end of the first partial monitoring period;
A step-up switching regulator having a The step-up switching regulator according to any one of claims 10 to 13, wherein the protection unit stops the on/off operation of the switching element through the switching control unit when the load switch is turned off.

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