JP2007116040A - Circuit board - Google Patents

Circuit board Download PDF

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Publication number
JP2007116040A
JP2007116040A JP2005308498A JP2005308498A JP2007116040A JP 2007116040 A JP2007116040 A JP 2007116040A JP 2005308498 A JP2005308498 A JP 2005308498A JP 2005308498 A JP2005308498 A JP 2005308498A JP 2007116040 A JP2007116040 A JP 2007116040A
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Prior art keywords
land
film
pattern
circuit board
film removal
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Withdrawn
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JP2005308498A
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Japanese (ja)
Inventor
Hiroyuki Tanitsu
宏幸 谷津
Shuichi Takeda
秀一 武田
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Alps Alpine Co Ltd
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Alps Electric Co Ltd
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Priority to JP2005308498A priority Critical patent/JP2007116040A/en
Publication of JP2007116040A publication Critical patent/JP2007116040A/en
Withdrawn legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/1012—Auxiliary members for bump connectors, e.g. spacers
    • H01L2224/10152—Auxiliary members for bump connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body
    • H01L2224/10175—Flow barriers

Abstract

<P>PROBLEM TO BE SOLVED: To provide a circuit board having satisfactory formation precision of an insulating film, and no risk of dielectric breakdown. <P>SOLUTION: In the circuit board, the insulating film 7 having a square film removal section 7a is provided on an insulating substrate 1, and a plurality of lands 4 of a conductive pattern 2 are positioned in the film removal section 7a. Even if the pitch of the land 4 becomes narrow corresponding to an increase in density, the film removal section 7a becomes common to the plurality of lands 4. As a result, the shape of the insulating film 7 is simplified, those having satisfactory print precision can be obtained such as resist for forming an insulating film. A pattern part 3 connected to the land 4 and is positioned in the film removal section 7a is set vertical to a side 7b of the film removal section 7a, thus increasing the space between the pattern parts 3 corresponding to an increase in density, and hence obtaining those without any risk of dielectric breakdown. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、種々の電子機器や電子回路ユニット等に使用され、特に、半導体部品の取付に適した回路基板に関するものである。   The present invention relates to a circuit board that is used in various electronic devices, electronic circuit units, and the like, and particularly suitable for mounting semiconductor components.

半導体部品の取付に使用される従来の回路基板を図３に基づいて説明すると、絶縁基板５１に設けられた導電パターン５２は、電気信号が流れるパターン部５３と、このパターン部５３の一端に設けられたランド部５４を有し、このパターン部５３は、ランド部５４に対して不規則な位置から引き出されており、また、絶縁基板５１上には絶縁被膜５５が設けられ、個々のランド部５４と、パターン部５３のランド部５４の近傍部５３ａは、絶縁被膜５５に設けられた丸形被膜除去部５５ａによって露出され、露出したランド部５４と近傍部５３ａには、半導体部品の電極が半田付けされるようになって、従来の回路基板が形成されている（例えば、特許文献１参照）。
特開２００１−６８８３６号公報 A conventional circuit board used for mounting a semiconductor component will be described with reference to FIG. 3. A conductive pattern 52 provided on an insulating substrate 51 is provided with a pattern portion 53 through which an electric signal flows and at one end of the pattern portion 53. The pattern portion 53 is drawn from an irregular position with respect to the land portion 54, and an insulating film 55 is provided on the insulating substrate 51, and the individual land portions are provided. 54 and the vicinity 53a of the land part 54 of the pattern part 53 are exposed by a round film removing part 55a provided on the insulating film 55, and the exposed land part 54 and the vicinity part 53a have electrodes of semiconductor components. A conventional circuit board is formed by soldering (see, for example, Patent Document 1).
JP 2001-68836 A

しかし、近年の高密度化の要求における従来の回路基板にあっては、個々のランド部５４が絶縁被膜５５に設けられた個々の丸形被膜除去部５５ａによって露出されるようになっているため、高密度化に対応してランド部５４のピッチが狭くなると、丸形被膜除去部５５ａ同士が互いに重なり合うようになり、その結果、絶縁皮膜５５の形状が複雑となって、絶縁皮膜５５形成のためのレジスト等の印刷に高い精度が必要になり、また、パターン部５３は、ランド部５４に対して不規則な位置から引き出されているため、高密度化に対応したパターン部５３間の間隔が狭くなって、半田ブリッジによるショートを起こす恐れがあるという問題がある。   However, in the conventional circuit board in the recent demand for higher density, the individual land portions 54 are exposed by the individual circular film removing portions 55 a provided on the insulating film 55. When the pitch of the land portions 54 is reduced corresponding to the increase in density, the round film removal portions 55a overlap each other. As a result, the shape of the insulating film 55 becomes complicated, and the insulating film 55 is formed. For this reason, high accuracy is required for printing resist and the like, and the pattern portion 53 is drawn from an irregular position with respect to the land portion 54. However, there is a problem that a short circuit may occur due to a solder bridge.

本発明は、このような従来技術の実情に鑑みてなされたもので、その目的は、絶縁被膜の形成精度が良好で、絶縁破壊の恐れの無い回路基板を提供することにある。   The present invention has been made in view of such a state of the art, and an object of the present invention is to provide a circuit board that has good formation accuracy of an insulating film and has no fear of dielectric breakdown.

上記の目的を達成するために、本発明の第１の解決手段として、金属からなる導電パターンが形成された絶縁基板と、この絶縁基板上に設けられた絶縁被膜とを備え、前記導電パターンは、複数のランド部と、このランド部に接続されたパターン部を有すると共に、前記絶縁被膜には、四角形状の被膜除去部が設けられ、複数の前記ランド部は、前記被膜除去部内に位置すると共に、前記ランド部に繋がって前記被膜除去部内に位置する前記パターン部は、前記被膜除去部の辺に対して垂直状態にした構成とした。   In order to achieve the above object, as a first solving means of the present invention, an insulating substrate on which a conductive pattern made of metal is formed, and an insulating film provided on the insulating substrate, the conductive pattern includes: And a plurality of land portions and a pattern portion connected to the land portions, and the insulating coating is provided with a quadrangular coating removal portion, and the plurality of land portions are located in the coating removal portion. At the same time, the pattern portion connected to the land portion and located in the film removal portion is configured to be perpendicular to the side of the film removal portion.

また、第２の解決手段として、複数の前記ランド部は、前記被膜除去部の辺に沿って配設された構成とした。   As a second solution, the plurality of land portions are arranged along the sides of the film removal portion.

また、第３の解決手段として、前記導電パターンは、電気信号が流れる前記パターン部、及び前記ランド部と、電気信号が流れないＮＣランド部、及びこのＮＣランド部に接続された延設パターン部を有し、前記ＮＣランド部は、前記被膜除去部内に位置すると共に、前記ＮＣランド部に繋がって前記被膜除去部内に位置する前記延設パターン部は、前記被膜除去部の辺に対して垂直状態にした構成とした。   As a third solution, the conductive pattern includes the pattern portion through which an electric signal flows, the land portion, an NC land portion through which no electric signal flows, and an extended pattern portion connected to the NC land portion. The NC land part is located in the film removal part, and the extended pattern part connected to the NC land part and located in the film removal part is perpendicular to the side of the film removal part. The configuration is in the state.

また、第４の解決手段として、前記ランド部と前記ＮＣランド部は、前記被膜除去部の辺に沿って少なくとも一列に配設された構成とした。   Further, as a fourth solving means, the land portion and the NC land portion are arranged in at least one line along the side of the film removal portion.

また、第５の解決手段として、複数の電極を有する半導体部品を備え、前記電極がランド部と前記ＮＣランド部に半田付けされた構成とした。   As a fifth solution, a semiconductor component having a plurality of electrodes is provided, and the electrodes are soldered to the land portion and the NC land portion.

本発明の回路基板において、絶縁基板には、四角形状の被膜除去部を有する絶縁被膜が設けられ、導電パターンの複数のランド部は、被膜除去部内に位置するようにしたため、高密度化に対応してランド部のピッチが狭くなっても、被膜除去部は複数のランド部に対して共通となって、その結果、絶縁皮膜の形状が簡素化され、絶縁皮膜形成のためのレジスト等の印刷の精度の良好なものが得られると共に、ランド部に繋がって被膜除去部内に位置するパターン部は、被膜除去部の辺に対して垂直状態にしたため、高密度化に対応してもパターン部間の間隔を大きくできて、絶縁破壊の恐れの無いものが得られる。   In the circuit board of the present invention, the insulating substrate is provided with an insulating coating having a square-shaped coating removing portion, and the plurality of land portions of the conductive pattern are located within the coating removing portion, so that high density is achieved. Even if the pitch of the land portions becomes narrow, the film removal portion becomes common to a plurality of land portions, and as a result, the shape of the insulating film is simplified and printing of a resist or the like for forming the insulating film is performed. The pattern portion connected to the land portion and positioned in the film removal portion is in a state perpendicular to the side of the film removal portion. Can be made large so that there is no risk of dielectric breakdown.

また、複数のランド部は、被膜除去部の辺に沿って配設されたため、被膜除去部内に露出したパターン部の表面積を等しくでき、半導体部品の半田付を行った際、半田の盛り上がりを等しくできて、半田の平坦度（コプラナリティ）が得られ、半導体部品の半田付の信頼性を向上させることができる。   In addition, since the plurality of lands are arranged along the side of the film removal part, the surface area of the pattern part exposed in the film removal part can be made equal, and when the semiconductor parts are soldered, the rise of the solder is made equal. Thus, the flatness (coplanarity) of the solder can be obtained, and the reliability of soldering of the semiconductor component can be improved.

また、導電パターンは、被膜除去部内に位置し、電気信号が流れないＮＣランド部が設けられたため、半導体部品の半田付を行った際、半導体部品がＮＣランド部にも半田付けされて、半導体部品の取付が確実になると共に、ＮＣランド部に繋がって被膜除去部内に位置する延設パターン部は、被膜除去部の辺に対して垂直状態にしたため、高密度化に対応してもパターン部と延設パターン部間の間隔を大きくできる。   In addition, since the conductive pattern is provided in the film removal portion and provided with an NC land portion through which an electric signal does not flow, when the semiconductor component is soldered, the semiconductor component is also soldered to the NC land portion. In addition to ensuring the mounting of the parts, the extended pattern part connected to the NC land part and positioned in the film removal part is in a state perpendicular to the side of the film removal part. And the interval between the extended pattern portions can be increased.

また、ランド部とＮＣランド部は、被膜除去部の辺に沿って少なくとも一列に配設されたため、被膜除去部内に露出したパターン部と延設パターン部の表面積を等しくでき、半導体部品の半田付を行った際、半田の盛り上がりを等しくできて、半田の平坦度（コプラナリティ）が得られ、半導体部品の半田付の信頼性を向上させることができる。   Further, since the land portion and the NC land portion are arranged in at least one line along the side of the film removal portion, the surface area of the pattern portion exposed in the film removal portion and the extended pattern portion can be made equal, and soldering of semiconductor components can be performed. When soldering is performed, the rise of the solder can be made equal, the flatness of the solder (coplanarity) can be obtained, and the reliability of soldering of the semiconductor component can be improved.

また、複数の電極を有する半導体部品を備え、電極がランド部とＮＣランド部に半田付けされたため、半導体部品の取付が確実にできる。   In addition, since the semiconductor component having a plurality of electrodes is provided and the electrodes are soldered to the land portion and the NC land portion, the semiconductor component can be securely attached.

発明の実施の形態について図面を参照して説明すると、図１は本発明の回路基板に係り、半導体部品を取り付けた状態の要部の拡大断面図、図２は本発明の回路基板に係る要部の平面図であり、次に、本発明の回路基板に係る構成を図１，図２に基づいて説明すると、セラミック等からなる絶縁基板１には、導電パターン２が設けられ、この導電パターン２は、電気信号が流れるパターン部３と、このパターン部３の一端に設けられた複数のランド部４と、電気的にノンコネクション（非接続）の複数のＮＣランド部５と、このＮＣランド部５に接続された電気的にノンコネクション（非接続）の延設パターン部６を有しており、そして、ランド部４とＮＣランド部５は、表面積が等しく形成されると共に、パターン部３と延設パターン部６は、互いにパターン幅が等しく形成されている。   An embodiment of the invention will be described with reference to the drawings. FIG. 1 relates to a circuit board of the present invention, and is an enlarged cross-sectional view of a main part with a semiconductor component attached, and FIG. Next, the configuration of the circuit board according to the present invention will be described with reference to FIGS. 1 and 2. An insulating substrate 1 made of ceramic or the like is provided with a conductive pattern 2, and this conductive pattern 2 includes a pattern portion 3 through which an electric signal flows, a plurality of land portions 4 provided at one end of the pattern portion 3, a plurality of NC land portions 5 that are electrically non-connected (not connected), and the NC land An electrically non-connected extended pattern portion 6 connected to the portion 5 is provided, and the land portion 4 and the NC land portion 5 have the same surface area and the pattern portion 3. And extended pattern part 6 , The pattern width is formed equal to each other.

また、絶縁基板１上には、レジストを印刷して形成された絶縁被膜７が設けられ、この絶縁被膜７は、四角形状の被膜除去部７ａが設けられ、この皮膜除去部７ａ内には、ランド部４とＮＣランド部５が皮膜除去部７ａの辺７ｂに沿って一列に配設されると共に、皮膜除去部７ａ内で露出するパターン部３の露出部３ａと延設パターン部６の露出部６ａは、被膜除去部７ａの辺７ｂに対して垂直状態となって、本発明の回路基板が形成されている。   Further, an insulating coating 7 formed by printing a resist is provided on the insulating substrate 1, and this insulating coating 7 is provided with a square-shaped coating removing portion 7a. In the coating removing portion 7a, The land part 4 and the NC land part 5 are arranged in a line along the side 7b of the film removing part 7a, and the exposed part 3a of the pattern part 3 exposed in the film removing part 7a and the exposed pattern part 6 are exposed. The part 6a is in a state perpendicular to the side 7b of the film removing part 7a, and the circuit board of the present invention is formed.

このような本発明の回路基板には、図１に示すように、ベアチップ等からなる四角形状をなした半導体部品８の複数の電極９が露出部３ａを含むランド部４、及び露出部６ａを含むＮＣランド部５上に半田１０付されるようになっており、この時、露出部３ａを含むランド部４と露出部６ａを含むＮＣランド部５は、露出表面積が等しいため、半田１０の盛り上がりを等しくできて、半田１０の平坦度（コプラナリティ）が得られ、半導体部品の半田１０付の信頼性を向上させることができる。また、ＮＣランド部５は、一般的には半導体部品８の半田付強度を増大させたり、将来の半導体回路の増加のために予備的に設けたり、或いは、現在では使用されなくなった半導体回路の残存用として存在している。   In such a circuit board of the present invention, as shown in FIG. 1, a plurality of electrodes 9 of a semiconductor component 8 having a square shape made of a bare chip or the like have land portions 4 including exposed portions 3a, and exposed portions 6a. Solder 10 is applied onto the NC land portion 5 including the exposed portion 3a and the NC land portion 5 including the exposed portion 6a have the same exposed surface area. The swell can be made equal, the flatness (coplanarity) of the solder 10 can be obtained, and the reliability of the semiconductor component with the solder 10 can be improved. Further, the NC land portion 5 generally increases the soldering strength of the semiconductor component 8, is provided in advance for an increase in future semiconductor circuits, or is a semiconductor circuit that is no longer used at present. It exists for surviving use.

なお、上記実施例では、図２に示すように、四角形状の全体に皮膜除去部７ａが設けられたもので説明したが、図２に示す二点鎖線の範囲に絶縁皮膜７を設けて、皮膜除去部７ａを帯状の四角形状としても良い。   In addition, in the said Example, as shown in FIG. 2, it demonstrated by what the film removal part 7a was provided in the whole square shape, but provided the insulating film 7 in the range of the dashed-two dotted line shown in FIG. It is good also considering the film removal part 7a as a strip-shaped square shape.

本発明の回路基板に係り、半導体部品を取り付けた状態の要部の拡大断面図である。It is an expanded sectional view of the principal part in the state which concerns on the circuit board of this invention, and the semiconductor component was attached. 本発明の回路基板に係る要部の平面図である。It is a top view of the principal part concerning the circuit board of the present invention. 従来の回路基板に係る要部の平面図である。It is a top view of the principal part concerning the conventional circuit board.

符号の説明Explanation of symbols

１ 絶縁基板
２ 導電パターン
３ パターン部
３ａ 露出部
４ ランド部
５ ＮＣランド部
６ 延設パターン部
６ａ 露出部
７ 絶縁被膜
７ａ 皮膜除去部
７ｂ 辺
８ 半導体部品
９ 電極
１０ 半田 DESCRIPTION OF SYMBOLS 1 Insulating substrate 2 Conductive pattern 3 Pattern part 3a Exposed part 4 Land part 5 NC land part 6 Extension pattern part 6a Exposed part 7 Insulating film 7a Film removal part 7b Side 8 Semiconductor component 9 Electrode 10 Solder

Claims (5)

金属からなる導電パターンが形成された絶縁基板と、この絶縁基板上に設けられた絶縁被膜とを備え、前記導電パターンは、複数のランド部と、このランド部に接続されたパターン部を有すると共に、前記絶縁被膜には、四角形状の被膜除去部が設けられ、複数の前記ランド部は、前記被膜除去部内に位置すると共に、前記ランド部に繋がって前記被膜除去部内に位置する前記パターン部は、前記被膜除去部の辺に対して垂直状態にしたことを特徴とする回路基板。 An insulating substrate on which a conductive pattern made of metal is formed and an insulating film provided on the insulating substrate, the conductive pattern having a plurality of land portions and a pattern portion connected to the land portions. The insulating film is provided with a quadrangular film removing portion, and the plurality of land portions are located in the film removing portion, and the pattern portion is connected to the land portion and located in the film removing portion. A circuit board characterized by being in a state perpendicular to the side of the film removal portion. 複数の前記ランド部は、前記被膜除去部の辺に沿って配設されたことを特徴とする請求項１記載の回路基板。 The circuit board according to claim 1, wherein the plurality of land portions are disposed along a side of the film removal portion. 前記導電パターンは、電気信号が流れる前記パターン部、及び前記ランド部と、電気信号が流れないＮＣランド部、及びこのＮＣランド部に接続された延設パターン部を有し、前記ＮＣランド部は、前記被膜除去部内に位置すると共に、前記ＮＣランド部に繋がって前記被膜除去部内に位置する前記延設パターン部は、前記被膜除去部の辺に対して垂直状態にしたことを特徴とする請求項１，又は２記載の回路基板。 The conductive pattern includes the pattern portion through which an electric signal flows, the land portion, an NC land portion through which no electric signal flows, and an extended pattern portion connected to the NC land portion. The extended pattern portion, which is located in the coating removal portion and is connected to the NC land portion and located in the coating removal portion, is perpendicular to the side of the coating removal portion. Item 3. The circuit board according to item 1 or 2. 前記ランド部と前記ＮＣランド部は、前記被膜除去部の辺に沿って少なくとも一列に配設されたことを特徴とする請求項３記載の回路基板。 4. The circuit board according to claim 3, wherein the land portion and the NC land portion are arranged in at least one line along a side of the film removal portion. 複数の電極を有する半導体部品を備え、前記電極がランド部と前記ＮＣランド部に半田付けされたことを特徴とする請求項３、又は４記載の回路基板。 5. The circuit board according to claim 3, further comprising a semiconductor component having a plurality of electrodes, wherein the electrodes are soldered to the land portion and the NC land portion.
JP2005308498A 2005-10-24 2005-10-24 Circuit board Withdrawn JP2007116040A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009054846A (en) * 2007-08-28 2009-03-12 Fujitsu Ltd Printed wiring substrate, and method for manufacturing electronic device
JP2009147029A (en) * 2007-12-12 2009-07-02 Shinko Electric Ind Co Ltd Wiring board and mounting structure of electronic component

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009054846A (en) * 2007-08-28 2009-03-12 Fujitsu Ltd Printed wiring substrate, and method for manufacturing electronic device
US8338715B2 (en) 2007-08-28 2012-12-25 Fujitsu Limited PCB with soldering pad projections forming fillet solder joints and method of production thereof
JP2009147029A (en) * 2007-12-12 2009-07-02 Shinko Electric Ind Co Ltd Wiring board and mounting structure of electronic component

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