JP2007115838A - Manufacturing method and manufacturing apparatus of semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor device which prevents an abnormality in which a dimension after etching processing is out of a standard, by detecting a change of an impedance of a reaction chamber, in advance and in real time at that. <P>SOLUTION: A conductive film is formed through an insulating film on a semiconductor substrate, a resist film is patterned on the conductive film, and the conductive film is etched by using the resist film as a mask in parallel with a plurality of reaction chambers 2A, 2B. A variable capacitance capacitor constitutes impedance matching devices 4A, 4B which perform impedance matching between high frequency power supplies 3A, 3B which supply power to the reaction chamber and each reaction chamber. The capacitance value is measured in the variable capacitance capacitor, a difference in the capacitance value of the variable capacitance capacitor corresponding to each reaction chamber is calculated, and etching is stopped when the difference in the capacitance value is equal to or more than a threshold value. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device using dry etching, and an apparatus for manufacturing a semiconductor device.

  In recent years, MOS field-effect transistors have become mainstream as elements constituting semiconductor devices with miniaturization. Further, with the miniaturization of MOS field effect transistors, a method for forming a fine gate electrode has become important.

  A dry etching process using plasma is often used for processing a semiconductor device. Dry etching is a technique in which an etching gas is introduced into a reaction chamber under reduced pressure, the etching gas is dissociated using high-frequency power or the like, and a processing region on a semiconductor substrate is etched.

  Here, a particularly serious problem is that etching is performed using a resist film patterned in a photolithography process as a mask pattern, but between the dimension of the mask pattern and the dimension of the processed region where etching is performed. There is a case where an error may occur. This error is called a dimension conversion difference (CD shift), and has become a problem as miniaturization progresses.

  For example, the dimensional accuracy of the gate electrode of a 0.15 μm device is required to be as high as 150 ± 15 nm. When the dimension of the gate electrode changes, the threshold voltage of the transistor changes. When the magnitude of the CD shift exceeds the standard value, problems such as a decrease in the leakage current and driving current value of the transistor occur.

  In a semiconductor device manufacturing process, after etching, resist ashing, and cleaning processes, dimensions after etching are finally measured. Therefore, since abnormalities in the processing dimensions are discovered only at that stage, the etching is continued in the state of the apparatus in which the defect occurs until the abnormality is detected in the dimension measurement after the etching process. This greatly reduces the production yield of the product.

  In the mass production site of semiconductor devices, in order to prevent a decrease in yield, measures are being taken to eliminate as many as possible various factors of processing devices caused by repeated formation of fine gate electrodes with high accuracy. .

  Conventionally, in an etching apparatus, the power is measured between a matching unit connected to a high-frequency application electrode in the apparatus and a high-frequency power source, and a control device is used to follow the change even if the impedance of the reaction chamber changes. The impedance of the matching unit is adjusted. For this reason, there is a problem in that variations in processes and differences between apparatuses performing the same processing cannot be detected, resulting in fluctuations in device manufacturing yield.

  FIG. 8 is a block diagram showing a configuration example (for example, see Patent Document 1) of a semiconductor manufacturing apparatus for solving the above problem. An upper electrode 102 and a lower electrode 103 are provided inside the reaction chamber 101, and a wafer 104, which is a stacked body in which a conductive film and a resistor are formed on the semiconductor substrate, is placed on the lower electrode 103. The process gas is introduced into the reaction chamber 101 via a flow meter (not shown). The pressure gauge 105 measures the gas pressure inside the reaction chamber 101, and the control device 108 adjusts the reaction chamber 101 to a predetermined pressure by a pressure adjustment valve 107 attached between the exhaust pump 106 and the reaction chamber 101. To control.

  The high frequency power source 109 applies high frequency power between the upper electrode 102 and the lower electrode 103 to generate plasma. A current-voltage phase difference sensor 121 is attached between the lower electrode 103 and the high-frequency power matching unit 120. The current / voltage phase difference sensor 121 can directly measure the current and voltage actually applied to the plasma etching apparatus and the phase difference without including the loss in the matching unit 120, and the measurement result is displayed on the current / voltage phase difference meter 122. To do. As a result, the amount of power input to the plasma etching apparatus can be detected and the shift amount of the CD shift can be monitored, so that a reduction in device manufacturing yield can be suppressed.

  By using the above etching apparatus, it is possible to mass-produce fine gate electrode formation with a certain accuracy. However, although the dimensional processing accuracy of the fine gate electrode is increased by using the above-described etching apparatus, there arises a problem that a large amount of products in which the CD shift is out of specification occurs. Specifically, an abnormality that the size of the region to be processed after etching becomes larger than expected frequently occurs especially when the dry etching apparatus is close to the maintenance time.

When these problems occur, the etching apparatus is immediately stopped and each part of the etching apparatus is wet-cleaned to solve the problem. In addition, when a CD shift abnormality occurs, measures are taken such as shortening the maintenance cycle as compared with the conventional case so as not to cause a defect.
JP 2003-174015 A

  However, even if the maintenance period is shortened, the dimensional abnormality occurs after a certain amount of time, although it is improved immediately after the maintenance.

  For the purpose of capturing the abnormal state of this etching apparatus, the monitor is used to measure the etching rate of the apparatus, monitor the change in the intensity of plasma emission in the reaction chamber, or the DC voltage component (self-applied to the laminate being processed). The bias potential, more precisely the peak value of the potential applied to the laminate, was measured, but no anomaly could be detected.

  Further, when the etching apparatus after occurrence of abnormality was investigated, when the reaction chamber was sealed and kept in a vacuum, the pressure increase per unit time was larger than that in the normal state. Further, when the etching apparatus in which an abnormality occurred was examined in detail, when the pressure increase was measured after evacuation for a long time of about 1 hour, there was no significant difference from the normal time. On the other hand, when the vacuum holding was measured after introducing the etching gas into the reaction chamber for a long time, the pressure increase was remarkable. In addition, no abnormality was found in the management items of other devices.

  Therefore, the phenomenon in which the pressure increase described above becomes significant after product processing and the phenomenon in which the dimension after etching processing becomes an unexpected size are the same cause. In the etching apparatus, a reaction product generated during processing adheres to and accumulates on the wall surface and components in the reaction chamber every time the substrate processing is repeated. When this reaction product adsorbs and releases the etching gas being processed, the partial pressure ratio of the etching gas originally assumed changes, and the atmosphere in the reaction chamber changes. Then, the processing parameters of the etching are changed, and as a result, an abnormality in which the dimension after the etching processing becomes large is caused.

  From the above, in order to prevent the above-described abnormality in which the dimension after the etching process becomes large, it is possible to prevent the increase in pressure by measuring at a short cycle such as every wafer. However, the measurement of the pressure rise requires a work time of at least about 5 minutes to 10 minutes, which greatly impairs the operation efficiency of the etching apparatus and causes a problem.

  In order to solve the above problem, an object of the present invention is to provide a method for manufacturing a semiconductor device that prevents an abnormality in which a dimension after etching processing is out of specification, and detects it in real time. To do.

  In order to achieve the above object, according to a first method of manufacturing a semiconductor device of the present invention, a conductive film is formed on a semiconductor substrate via an insulating film, a resist film is patterned on the conductive film, and a plurality of reactions are performed. In a method of manufacturing a semiconductor device in which the conductive film is etched using the resist film as a mask in parallel in a chamber, a high-frequency power source that supplies power to the reaction chamber and an impedance matching unit that performs impedance matching between the reaction chambers Measuring the capacitance value of the variable capacitor, calculating the difference between the capacitance values of the variable capacitor corresponding to each reaction chamber, and stopping the etching when the difference between the capacitance values exceeds a threshold value. It is characterized by.

  Further, in the second method for manufacturing a semiconductor device of the present invention, a conductive film is formed on a semiconductor substrate via an insulating film, a resist film is patterned on the conductive film, and a plurality of reaction chambers are arranged in parallel. In the method of manufacturing a semiconductor device in which the conductive film is etched using the resist film as a mask, a high-frequency power source that supplies power to the reaction chamber and each reaction chamber each time the conductive film on the predetermined number of the semiconductor substrates is etched And measuring the capacitance value of the variable capacitor constituting the impedance matching device for impedance matching, and stopping the etching when the detected capacitance value meets a predetermined condition.

  According to another aspect of the present invention, there is provided a first apparatus for manufacturing a semiconductor device, comprising: a plurality of stacked bodies including a conductive film formed on a semiconductor substrate via an insulating film; and a resist film patterned on the conductive film. In a semiconductor device manufacturing apparatus that etches the conductive film using the resist film as a mask, a reaction chamber that etches the conductive film, a high-frequency power source that supplies power to the reaction chamber, and the reaction chamber and the high-frequency power source are connected. A plurality of processing units having an impedance matching unit that performs impedance matching between the reaction chamber and the high-frequency power source, and a capacitance measuring unit that detects a capacitance value of a variable capacitor included in the impedance matching unit, and etching into the processing unit An equipment interlock capable of stopping the operation, an arithmetic circuit connected to the equipment interlock, and the variable capacity capacitor And a storage device that stores a result of calculation by the arithmetic circuit, and the capacitance measuring device calculates a capacitance value of the variable capacitance capacitor while etching is being performed in a corresponding reaction chamber. And the arithmetic circuit calculates a difference between the capacitance values of the variable capacitors for each of the processing units, and the facility interlock causes the processing unit to detect when the difference between the capacitance values exceeds a preset threshold value. The etching is stopped.

  According to another aspect of the present invention, there is provided a manufacturing apparatus for a semiconductor device, comprising: a plurality of stacked bodies including a conductive film formed on a semiconductor substrate via an insulating film; and a resist film patterned on the conductive film. In a semiconductor device manufacturing apparatus that etches the conductive film using the resist film as a mask, a reaction chamber that etches the conductive film, a high-frequency power source that supplies power to the reaction chamber, and the reaction chamber and the high-frequency power source are connected. A processing unit having an impedance matching unit that matches impedances of the reaction chamber and the high-frequency power source, and a capacitance measuring unit that measures a capacitance value of the variable capacitance capacitor included in the impedance matching unit, and a capacitance value of the variable capacitance capacitor And a storage device for storing the result calculated by the arithmetic circuit and the processing section can stop etching. And the storage device and an arithmetic circuit connected to the equipment interlock, and the capacity measuring device is etched each time a predetermined number of laminated bodies are processed in the reaction chamber. And measuring the capacitance value of the corresponding variable capacitor while the storage device stores the capacitance value, and when the capacitance value stored in the storage device meets a predetermined condition, the facility interface The lock is characterized in that the processing unit stops etching.

  According to the present invention, there is provided a method for detecting and preventing an abnormality in which a dimension after etching processing is out of specification by detecting a change in impedance of a reaction chamber in advance and in real time, and a semiconductor device manufacturing apparatus. Can be provided.

  In the first and second methods of manufacturing a semiconductor device of the present invention, the process of etching the conductive film is performed in a region where the resist film is not formed in the conductive film until a part of the insulating film appears. It includes a step of etching and a step of etching the residue of the conductive film. In the step of etching the residue, the capacitance value of the variable capacitor can be measured. According to such a method for manufacturing a semiconductor device, fluctuations in the impedance of the reaction chamber can be detected in a state where the influence of the composition variation of the conductive film is small.

  Further, in the process of etching the conductive film, in the step of etching the conductive film until a part of the insulating film appears, a mixture of a hydrogen bromide gas and a chlorine gas gasified in the reaction chamber is mixed. Etching is performed with an etching gas mainly containing a gas, and in the step of etching the residue, the etching is performed with an etching gas mainly containing a hydrogen bromide-based gas that is plasmatized in the reaction chamber. Also good.

  In the second method of manufacturing a semiconductor device according to the present invention, the predetermined condition is that a difference between a capacitance value of the variable capacitor measured at a predetermined time and a capacitance value measured immediately before is not less than a predetermined threshold. When the state in which the difference between the capacitance values is equal to or greater than a predetermined threshold continues for a predetermined number of times, or the measured capacitance value is continuously measured a predetermined number of times before the previous measurement. The capacity value may be at least one of the larger capacity values.

  Further, in the first and second semiconductor device manufacturing apparatuses according to the present invention, in the etching process of the conductive film, the resist film in the conductive film is not formed until a part of the insulating film appears. The capacitance measuring device may include a step of etching the region and a step of etching the residue of the conductive film, and the capacitance measuring device may measure the capacitance value of the variable capacitor in the step of etching the residue. According to such a semiconductor device manufacturing apparatus, fluctuations in the impedance of the reaction chamber can be detected in a state where the influence of the composition variation of the conductive film is small.

  In the second semiconductor device manufacturing apparatus of the present invention, the predetermined condition is that a difference between the capacitance value of the variable capacitance capacitor detected at a predetermined time point and the capacitance value detected immediately before is equal to or greater than a predetermined threshold value. The measured capacitance value is measured one time before the immediately preceding measurement when the difference between the capacitance values is equal to or greater than a predetermined threshold for a predetermined number of times, or continuously for a predetermined number of times. It is also possible to adopt a configuration that is at least one of the cases where the capacitance value is greater than the specified capacitance value.

  DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of a semiconductor device manufacturing apparatus according to the present invention will be described with reference to the drawings, taking as an example an etching apparatus, particularly an inductively coupled plasma apparatus (ICP) which is a high-density plasma etching apparatus.

(First embodiment)
FIG. 1 is a block diagram showing a configuration of an etching apparatus in the present embodiment. The processing units 1A and 1B include reaction chambers 2A and 2B for etching, high-frequency power sources 3A and 3B, impedance matching units 4A and 4B for impedance matching between the reaction chambers 2A and 2B and high-frequency power sources 3A and 3B, and impedances, respectively. Capacitance measuring devices 5A and 5B for measuring the capacitance values of the variable capacitors constituting the matching devices 4A and 4B are provided.

  The capacitance values of the variable capacitors in the impedance matching devices 4A and 4B are Ca and Cb, respectively. The temporary storage medium 15 (storage device) stores the capacitance values Ca and Cb measured by the capacity measuring devices 5A and 5B. The equipment command input unit 13 can input a command from an operator. The equipment interlock 14 sends a signal for stopping the substrate processing based on the data from the arithmetic circuit 16 to a substrate transport system or a control device for the entire apparatus (not shown). Based on a command from the equipment command input unit 13, the arithmetic circuit 16 performs an operation using a value stored in the temporary storage medium 15. The storage device 17 stores the result calculated by the arithmetic circuit 16.

  Next, the processing unit 1A will be described in detail with reference to FIGS. The processing unit 1A and the processing unit 1B have the same configuration. The high frequency power source 3A applies high frequency power to the upper electrode 7 to turn the etching gas introduced into the reaction chamber 2A into plasma. The impedance matching unit 4A controls the impedance so that the power applied to the upper electrode 7 is maximized. The antenna coil 6 generates a magnetic field to generate an induction electric field in the plasma, and a higher density plasma is generated by acceleration of electrons by the induction electric field.

  The high frequency power supply 8 applies high frequency power to the lower electrode 11 to cause the plasma generated in the reaction chamber 2 </ b> A to react with the object to be etched (laminated body) 12. The impedance matching unit 9 controls the impedance so that the power from the high-frequency power source 8 applied to the lower electrode 11 is maximized.

  A capacitor 10 is provided between the lower electrode 11 and the impedance matching unit 9. When high frequency power is applied from the high frequency power supply 8 to the lower electrode 11, the flow of electrons is blocked by the capacitor 10, and a negative self-bias voltage is generated in the stacked body 12. Due to the self-bias voltage, an electric field for accelerating cations in the plasma toward the substrate 12 is generated in the vicinity of the substrate 12, and the cations in the plasma collide with the stacked body 12 by this electric field to perform etching.

  FIG. 3 is a circuit diagram showing an electrical relationship between the high-frequency power source 3A shown in FIG. 2 and the impedance matching unit 4A that performs impedance matching between the reaction chamber 2A.

  The impedance matching unit 4A includes a variable capacitor 22 and an inductor 23 connected in series to the reaction chamber 2A as viewed from the high frequency power source 3A, and a variable capacitor 21 connected in parallel. The impedance matching unit 4A controls its own impedance by changing the capacities of the variable capacitors 22 and 23 by a control device (not shown) so that the high frequency power applied to the reaction chamber 2A by the high frequency power source 3A is maximized. In the impedance control method, first, the inductor 23 makes a constant change in the phase of the high frequency power. Next, the phase and absolute value of the impedance are adjusted by the variable capacitors 21 and 22.

  Next, a manufacturing process of the semiconductor device using the etching apparatus according to this embodiment will be described. FIG. 4 is a process cross-sectional view illustrating the formation of a semiconductor element, particularly a line pattern (gate electrode formation) using the etching apparatus according to this embodiment.

First, as shown in FIG. 4A, an insulating film 32 is formed on the semiconductor substrate 31, and a conductive film 33 is formed on the insulating film 32. Next, a resist film 34 is formed on the conductive film 33 and patterned to form an object to be etched (laminated body) 38 to be etched in the next step. Here, the film type constituting the insulating film 32 is, for example, SiO ₂ and the film thickness is, for example, 3 nm. Moreover, the film | membrane type | mold which comprises the electrically conductive film 33 shall be polysilicon, for example, and the film thickness shall be 150 nm, for example. Further, the film thickness of the resist film 34 is, for example, 500 nm. The line width of the line shape 35 to be patterned is set to 150 nm, for example.

Next, using an etching apparatus, as shown in FIG. 4B, using the patterned resist film 34 of the stacked body 38 as a mask, the conductive film 33 in the processing region 36 whose surface is not protected by the resist film 34. Etch. As an etching gas, a mixed gas containing, for example, HBr, Cl ₂ , He, and O ₂ containing hydrogen bromide gas and chlorine gas as main components is introduced into the reaction chamber 2A and is converted into plasma to select the processing region 36. Etch. When a part of the surface of the insulating film 32 appears, the process proceeds to the next step. Hereinafter, this process is referred to as a main etch step.

Next, as shown in FIG. 4C, the conductive film residue 37 in the region to be processed 36 that could not be completely removed in the main etching step is completely removed without etching the insulating film 32. To do. As an etching gas, for example, a gas containing, for example, HBr, He, or O ₂ containing hydrogen bromide gas as a main component is introduced into the reaction chamber 2A. The introduced etching gas is turned into plasma, and the conductive film residue 37 is etched. Hereinafter, this process is referred to as an overetch step.

  In the over-etching step, an etching process is performed for a necessary and sufficient time to completely remove the conductive film residue 37. For example, after the conductive film residue 37 is completely removed, the etching is further performed for about 30 seconds. Continue processing. Through this overetching step, a series of line pattern forming steps is completed.

  FIG. 5 is a graph showing the capacitance of the variable capacitor 21 of the impedance matching device 4 shown in FIG. 3 in the overetching step shown in FIG. 4C of the semiconductor device manufacturing process. The horizontal axis is the processing time, and the vertical axis is the capacitance of the variable capacitor 21. Reference numeral 45 denotes a capacity value in an atmosphere state (normal state) in a normal reaction chamber that can process the processing dimension of the substrate within the assumed allowable value. Reference numeral 46 denotes an abnormal reaction in which the processing dimension of the substrate falls outside the assumed allowable value. The capacity value in an indoor atmosphere state (abnormal state) is shown.

  The overetch step processing period 41 is divided into an initial period 42 that is an initial state of etching, an intermediate period 43 in which etching is stably performed, and an end period 44 that is a state in which there is little residue. In the initial period 42, the capacitance value of the variable capacitor 21 decreases suddenly. In the intermediate period 43, the capacitance value of the variable capacitor 21 continues to be a constant value, and in the final period 44, it increases with time.

  In the initial period 42 and the final period 44, there is almost no difference in the capacitance value of the variable capacitor 21 between the normal time and the abnormal time. On the other hand, in the intermediate period 43, there is a significant difference in the capacitance value of the variable capacitor 21 between the normal state and the abnormal state. Accordingly, whether or not the reaction chamber 2A is in a normal state can be detected by measuring the capacitance value of the variable capacitor 21 in the intermediate period 43.

  The etching apparatus according to the present embodiment measures the capacitance values of the variable capacitors 21 of the impedance matching units 4A and 4B when the processing units 1A and 1B perform the etching process under the same conditions. Calculate the difference. The reaction chambers 2A and 2B are in a normal state by calculating whether or not the difference is equal to or greater than a threshold value determined based on an assumed allowable value of the processing dimension of the substrate (or an allowable value of variation of the processing dimension). Whether or not is detected.

  In the reaction chambers 2A and 2B, the number of processing substrates that are in an abnormal state is not constant, and it is rare that the reaction chamber A and the reaction chamber 2B are in an abnormal state at the same time. Accordingly, the abnormal state can be detected by comparing the impedances of the reaction chambers 2A and 2B.

  Next, the operation of the etching apparatus according to this embodiment will be described. In FIG. 1, high-frequency power is supplied from the high-frequency power sources 3A and 3B to the reaction chambers 2A and 2B, and an etching process is performed in the reaction chambers 2A and 2B. The impedance matching units 4A and 4B control their impedance so that the power supplied from the high-frequency power sources 3A and 3B to the reaction chambers 2A and 2B is maximized. The capacitance measuring devices 5A and 5B measure the capacitance values Ca and Cb of the variable capacitance capacitors 21 of the impedance matching devices 4A and 4B at regular intervals and supply them to the temporary storage medium 15.

  The equipment command input unit 13 calculates the minimum values Ca_min and Cb_min of the capacitance values Ca and Cb in the intermediate period 42 from the capacitance values Ca and Cb at each time stored in the temporary storage medium 15 according to the input command. To detect. Further, the difference C_dif of the minimum capacity value is calculated by the arithmetic circuit 16, the result is stored in the storage device 17, and the difference C_dif of the minimum capacity value is also transmitted to the equipment interlock 14.

  When the difference C_dif in the minimum capacity value exceeds the threshold value T, the equipment interlock 14 sends a signal for stopping the substrate processing to a substrate transfer system or a control device for the entire apparatus (not shown). The substrate processing stop signal may be sent from the equipment interlock 14 to the entire control apparatus during the substrate processing in some cases. In this case, the substrate processing is continued, and steps such as substrate transfer after the substrate processing is completed are stopped. In addition, after the substrate processing is completed, it is notified that an abnormality has occurred in the reaction chamber, if necessary. When this system is used, it is possible to record a change in the minimum capacitance value difference C_dif with respect to time, and it is possible to detect an abnormality in the etching apparatus, as will be described later.

  FIG. 6 is a flowchart showing abnormality detection of the etching apparatus according to the present embodiment. First, the first substrate is processed in the reaction chamber 2A (step S101). Ca_min at the time of processing (hereinafter referred to as Ca_min [1]) is stored in the temporary storage medium 15. Next, the first substrate is processed in the reaction chamber 2B (step S102). Cb_min at the time of processing (hereinafter referred to as Cb_min [1]) is stored in the temporary storage medium 15. Next, the arithmetic circuit 16 obtains a value of | Ca_min [1] −Cb_min [1] | (hereinafter referred to as C_dif [1,1]). Further, it is determined whether or not C_dif [1, 1] is less than the threshold value Th (step S103). If C_dif [1, 1] is not less than Th, the substrate processing is stopped (step S104). After stopping the substrate processing, an alarm is issued (step S105), and the abnormality detection is finished.

  If C_dif [1,1] is less than Th in step S103, the nth (here, n = 2) th substrate is processed in the reaction chamber 2A (step S106). Ca_min [n] at the time of processing is stored in the temporary storage medium 15. Next, the arithmetic circuit 16 calculates C_dif [n, n−1]. Further, it is determined whether or not C_dif [n, n−1] is less than the threshold value Th (step S107). If C_dif [n, n−1] is not less than Th, the substrate processing is stopped (step S108). After stopping the substrate processing, an alarm is issued (step S109), and the abnormality detection is finished.

  If C_dif [n, n−1] is less than Th in step S107, then the nth substrate is processed in the reaction chamber 2B (step S110). Cb_min [n] at the time of processing is stored in the temporary storage medium 15. Next, the value of C_dif [n, n] is obtained in the arithmetic circuit 16. Further, it is determined whether or not C_dif [n, n] is less than the threshold value Th (step S111). If C_dif [n, n] is not less than Th, the substrate processing is stopped (step S112). After stopping the substrate processing, an alarm is issued (step S113), and the abnormality detection is finished.

  In step S111, if C_dif [n, n] is less than Th, n is replaced with n + 1 (step S114), the process returns to step S106, and substrate processing is performed in the reaction chamber 2A.

  Since the threshold Th varies depending on the type of semiconductor device to be manufactured, a value may be obtained and stored in advance through experiments based on the type of semiconductor device, or the threshold may be input according to processing conditions or the like. preferable. By doing in this way, even if it is the same etching apparatus, it becomes possible to handle many kinds. It is also possible to process semiconductor devices having different processing dimension settings. Furthermore, since no person is involved in the process of detecting an abnormality, it is possible to prevent human error.

  As described above, in the etching apparatus according to the present embodiment, the reactive substance adheres to the reaction chamber wall and the atmosphere in the reaction chamber fluctuates due to repeated substrate processing. Therefore, a plurality of reaction chambers are provided, substrate processing is performed in parallel, and the capacitance values of the impedance matching devices in both reaction chambers are compared. When the difference between the capacity values of the two reaction chambers is equal to or greater than a threshold value that is an assumed allowable value (or an allowable amount of variation in processing dimensions), the substrate processing is stopped and an alarm is issued. Then, it is possible to prevent an etching failure from occurring by confirming whether or not the apparatus has any abnormality after the substrate processing (for example, measuring the pressure increase in the reaction chamber described above).

  In the present embodiment, the capacitance value of the variable capacitor 21 is measured. However, the capacitance value of the variable capacitor 22 may be measured.

  Moreover, although the case where there are two reaction chambers has been shown as an example of the system configuration, the same effect can be obtained when there are three or more reaction chambers.

(Second Embodiment)
An etching apparatus according to the second embodiment of the present invention will be described. The etching apparatus according to this embodiment is the same as the configuration shown in FIG. 1 in the first embodiment, and the operation in the arithmetic circuit 16 and the like is different. As will be described below, the etching apparatus according to the present embodiment compares the capacitance value of the variable capacitance capacitor 21 of the impedance matching device measured by the capacitance measuring device 5A with the previous measurement value by the arithmetic circuit 16. Detects abnormal conditions.

  FIG. 7 is a graph showing an example of a change in the capacitance value of the variable capacitor 21 arranged in the impedance matching device according to the present embodiment with respect to the number of processed substrates. The capacitance value in FIG. 7 is the capacitance value of the variable capacitor 21 in the intermediate period 43 shown in FIG. 5, and the minimum value is indicated by a diamond and the maximum value is indicated by a hyphen. The sampled capacitance value is a capacitance value at the time of substrate processing of the substrate to be processed last per batch processing. Here, one batch means that 25 substrates are placed on one carrier.

  In batch processing in which an etching apparatus continuously processes a substrate, the capacitance value tends to increase consistently from the first substrate to the last substrate to be processed. Therefore, the capacitance value of the variable capacitor 21 at the time of substrate processing of the substrate to be processed last is handled as a value representing the capacitance value of the entire batch.

  In FIG. 7, it is confirmed that the processed dimension of the substrate subjected to the cleaning process after the over-etching step is increased by 15 nm at the maximum with respect to the assumed dimension of 150 nm in the substrate having 1,375 or more processed substrates (51 in FIG. 7) It was done. In order to prevent such an abnormality in advance, the threshold value determined based on the assumed allowable value of the processing dimension of the substrate is set to 82 pF, and the etching process is stopped at the stage 52 where the minimum value of the variable capacitance exceeds the threshold value. That's fine.

  Further, for example, at the stage 53 when the minimum capacity value has increased continuously for 5 batch processing, the substrate processing is stopped or an alarm is issued to check whether there is any abnormality in the apparatus after stopping the substrate processing, for example, the above-described reaction You may make it measure the pressure rise in a room | chamber interior. This is based on the result that when the minimum capacity value rises continuously for 5 batch processes, the frequency that the processing dimension shows an abnormal value in a short time increases in the subsequent substrate processing. In this way, the process abnormality can be monitored by managing the change tendency of the capacitance value of the impedance matching device.

  As described above, as shown in the present embodiment, the capacitance value of the variable capacitor is monitored, and when a predetermined behavior change is detected with respect to the capacitance value, the substrate processing is stopped, so that the etching failure is prevented. Can be prevented.

  The etching apparatus according to this embodiment can also be applied when there is one reaction chamber.

  In the first and second embodiments, an inductively coupled plasma apparatus (ICP) is used as an etching apparatus. However, for example, in reactive ion etching (RIE), atmospheric fluctuations in the reaction chamber appear as impedance fluctuations in the reaction chamber. In some cases, the same effect can be obtained.

  In addition, although an apparatus using two high-frequency power supplies is used as an etching apparatus, for example, in an apparatus whose structure is simplified with one high-frequency power supply or an apparatus whose structure is complicated by three or more high-frequency power supplies, A similar effect can be obtained when the atmosphere variation in the reaction chamber appears as the impedance variation in the reaction chamber.

  Also, in the overetch step, an abnormality was detected by observing the impedance variation. For example, when the atmospheric variation in the reaction chamber appears as the impedance variation in the reaction chamber even in the main etch step, the impedance matching unit in that step. The same effect can be obtained by monitoring the behavioral change. However, the change in the behavior of the impedance matching unit in the main etch step is usually caused by variations in the composition of the conductive film to be etched and variations in film thickness. For this reason, it is not easy to detect a change in the conditions in the reaction chamber, so it is desirable to monitor changes in the overetch step.

  The method for manufacturing a semiconductor device and the apparatus for manufacturing a semiconductor device according to the present invention have the advantage of preventing the occurrence of etching defects for forming a line pattern in a conductive film formed on a substrate. Is available.

The block diagram which shows the structure of the etching apparatus which concerns on the 1st Embodiment of this invention. The block diagram which shows the structure of the process part of an etching apparatus same as the above Circuit diagram showing the configuration of the impedance matching unit of the etching apparatus Sectional process drawing of the semiconductor device showing the etching process of the etching apparatus The graph which shows the capacitance value of the variable capacitor of the impedance matching device when the etching apparatus is normal and abnormal The flowchart which shows the flow of abnormality detection of an etching apparatus same as the above The graph which shows the relationship between the number of etching processes of the etching apparatus which concerns on the 2nd Embodiment of this invention, and the capacitance value of a variable capacitor Block diagram showing the configuration of a conventional etching apparatus

Explanation of symbols

1A, 1B Processing unit 2A, 2B Reaction chamber 3A, 3B, 8 High frequency power supply 4A, 4B, 9 Impedance matching device 5A, 5B Capacitance measuring device 6 Antenna coil 7 Upper electrode 10 Capacitor 11 Lower electrode 12, 38 Semiconductor substrate 13 Equipment command Input unit 14 Equipment interlock 15 Temporary storage medium 16 Arithmetic circuit 17 Storage device 21, 22 Variable capacitor 23 Inductor 31 Semiconductor substrate 32 Insulating film 33 Conductive film 34 Resist 35 Line shape 36 Processed area 37 Conductive film residue 41 Overetch Step processing period 42 Intermediate period 43 Capacity value in normal state 44 Capacity value in abnormal state 51 Period after processing number of 1375 sheets 52 Stage when minimum value of variable capacity exceeds threshold value 53 5 batch processing Minimum capacity continuously The stage where the value rose

Claims (9)

A semiconductor device in which a conductive film is formed on a semiconductor substrate through an insulating film, a resist film is patterned on the conductive film, and the conductive film is etched using the resist film as a mask in parallel in a plurality of reaction chambers. In the manufacturing method,
Measure the capacitance value of a variable capacitor that constitutes an impedance matching unit that performs impedance matching between the high-frequency power source that supplies power to the reaction chamber and each reaction chamber,
A method of manufacturing a semiconductor device, comprising: calculating a difference between capacitance values of the variable capacitance capacitors corresponding to the reaction chambers, and stopping etching when the difference between the capacitance values exceeds a threshold value. A semiconductor device in which a conductive film is formed on a semiconductor substrate through an insulating film, a resist film is patterned on the conductive film, and the conductive film is etched using the resist film as a mask in parallel in a plurality of reaction chambers. In the manufacturing method,
Each time the conductive film on the predetermined number of the semiconductor substrates is etched, the capacitance value of the variable capacitor constituting the impedance matching unit that performs impedance matching between the high frequency power source that supplies power to the reaction chamber and each reaction chamber is set. Measure and
The method of manufacturing a semiconductor device, wherein the etching is stopped when the detected capacitance value meets a predetermined condition. The process of etching the conductive film includes:
Etching a region of the conductive film where the resist film is not formed until a part of the insulating film appears;
Etching the residue of the conductive film,
The method of manufacturing a semiconductor device according to claim 1, wherein in the step of etching the residue, a capacitance value of the variable capacitor is measured. The process of etching the conductive film includes:
In the step of etching the conductive film until a part of the insulating film appears, etching is performed with an etching gas mainly composed of a mixed gas of a hydrogen bromide-based gas and a chlorine-based gas that is plasmatized in the reaction chamber. Done,
4. The method of manufacturing a semiconductor device according to claim 3, wherein in the step of etching the residue, etching is performed with an etching gas mainly composed of a hydrogen bromide-based gas that has been made plasma in the reaction chamber. The predetermined condition is:
When the difference between the capacitance value of the variable capacitance capacitor measured at a predetermined time and the capacitance value measured immediately before is equal to or greater than a predetermined threshold value,
When the state where the difference between the capacitance values is equal to or greater than a predetermined threshold continues a predetermined number of times,
Or it is at least any one in case the said capacitance value measured continuously predetermined times is larger than the capacitance value measured 1 time before the said last measurement. The manufacturing method of the semiconductor device as described in any one of Claims 1-3. A semiconductor device that etches a plurality of stacked conductive films each including a conductive film formed on a semiconductor substrate via an insulating film and a resist film patterned on the conductive film, using the resist film as a mask. In the manufacturing equipment of
A reaction chamber that etches the conductive film, a high-frequency power source that supplies power to the reaction chamber, an impedance matching unit that connects the reaction chamber and the high-frequency power source, and performs impedance matching between the reaction chamber and the high-frequency power source, and the impedance A plurality of processing units having a capacitance measuring device for detecting a capacitance value of a variable capacitor included in the matching unit;
An equipment interlock capable of stopping etching in the processing section;
An arithmetic circuit connected to the equipment interlock;
A storage device for storing a capacitance value of the variable capacitor and a result calculated by the arithmetic circuit;
The capacitance measuring device measures a capacitance value of the variable capacitor while etching is performed in a corresponding reaction chamber,
The arithmetic circuit calculates a difference in capacitance value of the variable capacitor for each processing unit,
The equipment interlock is an apparatus for manufacturing a semiconductor device, wherein the processing unit stops the etching when the difference between the capacitance values becomes equal to or greater than a preset threshold value. A semiconductor device that etches a plurality of stacked conductive films each including a conductive film formed on a semiconductor substrate via an insulating film and a resist film patterned on the conductive film, using the resist film as a mask. In the manufacturing equipment of
A reaction chamber that etches the conductive film, a high-frequency power source that supplies power to the reaction chamber, an impedance matching unit that connects the reaction chamber and the high-frequency power source, and matches impedances of the reaction chamber and the high-frequency power source, and the impedance A processing unit having a capacitance measuring device that measures the capacitance value of the variable capacitor included in the matching unit;
A storage device for storing a capacitance value of the variable capacitor and a result calculated by the arithmetic circuit;
An equipment interlock capable of stopping etching in the processing section;
An arithmetic circuit connected to the storage device and the equipment interlock,
The capacitance measuring device measures a capacitance value of the corresponding variable capacitance capacitor during etching each time a predetermined number of stacked bodies are processed in the reaction chamber,
The storage device stores the capacity value;
The apparatus for manufacturing a semiconductor device, wherein the equipment interlock causes the processing unit to stop etching when a capacitance value stored in the storage device matches a predetermined condition. The process of etching the conductive film includes:
Etching a region of the conductive film where the resist film is not formed until a part of the insulating film appears;
Etching the residue of the conductive film,
8. The semiconductor device manufacturing apparatus according to claim 6, wherein the capacitance measuring device measures a capacitance value of the variable capacitance capacitor in the step of etching the residue. The predetermined condition is:
When the difference between the capacitance value of the variable capacitance capacitor detected at a predetermined time and the capacitance value detected immediately before is equal to or greater than a predetermined threshold value,
When the state where the difference between the capacitance values is equal to or greater than a predetermined threshold continues a predetermined number of times,
9. The semiconductor device according to claim 7, wherein the measured capacitance value is at least any one of a case where the measured capacitance value is larger than the capacitance value measured one time before the immediately preceding measurement. Manufacturing equipment.

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