JP2007115754A - Non-volatile semiconductor storage device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a non-volatile semiconductor storage device suppressing a writing disturbance phenomenon with respect to an adjacent non-selection memory cell adjacent to a selected selection memory cell in a writing operation. <P>SOLUTION: The non-volatile semiconductor storage device is provided with a memory cell array, where a plurality of non-volatile memory cells with MOSFET structures having charge holders accumulating a charge formed on a semiconductor substrate through an insulating film are arranged in a row direction and a column direction; control gates of the memory cells in the same row are mutually connected, and it is set to be a common word line extending in the row direction; diffusion regions forming drains or sources of the memory cells in the same column are mutually connected; and it is constituted as a common bit line extending in the column direction; which is formed of diffusion wiring. A shielding body 9 formed of a conductor or a conductive semiconductor is formed between the charge holders of the memory cells adjacent in the row direction. The upper end of the shielding body is positioned upper than an upper face of the semiconductor substrate 1. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a structure and a manufacturing method of a nonvolatile semiconductor memory device.

  As a conventional semiconductor memory device, there is a non-volatile semiconductor memory device in which a bit line is formed by extending impurity diffusion regions serving as source and drain regions of a transistor constituting a memory cell in parallel as diffusion wirings (for example, Patent Document 1).

  Here, FIG. 6 is a cross-sectional view of the memory cell array of the nonvolatile semiconductor memory device described in Patent Document 1, and FIG. 7 is a plan view of the memory cell array. FIG. 6 is a cross-sectional view taken along the line A1-A2 in FIG.

  In this nonvolatile semiconductor memory device, a floating gate 16 is formed on a semiconductor substrate 1 via a tunnel insulating film 3. An impurity diffusion layer 15 having a conductivity type opposite to that of the semiconductor substrate 1 is formed in the semiconductor substrate 1 between the adjacent floating gate 16 and the lower region of the tunnel insulating film 3. The impurity diffusion layer 15 functions as a source / drain of the memory cell, and functions as a diffusion wiring (bit line) of the memory cell array. Further, this nonvolatile semiconductor memory device is a contactless NOR flash memory, and as shown in FIG. 7, a plurality of memory cells are arranged in a matrix in the row direction and the column direction, respectively.

  Next, the operation of the nonvolatile semiconductor memory device shown in FIGS. 6 and 7 will be described. Here, FIG. 9 shows a memory cell array having a plurality of word lines (control gate 17) and bit lines (source / drain) 15, and n-th and n + 1-th bit lines BLn, BLn + 1 and m-th word line WLm. A voltage application condition in the case of selectively operating the memory cell 19 located at the intersection is shown. In the write operation, a write current flows and hot electrons are injected into the floating gate 16 by applying a voltage to the bit line 15 and the word line 17 under the write condition shown in FIG. Is done. In the read operation, a voltage is applied to the selected memory cell under the read condition shown in FIG. 9 to the bit line 15 and the word line 17, whereby a read current corresponding to the amount of electrons accumulated in the floating gate 16 of the selected memory cell. Is done. In the erasing operation, a voltage is applied to all the word lines 17 and all the bit lines 15 under the erasing condition shown in FIG. 9, and electrons accumulated in the floating gate are extracted to the substrate or the bit line by a tunnel oxide film tunneling phenomenon. Done in

JP-A-2003-179168

  However, in the structure of the memory cell array described in Patent Document 1, hot electrons generated in the drain region (on the bit line BLn + 1 side) of the selected memory cell 19 during the write operation with the miniaturization of the memory cell are connected to the selected memory cell 19. It becomes easy to inject into the floating gate of the adjacent non-selected memory cell 20 adjacent to the drain side on the same word line. More specifically, the space between the floating gates 16 of the memory cells on the same word line is narrowed due to the miniaturization of the memory cells, so that the physically selected memory cell 19 and the adjacent non-selected memory cell 20 are separated from each other. And a part of hot electrons generated in the drain region of the selected memory cell 19 are injected into the floating gate 16 of the adjacent non-selected cell 20 through the insulating film 11 or the impurity diffusion layer 15 between the floating gates 16. It becomes easy to be done. As a result, there is a problem that the threshold voltage of the adjacent non-selected memory cell 20 increases, data is erroneously read, write disturb occurs, and reliability decreases.

  FIG. 8 shows the measurement evaluation result of the dependency between the floating gates of both memory cells on the threshold increase value of the adjacent non-selected memory cell 20 when an arbitrary write voltage is applied to the selected memory cell 19 for an arbitrary time. Yes. As can be seen from FIG. 8, when the width between the floating gates of the selected memory cell and the adjacent non-selected memory cell is narrowed, the threshold value of the adjacent non-selected memory cell is rapidly increased.

  The present invention has been made in view of the above problems, and an object of the present invention is to suppress a write disturb phenomenon for an adjacent unselected memory cell adjacent to a selected memory cell selected as a write target in a write operation. A nonvolatile semiconductor memory device is provided.

  In order to achieve the above object, a non-volatile semiconductor memory device according to the present invention includes a non-volatile memory cell having a MOSFET structure provided with a charge holding portion capable of accumulating electric charges formed on a semiconductor substrate via an insulating film. A plurality of memory cells are arranged in the row direction and the column direction, and the control gates of the memory cells in the same row are connected to each other to form a common word line extending in the row direction, thereby forming the drains or sources of the memory cells in the same column. A non-volatile semiconductor memory device comprising a memory cell array configured as a common bit line extending in a column direction composed of diffusion lines by interconnecting diffusion regions, wherein the charge of the memory cells adjacent in the row direction A shield body made of a conductor or a conductive semiconductor is formed between the holding portions, and the upper end of the shield body is positioned above the upper surface of the semiconductor substrate. Is that the first feature of being.

  The nonvolatile semiconductor memory device according to the present invention having the above characteristics is characterized in that the shield body is connected to the diffusion wiring located below.

  The nonvolatile semiconductor memory device according to the present invention having any one of the above characteristics is characterized in that the upper end of the shield body is located above the lower end of the charge holding portion.

  Furthermore, the nonvolatile semiconductor memory device according to the present invention having any one of the above characteristics is characterized in that the upper end of the shield body is located below the upper end of the charge holding portion.

  Moreover, the nonvolatile semiconductor memory device according to the present invention having any one of the above characteristics is characterized in that the lower end of the shield body is located below the upper end of the semiconductor substrate.

  The nonvolatile semiconductor memory device according to the present invention having any one of the above characteristics is characterized in that the lower end of the shield body is located above the lower end of the diffusion region.

  The nonvolatile semiconductor memory device according to the present invention having any one of the above characteristics is characterized in that the specific resistance of the shield body is 700 μΩ · cm or less, as a seventh characteristic.

  The nonvolatile semiconductor memory device according to the present invention having any one of the above characteristics is characterized in that, in a write operation, the bit line serving as a drain of a selected memory cell selected as a write target and the drain adjacent to the drain side of the selected memory cell An eighth feature is that the shield body has the same potential.

  In order to achieve the above object, a method of manufacturing a nonvolatile semiconductor memory device according to the present invention includes forming a first insulating film as a tunnel insulating film and a charge holding film as a charge holding portion on a semiconductor substrate. Forming a second insulating film on the charge holding film; forming a resist pattern on the second insulating film; and using the resist pattern as a mask, the first insulating film, the charge holding film, and the first (2) etching the insulating film, and implanting impurity ions of a conductivity type opposite to the semiconductor substrate into the semiconductor substrate using the etched second insulating film, the charge holding film and the first insulating film as a mask Forming a sidewall-shaped third insulating film on both side walls of the charge retention film by anisotropic etching, and using the second insulating film and the third insulating film as a mask A step of digging the semiconductor substrate into a groove shape, a step of depositing a shield body made of a conductor layer or a semiconductor layer on the entire surface of the semiconductor substrate, and an upper end of the shield body at least below the upper end of the charge retention film Etching back the shield body until it is positioned above the semiconductor substrate, depositing a fourth insulating film on the entire surface of the semiconductor substrate, and the fourth until at least the upper end of the charge retention film is exposed. The first feature is that a step of planarizing the insulating film and a step of patterning the control gate and the charge holding portion are performed.

  The method for manufacturing a nonvolatile semiconductor memory device according to the present invention having the above characteristics is characterized in that the charge retention film is formed of a polysilicon film.

  The method for manufacturing a nonvolatile semiconductor memory device according to the first aspect of the present invention is characterized in that the charge retention film is formed by laminating a silicon oxide film on a silicon nitride film.

  According to the present invention, the conductor or the conductive semiconductor is formed between the charge holding portions of the memory cells adjacent in the row direction, and the upper end of the conductor or the conductive semiconductor is positioned above the upper surface of the semiconductor substrate. With this configuration, the conductor or the conductive semiconductor acts as a shield against charges injected into the charge holding unit such as hot electrons, so that the adjacent non-adjacent memory is on the same word line as the selected memory cell in the write operation. It is possible to suppress erroneous injection of charge into the charge holding portion of the selected cell. Specifically, the potential distribution of the shield body made of a conductor or a conductive semiconductor is uniform, and no electric field is generated inside. Therefore, movement due to electric field drift of electrons does not occur. That is, the electrons that have entered the shield body remain inside without penetrating the shield body. Due to this effect, the shield body acts as a shield against charges injected into the charge holding portion of the adjacent non-selected memory cell. As a result, it is possible to realize a highly reliable memory cell by suppressing fluctuations in the threshold voltage of adjacent non-selected memory cells and suppressing write disturb. In addition, it is possible to suppress the characteristic deterioration due to the write disturb accompanying the scaling of the area of the memory cell, and it is possible to realize the miniaturization of the memory cell and the improvement of the reliability toward the large capacity of the memory.

  Here, since the upper end of the shield body is located above the upper surface of the semiconductor substrate, the shield effect is effectively exerted on the charge holding portions of the adjacent non-selected memory cells formed on the semiconductor substrate. In addition, the shield body is connected to the diffusion wiring located below, the upper end of the shield body is located above the lower end of the charge holding unit, and the lower end of the shield body is located below the upper end of the semiconductor substrate. Thus, the shielding effect is further improved. In addition, when the upper end of the shield body is located below the upper end of the charge holding portion, the injection of charges into the charge holding portion of the adjacent non-selected memory cell is performed in the channel region or the diffusion region, that is, on the semiconductor substrate side. Therefore, even if the upper end position of the shield body is lowered, the shielding effect is not lowered, and unnecessary capacity for the charge holding portion can be reduced. In addition, if the specific resistance of the shield body is 700 μΩ · cm or less, the resistance is small, so that electric field drift movement does not occur and the shielding effect can be exhibited.

  Embodiments of a nonvolatile semiconductor memory device and a method for manufacturing the same according to the present invention (hereinafter, abbreviated as “the device of the present invention” and “the method of the present invention” where appropriate) will be described below with reference to the drawings.

<First Embodiment>
First, the configuration of the device of the present invention in this embodiment will be described with reference to FIG.
As shown in FIG. 1, the device according to the present invention is a memory cell having a MOSFET structure in which a charge holding portion composed of a polysilicon layer 4 is formed between a channel region 23 and a control gate 13 via a tunnel oxide film 3 and an ONO film 12. Are arranged in a row direction and a column direction, and control gates of memory cells in the same row are connected to each other to form a common word line 13, and diffusion regions forming drains or sources of the memory cells in the same column are mutually connected. A memory cell array configured as a common bit line composed of diffusion wirings 15 connected thereto is provided, and a conductor or a conductive semiconductor is interposed between the polysilicon layer 4 and the silicon nitride film 5 of the memory cells adjacent in the row direction. The shield body 9 is formed such that the upper end of the shield body 9 is above the upper surface of the semiconductor substrate 1 where the channel region 23 is formed, and the lower end is the upper surface of the semiconductor substrate 1. Ri is configured to positioned lower. In the present embodiment, the polysilicon layer 4 functions as a conductive charge holding portion (floating gate). The shield body 9 is formed of polysilicon implanted with impurities, which is a conductive semiconductor. Since the shield body made of a conductive semiconductor has resistance to deformation and characteristic fluctuation even in a high temperature process exceeding about 700 ° C., compared to a conductor such as a metal, the manufacturing process treatment is simple.

  Next, the method of the present invention in this embodiment will be described with reference to FIGS. Here, FIG.2 and FIG.3 is process sectional drawing which shows each process in the method of this invention. This will be described in detail with reference to these drawings.

First, as shown in FIG. 2A, for example, B (boron) or BF _{2 is} used as an ion species for adjusting the threshold voltage of the memory cell on the semiconductor substrate 1 of the first conductivity type (for example, P type). Ions are implanted under conditions of an implantation energy of 10 to 40 KeV and an implantation amount of 7 × 10 ^{12 to} 3 × 10 ¹³ / cm ² (arrow 2). Subsequently, as shown in FIG. 2B, a tunnel oxide film 3 (first insulating film) is formed to a thickness of about 8 to 12 nm by thermal oxidation, and then a high concentration impurity is formed by CVD. A polysilicon layer 4 to which is added is deposited so as to have a film thickness of about 30 to 200 nm, and a silicon nitride film 5 (second insulating film) is sequentially stacked so as to have a film thickness of about 30 to 300 nm.

  Subsequently, as shown in FIG. 2C, the resist pattern 6 is patterned using a lithography technique, and the silicon nitride film 5, the polysilicon layer 4, and the tunnel oxide film 3 are selectively etched using the resist pattern 6 as a mask. Then, the resist pattern 6 is peeled off.

Subsequently, as shown in FIG. 2 (d), for example, phosphorus or arsenic is ion-implanted under an implantation condition of an implantation energy of 5 to 40 KeV and an implantation amount of 1 × 10 ¹⁴ to 1 × 10 ¹⁶ / cm ^2. Do (arrow 7). As a result, as shown in FIG. 2E, an impurity diffusion region 15 ′ having a conductivity type (for example, N type) different from that of the semiconductor substrate is formed. Further, a silicon oxide film is deposited by CVD to have a film thickness of about 10 to 100 nm, and then the silicon oxide film is anisotropically etched to form sidewalls 8 (third insulating film).

Subsequently, as shown in FIG. 2 (f), the semiconductor substrate 1 (impurity diffusion region 15 ′) is removed by etching using the silicon nitride film 5 and the sidewall 8 as a mask to form a groove 21. More specifically, the groove 21 is formed such that the lower end of the polysilicon layer 9 (shield body) filled in the groove 21 is located below the upper end of the semiconductor substrate and above the lower end of the diffusion region. To do. Subsequently, as shown in FIG. 2 (g), it is deposited by CVD to 1 × ¹⁰ 20 / cm ³ or more polysilicon layer 9 a high concentration impurity is added to a film thickness of about 10 to 500 nm. Since the trench 21 is formed by removing the diffusion region 15 ′ by etching, the polysilicon layer 9 deposited in the trench 21 is connected to the diffusion wiring 15 located below. The specific resistance of the polysilicon layer 9 is 700 μΩ · cm or less. Here, the polysilicon layer 9 is not limited to the polysilicon layer 9 to which high-concentration impurities are added. Instead, a conductive metal layer (Al, Cu, Ti, Co, W, etc.) or a silicide layer Etc. may be deposited.

  Subsequently, as shown in FIG. 2H, the polysilicon layer 9 is etched back so that the upper end of the polysilicon layer 9 is positioned about α = 0 to 100 nm below the upper end of the polysilicon layer 4. More specifically, α is set so that the upper end of the polysilicon layer 9 is located above the lower end of the polysilicon layer 4 and below the upper end of the polysilicon layer 4.

  Subsequently, as shown in FIG. 2I, an HDP (High Density Plasma) silicon oxide film 11 (fourth insulating film) is deposited so as to have a thickness of about 300 to 500 nm, and thereafter, FIG. As shown, the HDP silicon oxide film 11 is etched back until the surface of the silicon nitride film 5 appears. Here, the silicon nitride film 5 may be planarized using a CMP (Chemical Mechanical Polishing) method using the etch back stopper.

  Subsequently, as shown in FIG. 3K, the silicon nitride film 5 is removed. Subsequently, as shown in FIG. 3L, planarization is performed using the CMP method until the surface of the polysilicon layer 4 appears. Subsequently, as shown in FIG. 3 (m), an ONO film 12 (Oxide−) composed of a silicon oxide film (film thickness 4-5 nm), a silicon nitride film (5-10 nm), and a silicon oxide film (5-10 nm). (Nitride-Oxide film), and then, as shown in FIG. 3 (n), a polysilicon layer 13 is deposited to a thickness of about 20 to 50 nm, and a tungsten silicide layer 14 is formed to a thickness of Deposition is performed so as to have a thickness of about 20 to 50 nm.

Subsequently, although not shown, after patterning the resist pattern using a lithography technique, the tungsten silicide layer 14, the polysilicon layer 13, the ONO film 12, and the polysilicon layer 4 are selectively etched away using the resist pattern as a mask. Thus, a floating gate (charge holding portion) and a control gate are formed. Subsequently, for example, ions of B or BF ₂ are implanted under the conditions of ¹⁵ to 30 keV and 5 × 10 ¹² to 1 × 10 ¹⁴ / cm ² , and element isolation impurities are formed between the control gates and the bit lines. A diffusion layer is formed. Subsequently, annealing is performed at a temperature of 800 ° C. for 30 minutes in order to recover the crystal of the implanted region into which ions have been implanted and to activate the implanted impurities. Subsequently, a BPSG (Boron Phosphorus Silicate Glass) protective film is deposited to a thickness of about 100 nm to 1000 nm. Thereafter, contact holes, aluminum electrodes, and the like are formed according to a normal process to complete the device of the present invention.

Second Embodiment
A second embodiment of the method of the present invention will be described with reference to FIGS. As shown in FIG. 4, the device of the present invention of the present embodiment basically includes a memory cell array having the same structure as that of the first embodiment. The difference from the first embodiment is that the charge holding portion is composed of the silicon nitride film 5 and the silicon oxide film 22 formed thereon. The silicon nitride film 5 has a substantial function of the charge holding portion.

  Next, the method of the present invention in this embodiment will be described with reference to FIG. Here, FIGS. 5A to 5K are process cross-sectional views showing each process in the method of the present invention. This will be described in detail with reference to these drawings.

First, as shown in FIG. 5A, for example, B or BF ₂ is implanted into the first conductivity type (for example, P type) semiconductor substrate 1 as an ion species for adjusting the threshold voltage of the memory cell. Then, ion implantation is performed under an implantation condition of an implantation amount of 7 × 10 ^{12 to} 3 × 10 ¹³ cm ² (arrow 2). Subsequently, as shown in FIG. 5B, a tunnel oxide film 3 (first insulating film) is formed to a thickness of about 6 to 12 nm by thermal oxidation, and then the silicon nitride film 5 is formed by CVD. The silicon oxide film 22 (second insulating film) is sequentially stacked so that the film thickness becomes about 6 to 100 nm.

Subsequently, as shown in FIG. 5C, the resist pattern 6 is patterned using a lithography technique, and the silicon oxide film layer 22, the silicon nitride film 5 and the tunnel oxide film 3 are selectively removed by etching. The pattern 6 is peeled off. Subsequently, as shown in FIG. 5D, for example, phosphorus, arsenic, or the like is ion-implanted as ion species under an implantation condition of an implantation energy of 5 to 40 KeV and an implantation amount of 1 × 10 ¹⁴ to 1 × 10 ¹⁶ cm ^2. (Arrow 7). As a result, as shown in FIG. 5E, an impurity diffusion region 15 ′ having a conductivity type (for example, N type) different from that of the semiconductor substrate is formed. Further, a silicon oxide film is deposited by CVD to have a film thickness of about 10 to 100 nm, and then the silicon oxide film is anisotropically etched to form sidewalls 8 (third insulating film).

Subsequently, as shown in FIG. 5F, the semiconductor substrate 1 is removed by etching using the silicon oxide film 22 and the sidewalls 8 as a mask to form a groove 21. More specifically, the groove 21 is formed such that the lower end of the polysilicon layer 9 (shield body) filled in the groove 21 is located below the upper end of the semiconductor substrate and above the lower end of the diffusion region. To do. Subsequently, as shown in FIG. 5 (g), it is deposited by CVD to 1 × ¹⁰ 20 / cm ³ or more polysilicon layer 9 a high concentration impurity is added to a film thickness of about 10 to 500 nm. Here, a metal layer or a silicide layer of a conductor may be deposited instead of the polysilicon layer 9 to which a high concentration impurity is added.

  Subsequently, as shown in FIG. 5H, the polysilicon layer 9 is etched back so that the upper end of the polysilicon layer 9 is positioned about α = 0 to 100 nm below the upper portion of the silicon oxide film 22. . More specifically, α is set so that the upper end of the polysilicon layer 9 is located above the lower end of the polysilicon layer 4 and below the upper end of the polysilicon layer 4.

  Subsequently, as shown in FIG. 5 (i), the HDP silicon oxide film 11 (fourth insulating film) is deposited so as to have a film thickness of about 300 to 500 nm. Further, as shown in FIG. The HDP silicon oxide film 11 is etched back until the surface of the silicon oxide film 22 appears. Here, the HDP silicon oxide film 11 may be planarized using a CMP method. Thereafter, as shown in FIG. 5 (k), a polysilicon layer 13 is deposited so as to have a film thickness of about 20 to 50 nm, and a tungsten silicide layer 14 is formed on the polysilicon layer 13 with a film thickness of 20 to 50 nm. Deposit to a degree. Further, although not shown, after the resist pattern is patterned using a lithography technique, the tungsten silicide layer 14 and the polysilicon layer 9 are selectively removed by etching using the resist pattern as a mask, thereby controlling the charge holding portion. Form a gate. Subsequently, annealing is performed at a temperature of 800 ° C. for 30 minutes for crystal recovery of the implanted region and activation of implanted impurities. Next, a BPSG protective film is deposited to a thickness of about 100 nm to 1000 nm. Thereafter, contact holes, aluminum electrodes, and the like are formed according to a normal process to complete the device of the present invention.

Structure sectional view showing the structure in the first embodiment of the nonvolatile semiconductor memory device according to the present invention Process sectional drawing which shows each process in 1st Embodiment of the manufacturing method of the non-volatile semiconductor memory device concerning this invention Process sectional drawing which shows each process in 1st Embodiment of the manufacturing method of the non-volatile semiconductor memory device concerning this invention Structural sectional drawing which shows the structure in 2nd Embodiment of the non-volatile semiconductor memory device based on this invention Process sectional drawing which shows each process in 2nd Embodiment of the manufacturing method of the non-volatile semiconductor memory device based on this invention Sectional drawing of the non-volatile semiconductor memory device which concerns on a prior art Plan view of nonvolatile semiconductor memory device according to prior art A graph showing the relationship between the amount of increase in threshold voltage and the width between floating gates in adjacent non-selected memory cells Table showing voltage conditions in each operation of the nonvolatile semiconductor memory device according to the prior art

Explanation of symbols

1: Semiconductor substrate 2: Ion implantation 3: Tunnel oxide film (first insulating film)
4: Polysilicon layer (charge holding portion)
5: Silicon nitride film (charge holding portion)
6: Resist pattern 7: Ion implantation 8: Side wall spacer (silicon oxide film, third insulating film)
9: Polysilicon layer (shield body)
10: Side wall spacer (high concentration polysilicon)
11: HDP silicon oxide film (fourth insulating film)
12: ONO (Oxide-Nitride-Oxide) film 13: Polysilicon layer 14: Tungsten silicide 15: Impurity diffusion region (source / drain)
15 ': Impurity diffusion region 16: Floating gate 17: Control gate (word line)
18: element isolation region 19: selected memory cell 20: adjacent non-selected memory cell 21: groove 22: silicon oxide film (second insulating film)
23: Channel region

Claims (11)

A plurality of non-volatile memory cells of MOSFET structure each having a charge holding portion capable of accumulating charges formed on a semiconductor substrate via an insulating film are arranged in a row direction and a column direction, respectively. A common word line extending in the row direction by connecting the control gates to each other, and a diffusion region forming the drain or source of the memory cell in the same column is connected to each other and extended in the column direction composed of the diffusion wiring A nonvolatile semiconductor memory device comprising a memory cell array configured as a bit line of
A shield body made of a conductor or a conductive semiconductor is formed between the charge holding portions of the memory cells adjacent in the row direction, and the upper end of the shield body is positioned above the upper surface of the semiconductor substrate. A non-volatile semiconductor memory device.   The nonvolatile semiconductor memory device according to claim 1, wherein the shield body is connected to the diffusion wiring located below.   The nonvolatile semiconductor memory device according to claim 1, wherein an upper end of the shield body is located above a lower end of the charge holding unit.   4. The nonvolatile semiconductor memory device according to claim 1, wherein an upper end of the shield body is positioned below an upper end of the charge holding unit.   The nonvolatile semiconductor memory device according to claim 1, wherein a lower end of the shield body is positioned below an upper end of the semiconductor substrate.   The nonvolatile semiconductor memory device according to claim 1, wherein a lower end of the shield body is located above a lower end of the diffusion region.   The nonvolatile semiconductor memory device according to claim 1, wherein a specific resistance of the shield body is 700 μΩ · cm or less.   2. The write circuit according to claim 1, wherein the bit line serving as a drain of a selected memory cell selected as a write target and the shield body adjacent to the drain side of the selected memory cell have the same potential during a write operation. The nonvolatile semiconductor memory device according to any one of? Forming a first insulating film as a tunnel insulating film and a charge holding film serving as a charge holding portion on a semiconductor substrate;
Forming a second insulating film on the charge retention film;
Forming a resist pattern on the second insulating film, and etching the first insulating film, the charge retention film, and the second insulating film using the resist pattern as a mask;
Implanting impurity ions of a conductivity type opposite to the semiconductor substrate into the semiconductor substrate using the etched second insulating film, the charge holding film and the first insulating film as a mask;
Forming a sidewall-shaped third insulating film on both side walls of the charge retention film by anisotropic etching;
Digging the semiconductor substrate into a groove shape using the second insulating film and the third insulating film as a mask;
Depositing a shield layer comprising a conductor layer or a semiconductor layer on the entire surface of the semiconductor substrate;
Etching back the shield body until the upper end of the shield body is positioned at least below the upper end of the charge retention film and above the semiconductor substrate;
Depositing a fourth insulating film on the entire surface of the semiconductor substrate;
Planarizing the fourth insulating film until at least the upper end of the charge retention film is exposed;
And a step of patterning the control gate and the charge holding portion. A method for manufacturing a nonvolatile semiconductor memory device, comprising:   The method of manufacturing a nonvolatile semiconductor memory device according to claim 9, wherein the charge retention film is formed of a polysilicon film.   10. The method for manufacturing a nonvolatile semiconductor memory device according to claim 9, wherein the charge retention film is formed by laminating a silicon oxide film on a silicon nitride film.