JP2007110845A - Switched mode power supply and semiconductor integrated circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a switched mode power supply capable of improving efficiency and obtaining new functions. <P>SOLUTION: In this switched mode power supply, a capacitor is provided between the output side of an inductor generating an output voltage and ground potential. A first switching element supplies a current from an input voltage to the input side of the inductor and a second element which is brought into an on-state when the first switching element is brought into an off-state, controls the input side of the inductor to its predetermined electric potential. When a control circuit is determined to be a light load by a load current detection circuit, the control circuit lengthens a dead time from a time when either of the first and the second switching element is changed to the off-state to a time when the other is changed to the on-state. On the other hand, when determined to be a heavy load, the dead time is shortened. Further, when the control circuit is determined to be the light load and an output voltage is low, the second switching element is changed to the off-state. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a switching power supply and a semiconductor integrated circuit device. For example, the present invention relates to a switching power supply that converts a high voltage to a low voltage and a technology that is effective when applied to a semiconductor integrated circuit device used therefor.

  Switching power supplies require low price, small size, high efficiency, low voltage, and large current. Therefore, an inexpensive, low on-resistance (low Ron) and low Qgd (low gate charge charge) N-channel power MOSFET (hereinafter abbreviated as NMOS) is often used as the switch element. FIG. 12 shows a block diagram of a step-down switching power supply studied prior to the present invention. In the switching power supply shown in the figure, a current is supplied to the input side of the inductor LO through a high potential side switch MOSFET M1 that is switch-controlled by a PWM signal, and a capacitor CO is provided between the output side of the inductor LO and the ground potential of the circuit. The output voltage Vout is obtained. A low potential side switch MOSFET M2 is provided between the inductor LO and the ground potential. This MOSFET M2 clamps the input side of the inductor LO when the MOSFET M1 is turned off to the ground potential of the circuit.

  In order to use an N-channel MOSFET for the high-potential side switch MOSFET M1, a booster circuit including a bootstrap capacitor CB and a diode D and a level shift circuit LS are provided. In the booster circuit, a level shift circuit LS that forms a voltage (VDD-Vf) higher than the source potential of the MOSFET M1 by a voltage (VDD−Vf) lower than the power supply voltage VCC by the forward voltage Vf of the diode D, and uses this as an operating voltage. As a result, the gate voltage GH of the high potential side switch MOSFET M1 is formed. As a result, a voltage larger than the threshold voltage is supplied between the gate and the source of the MOSFET M1, such as VDD−Vf, and a voltage corresponding to the input voltage Vin can be output from the source.

  Delay circuits DL1 and DL2 generate signal delay times td1 and td2 only when the input signal rises from a low level to a high level. Therefore, as shown in the timing chart of FIG. 13, when the high potential side switch MOSFET M1 is turned on by the high level of the PWM signal, the low potential side switch MOSFET M2 is turned off by the low level of the / PWM signal, and the delay circuit DL1 After the signal delay time td1, the high potential side switch MOSFET M1 is turned on. When the high potential side switch MOSFET M1 is turned off by the low level of the PWM signal, the high potential side switch MOSFET M1 is turned off by the low level of the PWM signal, and the low potential side switch MOSFET M2 is turned on after the signal delay time td2 in the delay circuit DL2. Turn it on. In this way, a dead time during which the MOSFETs M2 and M1 are both turned off is provided corresponding to the signal delay times td1 and td2.

Examples of the transformer type synchronous rectification converter include Japanese Patent Laid-Open Nos. 2000-358365 and 2001-286135.
JP 2000-358365 A JP2001-286135

  The inventor of the present application has found that the setting of the dead time greatly affects the efficiency in the switching power supply as shown in FIG. That is, if the dead time is shortened, the efficiency is improved at a heavy load with a large load current, and the efficiency at a light load with a small load current is deteriorated. On the contrary, if the dead time is lengthened, the efficiency is poor at a heavy load with a large load current, and the efficiency at a light load with a small load current is improved. Therefore, the present inventor considered changing the dead time in accordance with the load current. In addition, we considered adding a new function using the light load detection function to the switching power supply.

  An object of the present invention is to provide a switching power supply and a semiconductor integrated circuit device that achieves improved efficiency and new functions. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The outline of a typical invention among the inventions disclosed in the present application will be briefly described as follows. That is, a capacitor is provided between the output side of the inductor where the output voltage is formed and the ground potential. A current is supplied from the input voltage to the input side of the inductor by the first switch element, and the input side of the inductor is predetermined by the second switch element having a time for turning on when the first switch element is off. Set to potential. By the control circuit, when the load current detection circuit determines that the load is light, the dead time from when one of the first or second switch elements is turned off to when the other is turned on is lengthened. When it is determined that the load is heavy, the dead time is shortened.

  Loss in the first and second switch elements is reduced, and high efficiency can be achieved. Parallel operation can be realized.

  FIG. 1 shows a schematic circuit diagram of an embodiment of a switching power supply according to the present invention. This embodiment is directed to a so-called step-down switching power supply that forms an output voltage Vout obtained by stepping down an input voltage Vin. Although not particularly limited, the input voltage Vin is a relatively high voltage such as about 12V, and the output voltage Vout is a low voltage of about 3V.

  The input voltage Vin is supplied with current from the input side of the inductor LO via the high potential side switch MOSFET M1. A capacitor CO is provided between the output side of the inductor LO and the ground potential VSS of the circuit, and an output voltage Vout smoothed by the capacitor CO is formed. A switch MOSFET M2 is provided between the input side of the inductor LO and the circuit ground potential VSS. The MOSFET M2 is in an on state when the switch MOSFET M1 is in an off state, and clamps a counter electromotive voltage generated in the inductor LO with the midpoint LX as a ground potential of the circuit. The switch MOSFETs M2 and M1 are N-channel power MOSFETs. As described above, the connection point of the switch MOSFETs M2 and M1 is the midpoint LX of the so-called inverted push-pull output circuit, and is connected to the input side of the inductor LO.

  A PWM signal is input so as to control the output voltage Vout to a set voltage such as about 3V. On the one hand, this PWM signal is supplied to one input of the switch SW1 through the delay circuit DL1. On the other hand, this PWM signal is supplied to one input a of the OR gate circuit G1 through the delay circuit DL3. The output signal of the voltage comparison circuit VC1 is supplied to the other input of the OR gate circuit G1. The voltage comparison circuit VC1 monitors the potential at the midpoint LX and forms a comparison output signal with the reference voltage Vref1. The output signal of the OR gate circuit G1 is supplied to the other input b of the switch SW1. The signal selected by the switch SW1 is used as a switch control signal for the high potential side switch MOSFET M1.

  The PWM signal is inverted by the inverter circuit NV1, and is supplied to one input a of the switch SW2 through the delay circuit DL2. The inverted signal of the PWM signal is supplied to one input of the AND gate circuit G2. The output signal of the voltage comparison circuit VC2 is supplied to the other input of the AND gate circuit G2. The voltage comparison circuit VC2 monitors the potential at the midpoint LX and forms a comparison output signal with the reference voltage Vref2. The output signal of the AND gate circuit G2 is supplied to the other input b of the switch SW2. The signal selected by the switch SW2 is used as a switch control signal for the low potential side switch MOSFET M2.

  As the switching power supply, a level shift is performed such that the control signal for forming the PWM signal and the drive signal supplied to the gate of the high-potential side switch MOSFET M1 are higher than the input voltage Vin by the threshold voltage of the switch MOSFET M1. Although a circuit is provided, it is omitted in the figure.

  In this embodiment, a load current detection circuit is provided to determine whether the load is light or heavy and to perform switch control of the switches SW1 and SW2. For example, if it is determined that the load is light, the switches SW1 and SW2 select the input b side. If it is determined that the load is heavy, the switches SW1 and SW2 are switched to select the input a.

  The delay circuit DL1 is configured to have a short delay time so as to set a minimum dead time suitable for heavy loads. The delay circuit DL2 is set to have a short delay time so as to set a minimum dead time suitable for heavy loads, and turns on the low-voltage side MOSFET M2. The delay circuit DL3 is configured to have a long delay time adapted to light load.

  The voltage comparison circuits VC1 and VC2 detect that the voltage between the source and drain of the switch MOSFETs M1 and M2 is smaller than that of the body diode, respectively, and turn on the corresponding switch MOSFETs M1 and M2. Form a control signal. That is, at the time of a light load as will be described later, since the potential change at the midpoint LX is slow, the switch MOSFETs M1 and M2 are turned on after the potential of the midpoint potential LX reaches the potential as described above to increase efficiency. It is intended to plan.

  FIG. 2 shows a circuit diagram of an embodiment of the switching power supply according to the present invention. This embodiment is a more detailed circuit diagram of FIG. 1 and specifically shows specific configurations of the booster circuit, the control circuit, and the load current detection circuit. The control circuit of this embodiment is formed by the following circuit. As an example, the output voltage Vout is divided by a voltage dividing circuit composed of resistors R1 and R2, and supplied to one input (−) of the error amplifier EA. A reference voltage Vref4 is supplied to the other input (+) of the error amplifier EA. A difference voltage between the divided voltage and the reference voltage Vref4 is supplied to one input (+) of the voltage comparison circuit VC4. The other input (−) of the voltage comparison circuit VC4 is supplied with a triangular wave formed by a triangular wave generating circuit. The output signal of the voltage comparison circuit VC4 is a PWM signal. Even if it is not a PWM signal, a PFM (Pulse Amplitude Modulation) signal, a PDM (Pulse Density Modulation) signal or the like can be used as long as it controls the switching of the power MOSFET so that the output voltage Vout becomes a desired voltage. Not limited.

  Although not particularly limited, the ramp waveform from the soft start circuit SS is also input to the voltage comparison circuit VC4. The soft start circuit SS includes, for example, a constant current source and a capacitor charged up by the constant current source. When the power supply voltage VCC is turned on, the soft start circuit SS forms a ramp waveform with the capacitor charged up by the constant current, and controls the output voltage Vout to reach a desired voltage accordingly.

  In this embodiment, an N-channel power MOSFET having a low on-resistance and low Qgd is used as the switch element M1 and is operated as a source follower output circuit. Therefore, in order to obtain the potential at the midpoint LX up to a high voltage corresponding to the input voltage Vin, in other words, the potential at the midpoint LX is lowered by the threshold voltage of the MOSFET M1 to cause a loss. In order to prevent this, a booster circuit is provided. That is, the booster circuit performs an operation of setting the gate voltage when the MOSFET M1 is in an on state to a high voltage equal to or higher than the threshold voltage with respect to the input voltage Vin.

  The midpoint LX is connected to one end of the bootstrap capacitor CB. A power supply voltage VCC is supplied to the other end of the bootstrap capacitor CB through a diode D. The power supply voltage VCC is a low voltage such as about 5V, and is used as an operating voltage of the low voltage side circuit of the error amplifier EA, the voltage comparison circuit VC4, the triangular wave generation circuit, and the level shift circuit LS, which will be described later. Is also used. The bootstrap capacitor CB is precharged through the die auto D when the switch MOSFET M2 is on and the midpoint LX is the circuit ground potential. When the MOSFET M2 is turned off and the MOSFET M1 is turned on, a boosted voltage that is higher by the precharge voltage of the bootstrap capacitor CB is formed as the midpoint LX rises due to the MOSFET M1 being turned on. The level shift circuit LS operates at the boosted voltage to increase the gate voltage of the MOSFET M1 by the precharge voltage of the bootstrap capacitor CB with respect to the midpoint LX (source potential), and to reduce the level of the input voltage Vin. Can be transmitted to the input side of the inductor LO.

  The load current detection circuit includes the following circuits. The drive signal supplied to the gate of the MOSFET M2 is inverted through the inverter circuit NV2 and supplied to one input of the OR gate circuit G4. A signal obtained by delaying the drive signal supplied to the gate of the MOSFET M2 by the delay circuit DL4 is supplied to the other input of the OR gate circuit G4. The output signal of the OR gate circuit G4 is supplied to the reset input R of the flip-flop circuit FF. The voltage at the midpoint LX is supplied to the input (+) of the voltage comparison circuit VC3. The reference voltage Vref3 is supplied to the other input (−) of the voltage comparison circuit VC3. The output signal of the voltage comparison circuit VC3 is supplied to one input of the AND gate circuit G3. The delay signal of the delay circuit DL4 is supplied to the other input of the AND gate circuit G3. The output signal of the AND gate circuit G3 is supplied to the set input S of the flip-flop circuit FF. The output signal Q of the flip-flop circuit FF is used as a control signal for the switches SW1 and SW2.

  The load current detection circuit is determined as a light load when the gate voltage of the MOSFET M2 is at a high level and is on, and is higher than the voltage Vref3 at the midpoint LX. The delay circuit DL4 masks noise generated at the midpoint LX when the MOSFET M1 is turned off and the MOSFET M2 is turned on. If the output signal of the voltage comparison circuit VC3 becomes high level when the MOSFET M2 is in the on state except for the noise generation period, it is determined that the load is light and the flip-flop circuit FF is set. Otherwise, the flip-flop circuit FF is reset by the delay signal of the delay circuit DL4. Therefore, when the flip-flop circuit FF is in the set state, that is, when it is determined that the load is light, the output signal Q is set to the high level. Further, when the flip-flop circuit FF is in the reset state, that is, when it is determined that the load is heavy, the output signal Q is set to the low level.

  When the output signal Q of the flip-flop circuit FF is at a low level, the switch SW1 and the switch SW2 each select the input a side, so that a dead time due to a short delay time corresponding to a heavy load is set. When the output signal Q of the flip-flop circuit FF is at a high level, the switch SW1 and the switch SW2 select the input b side, so that a dead time due to a long delay time corresponding to a light load is set.

  At the time of the light load, the dead time is set by the monitor output that the drain-source voltages of the switch MOSFETs M1 and M2 are lower than the forward voltages of the body diodes. For example, in the high potential side MOSFET M1, the dead time is set so that the MOSFET M1 is turned on when the voltage at the midpoint LX becomes larger than the reference voltage Vref1. In the low voltage side MOSFET M2, the dead time is set so that the MOSFET M2 is turned on when the potential at the midpoint LX becomes lower than the reference voltage Vref2. As will be described later, since the current flowing through the inductor LO at a light load is small and the midpoint LX may not reach the reference voltage Vref1, the maximum delay time is set by the delay circuit DL3, and the OR gate circuit G1 Therefore, the on-timing of the high potential side MOSFET M1 is set by the delay time td3 of the delay circuit DL3.

  From the next cycle after the switching of the switches SW1 and SW2 by the flip-flop circuit FF, the operation is performed with a dead time corresponding to the light load or heavy load. The period of the PWM signal is not particularly limited, but is set to a high frequency such as 1 MHz. On the other hand, the load current change is extremely slow when viewed from the high frequency as described above. Therefore, the determination of the load current and the setting of the dead time as described above are shifted by one cycle of the PWM signal. But it doesn't really matter.

  3, 4 and 5 are waveform diagrams for explaining the operation of the switching power supply according to the present invention. FIG. 3 shows an example of a waveform diagram at light load, FIG. 4 shows an example of a waveform diagram at heavy load, and FIG. 5 shows another example of a waveform diagram at light load. . In these figures, the drive waveforms GL and GH of the switch MOSFETs M2 and M1 are shown by shifting 0 V in the same manner as in FIG. 13 in order to facilitate understanding of the mutual relationship.

  In FIG. 3, light load detection is performed when the potential at the midpoint LX becomes greater than the reference voltage Vref3 during light load. In this way, the light load / heavy load determination is performed based on whether or not the voltage at the midpoint LX is higher than Vref3 when the MOSFET M2 is in the ON state due to the high level of the drive waveform GL.

  The reference voltage Vref3 is a voltage corresponding to the ground potential 0V of the circuit, and 0V cannot be detected when the voltage comparison circuit VC3 is operated with a power supply voltage such as the power supply voltage VCC. The voltage level-shifted to the reference voltage Vref3 corresponding to the operation range is detected. A level shift means is provided at the input (+) of the voltage comparison circuit VC3. The same applies to the voltage comparison circuits VC1 and VC2. That is, in the voltage comparison circuit VC1, the voltage at the midpoint LX is lowered. In the voltage comparison circuit VC2, the voltage at the midpoint LX is raised as in the voltage comparison circuit VC3. However, if the voltage comparison circuits VC2 and VC3 are operated with a high voltage and a negative voltage, the level shift is not necessary. If the voltage comparison circuit VC1 is also operated with a boosted voltage, the level shift becomes unnecessary.

  As shown in the waveform diagram of FIG. 4, when the high voltage side MOSFET M1 is in the OFF state, a load current is formed by the voltage generated by the counter electromotive force of the inductor LO. Since a large load current IL is supplied by the MOSFET M1 at the time of heavy load, a counter electromotive force is generated so that the same large current IL is maintained in the inductor LO when it is turned off. Therefore, the potential at the midpoint LX is always negative with respect to the ground potential of 0 V by the voltage drop at the body diode of the low potential side MOSFET M2 or the on-resistance of the MOSFET M2. However, when the load is light, the current IL consumed on the load side is small and the back electromotive force is small. Therefore, a reverse current flows from the load side through the inductor LO to the middle point LX side to make the midpoint potential LX positive. In the light load detection of FIG. 3, the above state is detected. The delay time td4 in the delay circuit DL4 is for eliminating the influence of ringing that occurs when the high-potential side MOSFET M1 is turned off and the MOSFET M2 is turned on.

  By the light load detection of FIG. 3, the output signal FF-Q of the flip-flop circuit FF changes to high level, and the switches SW1 and SW2 are switched to the b side. Therefore, the dead time of the next cycle is switched to a dead time at a light load as described in FIG. FIG. 5 shows a waveform diagram at a light load. When the load is light, parasitic capacitances such as the sources and drains of the MOSFETs M2 and M1 existing at the midpoint LX exist. Therefore, when the high potential side MOSFET M2 is in the ON state, the parasitic capacitance is charged with a high voltage corresponding to the input voltage Vin. Even when the high potential side MOSFET M1 is turned off, the load current is supplied by the charge from the parasitic capacitance, and the potential at the midpoint LX decreases corresponding to the magnitude of the load current IL. That is, when the load current I is small, the fall thereof is delayed.

  In this embodiment, when the potential at the midpoint LX is lower than the reference voltage Vref2, the low potential side MOSFET M2 is turned on. The reference voltage Vref2 is set to a voltage smaller than the voltage between the source and drain of the low potential side MOSFET M2. By delaying the on-timing of the MOSFET M2 in this way, the supply of the load current IL can be continued by effectively using the charge from the parasitic capacitance, so that high efficiency can be achieved. That is, if the MOSFET M2 is turned on when the midpoint LX is sufficiently high, the power for discharging the parasitic capacitance is consumed by the MOSFET M2, so that the efficiency is deteriorated.

  At the time of heavy load, the charge of the parasitic capacitance is immediately discharged by the large load current IL at the time of heavy load, and the input side (LX) of the inductor LO is voltage clamped by the body diode of the low potential side MOSFET M2. Therefore, if the dead time is lengthened at the time of heavy load, a large voltage loss due to the body diode occurs during that time, resulting in poor efficiency. In this embodiment, the dead time dt2 is set small as shown in FIG. 4, and the large power loss time in the body diode as described above is minimized. That is, the MOSFET M2 is turned on as quickly as possible, and the clamp voltage on the input side (LX) of the inductor LO is reduced by a small on-resistance between the drain and the source, thereby improving the efficiency.

  The dead time until the low-potential side MOSFET M2 is turned off and the high-potential side MOSFET M1 is turned on is also clamped by the body diode of the MOSFET M2, so the dead time td1 is set to be as short as above and is as fast as possible. The MOSFET M2 is turned on at timing. Thus, at the time of heavy load, high efficiency can be realized by setting the voltage clamping time by the body diode in the MOSFET M2 to the minimum necessary.

  The timing for turning on the low potential side MOSFET M2 at the time of light load is controlled to be different as in the discharge time dead time t1, t2 of the parasitic capacitance according to the magnitude of the load current IL as shown in FIG. High efficiency can be achieved by maximally effectively using the charge of the parasitic capacitance. In other words, if the MOSFET M2 is turned on when the potential at the midpoint LX becomes equal to or lower than the voltage between the source and drain of the low potential side MOSFET M2, the charge of the parasitic capacitance is effectively utilized, and the switching loss in the MOSFET M2 is reduced. It can be virtually eliminated.

  The timing of turning on the high potential side MOSFET M1 at the time of light load is also performed by the output of the voltage comparison circuit VC1 using the reference voltage Vref1 to charge up the parasitic capacitance due to the backflow current from the load side. Thereby, the switching loss in MOSFET M1 can be substantially eliminated. As shown in FIG. 5, the rise of the midpoint LX changes depending on the magnitude of the load current IL, and the reference voltage Vref1 may not be reached when the load current IL is small. Therefore, the MOSFET M1 is caused by the delay time td3 of the delay circuit DL3. The ON timing of is controlled. The MOSFET M1 is turned on by using the reverse current from the output-side capacitor CO via the inductor LO, that is, by entrusting charge-up to the parasitic capacitance, thereby realizing high efficiency. be able to. In this way, the efficiency of the switching power supply can be realized by appropriately controlling the dead time corresponding to the load current.

  The switching loss in the MOSFETs M1 and M2 that charge and discharge the parasitic capacitance at the midpoint LX is not negligible as compared with the overall loss, and if the switching frequency is as high as 1 MHz, it occupies a large proportion. Similarly, wasteful power consumed by the body diode in the MOSFET M2 cannot be ignored even if the period is short if the switching frequency is as high as 1 MHz. The idea of switching the dead time corresponding to the load current as in this embodiment is extremely useful in a synchronous rectification type DC-DC converter that is switched at a high frequency.

  FIG. 6 shows a circuit diagram of another embodiment of the switching power supply according to the present invention. In this embodiment, a new function suitable for parallel operation of switching power supplies is added using the detection signal of the load current detection circuit. A voltage comparison circuit VC5 is newly provided. This voltage comparison circuit VC5 compares the voltage obtained by dividing the reference voltage Vref4 by the resistors R3 and R4 with the output voltage Vout divided by the resistors R1 and R2. The voltage comparison circuit VC4 outputs a low level (logic 0) when the divided voltage of the output voltage Vout is smaller than the divided reference voltage. This output signal and the output signal of the load current detection circuit are input to an AND gate circuit G5. The output signal of the AND gate circuit G5 is inverted by the inverter circuit NV3 and transmitted to the AND gate circuit G6. The drive signal transmitted through the switch SW2 is transmitted to the gate of the MOSFET M2 through the AND gate circuit G6.

  The output signal of the voltage comparison circuit VC1 is supplied to the AND gate circuit G8 together with the PWM signal. The output signal of the AND gate circuit G8 is supplied to the other input of the OR gate circuit G1. A control terminal EN for controlling the operation of the switching power supply is provided, and an operation control signal that passes through the control terminal EN is input to the AND gate circuit G7 and the AND gate circuit G6. The AND gate circuit G7 performs an operation of selectively transmitting the drive signal passed through the level shift circuit LS to the gate of the MOSFET M1. In other words, the MOSFET M1 is forcibly turned off by the control terminal EN to stop the operation. The AND gate circuit G6 also forcibly turns off the MOSFET M2 by the control terminal EN to stop the operation.

  FIG. 7 is a waveform diagram for explaining an example of the operation of the switching power supply of FIG. In FIG. 7, light load detection is performed when the potential at the midpoint LX becomes larger than the reference voltage Vref3 during light load as in FIG. If this light load detection signal is formed, the output voltage Vout has not reached the desired voltage, and the output signal of the voltage comparison circuit VC5 is at the high level, the output signal of the AND gate circuit G5 is set to the high level, and the inverter The input of the AND gate circuit G6 is set to low level through the circuit NV3. As a result, the MOSFET M2 is turned off. This is based on the premise that the control terminal EN is at a high level and the switching power supply is in an operating state.

  One of the new functions provided in the switching power supply of this embodiment is to turn off the MOSFET M2 if the output voltage Vout has not reached the desired voltage and it is determined that the load is light. This is indispensable for the parallel operation of the switching power supply described later. When the MOSFET M2 is turned off at the timing determined as the light load state in this way, the current flowing through the MOSFET M2 is cut off, the midpoint LX enters the floating state, and ringing due to the counter electromotive voltage of the inductor LO occurs. . When this voltage is close to the input voltage Vin as indicated by the dotted line and, more precisely, becomes higher than the reference voltage Vref1, the voltage comparison circuit VC1 generates a high-level detection signal and turns on the MOSFET M1. A drive signal is formed.

  In order to prevent such a malfunction, the AND gate circuit G8 is provided. Since the AND gate circuit G8 opens the gate when the PWM signal is at a high level, even if the voltage comparison circuit VC1 sets the drive signal to a high level in response to the noise as described above, the transmission is prohibited. Operate. Further, as shown in the operation waveform diagram of FIG. 8, when the MOSFET M2 is turned off at the light load detection timing, when the backflow current is large, the midpoint LX becomes higher than the reference voltage Vref1 before the PWM signal becomes high level. May be. Also at this time, it is possible to prevent the MOSFET M1 from being erroneously turned on by the AND gate circuit G8. That is, the MOSFET M1 is turned on when the PWM signal is at a high level and the potential at the midpoint LX becomes higher by the reference voltage Vref1. When the reverse current is small as indicated by the dotted line, the MOSFET M1 is turned on after waiting for the delay time td3 of the delay circuit DL3. Others are the same as described in FIG.

  The control terminal EN is used to input an operation control signal for the switching power supply. When the power supply voltage supplied to the load circuit is formed with only one switching power supply, the control terminal EN is supplied with a power supply voltage such as the input voltage Vin, for example. In the case of operating the gate circuit G6 with the power supply voltage VCC, a level shift circuit for level shifting Vin to VCC is provided, and an operation control signal is supplied to the gate circuit G6.

  FIG. 9 is an explanatory diagram of another embodiment of the present invention. In this embodiment, the switching power supplies SW-REG1 and SW-REG2 are operated in parallel as shown in FIG. That is, the output terminals of the two switching power supplies SW-REG1 and SW-REG2 are connected to form an operating voltage and a load current for one load circuit. When the operation of the two switching power supplies SW-REG1 and SW-REG2 starts simultaneously, the rising of the output voltages Vout1 and Vout2 is the charge-up voltage of the capacitor formed by the soft start circuit SS as shown in FIG. 8B. Dependent. Since the variation in the capacitance value of the capacitor is as large as 30% to 40%, there is a rising difference voltage between the output voltages Vout1 and Vout2.

  When there is a difference voltage at the rise of the output voltages Vout1 and Vout2, the output with a fast rise indicated by the dotted line in the figure toward the switching power supply SW-REG2 forming the slow rise output voltage Vout2 indicated by the solid line in the figure. The backflow current is flows from the switching power supply SW-REG1 that forms the voltage Vout1. At this time, the rapidly rising switching power supply SW-REG1 bears the load current Iout toward the load circuit and the current is flowing toward the slowly rising switching power supply SW-REG2, and an excessive current flows and the element is destroyed. In addition, the protection circuit operates to disable the parallel operation as described above.

  Furthermore, two power supplies SW-REG1 and SW-REG2 are provided, and one power supply SW-REG1 is always in an operating state to form an output voltage Vout indicated by a solid line as shown in FIG. 9B. When the load current of the load circuit increases, if the SW-REG2 is operated using the control terminal EN, the two power supplies SW-REG1 and SW-REG2 have a large output voltage Vout. SW-REG2 is started in a state where the differential voltage is generated. At this time, the power supply SW-REG1 also bears a current that flows back to the SW-REG2 in addition to the increased load current, and an excessive current flows to break the element or operate the protection circuit as described above. The possibility of making difficult parallel operation impossible increases.

  However, when the switching power supply as shown in FIG. 6 is used as the switching power supplies SW-REG1 and SW-REG2, the SW-REG2 is in the light load mode, and the output voltage Vout is shown by a dotted line in FIG. The voltage comparison circuit VC5 detects that the output voltage Vout ′ shown in FIG. 1 has not been reached, and the MOSFET M1 is turned off. As a result, the generation of the backflow current is as described above is prohibited. Therefore, a parallel operation such as the switching power supplies SW-REG1 and SW-REG2 is realized by adding a function of turning off the MOSFET M2 using the light load detection signal and the output voltage detection result by the voltage comparison circuit. Can be possible. In such parallel operation, since the operation with one switching power supply is stopped when the load current is small, the efficiency is improved as compared with the case where a single switching power supply forms a small load current to a large load current. Can be achieved.

  FIG. 10 shows a block diagram of an embodiment of a switching power supply according to the present invention. In the switching power supply of this embodiment, a portion surrounded by a thick frame is constituted by one semiconductor integrated circuit (IC). In this embodiment, instead of the diode D, a P-channel MOSFET M3 is used as the switch element M3 constituting the booster circuit. In the semiconductor integrated circuit device, in addition to the high potential side MOSFET M1, the low voltage side MOSFET M2, and the MOSFET M3, level shift circuits LS1 and LS2, an error amplifier EA, a voltage comparison circuit CMP, a triangular wave generation circuit TWG, a control circuit CONT, and the like are formed. Is done. The inductor LO, the bootstrap capacitor CB and the capacitor CO, and the resistors R1 and R2 constituting the voltage dividing circuit are also constituted by external single elements. The MOSFETs M2 and M1 are formed on a semiconductor chip as indicated by dotted lines in the figure, and are integrated into a package together with the semiconductor chip on which the control circuit CONT and the like are formed. It may be considered as one semiconductor integrated circuit device (multi-chip module).

  The level shift circuit LS1 generates an output signal that turns off the P-channel MOSFET M3. The level shift circuit LS2 forms a drive signal for the MOSFET M1. In this embodiment, the control part is formed as a semiconductor integrated circuit and the bootstrap switch element M3 is also incorporated, so that the number of power supply components can be reduced and the size can be reduced.

  FIG. 11 is a block diagram showing still another embodiment of the switching power supply according to the present invention. In the figure, two semiconductor integrated circuit devices, a control IC and a driver IC, are used. For example, a common operating voltage VCC is applied to the control IC and the driver IC. The driver IC of this embodiment may be a high voltage corresponding to the input voltage Vin. For this reason, the driver IC is provided with a step-down power supply circuit Reg, and an internal voltage corresponding to the VCC is formed. Other configurations are the same as those of the embodiment of FIG. Also in the driver IC, MOSFETs M2 and M1 are each formed in a semiconductor chip as indicated by a dotted line in the figure, and are integrated into a package together with a semiconductor chip on which a control circuit DCT and the like are formed, It may be seen as one semiconductor integrated circuit device (multichip module).

  10 and 11, in the semiconductor integrated circuit for generating the drive signals for the switch MOSFETs M1 and M2, a load current detection circuit for controlling the dead time as shown in FIGS. Is provided. As described above, the control terminal EN for parallel operation of the switching power supply is also provided.

  Although the invention made by the inventor has been specifically described based on the above embodiment, the present invention is not limited to the above embodiment, and various modifications can be made without departing from the scope of the invention. For example, the switches SW1 and SW2 can take various embodiments such as an analog switch such as a transfer gate using MOSFETs, or a circuit that transmits any signal by a logic gate circuit. In addition to monitoring the potential at the midpoint LX when the load is light, and setting the dead time by setting the on-timing of the switch MOSFETs M2 and M1, the control is performed with a predetermined average dead time at the light load. You may make it do. The specific configuration of each circuit block can take various embodiments. The present invention can be widely used for a switching power supply such as a step-down type and a semiconductor integrated circuit device used therefor.

1 is a schematic circuit diagram showing an embodiment of a switching power supply according to the present invention. It is a circuit diagram which shows one Example of the switching power supply which concerns on this invention. It is a wave form diagram for demonstrating operation | movement of the switching power supply of FIG. FIG. 6 is another waveform diagram for explaining the operation of the switching power supply of FIG. 2. FIG. 6 is another waveform diagram for explaining the operation of the switching power supply of FIG. 2. It is a circuit diagram which shows another Example of the switching power supply which concerns on this invention. It is a wave form diagram for demonstrating operation | movement of the switching power supply of FIG. FIG. 7 is another waveform diagram for explaining the operation of the switching power supply of FIG. 6. It is explanatory drawing of other one Example of this invention. It is a block diagram which shows one Example of the switching power supply which concerns on this invention. It is a block diagram which shows another one Example of the switching power supply which concerns on this invention. It is a block diagram of the switching power supply examined prior to this invention. It is a wave form diagram for demonstrating the switching power supply of FIG.

Explanation of symbols

  M1-M3 ... MOSFET, LO ... inductor, CO ... capacitor, CB ... bootstrap capacitance, SW1, SW2 ... switch, G1-G8 ... gate circuit, FF ... flip-flop circuit, DL1-DL4 ... delay circuit, VC1-VC5 ... Voltage comparison circuit, NV1 to NV3 ... inverter circuit, D ... diode, EA ... error amplifier, TWG ... triangular wave generation circuit, CONT ... control circuit, R1-R4 ... resistance, Reg ... power supply circuit, LS, LS1, 2 ... level shift circuit.

Claims (14)

An inductor;
A capacitor provided between the output side of the inductor where the output voltage is formed and the ground potential;
A first switch element for supplying a current from an input voltage to the input side of the inductor;
A second switch element having a time to turn on when the first switch element is off;
A control circuit for forming a control signal to be supplied to the first and second switch elements so that the output voltage becomes a desired voltage;
A load current detection circuit,
The control circuit has a dead time from when one of the first or second switch elements is turned off to when the other is turned on when the load current detection circuit determines that the load is light. A switching power supply comprising the control signal for shortening the dead time when it is determined that the load is heavy. In claim 1,
The control circuit is
The first and second delay circuits corresponding to the dead time suitable for the heavy load are provided, and when the heavy load is determined, the second switch element is turned off and set by the first delay circuit. The first switch element is turned on by a dead time, and the second switch element is turned on by a dead time set by the second delay circuit after the first switch element is turned off. Switching power supply. In claim 2,
The control circuit is
A first and second voltage comparison circuit for comparing the voltage on the input side of the inductor with the first and second reference voltages;
The first voltage comparison circuit detects that a voltage difference between both ends of the second switch element is a predetermined potential or less,
The second voltage comparison circuit detects that the voltage across the first switch element is equal to or lower than a predetermined potential;
When it is determined that the load is light, the first switch element is turned off, the second switch element is turned on according to the detection output of the first voltage detection circuit, and the second switch element is turned off. The switching power supply, wherein the first switch element is turned on according to the detection output of the second voltage detection circuit. In claim 3,
The control circuit is
A third delay circuit corresponding to the dead time suitable for the light load, and when the light load is determined, either the detection output of the first voltage detection circuit or the output signal of the third delay circuit; A switching power supply, wherein the second switch element is turned on at an early timing. In claim 4,
The load current detection circuit is
The third voltage comparator circuit determines that the load is light if the input-side potential of the inductor is positive with respect to the ground potential while the second switch element is on, and determines that the load is heavy if the negative voltage is negative. Switching power supply. In claim 5,
The output signal of the third voltage comparison circuit is subjected to the determination by being multiplexed by a delay signal corresponding to a noise generation period when the first switch element is turned off and the second switch element is turned on. Switching power supply. In claim 6,
The control circuit further includes a flip-flop circuit that is set / reset according to the determination result,
A switching power supply wherein the dead time of the next cycle is set by a set / reset output of the flip-flop circuit. In claim 7,
A switching power supply characterized in that the control signal is a PWM signal having a high frequency exceeding 1 MHz. In claim 8,
The first switch element and the second switch element are N-channel MOSFETs,
A booster circuit including a bootstrap capacitor having one end connected to a source of an N-channel MOSFET constituting the first switch element;
A switching power supply further comprising a level shift circuit for forming a drive signal corresponding to a boosted voltage formed by the booster circuit at a gate of an N-channel MOSFET constituting the first switch element. An inductor;
A capacitor provided between the output side of the inductor where the output voltage is formed and the ground potential;
A first switch element for supplying a current from an input voltage to the input side of the inductor;
A second switch element having a time to turn on when the first switch element is off;
A control circuit for forming a control signal to be supplied to the first and second switch elements so that the output voltage becomes a desired voltage;
A comparator for detecting the output voltage;
A load current detection circuit,
The control circuit has a dead time from when one of the first or second switch elements is turned off to when the other is turned on when the load current detection circuit determines that the load is light. Forming the control signal that shortens the dead time when it is determined that the load is heavy,
The comparison unit compares the output voltage with a predetermined voltage, turns off the second switch element when the output voltage is lower than the predetermined voltage, and when the output voltage is higher than the predetermined voltage. A switching power supply, wherein the switching operation of the second switch element is enabled in accordance with the control signal. In claim 10,
An operation control terminal;
In a state where a control signal of one level is supplied to the operation control terminal, the control signal is validated and switch control of the first and second switch elements is performed,
The switching power supply, wherein the first and second switch elements are turned off when a control signal of the other level is supplied to the operation control terminal. In claim 11,
The switching power supply includes a first circuit and a second circuit,
The output terminals of the first circuit and the second circuit are connected in common,
A control signal of one level is constantly supplied to the operation control terminal of the first circuit,
A switching power supply comprising: the operation control terminal of the second circuit, wherein control signals of one level and the other are switched and input. A first terminal that outputs a drive signal of a first switch element that supplies current from the input voltage to the input side of the inductor;
A second terminal for outputting a drive signal of the second switch element having a time for which the first switch element is turned on when the first switch element is turned off;
A control circuit for forming an output voltage by providing an output side of the inductor and a ground potential capacitor, and forming drive signals for the first and second switch elements so that the output voltage becomes a desired voltage;
A load current detection circuit flowing through the inductor,
The control circuit has a dead time from when one of the first or second switch elements is turned off to when the other is turned on when the load current detection circuit determines that the load is light. A semiconductor integrated circuit device characterized by forming the drive signal for shortening the dead time when it is determined that the load is heavy. In claim 13,
The control circuit and the load current detection circuit are formed in the first semiconductor chip,
The first and second switch elements are formed in second and third semiconductor chips,
A semiconductor integrated circuit device, wherein the first to third semiconductor chips are built in one package.

Images