JP2007109199A - Buffer device, control method for buffer device, and information processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To facilitate materialization of system-on-chip by providing a buffer circuit allowing easy connection of an existing peripheral circuit operated by various operation clocks. <P>SOLUTION: This buffer device 100 includes: a buffer 110 storing at least one of data and an address necessary for an exchange of the data between a first circuit and a second circuit; a first interface part 130 that is a connection part with the first circuit; an interface part 140 that is a connection part with the second circuit; a clock changeover control circuit 150 deciding timing of a changeover of a clock supplied to the buffer on the basis of an access situation of the first circuit and the second circuit to the buffer, and generating a clock changeover control signal 152 for instructing selection or the changeover of the clock supplied to the buffer; and a clock changeover circuit 120 inputted with the plurality of clocks including the operation clock of the first circuit and the operation clock of the second circuit, selecting one clock on the basis of the clock changeover signal, and supplying it to the buffer. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a buffer device, a control method for the buffer device, and an information processing device.

With regard to data transfer between circuits that operate with different clocks, for example, a two-port memory is placed in between, and each port is accessed in synchronization with a different clock, or two stages between circuits operating between different clocks. There are two general methods of placing a buffer and controlling the buffer with data and a necessary control signal by a clock on the data receiving side.
JP 2001-222407 A JP 2003-198518 A Japanese Patent Laid-Open No. 5-100820 JP 2001-134421 A

  However, the above two methods have a problem in that it is basically impossible to cope with the case where the clock type is 3 or more.

  If the clock type is 3 or more, each of the above two methods must have a circuit, and the host interface (bus interface) must be redesigned. As a result, all peripheral circuits have buffers. Become.

  Due to this buffering, a time difference occurs between the access order from the host CPU to each peripheral device and the access order to the actual peripheral circuit, which causes a problem that control becomes difficult.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a buffer circuit capable of easily connecting existing peripheral circuits operating with various operation clocks. The purpose is to facilitate system-on-chip.

(1) The present invention
A buffer device that exists between a first circuit and a second circuit that operate with clocks having different frequencies,
A buffer for storing at least one of an address and data necessary for data exchange between the first circuit and the second circuit;
A first interface unit which is a connection unit between the first circuit and the buffer;
A second interface unit that is a connection between the second circuit and the buffer;
Based on the access status to the buffers of the first circuit and the second circuit, the timing for switching the clock supplied to the buffer is determined, and a clock switching control signal for instructing selection or switching of the clock supplied to the buffer is provided. A clock switching control circuit to be generated;
A clock switching circuit that receives a plurality of clocks including an operation clock of the first circuit and an operation clock of the second circuit, selects one of the clocks based on the clock switching signal, and supplies the selected clock to the buffer;
It is characterized by including.

  The first interface unit is an interface unit for exchanging signals when the first circuit accesses the buffer.

  The second interface unit is an interface unit for exchanging signals when the second circuit accesses the buffer.

  When the first circuit reads / writes to / from the buffer, the clock switching control circuit supplies the buffer with the clock having the operating frequency of the first circuit, and the second circuit reads / writes from / to the buffer. In this case, a clock switching control signal for switching the clock supplied to the buffer is generated so that the clock having the operating frequency of the second circuit is supplied to the buffer.

  The clock switching circuit receives a plurality of clocks including a clock having an operating frequency of the first circuit and a clock having an operating frequency of the second circuit, selects one of the clocks based on a predetermined control signal, and inputs the clock to the buffer. This can be realized by an output selection circuit.

  Here, a plurality of circuits having different frequencies may be connected as the second circuit. In such a case, the clock switching circuit inputs the operating frequencies of the plurality of circuits having different frequencies, and performs clock switching control from among the operating frequencies of the first circuit and the plurality of different frequencies. One of the frequencies is selected and output based on the signal.

(2) The buffer device of the present invention includes:
The buffer is
It consists of multiple stages,
The clock switching control circuit includes:
Based on the access status to the buffer of each stage of the first circuit and the second circuit, the timing to switch the clock supplied to the buffer of each stage is determined, and a clock switching control signal corresponding to each stage is generated,
The clock switching circuit is
A plurality of clocks including an operation clock of the first circuit and an operation clock of the second circuit are input corresponding to the exceptional level of the buffer, and one of the clocks is selected based on the clock switching signal corresponding to each stage. Supply to the buffer of each stage.

(3) The buffer device of the present invention includes:
The second interface unit includes:
A FIFO for storing a pointer to the buffer at the stage of writing when writing to the buffer of the first circuit occurs;
Control is performed so as to permit access to the buffer from the second circuit in first-in first-out order in the output order of the FIFO.

(4) The buffer device of the present invention includes:
The buffer device includes:
A buffer device that exists between a plurality of peripheral circuits that operate with clocks having different frequencies and a control unit that controls the plurality of peripheral circuits,
The first interface unit includes:
It is configured as a host port or bus that connects the control unit,
The second interface unit includes a plurality of peripheral circuit interface circuits corresponding to the plurality of peripheral circuits,
The buffer is
It stores at least one of an address and data necessary for access between the control unit and the peripheral device.

(5) The buffer device of the present invention includes:
Each of the peripheral circuit interface circuits is
Each peripheral circuit includes a FIFO for storing a pointer to the buffer at the stage where writing has been performed when writing to the buffer of the first circuit occurs in the buffer of the first circuit. Control is performed to permit access to the buffer from the peripheral circuit.

(6) The buffer device of the present invention includes:
Each peripheral circuit has a bus independent of other peripheral circuits,
Each of the peripheral circuit interface circuits is
It is connected to a bus of a corresponding peripheral circuit.

  This makes it possible to operate in a parallel mode.

(7) The buffer device of the present invention includes:
The clock switching control circuit includes:
When the end of writing to the buffer of the first circuit is detected, a clock switching control signal for instructing to switch the clock supplied to the buffer to the operation clock of the second circuit is generated.

(8) The buffer device of the present invention includes:
The buffer is
An R / W identification flag for identifying whether the content written in the buffer is a read or write to the second circuit;
The clock switching control circuit includes:
When the R / W identification flag indicates writing, when it is detected that the buffer contents have been read from the second circuit, the clock supplied to the buffer is switched to the operation clock of the first circuit. Generating a clock switching control signal for instructing;

(9) The buffer device of the present invention includes:
The buffer is
An R / W identification flag for identifying whether the content written in the buffer is a read or write to the second circuit;
The clock switching control circuit includes:
When the R / W identification flag indicates reading, when it is detected that writing from the second circuit to the buffer has been performed, the clock supplied to the buffer is switched to the operation clock of the first circuit. Generating a clock switching control signal for instructing to do so.

(10) The buffer device of the present invention includes:
The buffer is
An R / W identification flag for identifying whether the content written in the buffer is a read or write to the second circuit;
The clock switching control circuit includes:
When the R / W identification flag indicates reading, when the end of reading is detected from the second circuit and the read data is output to the first circuit, the clock supplied to the buffer is supplied to the first circuit. A clock switching control signal for instructing switching to the operation clock is generated.

(11) The buffer device of the present invention includes:
A mode setting register for storing information on whether the mode is the sequential mode or the parallel mode;
When the value of the mode setting register indicates the sequential mode, control is performed so that the processing is executed in the order of access from the first circuit, and the value of the mode setting register indicates the parallel mode. And a circuit that controls to execute the process regardless of the order of access from the first circuit,
The value of the mode setting register is set based on an instruction signal from the first circuit.

  (12) The present invention is an information processing apparatus including the buffer device according to any one of the above, a first circuit, and a second circuit.

  An information processing apparatus comprising the buffer device according to claim 1, a first circuit, and a second circuit.

(13) The present invention provides:
A buffer that exists between a first circuit and a second circuit that operate with clocks having different frequencies and stores at least one of an address and data necessary for data exchange between the first circuit and the second circuit; A control method for a buffer device, comprising:
Based on the access status to the buffers of the first circuit and the second circuit, the timing for switching the clock supplied to the buffer is determined, and a clock switching control signal for instructing selection or switching of the clock supplied to the buffer is provided. Generating step;
Inputting a plurality of clocks including an operation clock of the first circuit and an operation clock of the second circuit, selecting any one of the clocks based on the clock switching signal, and supplying the selected clock to the buffer;
It is characterized by including.

(14) The control method of the present invention includes:
Setting an execution mode based on an instruction signal from the first circuit;
When the execution mode is set to the sequential mode, control is performed so that processing is executed in the order of access from the first circuit. When the execution mode is set to the parallel mode, access from the first circuit is controlled. A step for controlling the processing to be executed regardless of the order; and
It is characterized by including.

1. Integrated Circuit Device Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a diagram for explaining a buffer device according to the present embodiment.

  The buffer device 100 according to the present embodiment is a buffer device 100 that exists between a first circuit 180 and a second circuit 190 that operate with operation clocks having different frequencies, and includes a first interface unit 130 and a second circuit 190. Interface section 140, buffer 110, control section 170, and clock switching section 120.

  The information processing apparatus 300 according to the present embodiment includes a buffer device 100, a first circuit 180, and a second circuit 190.

  The first interface unit 130 is an interface circuit for connecting the first circuit. The second interface unit 140 is an interface circuit for connecting the second circuit.

  The first interface unit 130 includes a connection unit (not shown) to a host port or bus that connects the first circuit (control unit) 180.

  The second interface unit 140 includes a peripheral port (not shown) for connecting a second circuit (peripheral circuit) 190, a FIFO 142, a selector 146, and a bus driver receiver 148.

  A peripheral port (not shown) may have a clock input terminal of the second circuit (peripheral circuit) 190 connected to the peripheral port.

  The FIFO 142 stores pointers of the address buffer and the data buffer. When writing to the buffer 110 of the first circuit 180 occurs, the FIFO 142 stores a pointer to the buffer at the stage where writing has been performed. Control is performed so that access to the buffer from the second circuit 190 is permitted in first-in first-out order in the order of output of the FIFO 142.

  The buffer 110 is a buffer that stores at least one of an address and data necessary for data exchange between the first circuit 180 and the second circuit 190.

  The buffer 110 includes a plurality of stages (110-0, 110-1,... 110-n), and the clock switching unit 120 (120-0, 120-1,..., 120-n). Is provided corresponding to each stage 110-0, 110-1,... 110-n of the buffer, and switches the clock supplied to each stage of the buffer.

  Further, the buffer may be composed of a plurality of address buffers for storing addresses mapped in the memory space or IO space, and a data buffer for storing write data and read data corresponding to the address buffers.

  The peripheral circuits may be accessed in the order written in the buffers 110-0, 110-1, 110-2,... (Sequential mode).

  The control unit 170 performs response control and buffer control for all accesses from the first circuit (host). The control unit 170 includes a clock switching control circuit 150.

  The clock switching control circuit 150 determines the timing for switching the clock supplied to the buffer 110 based on the access status of the first circuit 180 and the second circuit 190 to the buffer 110, and selects the clock to be supplied to the buffer or A clock switching control signal 152 for instructing switching is generated.

  The clock switching control circuit 150 has buffers 110-0, 110-1,..., 110- in each stage of the first circuit 180 and the second circuit 190, when the buffer is composed of a plurality of stages. , 110-n is determined based on the access status to n, and a clock switching control signal 152- corresponding to each stage is determined. 0, 152-1,..., 152-n are generated.

  When the clock switching control circuit 150 detects the end of writing to the buffer of the first circuit, the clock switching control circuit 150 generates a clock switching control signal instructing to switch the clock supplied to the buffer to the operation clock of the second circuit. You may make it do.

  Here, the buffer 110 may include an R / W identification flag for identifying whether the content written in the buffer is reading or writing with respect to the second circuit 190.

In such a case, when the R / W identification flag indicates writing, the clock switching control circuit 150 detects that the contents of the buffer 110 have been read from the second circuit 190, and the buffer 110 A clock switching control signal 152 may be generated that instructs to switch the clock supplied to the operation clock of the first circuit.
In addition, when the R / W identification flag indicates reading, the clock switching control circuit 150 detects a clock written to the buffer from the second circuit 190 and supplies a clock to the buffer 110. The clock switching control signal 152 may be generated to instruct to switch to the operation clock of the first circuit 180. Although the path for storing the read data from the second circuit in the buffer is not shown, it is possible by providing a selector on the input side of the buffer and providing the output of the buffer to the first circuit. .
Since the read data from the second circuit can be output stably with respect to the change in the operation clock of the first circuit, the read data is directly buffered from the second circuit without being buffered. 1 may be output to one circuit. In this case, the operation clock of the buffer may be switched after detecting the end of reading data from the second circuit.

  The clock switching unit 120 receives a plurality of clocks including an operation clock of the first circuit 180 and an operation clock of the second circuit 190, selects one of the clocks based on the clock switching signal 152, and selects the buffer 110. To supply.

  The operation clock 182 of the first circuit 180 may be input from the first circuit via the first interface unit 130, for example.

  The operation clock of the second circuit may be input from the second circuit via the second interface unit 140, for example.

  When there is no valid value in the address buffer, the address buffer and the corresponding data buffer may be operated with the operation clock of the host port or bus to which the first circuit (control unit) 180 is connected.

  Then, when the peripheral circuit connected to the host port is accessed from the first circuit (control unit) 180, the address and data may be temporarily written in the address buffer and data buffer having no valid values.

  Then, the operation clock is switched to the clock input from the peripheral port, the pointer of the buffer is written to the FIFO 142 corresponding to the peripheral port, and the contents of the address buffer and data buffer are read by the pointer stored in the FIFO 142. Then, the second circuit (peripheral circuit) 190 connected to the peripheral port may be accessed.

  After the access is completed, the clock may be switched from the first circuit (control unit) 180 again.

  Although the portion connecting the second circuit (peripheral circuit) 190 is expressed as “peripheral port”, it is often a general-purpose bus.

  For example, when there are a plurality of types m of the second circuits (peripheral circuits) 190, the buffer device 100 has a plurality of bus interfaces, and the number thereof is host bus × 1 + peripheral circuit bus × m.

  According to the present embodiment, since the interface with the peripheral circuit may be the same as the conventional one, the peripheral circuit of the past design asset can be connected as it is. Even if the operation clock is different, existing peripheral circuits can be easily connected.

  Also, it can support as many different clocks as the number of peripheral circuit ports.

  Further, the circuit logic can be simplified because the buffer can be realized by a circuit that controls to switch to the clock on the access target side of the first circuit (host side) and the second circuit (slave side).

  FIG. 2 is a diagram when a plurality of peripheral circuit buses of the buffer device 100 are connected.

  Further, as shown in FIG. 2, the buffer device 100 may be configured as a buffer device that exists between a plurality of peripheral circuits that operate with clocks having different frequencies and a control unit (host) that controls the plurality of peripheral circuits.

  The first interface unit may be configured as a host port or bus 182 for connecting a control unit (host).

  The second interface unit includes a plurality of peripheral circuit interface circuits 140-0, 140-1,..., 140-m that connect peripheral circuits.

  The buffer 110 stores at least one of an address and data necessary for access between the control unit (host) and the peripheral device.

  Here, the read data 16 from the peripheral device is shown collectively from the peripheral device bus interface, but a plurality of read data 16 are not effective at the same time.

  Here, the buffer unit 110 includes a buffer and a clock control circuit.

  FIG. 3 is a configuration diagram of the buffer unit 110 of FIG.

  Each of the buffers 110-0, 110-1,... 110-n includes address buffers 112-0, 112-1,... 112-n, data buffers 114-0, 114-1,. 116-n, write flags 116-0, 116-1,... 116-n, and use flags 118-0, 118-1,.

  Address buffers 112-0, 112-1,... 112-n are buffers for storing addresses mapped in the memory space or IO space, and store addresses when accessed from the host bus.

  The data buffers 114-0, 114-1,... 114-n store data corresponding to the address buffer, store write data during write access from the host bus, and from peripheral devices during read access. You may make it store read data.

  The read / write flags 116-0, 116-1,... 116-n are flags indicating whether the access stored in the buffer is read or write.

  The use flags 118-0, 118-1,... 118-n are flags indicating whether or not the access stored in the buffer is completed. The buffer write enable signals 3-0, 3-1,..., 3-n from the peripheral device interface are turned off (not used).

  The clock switching units 120-0, 120-1,... 120-n switch clocks by peripheral circuit selection signals 6-0, 6-1,. The switching timing is when writing to the buffers 110-0, 110-1,.

  The buffer unit includes an empty buffer designation control unit 210, a next pointer 212, a current pointer 214, and a buffer write control unit 216.

  The empty buffer designation control unit 210 searches for an unused buffer based on the buffer use flag 118 and outputs a pointer number.

  The next pointer 212 stores the value of the next buffer pointer to be used next determined by the empty buffer designation control unit 210.

  The current pointer 214 indicates the address of the buffer to be written next. After execution of writing, the value of the next pointer 212 is stored.

  The buffer write controller 216 generates a permission signal for the next buffer to be written based on the value of the current pointer 214.

  The use flag signal 1 is a buffer use flag output, and is turned on when an address is written by an access from the host, and turned off when executed by a peripheral device.

  2 is a read / write flag signal, 3-0, 3-1, and 3-n are buffer write enable signals, 6 is a peripheral circuit selection signal, and 192-0 to 192-n are clocks of peripheral devices. , And 182 is a host clock.

  9 is a current pointer, 10 is an address signal from the host bus, 11 is a data signal from the host bus, 12 is an address output signal from the buffer, and 13 is a data output signal from the buffer. , 14 are read / write flag inputs from the host bus.

  FIG. 4 is a configuration diagram of the peripheral device interface.

  The peripheral device interface includes a pointer storage FIFO 142, a buffer selector 146, and a peripheral device bus interface 148.

  The pointer storage FIFO 142 is a FIFO for storing a buffer number (pointer) in which the address / data for accessing the peripheral device is stored. It consists of a storage area for a pointer 144 and a read / write flag 145.

  The buffer selector 146 selects a buffer based on the output 143 of the pointer storage FIFO 142.

  Peripheral device bus interface 148 converts the peripheral device to a bus. After the access is completed, the peripheral device access execution signal 17 for turning off the use flag of the buffer with the pointer storing FIFO control pointer is made valid.

  The peripheral device buffer pointer registration instruction signal 15 is an output signal from the buffer control unit.

  The read data 16 is read data from a peripheral device.

  Reference numeral 17 denotes a peripheral device access execution signal.

  Reference numeral 25 denotes a wait signal from the peripheral device bus interface.

  FIG. 5 is a block diagram of the buffer control unit.

  The buffer control unit includes a control unit 152, an address comparison unit 154, and a peripheral device registration unit 155.

  The peripheral device registration unit 155 includes a peripheral device access start address 156 and a peripheral device access area size 158.

  The peripheral device access start address 156 stores the start address on the memory map of the peripheral device mounted in the system.

  The access area size 158 of the peripheral device stores the access area size of the peripheral device mounted on the system.

  The control unit 152 performs response control and buffer control for all accesses from the host.

  The address comparison unit 154 determines whether the access from the host is for a registered peripheral device by comparing it with the peripheral value. The peripheral device selection signal and the peripheral device buffer pointer registration instruction signal for the registered peripheral device are validated.

  Reference numeral 19 denotes peripheral device registration data 1, 20 denotes peripheral device registration data m, and 21 denotes a host bus command signal.

  Reference numeral 22 denotes a peripheral device registration register control signal. Registration to the peripheral device registration unit 155 is performed at the time of system initialization after power-on.

  Reference numeral 23 denotes a host access signal control signal, which is not always compared, but when an access from the host occurs. The control unit 152 that performs response control of access from the host determines this timing, generates a signal, and instructs the address comparison unit 154.

  24 is a bus control signal, and 25 is a wait signal.

  FIG. 6 is an example of the access start address of the peripheral device and the access area size of the peripheral device registered in the peripheral device registration unit.

  In the present embodiment, the start address and area size of the peripheral device connected via the buffer device are registered in the peripheral device registration unit at the time of initial setting of the system.

  In this example, eight peripheral devices are connected, and the values shown in FIG. 6 are registered as addresses and area sizes.

  The number of buffer stages is 16. (Pointer value 0 to FH). The initial value of the current pointer 0 is 0H, and the initial value of the next pointer is 1H. The number of FIFO stages in the peripheral device interface is 16 stages, the same as the buffer.

  Next, an example of the operation in the parallel mode of this embodiment will be described.

  First, it is assumed that data 0000 # 000FH is written to 00A0 # 1000H from the CPU (step S1).

  Next, the control unit 152 recognizes the bus access by the bus command and validates the signal 23. When the signal 23 becomes valid, the buffer write control signal operates and the value of the current pointer is 0H, so that the signal 3 becomes valid. At the same time, the current pointer value is updated to the next pointer value. The empty buffer designation control unit sets 2H to the next pointer 212 because the use flag 118 of the buffer 2 next to the buffer 1 is OFF (step S2).

  Next, the signal 3 becomes valid, 00A0 # 1000H is stored in the address buffer 112-0, 0000 # 000FH is stored in the data buffer 114-0, and the buffer No. 1 is stored in the read / write flag 214 of 0. (When flag 214 is 1, it indicates writing). The use flag of the buffer 0 is turned on (step S3).

  Next, after the writing is completed, the clock of the buffer 0 is switched to the clock of the peripheral device 1 by the peripheral circuit selection signal 6 (step S4).

  Next, the buffer control unit 150 turns on the signal 23 and enables the signal 15. As a result, the value 0H of the current pointer is stored in the FIFO of the peripheral device interface 1. The FIFO write pointer is incremented by one. At the same time, the use flag of the stage written in the FIFO is turned on (step S5).

  Next, since the peripheral device bus 1 is not used, the FIFO value is immediately read and the read pointer value becomes +1. The use flag of the read FIFO stage is turned off (step S6).

  Next, the buffer selector 146 selects the output from the buffer 0 by the output of the FIFO, the address, data, and read / write flag are output to the peripheral device interface, and access to the peripheral device 1 is started. The peripheral device access execution signal 17 becomes active, is transmitted to the buffer unit together with the output of the FIFO, and the buffer use flag 118 indicated by the output value of the FIFO is turned off. In accordance with this, the operation clock of the buffer returns to the CPU bus clock. The address from the buffer may be converted into one that matches the peripheral device bus (step S7).

  In the case of a write operation, the access from the CPU ends the cycle of the CPU bus when the writing to the buffer is completed. The bus cycle is terminated without waiting for the write of the access already written in the buffer to the actual peripheral device. In the case of a read operation, the CPU bus cycle is terminated when the read operation is completed (step S8).

  Next, in the write access from the CPU bus, the above operation is repeated, and until the buffer is full, access to the peripheral device is executed regardless of the access order from the CPU. The used buffer is successively released when the processing flag 118 is turned off, and the access information from the next CPUU is stored. The empty buffer designation control unit 210 sets the use flag e of each buffer to the buffer number. Is checked in the +1 direction, and the next pointer 212 is updated (step S9).

  FIG. 7 is a flowchart showing the flow of processing in the parallel mode.

  A write operation occurs from the host CPU to the A port (step S110). Here, the A port is a port to which the peripheral device A is connected.

  Address data is stored in the pointer 001 buffer. Report the end of access to the host CPU. At this time, the buffer of the pointer 001 is operating with the clock of the host CPU (step S120).

  The clock of the pointer 001 is switched to the clock of the A port, and the pointer value 001 is stored in the pointer FIFO of the A port. After the access to the A port is completed, the buffer is switched to the host CPU side clock (step S130).

  Address data is saved in the buffer of pointer 002. Report the end of access to the host CPU (step S140).

  The clock of the pointer 002 is switched to the clock of the A port, and the pointer value 002 is stored in the pointer FIFO of the A port. After the A port access is completed, the host CPU side clock is switched (step S160).

  A write operation occurs from the host CPU to the B port (step S170). Here, the B port is a port to which the peripheral device B is connected.

Address data is saved in the buffer of pointer 003. Report the end of access to the host CPU. At this time, the buffer of the pointer 003 is operating with the clock of the host CPU (step S180).
The clock of the pointer 003 is switched to the clock of the B port, and the pointer value 003 is stored in the pointer FIFO of the B port. After the B port access is completed, the host CPU side clock is switched (step S190).
A write operation occurs from the host CPU to the A port (step S200).

  Address data is stored in the pointer 004 buffer. Report the end of access to the host CPU (step S210).

  The clock of the pointer 004 is switched to the clock of the A port, and the pointer value 004 is stored in the pointer FIFO of the A port. After the A port access is completed, the host CPU side clock is switched (step S220).

  A read operation occurs from the host CPU to the A port (step S230).

  The address is stored in the address buffer of the pointer 005 (step S240).

  The clock of the pointer 005 is switched to the clock of the A port, and the pointer value 005 is stored in the pointer FIFO of the A port (step S250).

  After the data read from the A port is stored in the data buffer of the pointer 005, the clock is switched to the host CPU (step S260).

  An access end signal is returned to the host CPU together with the read data (step S270).

  In step S190, sequential mode (a mode in which processing is executed in the order of access from the host) is realized by performing control so that port access is permitted after access of other ports before this is completed. be able to.

  When the sequential operation mode is set, a substantial access order can be guaranteed.

  When the parallel operation mode is set, access to each peripheral circuit is performed in parallel, so that the system performance can be improved. The effect is remarkable when the operation clock on the host CPU side and the operation clock on the peripheral circuit side are significantly different and the host side is fast.

  In the case of sequential processing, even if the host side CPU operates at high speed, it cannot proceed to the next operation until the access of the slow peripheral circuit is completed. It is possible to access another peripheral circuit without completing the access.

  Accordingly, when there is no cooperative control between the peripheral circuits, the parallel mode can be achieved by controlling each peripheral circuit in parallel, leading to an improvement in system performance.

  In addition, this invention is not limited to this embodiment, A various deformation | transformation implementation is possible within the range of the summary of this invention.

The figure for demonstrating the buffer apparatus of this Embodiment. The block diagram of the buffer apparatus which exists between a some peripheral circuit and a control part. The block diagram of a buffer part. The block diagram of a peripheral device interface. The block diagram of a buffer control part. An example of the access start address of the peripheral device registered in the peripheral device registration unit and the access area size of the peripheral device. The flowchart which shows the flow of a process in the case of parallel mode.

Explanation of symbols

100 buffer device, 110 buffer, 120 clock switching unit, 130 first I / F unit, 140 second I / F unit, 142 FIFO, 146 selector, 148 bus driver receiver, 150 clock switching control unit, 152 clock switching Control signal, 170 control unit, 180 first circuit, 190 second circuit, 300 information processing apparatus

Claims (14)

A buffer device that exists between a first circuit and a second circuit that operate with clocks having different frequencies,
A buffer for storing at least one of an address and data necessary for data exchange between the first circuit and the second circuit;
A first interface unit which is a connection unit between the first circuit and the buffer;
A second interface unit that is a connection between the second circuit and the buffer;
Based on the access status to the buffers of the first circuit and the second circuit, the timing for switching the clock supplied to the buffer is determined, and a clock switching control signal for instructing selection or switching of the clock supplied to the buffer is provided. A clock switching control circuit to be generated;
A clock switching circuit that receives a plurality of clocks including an operation clock of the first circuit and an operation clock of the second circuit, selects one of the clocks based on the clock switching signal, and supplies the selected clock to the buffer;
A buffer device comprising: In claim 1,
The buffer is
It consists of multiple stages,
The clock switching control circuit includes:
Based on the access status to the buffer of each stage of the first circuit and the second circuit, the timing to switch the clock supplied to the buffer of each stage is determined, and a clock switching control signal corresponding to each stage is generated,
The clock switching circuit is
A plurality of clocks including an operation clock of the first circuit and an operation clock of the second circuit are input corresponding to the exceptional level of the buffer, and one of the clocks is selected based on the clock switching signal corresponding to each stage. A buffer device for supplying to each stage buffer. In claim 2,
The second interface unit includes:
A FIFO for storing a pointer to the buffer at the stage of writing when writing to the buffer of the first circuit occurs;
A buffer device, wherein control is performed to permit access to the buffer from the second circuit in first-in first-out order in the output order of the FIFO. In any one of Claims 2 thru | or 3.
The buffer device includes:
A buffer device that exists between a plurality of peripheral circuits that operate with clocks having different frequencies and a control unit that controls the plurality of peripheral circuits,
The first interface unit includes:
It is configured as a host port or bus that connects the control unit,
The second interface unit includes a plurality of peripheral circuit interface circuits corresponding to the plurality of peripheral circuits,
The buffer is
A buffer device for storing at least one of an address and data necessary for access between a control unit and a peripheral device. In claim 4,
Each of the peripheral circuit interface circuits is
Each peripheral circuit includes a FIFO for storing a pointer to the buffer at the stage where writing has been performed when writing to the buffer of the first circuit occurs in the buffer of the first circuit. A buffer device that controls to permit access to the buffer from the peripheral circuit. In any of claims 4 to 5,
Each peripheral circuit has a bus independent of other peripheral circuits,
Each of the peripheral circuit interface circuits is
A buffer device connected to a bus of a corresponding peripheral circuit. In any one of Claims 1 thru | or 6.
The clock switching control circuit includes:
When the end of writing to the buffer of the first circuit is detected, a buffer device that generates a clock switching control signal that instructs to switch the clock supplied to the buffer to the operation clock of the second circuit . In any one of Claims 1 thru | or 7,
The buffer is
An R / W identification flag for identifying whether the content written in the buffer is a read or write to the second circuit;
The clock switching control circuit includes:
When the R / W identification flag indicates writing, when it is detected that the buffer contents have been read from the second circuit, the clock supplied to the buffer is switched to the operation clock of the first circuit. A buffer switching control signal for instructing In any one of Claims 1 thru | or 8.
The buffer is
An R / W identification flag for identifying whether the content written in the buffer is a read or write to the second circuit;
The clock switching control circuit includes:
When the R / W identification flag indicates reading, when it is detected that writing from the second circuit to the buffer has been performed, the clock supplied to the buffer is switched to the operation clock of the first circuit. A buffer device that generates a clock switching control signal instructing In any one of Claims 1 thru | or 8.
The buffer is
An R / W identification flag for identifying whether the content written in the buffer is a read or write to the second circuit;
The clock switching control circuit includes:
When the R / W identification flag indicates reading, when the end of reading is detected from the second circuit, the read data is output directly to the first circuit without passing through the buffer, and the clock supplied to the buffer is supplied. A buffer device for generating a clock switching control signal for instructing to switch to the operation clock of the first circuit. In any one of Claims 1 to 10,
A mode setting register for storing information on whether the mode is the sequential mode or the parallel mode;
When the value of the mode setting register indicates the sequential mode, control is performed so that the processing is executed in the order of access from the first circuit, and the value of the mode setting register indicates the parallel mode. And a circuit that controls to execute the process regardless of the order of access from the first circuit,
The buffer device characterized in that the value of the mode setting register is set based on an instruction signal from the first circuit.   An information processing apparatus comprising the buffer device according to claim 1, a first circuit, and a second circuit. A buffer that exists between a first circuit and a second circuit that operate with clocks having different frequencies and stores at least one of an address and data necessary for data exchange between the first circuit and the second circuit; A control method for a buffer device, comprising:
Based on the access status to the buffers of the first circuit and the second circuit, the timing for switching the clock supplied to the buffer is determined, and a clock switching control signal for instructing selection or switching of the clock supplied to the buffer is provided. Generating step;
Inputting a plurality of clocks including an operation clock of the first circuit and an operation clock of the second circuit, selecting any one of the clocks based on the clock switching signal, and supplying the selected clock to the buffer;
A control method for a buffer device. In claim 13,
Setting an execution mode based on an instruction signal from the first circuit;
When the execution mode is set to the sequential mode, control is performed so that processing is executed in the order of access from the first circuit. When the execution mode is set to the parallel mode, access from the first circuit is controlled. A step for controlling the processing to be executed regardless of the order; and
A control method for a buffer device.

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