JP2007108486A - Method of driving plasma display panel - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of driving a panel which does not cause discharge defect and has high display quality even when the panel has high luminance and high definition. <P>SOLUTION: In the method, a sustain pulse generation part which divides a one-field period into a plurality of sub-fields each having a write period and a sustain period and applies a sustain pulse to a display electrode pair in a sustain period to generate the sustain discharge of a discharge cell, is provided. The sustain pulse generation part has a power recovery part which applies a voltage to a display electrode pair by resonance between electrostatic capacity between electrodes of the display electrode pair and an inductor for power recovery and a clamp part which is connected to a specified power source or a ground potential to apply a voltage to the display electrode pair, and is characterized in that after a first discharge is generated in the end of the sustain period by applying the voltage to the display electrode pair, a second discharge is generated by further applying a voltage to the display electrode pair by using the clamp part. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a method for driving a plasma display panel.

  A typical AC surface discharge type panel as a plasma display panel (hereinafter abbreviated as “panel”) has a large number of discharge cells formed between a front plate and a back plate arranged to face each other. In the front plate, a plurality of display electrode pairs each consisting of a pair of scan electrodes and sustain electrodes are formed in parallel with each other on the front glass substrate, and a dielectric layer and a protective layer are formed so as to cover the display electrode pairs. Yes. The back plate has a plurality of parallel data electrodes on the back glass substrate, a dielectric layer so as to cover them, and a plurality of barrier ribs in parallel with the data electrodes formed on the back glass substrate. A phosphor layer is formed on the side walls of the barrier ribs. Then, the front plate and the back plate are arranged opposite to each other so that the display electrode pair and the data electrode are three-dimensionally crossed and sealed, and a discharge gas containing xenon is sealed in the internal discharge space. Here, a discharge cell is formed at a portion where the display electrode pair and the data electrode face each other. In the panel having such a configuration, ultraviolet light is generated by gas discharge in each discharge cell, and phosphors of RGB colors are excited and emitted by the ultraviolet light to perform color display.

  As a method of driving the panel, a subfield method, that is, a method of performing gradation display by combining subfields to emit light after dividing one field period into a plurality of subfields. Each subfield has an initialization period, an address period, and a sustain period. In the initialization period, an initialization discharge is generated, and wall charges necessary for the subsequent address operation are formed on each electrode. In the address period, address discharge is selectively generated in the discharge cells to be displayed to form wall charges. In the sustain period, a sustain pulse is alternately applied to the display electrode pair composed of the scan electrode and the sustain electrode, and a sustain discharge is generated in the discharge cell in which the address discharge is generated, and the phosphor layer of the corresponding discharge cell is caused to emit light. The image is displayed.

  Even in the subfield method, light emission that is not related to gradation display is achieved by performing initializing discharge using a slowly changing voltage waveform and selectively performing initializing discharge on discharge cells that have undergone sustain discharge. A novel driving method is disclosed in which the contrast ratio is improved as much as possible (see, for example, Patent Document 1).

  Various power consumption reduction techniques have been proposed to reduce the power consumption of a plasma display device using a panel. In particular, as one of the technologies for reducing the power consumption during the sustain period, focusing on the fact that each of the display electrode pairs is a capacitive load having an interelectrode capacitance of the display electrode pair, a resonant circuit including an inductor as a component is provided. So-called power recovery circuit that resonates the inductor and the capacitance between the electrodes, collects the charges stored in the capacitance between the electrodes in a capacitor for power recovery, and reuses the collected charges for driving the display electrode pair Is disclosed (for example, see Patent Document 2).

By driving the panel with an improved contrast ratio using such a power recovery circuit, a plasma display device with low power consumption and high contrast ratio can be realized.
JP 2000-242224 A Japanese Examined Patent Publication No. 7-109542

  In recent years, miniaturization of discharge cells has been promoted to meet the demand for improved definition of display images, while studies have been made to increase the xenon partial pressure of discharge gas in order to improve luminance. However, if the discharge cells are made finer as the panel becomes higher in definition, or if the xenon partial pressure is increased to increase the brightness of the panel, a discharge failure phenomenon such as the discharge cells to be discharged does not discharge occurs. There was a problem that display quality deteriorated.

  The present invention has been made in view of these problems, and an object of the present invention is to provide a method for driving a panel with high image display quality without causing defective discharge even in a high-luminance and high-definition panel.

  The present invention relates to a method for driving a panel having a plurality of discharge cells each having a display electrode pair composed of a scan electrode and a sustain electrode, and sustaining the discharge cell by applying a sustain pulse to the display electrode pair during the sustain period. The sustain pulse generator includes a power recovery unit that applies a voltage to the display electrode pair by resonance between the capacitance between the electrodes of the display electrode pair and the power recovery inductor, and a predetermined power source or ground. And a clamp unit that applies a voltage to the display electrode pair by connecting to the potential, and at the end of the sustain period, after applying a voltage to the display electrode pair using the power recovery unit to generate the first discharge The second discharge is generated by further applying a voltage to the display electrode pair using the clamp portion. This method can provide a method for driving a panel with high image display quality without causing defective discharge even for a high-luminance and high-definition panel.

  In the panel driving method of the present invention, after the second discharge is generated, a voltage is applied to the display electrode pair so as to reduce the potential difference between the electrodes of the display electrode pair before the second discharge converges. May be.

  Further, in the panel driving method of the present invention, after the voltage is started to be applied to the display electrode pair using the power recovery unit, the time until the voltage is further applied to the display electrode pair using the clamp unit is 650 ns to 750 ns. It is desirable that

  In the panel driving method of the present invention, it is desirable to apply a voltage to the display electrode pair so as to reduce the potential difference between the electrodes of the display electrode pair between 100 ns and 900 ns after the second discharge is generated. .

  ADVANTAGE OF THE INVENTION According to this invention, even if it is a high-intensity and high-definition panel, it becomes possible to provide the driving method of the panel which does not generate discharge failure but has high image display quality.

  Hereinafter, a panel driving method according to an embodiment of the present invention will be described with reference to the drawings.

(Embodiment)
FIG. 1 is an exploded perspective view showing a main part of a panel used in the embodiment of the present invention. The panel 10 is configured such that a glass front substrate 21 and a rear substrate 31 are arranged to face each other and a discharge space is formed therebetween. On the front substrate 21, a plurality of scanning electrodes 22 and sustaining electrodes 23 constituting a display electrode pair are formed in parallel with each other. A dielectric layer 24 is formed so as to cover the scan electrodes 22 and the sustain electrodes 23, and a protective layer 25 is formed on the dielectric layer 24. A plurality of data electrodes 32 covered with an insulating layer 33 are provided on the back substrate 31, and a grid-like partition wall 34 is provided on the insulating layer 33. A phosphor layer 35 is provided on the surface of the insulator layer 33 and the side surfaces of the partition walls 34. The front substrate 21 and the rear substrate 31 are arranged to face each other so that the scan electrode 22 and the sustain electrode 23 and the data electrode 32 intersect each other, and in the discharge space formed therebetween, for example, neon And a mixed gas of xenon. Note that the structure of the panel is not limited to the above-described structure, and for example, a structure having a stripe-shaped partition may be used.

  FIG. 2 is an electrode array diagram of the panel used in the embodiment of the present invention. N scan electrodes SC1 to SCn (scan electrode 22 in FIG. 1) and n sustain electrodes SU1 to SUn (sustain electrode 23 in FIG. 1) are arranged in the row direction, and m data electrodes D1 to D1 are arranged in the column direction. Dm (data electrode 32 in FIG. 1) is arranged. A discharge cell is formed at a portion where a pair of scan electrode SCi and sustain electrode SUi (i = 1 to n) and one data electrode Dj (j = 1 to m) intersect, and the discharge cell is in the discharge space. M × n are formed.

  FIG. 3 is a circuit block diagram of the plasma display device according to the embodiment of the present invention. The plasma display device includes a panel 10, an image signal processing circuit 51, a data electrode drive circuit 52, a scan electrode drive circuit 53, a sustain electrode drive circuit 54, a timing generation circuit 55, and a power supply circuit (not shown).

  The image signal processing circuit 51 converts the image signal sig into image data for each subfield. The data electrode driving circuit 52 converts the image data for each subfield into signals corresponding to the data electrodes D1 to Dm, and drives the data electrodes D1 to Dm. The timing generation circuit 55 generates various timing signals based on the horizontal synchronization signal H and the vertical synchronization signal V and supplies them to each circuit block. Scan electrode drive circuit 53 supplies drive voltage waveforms to scan electrodes SC1 to SCn based on timing signals, and sustain electrode drive circuit 54 supplies drive voltage waveforms to sustain electrodes SU1 to SUn based on timing signals. Here, scan electrode driving circuit 53 includes sustain pulse generating unit 100 for generating a sustain pulse to be described later, and sustain electrode driving circuit 54 includes sustain pulse generating unit 200 in the same manner.

  Next, a driving voltage waveform for driving the panel and its operation will be described. FIG. 4 is a diagram showing drive voltage waveforms applied to the respective electrodes of the panel used in the embodiment of the present invention. One field is divided into a plurality of subfields, and each subfield has an initialization period, an address period, Has a maintenance period.

  In the initializing period of the first subfield, first, in the first half, the data electrodes D1 to Dm and the sustain electrodes SU1 to SUn are held at 0 V, and from the voltage Vi1 that is lower than the discharge start voltage with respect to the scan electrodes SC1 to SCn. A ramp voltage that gradually increases toward the voltage Vi2 that exceeds the discharge start voltage is applied. Then, a weak initializing discharge is caused in all discharge cells, negative wall voltages are accumulated on scan electrodes SC1 to SCn, and positive wall voltages are accumulated on sustain electrodes SU1 to SUn and data electrodes D1 to Dm. The Here, the wall voltage on the electrode refers to a voltage generated by wall charges accumulated on the dielectric layer covering the electrode, the phosphor layer, or the like.

  Subsequently, in the second half of the initialization period, sustain electrodes SU1 to SUn are maintained at positive voltage Ve1, and a ramp voltage that gradually decreases from voltage Vi3 to voltage Vi4 is applied to scan electrodes SC1 to SCn. Then, a weak initializing discharge occurs again in all the discharge cells, the wall voltage between scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn is weakened, and the positive wall voltage on data electrodes D1 to Dm is reduced. Is adjusted to a value suitable for the write operation.

  In the present embodiment, the initializing operation in the first subfield is an all-cell initializing operation in which initializing discharge is performed on all discharge cells.

  In the subsequent address period, sustain electrodes SU1 to SUn are held at voltage Ve2, and scan electrodes SC1 to SCn are held at Vc. Next, a negative scan pulse voltage Va is applied to scan electrode SC1 in the first row, and data electrode Dk (k = 1 to m) of the discharge cell to be displayed in the first row among data electrodes D1 to Dm. A positive address pulse voltage Vd is applied. At this time, the voltage at the intersection of the data electrode Dk and the scan electrode SC1 is obtained by adding the wall voltage on the data electrode Dk and the wall voltage on the scan electrode SC1 to the externally applied voltage (Vd−Va). The starting voltage is exceeded. Then, an address discharge occurs between data electrode Dk and scan electrode SC1 and between sustain electrode SU1 and scan electrode SC1, and a positive wall voltage is accumulated on scan electrode SC1 of this discharge cell, and on sustain electrode SU1. And a negative wall voltage is also accumulated on the data electrode Dk. In this manner, an address operation is performed in which address discharge is caused in the discharge cells to be displayed in the first row and wall voltage is accumulated on each electrode. On the other hand, the voltage at the intersection of the data electrodes D1 to Dm to which the address pulse voltage Vd is not applied and the scan electrode SC1 does not exceed the discharge start voltage, so that address discharge does not occur. The above address operation is sequentially performed until the discharge cell in the nth row, and the address period ends.

  In the subsequent sustain period, driving is performed using a power recovery circuit in order to reduce power consumption. The details of the drive voltage waveform will be described later, and here, the outline of the sustain operation in the sustain period will be described. First, positive sustain pulse voltage Vs is applied to scan electrodes SC1 to SCn, and a ground potential, that is, 0 V is applied to sustain electrodes SU1 to SUn. Then, in the discharge cell in which the address discharge has occurred, the voltage between scan electrode SCi and sustain electrode SUi is the sum of sustain pulse voltage Vs and the wall voltage on scan electrode SCi and the wall voltage on sustain electrode SUi. Exceeding the discharge start voltage. Then, a sustain discharge occurs between scan electrode SCi and sustain electrode SUi, and phosphor layer 35 emits light by the ultraviolet rays generated at this time. Then, a negative wall voltage is accumulated on scan electrode SCi, and a positive wall voltage is accumulated on sustain electrode SUi. Further, a positive wall voltage is accumulated on the data electrode Dk. In the discharge cells in which no address discharge has occurred during the address period, no sustain discharge occurs, and the wall voltage at the end of the initialization period is maintained.

  Subsequently, 0 V is applied to scan electrodes SC1 to SCn, and sustain pulse voltage Vs is applied to sustain electrodes SU1 to SUn. Then, in the discharge cell in which the sustain discharge has occurred, since the voltage between sustain electrode SUi and scan electrode SCi exceeds the discharge start voltage, a sustain discharge occurs again between sustain electrode SUi and scan electrode SCi, and the sustain cell is maintained. Negative wall voltage is accumulated on electrode SUi, and positive wall voltage is accumulated on scan electrode SCi. Thereafter, similarly, the number of sustain pulse voltages corresponding to the luminance weight is alternately applied to scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn, and a potential difference is applied between the electrodes of the display electrode pair, thereby writing in the write period. The sustain discharge is continuously performed in the discharge cell that has caused the discharge.

  Note that at the end of the sustain period, a potential difference in the form of a narrow pulse is applied between scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn, and the positive wall charges on data electrode Dk are left while scanning. The wall voltage on the electrode SCi and the sustain electrode SUi is erased. Specifically, sustain electrodes SU1 to SUn are temporarily returned to 0V while scan electrodes SC1 to SCn are held at 0V. Then, sustain pulse voltage Vs is applied to scan electrodes SC1 to SCn. Then, a sustain discharge occurs between sustain electrode SUi and scan electrode SCi in the discharge cell in which the sustain discharge has occurred. Although details will be described later, in the present embodiment, the discharge at this time is a continuous discharge of two times (hereinafter abbreviated as “two peaks”) consisting of a first discharge and a second discharge. It is controlled to become. The voltage Ve1 is applied to the sustain electrodes SU1 to SUn before the discharge converges, that is, while charged particles generated by the discharge remain sufficiently in the discharge space. That is, the potential difference between the electrodes of sustain electrode SUi and scan electrode SCi is weakened to the extent of (Vs−Ve1). Then, the wall voltage between the scan electrodes SC1 to SCn and the sustain electrodes SU1 to SUn is the difference between the voltages applied to the respective electrodes (Vs−Ve1) while leaving the positive wall charges on the data electrode Dk. It is weakened to the extent of. Hereinafter, this discharge is referred to as “erase discharge”. Thus, the last sustain discharge in the sustain period in the present embodiment is two erasure discharges. Thus, the maintenance operation in the maintenance period is completed.

  In the initializing period of the second subfield, sustain electrodes SU1 to SUn are held at voltage Ve1, and data electrodes D1 to Dm are held at 0 V, respectively, and scan electrodes SC1 to SCn gradually drop from voltage Vi3 ′ to voltage Vi4. Apply the ramp voltage. Then, a weak initializing discharge is generated in the discharge cell in which the sustain discharge has been performed in the sustain period of the previous subfield, and the wall voltage on scan electrode SCi and sustain electrode SUi is weakened. For data electrode Dk, since the positive wall voltage is sufficiently accumulated on data electrode Dk in the immediately preceding sustain period, an excessive portion of this wall voltage is discharged, and the wall voltage suitable for the write operation is obtained. Adjusted to On the other hand, discharge cells that have not undergone sustain discharge in the previous subfield are not discharged, and the wall charges at the end of the initialization period of the previous subfield are maintained.

  As described above, the initializing operation of the second subfield is a selective initializing operation in which initializing discharge is selectively performed on the discharge cells that have undergone the sustain operation in the sustain period of the immediately preceding subfield.

  Since the operation in the writing period of the second subfield is the same as that of the first subfield, description thereof is omitted. The operation in the subsequent sustain period is the same as that in the first subfield except for the number of sustain pulses. In the subsequent subfields after the third subfield, substantially the same operation as in the second subfield is performed.

  In the present embodiment, it has been described that the all-cell initialization operation is performed in the initialization period of the first subfield and the selective initialization operation is performed in the initialization period of the second subfield. The invention is not limited to this, and the all-cell initializing operation and the selective initializing operation may be arbitrarily performed in each subfield.

  Next, details of the operation in the sustain period will be described. First, details of sustain pulse generators 100 and 200, which are drive circuits for applying a sustain pulse to display electrode pairs to sustain discharge the discharge cells, will be described. FIG. 5 is a circuit diagram of sustain pulse generators 100 and 200 of the plasma display device in accordance with the exemplary embodiment of the present invention. Sustain pulse generation unit 100 includes power recovery unit 110 and clamp unit 120. The power recovery unit 110 includes a power recovery capacitor C10, switching elements Q11 and Q12, backflow prevention diodes D11 and D12, and a power recovery inductor L10. The clamp unit 120 includes a power source VS having a voltage value Vs, and switching elements Q13 and Q14. The power recovery unit 110 and the clamp unit 120 are connected to the scan electrode 22 which is one end of the interelectrode capacitance Cp of the panel 10 via a scan pulse generation circuit. In FIG. 5, the scan pulse generating circuit is not shown. Capacitor C10 has a sufficiently large capacity compared to interelectrode capacity Cp, is charged to a voltage value of approximately Vs / 2, and functions as a power source for power recovery unit 110.

  Sustain pulse generator 200 has the same circuit configuration as sustain pulse generator 100, and includes power recovery capacitor C20, switching elements Q21 and Q22, backflow prevention diodes D21 and D22, and power recovery inductor L20. A recovery unit 210 and a clamp unit 220 having a power source VS and switching elements Q23 and Q24 are provided, and the output of the sustain pulse generator 200 is connected to the sustain electrode 23 which is the other end of the interelectrode capacitance Cp of the panel 10. For later explanation, FIG. 5 also shows a power supply VE for applying the voltage Ve1 to the sustain electrode 23, a switching element Q29, and a backflow prevention diode D29.

  Next, details of the drive voltage waveform will be described. FIG. 6 is a timing chart for explaining the operation of sustain pulse generating units 100 and 200 of the plasma display device in accordance with the exemplary embodiment of the present invention. One period of the sustain pulse is divided into six periods indicated by T1 to T6, and each period will be described.

(Period T1)
At time t1, switching element Q12 is turned on. Then, the charge on the scan electrode 22 side starts to flow to the capacitor C10 through the inductor L10, the diode D12, and the switching element Q12, and the voltage of the scan electrode 22 starts to decrease.

(Period T2)
Since the inductor L10 and the interelectrode capacitance Cp form a resonance circuit, the voltage of the scan electrode 22 decreases to around 0 V at time t2 after the time ½ of the resonance period has elapsed. However, due to power loss due to the resistance component of the resonance circuit, the voltage of the scan electrode 22 cannot be reduced to 0V. At time t2, switching element Q14 is turned on. Then, since scan electrode 22 is grounded through switching element Q14, the voltage of scan electrode 22 is forcibly lowered to 0V.

  Further, the switching element Q21 is turned ON at time t2. Then, current starts to flow from the power recovery capacitor C20 through the switching element Q21, the diode D21, and the inductor L20, and the voltage of the sustain electrode 23 starts to rise. In the present embodiment, the above-described resonance period is set to about 1200 ns, and the time from time t1 to time t2, that is, the time period T1 is set to 550 ns.

(Period T3)
Since the inductor L20 and the interelectrode capacitance Cp form a resonance circuit, the voltage of the sustain electrode 23 rises to near Vs at time t3 after the time ½ of the resonance period has elapsed, but the resistance component of the resonance circuit Therefore, the voltage of the sustain electrode 23 cannot be increased to Vs. At time t3, switching element Q23 is turned on. Then, since sustain electrode 23 is directly connected to power supply VS through switching element Q23, the voltage of sustain electrode 23 is forcibly increased to Vs. Then, in the discharge cell in which the address discharge has occurred, the voltage between the scan electrode 22 and the sustain electrode 23 exceeds the discharge start voltage, and a sustain discharge occurs.

  Switching element Q12 may be turned off after time t2 and before time t5, and switching element Q21 may be turned off after time t3 and before time t4. In order to lower the output impedance of sustain pulse generating units 100 and 200, switching element Q14 is preferably turned off immediately before time t5 and switching element Q23 is turned off immediately before time t4.

(Period T4-T6)
Since the sustain pulse applied to scan electrode 22 and the sustain pulse applied to sustain electrode 23 have the same waveform, the operation from period T4 to period T6 is the same as operation from period T1 to period T3. Since it is equivalent to the operation of replacing the electrode 23, the description thereof is omitted.

  The operations in the above periods T1 to T6 are repeated according to the required number of pulses. Note that in this embodiment, the time periods T2, T4, and T5 are set to 550 ns, similarly to the time period T1. In addition, the time periods T3 and T6 are set to 1450 ns.

  Next, a sustain pulse for giving a potential difference for generating the last sustain discharge in the sustain period between the electrodes of the display electrode pair will be described in detail.

(Period T7)
This period is the fall of the sustain pulse applied to the sustain electrode 23, and is the same as the period T4. That is, when switching element Q22 is turned on at time t7, the charge on sustain electrode 23 side begins to flow to capacitor C20 through inductor L20, diode D22, and switching element Q22, and the voltage of sustain electrode 23 begins to drop.

(Period T8)
At time t8, switching element Q24 is turned on to forcibly reduce the voltage of sustain electrode 23 to 0V.

(Period T9)
At time t9, the switching element Q11 is turned on. Then, current starts to flow from the power recovery capacitor C10 through the switching element Q11, the diode D11, and the inductor L10, and the voltage of the scan electrode 22 starts to rise. Since the inductor L10 and the interelectrode capacitance Cp form a resonance circuit, the voltage of the scan electrode 22 rises to near Vs after a time ½ of the resonance period has elapsed. If the voltage rising at this time is sufficiently high, the voltage between scan electrode 22 and sustain electrode 23 exceeds the discharge start voltage in the discharge cell in which the sustain discharge has occurred, and a first discharge is generated. Then, the voltage of the scan electrode 22 starts to decrease rapidly.

(Period T10)
At time t10 after the first discharge is generated, switching element Q13 is turned on. Then, the scan electrode 22 is directly connected to the power source VS through the switching element Q13, and the voltage of the scan electrode 22 rises steeply to Vs. Then, a voltage is applied again to the discharge space where sufficient charged particles exist before the first discharge converges, and a second discharge is generated in the discharge cell that caused the first discharge. The discharge at this time is very strong because the voltage rises sharply in a short time. In the present embodiment, the time from time t9 to time t10, that is, the time period T9 is set to 900 ns.

(Period T11)
The switching element Q29 is turned ON before the second discharge generated in the period T10 converges, that is, at time t11 when charged particles generated in the second discharge remain sufficiently in the discharge space. Then, since sustain electrode 23 is directly connected to erasing power source VE through switching element Q29 and diode D29, the voltage of sustain electrode 23 is forcibly increased to Ve1. Then, although the electric field in the discharge space changes, charged particles generated by the discharge generated in the period T10 are rearranged to form wall charges so as to relax the changed electric field. At this time, since the difference between the voltage Vs applied to scan electrode 22 and voltage Ve1 applied to sustain electrode 23 is small, the wall voltage on scan electrode 22 and sustain electrode 23 is weakened. Thus, the potential difference that generates the last sustain discharge is a narrow pulse-shaped potential difference that is changed so as to relax the potential difference applied between the electrodes of the display electrode pair before the last sustain discharge converges. The sustain discharge to be performed is an erasing discharge of two peaks. Further, the data electrode 32 is held at 0 V at this time, and the charged particles caused by the discharge have wall charges so as to reduce the potential difference between the voltage applied to the data electrode 32 and the voltage applied to the scanning electrode 22. As a result, a positive wall voltage is formed on the data electrode 32.

  As described above, sustain pulse generating units 100 and 200 charge and discharge each of the display electrode pairs by applying resonance between the capacitance between the electrodes of the display electrode pair and the power recovery inductor, and apply a voltage to the display electrode pair. It has a power recovery unit and a clamp unit that is connected to a predetermined power source or ground potential and applies a voltage to the display electrode pair. Then, the last sustain discharge in the sustain period starts with a voltage applied to one of the display electrode pair using the power recovery unit in a period longer than ½ of the resonance period of the power recovery unit. Is applied to generate a second discharge by further applying a voltage to one of the display electrode pair, in the present embodiment, the scanning electrode 22 using the clamp portion. This is a discharge of two mountains.

  In the present embodiment, the time of the period T10 is set to 400 ns as the time that the charged particles generated by the discharge remain sufficiently in the discharge space. However, this time is preferably set between 100 ns and 900 ns, although it depends on the discharge characteristics of the discharge cell and the intensity of discharge. This is because when the time is shorter than 100 ns, the discharge itself is weak and unstable, and when the time is longer than 900 ns, the charged particles generated by the discharge recombine and the charged particles remaining in the discharge space are insufficient.

  Although the mechanism of the occurrence of the discharge failure is not completely clarified, as described above, the last discharge in the sustain period is applied to the display electrode pair by using the power recovery unit to apply the first discharge. The inventors of the present invention have found that the discharge failure can be suppressed by applying two voltages to the display electrode pair by using the clamp portion and generating a second discharge that generates the second discharge. Confirmed experimentally. FIG. 7 shows experimental data showing the relationship between the drive timing and the drive voltage at that time. FIG. 7A shows the relationship between the time of the period T9 and the upper limit value of the sustain pulse voltage Vs, and FIG. The relationship between the time of T9 and the lower limit value of the voltage Ve1 applied to the sustain electrode is shown. The discharge failure is likely to occur when the sustain pulse voltage Vs is set high, and the discharge failure occurs when driven at a voltage higher than the sustain pulse voltage Vs shown in FIG. Therefore, FIG. 7A shows that the drive margin of the sustain pulse voltage Vs increases when the period T9 is extended. As described above, it was experimentally confirmed that the period T9 may be set longer in order to prevent discharge failure. On the other hand, as shown in FIG. 7B, if the time period T9 is extended, the voltage Ve1 to be applied to the sustain electrodes also increases. Therefore, it is desirable not to extend the time period T9 more than necessary. From the above viewpoint, in the present embodiment, the time period T9 is set between 650 ns and 750 ns. However, it is desirable that this value is optimally set in a period longer than ½ of the resonance period of the power recovery unit based on the discharge characteristics of the panel.

  Note that the time values of the periods T1 to T11 illustrated in the present embodiment are examples, and are not limited to these values, and are desirably set according to the discharge characteristics of the panel.

  The panel driving method of the present invention is capable of driving a panel with high image display quality without causing defective discharge even in a high-luminance and high-definition panel, and is used for a plasma display device using the panel. And useful.

The disassembled perspective view which shows the principal part of the panel used for embodiment of this invention. Electrode arrangement of the panel Circuit block diagram of plasma display device using the panel The figure which shows the drive voltage waveform impressed to each electrode of the panel Circuit diagram of sustain pulse generator of plasma display device using the panel Timing chart for explaining a panel driving method according to an embodiment of the present invention The figure which showed the experimental data which shows the relationship between the drive timing and the drive voltage at that time

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Panel 22 Scan electrode 23 Sustain electrode 32 Data electrode 51 Image signal processing circuit 52 Data electrode drive circuit 53 Scan electrode drive circuit 54 Sustain electrode drive circuit 55 Timing generation circuit 100,200 Sustain pulse generation part 110,210 Power recovery part 120, 220 Clamp part

Claims (4)

A method of driving a plasma display panel comprising a plurality of discharge cells having a display electrode pair consisting of a scan electrode and a sustain electrode,
A sustain pulse generator for sustaining and discharging the discharge cells by applying a sustain pulse to the display electrode pair in the sustain period;
The sustain pulse generator is connected to a power recovery unit that applies a voltage to the display electrode pair by resonance between a capacitance between the electrodes of the display electrode pair and a power recovery inductor, and a predetermined power source or ground potential. And a clamp part for applying a voltage to the display electrode pair,
At the end of the sustain period, a voltage is applied to the display electrode pair using the power recovery unit to generate a first discharge, and then a voltage is further applied to the display electrode pair using the clamp unit. And generating a second discharge. A method for driving a plasma display panel, comprising: A voltage is applied to the display electrode pair so as to relieve a potential difference between the electrodes of the display electrode pair after the second discharge is generated and before the second discharge converges. Item 8. A driving method of a plasma display panel according to Item 1. The time from when the voltage is started to be applied to the display electrode pair using the power recovery unit until the voltage is further applied to the display electrode pair using the clamp unit is 650 ns to 750 ns. The method for driving a plasma display panel according to claim 1 or 2. The voltage is applied to the display electrode pair so that the potential difference between the electrodes of the display electrode pair is relaxed between 100 ns and 900 ns after the second discharge is generated. Item 4. A driving method of a plasma display panel according to Item 3.

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