JP2007105921A - Print head and image forming apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To set the quantities of light from all LEDs within a redetermined range, in an LED print head compatible with higher definition. <P>SOLUTION: This print head comprises: a signal generating circuit 100 which outputs a lighting signal ΦI for making the LED emit the light is output, and which control the quantity of the light from the LED by fixing the pulse duration of the lighting signal ΦI to a predetermined value or changing the pulse duration of the lighting signal ΦI in a range including or exceeding the predetermined value; and a power supply voltage control part 119 for changing a value Vsub of a power supply voltage supplied to the LED, when the circuit 100 makes the pulse duration of the lighting signal ΦI fixed to the predetermined value. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a print head used for a print head of an image forming apparatus such as a copying machine or a printer, and more particularly to a print head using an LED as a light emitting element.

  In recent years, an LED print head (LPH: LED Print Head) composed of a self-scanning LED (SLED) array is used as a print head for an image forming apparatus such as an electrophotographic copying machine or printer. ) Has been developed. Such an SLED can employ a thyristor structure in a switching unit that selectively turns on and off an LED, which is a light emitting element, so that the switching unit and the LED can be arranged on the same chip. In addition, since the LED can be driven by two signal lines that transmit a timing signal for setting the LED to an on / off state and one signal line that transmits an image signal to the LED. It is also possible to simplify the wiring. Therefore, LPH using SLED is a very effective print head for downsizing the apparatus.

In such SLED, each LED is transmitted by transmitting (scanning) the lighting-enabled state (on state) of each LED one after another by a switching unit having a thyristor structure, and transmitting a pulse width modulated image signal in synchronization therewith. Lights up. Therefore, the amount of light emitted from each LED of the SLED is set by the pulse width of the image signal.
However, in each LED in the SLED, even if a signal having the same pulse width is received as an image signal, the amount of emitted light of each LED generally differs. That is, the amount of LED light emitted from the LPH varies due to differences in emission characteristics of the LEDs due to manufacturing variations, variations in the arrangement positions of the LEDs, and the like. In an LPH with a structure in which LEDs are arranged in a line in the main scanning direction, variations in the amount of light of each LED have a large effect on image quality, and image quality defects such as streaks along the sub-scanning direction and density unevenness in the main scanning direction Will be generated. Therefore, it is necessary to correct the light amount of each LED arranged in the LPH so that the light amounts of all the LEDs are within a predetermined range.

  Therefore, as a conventional technique for correcting the light amount of each light emitting element, correction data corresponding to the arrangement position of the LED on the chip is stored in advance, and lighting for each pixel (LED) is performed based on this correction data. There is a technique for reducing variation in the amount of light of each LED by correcting the time (pulse width) (see, for example, Patent Document 1).

JP 2000-246957 A (pages 7-8)

However, when trying to achieve high image resolution in an image forming apparatus equipped with LPH using SLED, the resolution in the sub-scanning direction is also reduced, so the pulse width of the image signal that lights each LED The (lighting time) is extremely short.
Here, a specific example will be described. For example, if the resolution in the sub-scanning direction is 4800 dpi and the process speed of the image forming apparatus is 200 mm / sec, the driving cycle per pixel in LPH is about 206 nsec. Among them, the transfer time in the switching unit (thyristor) is 50 nsec. In the LPH, in order to perform light amount correction of each LED, a light amount correction width by a pulse width is provided. Usually, the light amount correction width is set to maximum correction value / minimum correction value = 2. Further, an adjustment range for adjusting the total light amount of LPH is also set in LPH. Normally, the total light amount adjustment range is set to maximum reference light amount / minimum reference light amount = 3. Then, while the maximum lighting time of each LED is (206-50) nsec, the minimum lighting time is the light amount correction and the total light amount adjustment of each LED, so (206-50) · (1 / 2) · (1/3) = 26 nsec.

As described above, when the pulse width (lighting time) of the image signal is shortened to a level of 26 nsec, it is relatively greatly affected by the inductance and capacity of the signal line itself, and the output waveform from the drive circuit that drives the SLED is increased. Distortion becomes relatively large.
For this reason, in a high-resolution image forming apparatus, when the total light amount of LPH is set to be small in response to the sensitivity change of the photoconductor, etc., it is caused by distortion of the output waveform of the image signal that lights each LED from the drive circuit. As a result, there is a problem that the variation in the amount of light between the LEDs increases. As a result, there is a risk that image defects such as streaks and image density unevenness may occur in the formed image when setting a high light amount with a low resolution.
Note that the variation in the amount of light between the LEDs that occurs when the high resolution and low light amount is set is due to distortion of the output waveform caused by the circuit configuration. Therefore, as in the technique described in Patent Document 1 above, the variation in the amount of light between the LEDs is eliminated simply by correcting the lighting time (pulse width) for each pixel based on the correction data for each LED. Can not do it.

  Accordingly, the present invention has been made to solve the technical problems as described above, and an object of the present invention is to achieve a high resolution LED print head in which the light amounts of all LEDs are within a predetermined range. It is set to fit in.

  For this purpose, the print head of the present invention is a print head that exposes an image carrier in an image forming apparatus, and includes a plurality of light emitting elements arranged in a line and a light emitting element for the light emitting elements. A driving circuit that outputs a lighting signal to emit light and fixes the pulse width of the lighting signal to a predetermined value or changes it in a region that is equal to or larger than the predetermined value, and a lighting signal by the driving circuit And a voltage supply unit that changes a power supply voltage value supplied to the light emitting element when the pulse width is fixed to the predetermined value.

Here, the voltage supply unit can set the power supply voltage value based on an instruction signal that instructs the light amount of the entire light emitting element from the image forming apparatus. In addition, the voltage supply unit may be characterized in that the power supply voltage value is fixed to the above-described predetermined value when the drive circuit changes the pulse width of the lighting signal in a region of a predetermined value or more.
In addition, the drive circuit may be characterized in that the pulse width is set based on an instruction signal that instructs the light amount of the entire light emitting element from the image forming apparatus. Further, when the drive circuit receives an instruction signal for setting the light amount of the entire light emitting element to a predetermined value or more from the image forming apparatus, the drive circuit changes the pulse width based on the instruction signal in the region of the predetermined value or more. It can also be a feature. In addition, the drive circuit may be characterized by fixing the pulse width to the predetermined value when receiving an instruction signal for setting the light amount of the entire light emitting element to be smaller than a predetermined value from the image forming apparatus. .
The voltage supply unit includes a DA converter that converts an instruction signal that instructs the light amount of the entire light emitting element from the image forming apparatus into a voltage value, and a regulator that changes an output voltage according to the voltage value from the DA converter. Can be characterized. In particular, the voltage supply unit may change the output voltage by changing a voltage dividing resistance value provided in the regulator.

Further, the present invention is regarded as an image forming apparatus, and the image forming apparatus of the present invention includes a photosensitive member, a print head that exposes the photosensitive member, and a control unit that outputs an instruction signal that indicates the total light amount of the print head. The print head outputs a plurality of light emitting elements arranged in a line and a lighting signal for causing the light emitting elements to emit light, and sets a pulse width of the lighting signal based on an instruction signal from the control unit. A driving circuit that is fixed to a predetermined value or changed in a region that is equal to or greater than the predetermined value, and a power supply voltage value that is supplied to the light emitting element when the pulse width of the lighting signal is fixed to the predetermined value by the driving circuit. And a voltage supply unit to be changed.
Here, when receiving an instruction signal for setting the total light amount of the print head smaller than a predetermined value from the control unit, the drive circuit fixes the pulse width to the predetermined value based on the instruction signal. be able to. When receiving an instruction signal for setting the total light amount of the print head to a predetermined value or more from the control unit, the drive circuit changes the pulse width based on the instruction signal, and the voltage supply unit sets the power supply voltage value to the predetermined value. It can also be characterized by being fixed to.

  According to the present invention, even when the resolution of the image forming apparatus is increased, the amount of light of all the LEDs in the LED print head is within a predetermined range. It becomes possible to obtain a high-quality image without unevenness.

Embodiments of the present invention will be described below in detail with reference to the accompanying drawings.
FIG. 1 is a diagram showing an overall configuration of an image forming apparatus using an LED print head to be measured in the present embodiment. The image forming apparatus shown in FIG. 1 is a so-called tandem digital color printer 1, and includes an image forming process unit 10 that forms an image corresponding to image data of each color, a control unit 30 that controls the image forming process unit 10, For example, an image processing unit (IPS: Image Processing System) 40 that is connected to a personal computer (PC) 2 and an image reading device (IIT) 3 and performs predetermined image processing on image data received from these devices is provided. .

The image forming process unit 10 includes four image forming units 11Y, 11M, 11C, and 11K that are arranged in parallel at a predetermined interval. The image forming units 11Y, 11M, 11C, and 11K uniformly charge the surface of the photosensitive drum 12 as an image carrier that forms an electrostatic latent image and carries a toner image with a predetermined potential. The charger 13, the LED print head (LPH) 14 as an exposure device that exposes the photosensitive drum 12 charged by the charger 13, the developing device 15 that develops the electrostatic latent image obtained by the LPH 14, and the photosensitive after transfer A cleaner 16 for cleaning the surface of the body drum 12 is provided.
Further, a density detection circuit 17 that detects the toner image density of a test patch (density sample) formed on the photosensitive drum 12 is provided in the vicinity of the downstream side of the developing device 15 so as to face the photosensitive drum 12. It has been. The density detection circuit 17 is connected to the control unit 30 and outputs a toner image density detection value.
Here, the image forming units 11Y, 11M, 11C, and 11K are configured in substantially the same manner except for the toner stored in the developing unit 15. The image forming units 11Y, 11M, 11C, and 11K respectively form yellow (Y), magenta (M), cyan (C), and black (K) toner images.

  In addition, the image forming process unit 10 includes an intermediate transfer belt 21 to which the toner images of the respective colors formed on the photosensitive drums 12 of the image forming units 11Y, 11M, 11C, and 11K are transferred in a multiple manner, and the image forming units 11Y and 11Y. A primary transfer roll 22 as a primary transfer charger for sequentially transferring (primary transfer) each color toner image of 11M, 11C, and 11K to the intermediate transfer belt 21, and a superimposed toner image transferred onto the intermediate transfer belt 21 as a recording material (recording) A secondary transfer roll 23 serving as a secondary transfer charger that performs batch transfer (secondary transfer) on the paper P, which is a paper, and a fixing device 25 that fixes the secondary transferred image on the paper P.

  In the digital color printer 1 of the present embodiment, the image forming process unit 10 performs an image forming operation based on a control signal such as a synchronization signal supplied from the control unit 30. At that time, the image data input from the PC 2 or IIT 3 is subjected to image processing by the image processing unit 40 and supplied to each of the image forming units 11Y, 11M, 11C, and 11K via the interface. In the yellow image forming unit 11Y, for example, the surface of the photosensitive drum 12 uniformly charged at a predetermined potential by the charger 13 is exposed by the LPH 14 that emits light based on the image data obtained from the image processing unit 40. Thus, an electrostatic latent image is formed on the photosensitive drum 12. The formed electrostatic latent image is developed by the developing device 15, and a yellow toner image is formed on the photosensitive drum 12. Similarly, magenta, cyan, and black toner images are formed in the image forming units 11M, 11C, and 11K.

The color toner images formed by the image forming units 11Y, 11M, 11C, and 11K are sequentially electrostatically attracted by the primary transfer roll 22 onto the intermediate transfer belt 21 that rotates in the direction of arrow A in FIG. A toner image superimposed on the belt 21 is formed. The superimposed toner image is conveyed to a region (secondary transfer portion) where the secondary transfer roll 23 is disposed as the intermediate transfer belt 21 moves. When the superimposed toner image is conveyed to the secondary transfer unit, the paper P is supplied to the secondary transfer unit in accordance with the timing at which the toner image is conveyed to the secondary transfer unit. Then, the superimposed toner images are collectively electrostatically transferred onto the conveyed paper P by the transfer electric field formed by the secondary transfer roll 23 in the secondary transfer portion.
Thereafter, the sheet P on which the superimposed toner image has been electrostatically transferred is peeled off from the intermediate transfer belt 21 and conveyed to the fixing device 25 by the conveying belt 24. The unfixed toner image on the paper P conveyed to the fixing device 25 is fixed on the paper P by being subjected to a fixing process by heat and pressure by the fixing device 25. Then, the paper P on which the fixed image is formed is conveyed to a paper discharge mounting portion (not shown) provided in the discharge portion of the image forming apparatus.

  FIG. 2 is a view showing a configuration of an LED print head (LPH) 14 that is an exposure unit. 2, the LPH 14 includes a housing 61 as a support, a self-scanning LED array (SLED) 63 constituting a light emitting unit, and a drive circuit (signal generation circuit) 100 (drive signal generation means for driving the SLED 63 and SLED 63). The LED circuit board 62 and the rod lens array 64, which are optical members for forming an image of the light from the SLED 63 on the surface of the photosensitive drum 12, and the rod lens array 64 are supported from the outside. A shielding holder 65 and a leaf spring 66 for urging the housing 61 toward the rod lens array 64 are provided.

The housing 61 is formed of a block or sheet metal such as aluminum or SUS, and supports the LED circuit board 62. The holder 65 supports the housing 61 and the rod lens array 64, and is set so that the light emitting point of the SLED 63 and the focal point of the rod lens array 64 coincide. Furthermore, the holder 65 is configured to seal the SLED 63. Therefore, it is possible to prevent dust from adhering to the SLED 63 from the outside. On the other hand, the leaf spring 66 urges the LED circuit board 62 toward the rod lens array 64 via the housing 61 so as to maintain the positional relationship between the SLED 63 and the rod lens array 64.
The LPH 14 configured as described above is configured to be movable in the optical axis direction of the rod lens array 64 by an adjustment screw (not shown), and the imaging position (focal plane) of the rod lens array 64 is the surface of the photosensitive drum 12. It is adjusted so that it is located above.

As shown in FIG. 3 (plan view of the LED circuit board 62), the LED circuit board 62 includes, for example, SLEDs 63 composed of 58 SLED chips (CHIP1 to CHIP58) in parallel with the axial direction of the photosensitive drum 12. It is arranged in a row with high accuracy. In this case, as shown in FIG. 4 (a diagram for explaining a connecting portion of each SLED chip), each LED array is connected to each other at the end boundary of the LED array arranged in each SLED chip (CHIP1 to CHIP58). The SLED chips are alternately arranged in a staggered manner so as to be continuously arranged at the connecting portions. In FIG. 4, a connecting part of CHIP1, CHIP2, and CHIP3 is shown as an example.
The LED circuit board 62 includes a signal generation circuit 100, a level shift circuit 104, a three-terminal regulator 101 that outputs a power supply voltage, an EEPROM 102 that stores light amount correction value data in the SLED 63, and the digital color printer 1 main body. A harness 103 for transmitting and receiving signals is provided.

Next, the wiring configuration on the LED circuit board 62 will be described.
FIG. 5 is a diagram showing a wiring diagram formed on the LED circuit board 62. As shown in FIG. 5, on the LED circuit board 62, a + 3.8V power line 105 that supplies power to each SLED chip, a grounded (GND) power line 106, and each SLED chip from the signal generation circuit 100. Signal lines 107 (107_1 to 107_58) for transmitting lighting signals ΦI (ΦI1 to ΦI58), signal lines 108 (108_1 to 108_6) for transmitting transfer signals CK1 (CK1_1 to 1_6), and transfer signals CK2 (CK2_1 to 2_6) ) For transmitting signal lines 109 (109_1 to 109_6).
And the lighting signal (PHI) I with respect to CHIP1-CHIP58 is input into each SLED chip (CHIP1-CHIP58) via the signal line 107. FIG. Further, the transfer signal CK1 (CK1_1 to 1_6) is input to the CHIP1 to CHIP58 via the signal line 108, and the transfer signal CK2 (CK2_1 to 2_6) is input to the CHIP1 to CHIP58 via the signal line 108, respectively.

Next, the circuit configuration of the SLED 63 will be described.
FIG. 6 is a diagram for explaining the circuit configuration of the SLED 63. The SLED 63 of this embodiment is connected to the signal generation circuit 100 via the level shift circuit 104. The level shift circuit 104 has a configuration in which a resistor R1B and a capacitor C1, and a resistor R2B and a capacitor C2 are arranged in parallel, one end of each being connected to the input terminal of the SLED 63, and the other end of the signal generating circuit 100. Connected to the output terminal. Based on the transfer signals CK1R and CK1C and the transfer signals CK2R and CK2C output from the signal generation circuit 100, the transfer signal CK1 and the transfer signal CK2 are output to the SLED 63.
In addition, although 58 SLED chips are arranged in series in the SLED 63 of the present embodiment, only one SLED chip is shown in FIG. In the following description, the SLED chip is referred to as SLED 63 for convenience.

As shown in FIG. 6, the SLED 63 includes 128 thyristors S1 to S128 as switching elements, 128 LEDs L1 to L128 as light emitting elements, 128 diodes D1 to D128, and 128 resistors R1 to R128. In addition, the transfer current limiting resistors R1A and R2A are configured to prevent an excessive current from flowing through the signal line.
Here, a part mainly composed of thyristors S1 to S128 and diodes D1 to D128 for controlling supply of current to the LEDs L1 to L128 is referred to as a transfer unit.

In the SLED 63 of the present embodiment, the anode terminals (input terminals) A1 to A128 of the thyristors S1 to S128 are connected to the power supply line 105. A power supply voltage Vsub (= + 3.8 V) is supplied to the power supply line 105.
A transfer signal CK1 is transmitted from the signal generation circuit 100 to the cathode terminals (output terminals) K1, K3,..., K127 of the odd-numbered thyristors S1, S3,. Is done.
.., S128 to the even-numbered thyristors S2, S4,..., S128 from the signal generation circuit 100 through the level shift circuit 104 and the transfer current limiting resistor R2A. CK2 is transmitted.

On the other hand, gate terminals (control terminals) G1 to G128 of the thyristors S1 to S128 are respectively connected to the power supply line 106 via resistors R1 to R128 provided corresponding to the thyristors S1 to S128. The power supply line 106 is grounded (GND).
The gate terminals G1 to G128 of the thyristors S1 to S128 are connected to the gate terminals of the LEDs L1 to L128 provided corresponding to the thyristors S1 to S128, respectively.
Furthermore, the cathode terminals of the diodes D1 to D128 are connected to the gate terminals G1 to G128 of the thyristors S1 to S128. The gate terminals G1 to G127 of the thyristors S1 to S127 are connected to the anode terminals of the next-stage diodes D2 to D128, respectively. That is, the diodes D1 to D128 are connected in series with the gate terminals G1 to G127 interposed therebetween.
The anode terminal of the diode D1 is connected to the signal generation circuit 100 via the transfer current limiting resistor R2A and the level shift circuit 104, and the transfer signal CK2 is transmitted. Further, the cathode terminals of the LEDs L1 to L128 are connected to the signal generation circuit 100, and the lighting signal ΦI is transmitted.

  Further, the light shielding mask 50 is disposed in the SLED 63 so as to cover the thyristors S1 to S128 and the diodes D1 to D128 in the transfer unit. This is because during the image forming operation, light emission from the thyristors S1 to S128 in the on state and current is flowing, and from the diodes D1 to D128 in the current flow state is blocked, and unnecessary light is removed from the photoconductor. It is provided to suppress exposure of the drum 12.

Next, a signal (drive signal) for driving the SLED 63 output from the signal generation circuit 100 and the level shift circuit 104 will be described.
FIG. 7 is a timing chart showing drive signals output from the signal generation circuit 100 and the level shift circuit 104. Note that the timing chart shown in FIG. 7 shows a case where all LEDs perform optical writing (light emission).
(1) First, when a reset signal (RST) is input from the image forming apparatus to the signal generation circuit 100, the signal generation circuit 100 transfers the transfer signal CK1C to a high level (hereinafter referred to as “H”) and transfers. The signal CK1R is set to “H”, the transfer signal CK1 is set to “H”, the transfer signal CK2C is set to low level (hereinafter referred to as “L”), the transfer signal CK2R is set to “L”, and the transfer signal CK2 is set. Is set to a low level (“L”), and all thyristors S1 to S128 are set to an off state (FIG. 7A).
(2) Following the reset signal (RST), the line synchronization signal Lsync output from the signal generation circuit 100 becomes “H” (FIG. 7A), and the operation of the SLED 63 is started. Then, in synchronization with the line synchronization signal Lsync, as shown in FIGS. 7E, 7F, and 7G, the transfer signal CK2C and the transfer signal CK2R are set to “H”, and the transfer signal CK2 is set to “H”. (FIG. 7B).
(3) Next, as shown in FIG. 7C, the transfer signal CK1R is set to “L” (FIG. 7C).

(4) Subsequently, as shown in FIG. 7B, the transfer signal CK1C is set to “L” (FIG. 7D).
In this state, the gate current of the thyristor S1 starts to flow. At that time, the tri-state buffer B1R of the signal generation circuit 100 is set to high impedance (Hiz) to prevent current backflow.
Thereafter, the thyristor S1 starts to be turned on by the gate current of the thyristor S1, and the gate current gradually increases. At the same time, when a current flows into the capacitor C1 of the level shift circuit 104, the potential of the transfer signal CK1 also gradually increases.

(5) After a predetermined time (the time when the transfer signal CK1 potential becomes close to GND) elapses, the tristate buffer B1R of the signal generation circuit 100 is set to “L” (FIG. 7E). As a result, the potential of the signal line Φ1 and the potential of the transfer signal CK1 rise due to the rise of the gate G1 potential, and accordingly, a current starts to flow to the resistor R1B side of the level shift circuit 104. On the other hand, the current flowing into the capacitor C1 of the level shift circuit 104 gradually decreases as the potential of the transfer signal CK1 increases.
When the thyristor S1 is completely turned on and becomes a steady state, a current for maintaining the on state of the thyristor S1 flows to the resistor R1B of the level shift circuit 104, but does not flow to the capacitor C1.
At this time, as shown in FIG. 7B, the tri-state buffer B1C of the signal generating circuit 100 is set to high impedance (Hiz) (FIG. 7E).

  (6) With the thyristor S1 completely turned on, the lighting signal ΦI is set to “L” as shown in FIG. 7H (FIG. 7F). At this time, since the potential of the gate G1> the potential of the gate G2, the LED L1 having a thyristor structure is turned on earlier and lights up. As the LED L1 is turned on, the potential of the signal line Φ1 rises, so that the LEDs after the LED L2 are not turned on. That is, for the LEDs L1, L2, L3, L4,..., Only the LED L1 having the highest gate voltage is turned on (lighted).

(7) Next, as shown in FIG. 7 (F), when the transfer signal CK2R is set to “L” (FIG. 7 (g)), a current flows as in FIG. A voltage is generated across the capacitor C2 104.
(8) As shown in FIG. 7E, when the transfer signal CK2C is set to “L” in this state (FIG. 7H), the thyristor switch S2 is turned on.
(9) Then, as shown in FIGS. 7B and 7C, when the transfer signals CK1C and CK1R are simultaneously set to “H” (FIG. 7I), the thyristor switch S1 is turned off and passes through the resistor R1. As a result, the potential of the gate G1 gradually decreases. At that time, the thyristor switch S2 is completely turned on. Therefore, by turning on / off the lighting signal ΦI corresponding to the image data from the lighting signal terminal ID, the LED L2 can be turned on / off. In this case, since the potential of the gate G1 is already lower than the potential of the gate G2, the LED L1 is not turned on.

  (10) The above-described operation is sequentially performed to sequentially turn on the LEDs L1 to L128. Then, after the “transfer operation period” in FIG. 7 in which the termination LED L128 is extinguished, the transfer signals CK1C and CK1R are set to “H”, the transfer signal CK1 is set to “H”, and the transfer signals CK2C and CK2R are set to “H”. The transfer signal CK2 is set to “H” as “H”, and both the transfer signal CK1 and the transfer signal CK2 are kept in the “H” state for a predetermined time (“transfer thyristor is turned off” in FIG. 7). As a result, all thyristors S1 to S128 are turned off. Therefore, in this state, no current flows through all the thyristors S1 to S128, so that the thyristors S1 to S128 are held in the off state (not lit).

(11) Further, after the transfer signals CK1 and CK2 are both kept at "H" for a predetermined time, the transfer signals CK2C and CK2R are set to "L" and the transfer signal CK2 is set to "L" (in FIG. 7, “Period during which no current flows through the transfer unit”). Thereby, since no current flows through the diodes D1 to D128, all the diodes D1 to D128 are also kept in the non-lighted state.
As a result, during the unsteady operation including the state where the photosensitive drum 12 (see FIG. 1) stops rotating after the lighting signal ΦI is output and the image formation is completed, the transfer unit of the SLED 63 is operated. No current is applied. Therefore, in a state where the photosensitive drum 12 stops rotating, current does not flow through the thyristors S1 to S128 and the diodes D1 to D128 arranged in the transfer unit as well as the LEDs L1 to L128, and the thyristors S1 to S128. Since no light is emitted from the diodes D1 to D128, unnecessary exposure of the photosensitive drum 12 is suppressed.

Next, the configuration of the signal generation circuit 100 will be described in detail.
FIG. 8 is a block diagram showing a configuration of the signal generation circuit 100. The signal generation circuit 100 includes an image data development unit 110, a density unevenness correction data unit 112, a timing signal generation unit 114, a reference clock generation unit 116, and lighting time control / corresponding to each SLED chip (CHIP1 to CHIP58). The driving unit 118-1 to 118-58 constitutes a main part.
Image data is serially transmitted from the image processing unit (IPS) 40 to the image data development unit 110. The image data development unit 110 divides the transmitted image data into image data for each SLED chip (CHIP1 to CHIP58) and 1st to 128th dot, 129 to 256th dot,..., 7297 to 7424th dot. The image data developing unit 110 is connected to the lighting time control / drive units 118-1 to 118-58, and outputs the divided image data to the corresponding lighting time control / drive units 118-1 to 118-58.

The density unevenness correction data unit 112 stores density unevenness correction data for correcting image density unevenness at the time of image formation caused by variations in the amount of light for each LED in the SLED 63. Then, in synchronization with the data read signal from the density unevenness correction data unit 112, the density unevenness correction data is output to the lighting time control / drive units 118-1 to 118-58. The density unevenness correction data is data set for each LED in accordance with variations in the amount of light by each LED, and is formed as 8-bit (0 to 255) data in this embodiment.
The EEPROM 102 stores light amount correction value data for each LED. When the machine power is turned on, the light amount correction value data for each LED is downloaded from the EEPROM 102 to the density unevenness correction data unit 112. Thus, the light amount correction value data is stored in the density unevenness correction data unit 112 as density unevenness correction data.

Here, the light amount correction value data for each LED stored in the EEPROM 102 is obtained as follows. The light amount correction value data for each LED is generated based on the measured light amount data by measuring the light amount of each LED with an optical profile measuring device or the like.
First, the LPH 14 is installed in the optical profile measuring device, and each LED is turned on to measure the light quantity distribution data of each LED. Then, with respect to the measured light amount distribution data, an integrated value in a direction (sub-scanning direction) orthogonal to the main scanning direction at each coordinate position in the LED arrangement direction (main scanning direction) is calculated, and the light amount in the main scanning direction. Obtain the distribution (light profile).
Subsequently, the light quantity from the valley to the valley in the light profile is integrated, and the integrated value is divided by the distance from the valley to the valley to calculate the light quantity (exposure energy) density in the area between the valleys. . The exposure energy density of each region obtained in this way is used as the correction characteristic value of each LED. Then, the amount of light is increased / decreased in accordance with the difference from the target value so that the correction characteristic value matches the predetermined target value, so that the correction characteristic value in all regions becomes flat. The light amount correction value for each area subjected to such flattening processing is used as the light amount correction value for each LED.

Next, the reference clock generator 116 is connected to the main controller 30, the timing signal generator 114, and the lighting time control / drive units 118-1 to 118-58.
As shown in FIG. 9 (a block diagram illustrating the configuration of the reference clock generation unit 116), the reference clock generation unit 116 includes a crystal oscillator 140, a frequency divider 1 / M142, a frequency divider 1 / N144, and a phase comparator. 146 and a voltage controlled oscillator 148, and a lookup table (LUT) 132.
The LUT 132 stores a table for determining the frequency division ratios M and N based on the light amount adjustment data 1 from the control unit 30. The crystal oscillator 140 is connected to the frequency divider 1 / N144, oscillates at a predetermined frequency, and outputs the oscillated signal to the frequency divider 1 / N144. The frequency divider 1 / N 144 is connected to the LUT 132 and the phase comparator 146 and divides the signal oscillated by the crystal oscillator 140 based on the frequency division ratio N determined by the light amount adjustment data 1 from the LUT 132. The phase comparator 146 is connected to the frequency divider 1 / M142, the frequency divider 1 / N144, and the voltage controlled oscillator 148, and the output signal from the frequency divider 1 / M142 and the frequency divider 1 / N144. Is compared with the output signal. The control voltage supplied to the voltage controlled oscillator 148 is controlled according to the comparison result (phase difference) by the phase comparator 146. The voltage controlled oscillator 148 outputs a reference clock signal at a frequency based on the control voltage. In the present embodiment, a control voltage corresponding to a frequency that divides the possible lighting period into 256 is supplied, and a reference clock signal having this frequency is generated, and all lighting time control / drive units 118-1 to 118-58 are generated. Output to. The voltage controlled oscillator 148 is also connected to the frequency divider 1 / M142, and the reference clock signal output from the voltage controlled oscillator 148 is also branched and input to the frequency divider 1 / M142. The frequency divider 1 / M 142 divides the reference clock signal fed back from the voltage controlled oscillator 148 based on the frequency division ratio M determined by the light amount adjustment data 1 from the LUT 132.

The timing signal generation unit 114 is connected to the control unit 30 and the reference clock generation unit 116, and is synchronized with the horizontal synchronization signal (Lsync) from the control unit 30 based on the reference clock signal from the reference clock generation unit 116. Thus, transfer signals CK1R and CK1C and transfer signals CK2R and CK2C are generated. The transfer signals CK1R and CK1C and the transfer signals CK2R and CK2C are transferred to the LPH 14 as the transfer signal CK1 and the transfer signal CK2 via the level shift circuit 104.
The timing signal generation unit 114 is connected to the density unevenness correction data unit 112 and the image data development unit 110 and is synchronized with the Lsync signal from the control unit 30 based on the reference clock signal from the reference clock generation unit 116. Then, a data read signal for reading image data corresponding to each pixel from the image data development unit 110, and data for reading density unevenness correction data corresponding to each pixel (each LED) from the density unevenness correction data unit 112 A read signal is output to each. Further, the timing signal generation unit 114 is also connected to the lighting time control / drive units 118-1 to 118-58, and based on the reference clock signal from the reference clock generation unit 116, the Lsync signal from the control unit 30. In synchronization, a trigger signal for starting lighting of the SLED 63 is output.

The lighting time control / drive units 118-1 to 118-58 correct the lighting time of each pixel (each LED) based on the density unevenness correction data and the delay selection data, and control signals for lighting each pixel of the SLED 63. Is generated.
Specifically, as shown in FIG. 10 (block diagram for explaining the configuration of the lighting time control / drive unit 118), the lighting time control / drive units 118-1 to 118-58 are presettable digital one-shot multi A vibrator (PDOMV) 160, a linearity correction unit 162, and an AND circuit 170 are included.
The AND circuit 170 is connected to the image data development unit 110 and the timing signal generation unit 114. When the image data from the image data development unit 110 is 1 (ON), the trigger signal (TRG) from the timing signal generation unit 114 is displayed. ) Is output to the PDOMV 160, and when the image data is 0 (OFF), the trigger signal is set not to be output. The PDOMV 160 is connected to the AND circuit 170, the OR circuit 168, the density unevenness correction data unit 112, and the reference clock generation unit 116, and the number of clocks corresponding to the density unevenness correction data in synchronization with the trigger signal from the AND circuit 170. The lighting pulse is generated.

The linearity correction unit 162 corrects and outputs the lighting pulse signal from the PDOMV 160 in order to correct the variation in the light emission start time of each LED in the SLED 63. Specifically, the linearity correction unit 162 includes a plurality of delay circuits 164 (eight in this embodiment, 164-0 to 164-7), a delay selection register 166, a delay signal selection unit 165, and an AND circuit 167. , An OR circuit 168, and a lighting signal selection unit 169.
The delay circuits 164-0 to 164-7 are connected to the PDOMV 160, and different times for delaying the lighting pulse signal from the PDOMV 160 are set. The delay selection register 166 is connected to the delay signal selection unit 165 and the lighting signal selection unit 169, and the delay selection register 166 stores delay selection data for each LED in the SLED 63 and lighting signal selection data. . Delay selection data and lighting signal selection data for each LED are measured in advance and stored in the EEPROM 102. The delay selection data and lighting signal selection data stored in the EEPROM 102 are downloaded to the delay selection register 166 via the density unevenness correction data unit 112 when the machine power is turned on. Note that a flash ROM can also be used as the storage means, and in that case, the flash ROM itself can function as the delay selection register 166.

Here, the delay selection data stored in the EEPROM 102 will be described. FIG. 11 is a diagram showing the relationship between the pulse width of the lighting signal ΦI for lighting the LED and the light quantity of the LED. In FIG. 11 (a), the solid line indicates the distance from the LED when the pulse width of the lighting signal ΦI (for example, the length of L1 in FIG. 7 (H)) is changed for any one LED in the SLED 63. It is a light quantity measurement value of the light emitted through the rod lens array 64 (see FIG. 2). A broken line is a target light quantity characteristic (target light quantity characteristic) required when the LED is actually driven.
As shown in FIG. 11A, when light is actually emitted from the LED, the light emission start time is delayed because the output waveform of the lighting signal ΦI does not become a complete rectangle. The delay time usually has a variation of about 3 to 15 nsec. Therefore, in the LPH 14 of the present embodiment, the linearity correction unit 162 causes the lighting signal ΦI so that the light amount characteristic of the light from the LED substantially matches the target light amount characteristic in the pulse width region used in the image forming apparatus. The pulse width is offset.
FIG. 11 (b) shows the light quantity characteristic (solid line) of the LED when the offset correction is performed on the pulse width of the lighting signal ΦI to the LED. In FIG. 11B, the offset amount is determined so that the light amount of the LED matches the target light amount at the lower limit pulse width (offset correction position) of the used pulse width region. The offset amount is measured for each LED by such a method and stored in the EEPROM 102 as delay selection data.

The delay signal selection unit 165 is connected to the AND circuit 167 and the OR circuit 168, and is one of outputs from the delay circuits 164-0 to 164-7 based on the delay selection data stored in the delay selection register 166. Select one. The AND circuit 167 is a logical product of the lighting pulse signal from the PDOMV 160 and the delayed lighting pulse signal selected by the delay signal selection unit 165, that is, both the lighting pulse signal before the delay and the lighting pulse signal after the delay are in the lighting state. If so, a lighting pulse is output. The OR circuit 168 is a logical sum of the lighting pulse signal from the PDOMV 160 and the delayed lighting pulse signal selected by the delay signal selection unit 165, that is, at least one of the lighting pulse signal before the delay and the lighting pulse signal after the delay is in the lighting state. If so, a lighting pulse is output.
The lighting signal selection unit 169 selects one of the outputs from the AND circuit 167 or the OR circuit 168 based on the lighting selection data stored in the delay selection register 166. Then, the selected lighting pulse is output to the LPH 14 via the MOSFET 172 as the lighting signal ΦI.

By the way, as described above, the PDOMV 160 generates a lighting pulse of the number of clocks corresponding to the density unevenness correction data in synchronization with the trigger signal from the AND circuit 170 and outputs it to the AND circuit 167 and the OR circuit 168. Therefore, the lighting pulse input to the linearity correction unit 162 has already been corrected by the density unevenness correction data in the PDOMV 160. Therefore, the lighting pulse output to the LPH 14 via the MOSFET 172 as the lighting signal ΦI is output in a state where density unevenness correction (gain correction) and offset correction are performed.
FIG. 12 is a diagram showing the light quantity characteristics of the LED subjected to gain correction and offset correction. FIG. 12 shows a case where gain correction is performed with reference to the center position (gain correction position) of the pulse width region used in the image forming apparatus as an example.
As described above, in the lighting time control / drive units 118-1 to 118-58 of the present embodiment, the lighting pulse (pulse width) of each pixel (each LED) is corrected based on the density unevenness correction data and the delay selection data. As a result, the light amount characteristic in the pulse width region used in the image forming apparatus is substantially matched with the target light amount characteristic, and is output to the LPH 14. Thereby, the light quantity of all the LEDs is set to fall within a predetermined range in the use pulse width region.

  Next, the power supply voltage control unit 119 as an example of a voltage supply unit that supplies the power supply voltage to the LPH 14 performs digital / analog conversion on the light amount adjustment data 2 output from the control unit 30 as shown in FIG. The DA converter 120 that outputs the control voltage Vcont according to the light amount adjustment data 2, and the output voltage Vsub to the LPH 14 is variably set to +3.8 V or less according to the control voltage Vcont output from the DA converter 120 3 A terminal regulator 101 is included.

Here, operations of the reference clock generation unit 116 and the power supply voltage control unit 119 will be described.
In the image forming units 11Y, 11M, 11C, and 11K (see FIG. 1), a test patch (density sample) is formed on the photosensitive drum 12 at a predetermined timing, and the density detection circuit 17 detects the toner image density. . The toner image density data detected by the density detection circuit 32 is output to the control unit 30, and the control unit 30 calculates the light quantity at the LPH 14 from the input toner image density data to generate light quantity adjustment data. The generated light amount adjustment data is output as the light amount adjustment data 1 to the reference clock generation unit 116, and is output as the light amount adjustment data 2 to the power supply voltage control unit 119.
The light amount adjustment data (light amount adjustment data 1 and light amount adjustment data 2) includes, for example, changes in the sensitivity of the photosensitive drum 12, changes in the latent image potential (dark portion potential V _H and bright portion potential V _L ), and further in the developing unit 15. In order to maintain a constant toner image density due to a variation in the developer amount of the toner, etc., the total light amount in the LPH 14 (the light amount of the entire LED in the LPH 14) is adjusted in order to keep this constant. Data to be used. Therefore, the light amount adjustment data is output as an instruction value that indicates the pulse width of the lighting signal ΦI that drives the SLED 63 of the LPH 14.
In addition, since the total light quantity in LPH14 becomes large as the pulse width of lighting signal (PHI) I becomes long, it means that the total light quantity in LPH14 is set large, so that a pulse width instruction value is large.

  In the PLL circuit 134 in the reference clock generation unit 116 to which the light amount adjustment data 1 is input, when the light amount adjustment data 1 indicates a pulse width greater than a predetermined value (when the total light amount in the LPH 14 is set to a predetermined value or more). Similarly, the reference clock signal has a period of To = M × T / N where T is the period of the crystal oscillator oscillated by the crystal oscillator 140 and To is the reference clock period output from the PLL circuit 134. Is output. Here, M and N are the frequency division ratios of the frequency divider 1 / M142 and the frequency divider 1 / N144 set in order to obtain the reference clock period corresponding to the light amount adjustment data 1. The circumferential ratios M and N are stored in the LUT 132 in advance. That is, the reference clock generator 116 changes the cycle of the reference clock signal based on the light amount adjustment data 1. Accordingly, by increasing the reference clock period, the pulse width of the lighting signal ΦI can be increased, and the light quantity of the LED can be increased. Further, by shortening the reference clock cycle, the pulse width of the lighting signal ΦI can be shortened, and the light quantity of the LED can be lowered. In this way, the total light amount of the LPH 14 is adjusted. Note that it is preferable to select small values for the frequency division ratios M and N in order to shorten the comparison period of the PLL circuit 134.

  On the other hand, when the light amount adjustment data 1 indicates a pulse width smaller than a predetermined value (when the total light amount in the LPH 14 is set smaller than the predetermined value; the same applies hereinafter), the reference clock to which the light amount adjustment data 1 is input. The PLL circuit 134 in the generator 116 outputs a fixed reference clock cycle Tof (for example, 40 nsec). That is, the LUT 132 stores predetermined frequency division ratios M and N for setting the reference clock signal to the fixed reference clock period Tof when the light amount adjustment data 1 indicates a pulse width smaller than the predetermined value. .

Further, in the DA converter 120 of the power supply voltage control unit 119, when the light amount adjustment data 2 indicates a pulse width greater than or equal to a predetermined value, the DA converter 120 to which the light amount adjustment data 2 is input is connected to the three-terminal regulator 101. A predetermined control voltage value Vcont1 (see FIG. 13 in the subsequent stage) is output so that the output voltage Vsub is constant at + 3.8V.
On the other hand, when the light quantity adjustment data 2 indicates a pulse width smaller than a predetermined value, the DA converter 120 to which the light quantity adjustment data 2 is input is set for the three-terminal regulator 101 corresponding to the light quantity adjustment data 2. The controlled voltage Vcont is output. Then, the three-terminal regulator 101 sets the output voltage Vsub to +3.8 V or less according to the input control voltage Vcont.
FIG. 13 is a diagram illustrating an example of the relationship between the control voltage Vcont from the DA converter 120 and the output voltage Vsub of the three-terminal regulator 101. As shown in FIG. 13, the output voltage Vsub is set to change linearly with respect to the control voltage Vcont. In the three-terminal regulator 101 of the present embodiment, the output voltage Vsub changes linearly in the range of 3.2 to 3.8V by varying the control voltage Vcont in the range of 1.61 to 1.9V. Is set.
On the other hand, when the light amount adjustment data 2 indicates a pulse width greater than or equal to a predetermined value, the DA converter 120 sets the control voltage Vcont to a fixed value (Vcont1: 1.9 V in the example of FIG. 13). Thereby, the output voltage Vsub of the three-terminal regulator 101 is fixed at 3.8V.

  In the power supply voltage control unit 119 of the present embodiment, the three-terminal regulator 101 is configured to variably set the output voltage Vsub to the LPH 14 according to the control voltage Vcont output from the DA converter 120. Yes. However, in addition to such a configuration, in the three-terminal regulator 101, either or both of the voltage dividing resistors R1 and R2 for feedback are configured by variable resistors, and the output value from the DA converter 120 is obtained. Accordingly, it is also possible to adjust the output voltage Vsub to the LPH 14 by changing these resistance values.

In the LPH 14 according to the present embodiment, the reference clock generator 116 and the power supply voltage controller 119 are operated as described above. Thereby, for the LED subjected to gain correction and offset correction as shown in FIG. 12, when the resolution in the sub-scanning direction is set to a high resolution of, for example, 4800 dpi, that is, the pulse width region where the used pulse width region is lower Even when set to, it is possible to set so that the amount of light of all the LEDs falls within a predetermined range.
Hereinafter, the light amount control of the LED in the pulse width region used when the high resolution is set will be described.

First, as shown in FIGS. 11 and 12, in the region where the pulse width of the lighting signal ΦI is short (in the drawing, the region where the pulse width is shorter than the “use pulse width region”), the light emission amount of the LED in the SLED 63 And pulse width do not have linear characteristics. This is because the lighting signal ΦI is relatively greatly affected by the inductance and capacity of the signal line itself that transmits the lighting signal ΦI, so that the output waveform of the lighting signal ΦI from the signal generation circuit 100 that drives the SLED 63 is obtained. This is due to relatively large distortion.
Therefore, in a high-resolution image forming apparatus that uses an area having a shorter pulse width than the used pulse width area in FIGS. 11 and 12, each signal from the signal generation circuit 100 is set when the entire light amount of the LPH 14 is set small. Due to the distortion of the output waveform of the lighting signal ΦI for lighting the LED, there is a problem that the variation in the amount of light between the LEDs becomes large. As a result, image defects such as streaks and image density unevenness occur in the formed image when setting a high light amount with a low light amount.
That is, as shown in FIG. 14, in the use pulse width region 1 when the resolution in the sub-scanning direction is set to a normal value, for example, 2400 dpi, the light amount of the LED in the LPH 14 is obtained by performing gain correction and offset correction. It is possible to make the characteristics substantially coincide with the target light quantity characteristics. However, when the resolution in the sub-scanning direction is set to a high resolution, for example, 4800 dpi, an area with a shorter pulse width (used pulse width area 2) is used, and the amount of light emitted from the LED and the pulse width are reduced. This includes regions that do not have linear characteristics (regions with large errors). For this reason, the light quantity characteristic of the LED in the LPH 14 cannot be matched with the target light quantity characteristic, and the variation in the light quantity between the LEDs increases.

Therefore, in the LPH 14 of the present embodiment, in the region where the light emission amount of the LED and the pulse width do not have a linear characteristic and there is a large error from the target light amount characteristic (see FIG. 14), the reference clock generator 116 The PLL circuit 134 outputs a fixed reference clock period Tof (for example, 40 nsec). At the same time, the power supply voltage control unit 119 outputs the control voltage Vcont to the three-terminal regulator 101, and sets the output voltage Vsub of the three-terminal regulator 101 to + 3.8V or less according to the control voltage Vcont.
That is, in a region where the error from the target light quantity characteristic is large, the reference clock signal is set to the fixed reference clock period Tof, and the power supply voltage Vsub supplied to the power supply line 105 (see FIG. 6) of the SLED 63 is used as the light quantity adjustment data. The light quantity of the LED is adjusted by reducing it to +3.8 V or less according to 2.
Therefore, since the pulse width is fixed in a region where the error from the target light quantity characteristic is large, it is possible to suppress a relatively large distortion from occurring in the output waveform of the lighting signal ΦI by shortening the pulse width. The amount of emitted light can be stabilized. In addition, by adjusting the power supply voltage Vsub supplied to the power supply line 105 of the SLED 63 to +3.8 V or less according to the light amount adjustment data 2 in this state, the light amount of the LED is adjusted to substantially match the target light amount characteristic. It becomes possible to do.

  FIG. 15 shows the pulse width (indicated value) of the lighting signal ΦI instructed by the light amount adjustment data (light amount adjustment data 1) from the control unit 30 and the lighting time control / drive unit 118- in the LPH 14 of the present embodiment. It is a figure explaining the relationship with the pulse width (set pulse width) output from 1-118-58. As shown in FIG. 15, when the instruction value is 40 nsec or more, for example, the reference clock signal from the reference clock generator 116 is changed based on the light amount adjustment data 1 to set the set pulse width according to the instruction value. . On the other hand, when the instruction value is smaller than 40 nsec, for example, the reference clock signal from the reference clock generator 116 is fixed, and the set pulse width is fixed to 40 nsec. Here, the instruction value for changing the set pulse width to a fixed value is preferably set to about 40 nsec at which the light emission amount of the LED is stabilized.

  Next, FIG. 16 shows the pulse width (indicated value) of the lighting signal ΦI instructed by the light amount adjustment data (light amount adjustment data 2) from the control unit 30 and the power supply voltage control unit 119 in the LPH 14 of the present embodiment. It is a figure explaining the relationship with the output voltage Vsub (power supply voltage) output from A. As shown in FIG. 16, when the instruction value is 40 nsec or more, for example, the power supply voltage Vsub output from the power supply voltage control unit 119 is fixed to 3.8V. On the other hand, when the instruction value is smaller than 40 nsec, for example, the control voltage Vcont from the DA converter 120 is varied based on the instruction value, and the power supply voltage Vsub output from the power supply voltage control unit 119 is +3.2 to 3. It is set to change in the range of 8V.

FIG. 17 is a diagram for explaining the relationship between the pulse width (indicated value) of the lighting signal ΦI instructed by the light amount adjustment data from the control unit 30 and the light amount of the LED in the LPH 14 of the present embodiment. . In the LPH 14 according to the present embodiment, when the instruction value is equal to or greater than a predetermined value (for example, 40 nsec), the LED is switched according to the reference clock cycle corresponding to the light amount adjustment data 1 from the PLL circuit 134 in the reference clock generator 116. Adjust the amount of emitted light. When the instruction value is smaller than the predetermined value, the power supply voltage Vsub output from the power supply voltage control unit 119 is changed in the range of 3.2 to 3.8 V to adjust the light emission amount of the LED. Accordingly, as shown in FIG. 17, unlike the case of FIG. 14, even in the range where the instruction value is smaller than the predetermined value, the light quantity of the LED can be made to substantially match the target light quantity characteristic.
Thereby, even when the resolution in the sub-scanning direction is set to a high resolution of, for example, 4800 dpi, it is possible to set so that the light amounts of all the LEDs are within a predetermined range.

As described above, in the LPH 14 according to the present embodiment, the reference clock period set according to the light amount adjustment data 1 in the PLL circuit 134 in the reference clock generation unit 116 is set in a region having a pulse width greater than a predetermined value. Generated and output to all lighting time control / drive units 118-1 to 118-58. That is, in the pulse width region of a predetermined value or more, the entire light amount of the LPH 14 is adjusted by changing the pulse width of the lighting signal ΦI according to the light amount adjustment data.
On the other hand, in a region having a pulse width smaller than the predetermined value, the reference clock period To is set to the fixed value Tof based on the light amount adjustment data 1. Then, the power supply voltage Vsub supplied to the power supply line 105 (see FIG. 6) of the SLED 63 is set to +3.8 V or less according to the light quantity adjustment data 2, thereby adjusting the total light quantity of the LED. That is, in the pulse width region smaller than the predetermined value, the total light amount of the LPH 14 is adjusted by changing the power supply voltage Vsub to the SLED 63 according to the light amount adjustment data.
Therefore, even when the resolution in the sub-scanning direction is set to, for example, 4800 dpi, corresponding to the increase in resolution in the image forming apparatus, the LED light amount is almost equal to the target light amount characteristic in the use pulse width region where the pulse width is shorter. Adjustments can be made to match. As a result, the light quantity of all LEDs can be set to fall within a predetermined range, and high quality with reduced image defects such as streak and image density unevenness can be achieved even when setting a low light quantity with high resolution. An image can be formed.

1 is a diagram illustrating an overall configuration of an image forming apparatus using an LED print head according to an embodiment. It is the figure which showed the structure of the LED print head (LPH). It is a top view of a LED circuit board. It is a figure explaining the connection part of each SLED chip. It is the figure which showed the wiring diagram currently formed on the LED circuit board. It is a figure explaining the circuit structure of SLED. 3 is a timing chart showing drive signals output from a signal generation circuit and a level shift circuit. It is a block diagram which shows the structure of a signal generation circuit. It is a block diagram explaining the structure of a reference clock generation part. It is a block diagram explaining the structure of lighting time control and a drive part. It is the figure which showed the relationship between the pulse width of lighting signal (PHI) which lights up LED before and behind performing offset correction, and the light quantity of LED. It is the figure which showed the light quantity characteristic with respect to the pulse width of LED in which gain correction and offset correction were performed. It is the figure which showed an example of the relationship between the control voltage Vcont from a DA converter, and the output voltage Vsub of a 3 terminal regulator. It is a figure explaining the difference | error of the light quantity characteristic of LED and a target light quantity characteristic when the resolution of a subscanning direction is set to high resolution. It is a figure explaining the relationship between the pulse width (indication value) of lighting signal (PHI), and the pulse width (setting pulse width) output from lighting time control and a drive part. It is a figure explaining the relationship between the pulse width (indication value) of the lighting signal (PHI), and the output voltage Vsub (power supply voltage) output from a power supply voltage control part. It is a figure explaining the relationship between the pulse width (indication value) of lighting signal (PHI), and the light quantity of LED.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Digital color printer, 10 ... Image formation process part, 11Y, 11M, 11C, 11K ... Image formation unit, 12 ... Photosensitive drum, 14 ... LED print head (LPH), 30 ... Control part, 40 ... Image processing part (IPS), 62 ... LED circuit board, 63 ... self-scanning LED array (SLED), 64 ... rod lens array, 100 ... drive circuit (signal generation circuit), 102 ... EEPROM, 104 ... level shift circuit, 110 ... image Data development unit 112 ... Density unevenness correction data unit 114 ... Timing signal generation unit 116 ... Reference clock generation unit 118-1 to 118-58 ... Lighting time control / drive unit 119 ... Power supply voltage control unit 120 ... DA converter, R1, R2 ... Voltage divider resistor

Claims (11)

A print head for exposing an image carrier in an image forming apparatus,
A plurality of light emitting elements arranged in a line;
A lighting signal for causing the light emitting element to emit light is output to the light emitting element, and a pulse width of the lighting signal is fixed to a predetermined value or changed in a region equal to or greater than the predetermined value to thereby change the light amount of the light emitting element. A driving circuit for controlling
A print head comprising: a voltage supply unit configured to change a power supply voltage value supplied to the light emitting element when the pulse width of the lighting signal is fixed to the predetermined value by the drive circuit.   The print head according to claim 1, wherein the voltage supply unit sets the power supply voltage value based on an instruction signal instructing a light amount of the entire light emitting element from the image forming apparatus.   The said voltage supply part fixes the said power supply voltage value to predetermined value, when the said drive circuit changes the pulse width of the said lighting signal in the area | region more than the said predetermined value, The said power supply voltage value is fixed to predetermined value. Print head.   The print head according to claim 1, wherein the drive circuit sets the pulse width based on an instruction signal that instructs the light amount of the entire light emitting element from the image forming apparatus.   When the drive circuit receives an instruction signal for setting the light amount of the entire light emitting element to a predetermined value or more from the image forming apparatus, the drive circuit changes the pulse width in a region of the predetermined value or more based on the instruction signal. The print head according to claim 1.   The drive circuit fixes the pulse width to the predetermined value when receiving an instruction signal for setting a light amount of the entire light emitting element to be smaller than a predetermined value from the image forming apparatus. The printhead described.   The voltage supply unit includes a DA converter that converts an instruction signal indicating the light amount of the entire light emitting element from the image forming apparatus into a voltage value, and a regulator that changes an output voltage according to the voltage value from the DA converter. The print head according to claim 1, comprising:   The print head according to claim 7, wherein the voltage supply unit changes the output voltage by changing a voltage dividing resistance value provided in the regulator. A photoreceptor,
A print head for exposing the photoreceptor;
A control unit that outputs an instruction signal instructing the total light amount of the print head,
The print head is
A plurality of light emitting elements arranged in a line;
A lighting signal for causing the light emitting element to emit light is output to the light emitting element, and a pulse width of the lighting signal is fixed to a predetermined value based on the instruction signal from the control unit, or is equal to or greater than the predetermined value. A drive circuit that changes in a region;
An image forming apparatus comprising: a voltage supply unit configured to change a power supply voltage value supplied to the light emitting element when a pulse width of the lighting signal is fixed to the predetermined value by the driving circuit.   When receiving the instruction signal for setting the total light amount of the print head to be smaller than a predetermined value from the control unit, the drive circuit fixes the pulse width to the predetermined value based on the instruction signal. The image forming apparatus according to claim 9.   When receiving the instruction signal for setting the total light amount of the print head to a predetermined value or more from the control unit, the drive circuit changes the pulse width based on the instruction signal, and the voltage supply unit The image forming apparatus according to claim 9, wherein the power supply voltage value is fixed to a predetermined value.

Images