JP2007103832A - Standard cell library, method for designing semiconductor integrated circuit, semiconductor integrated circuit pattern and semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To dispose a standard cell containing transistors of different threshold value voltages at an arbitrary position without causing an area and a design cost to be increased. <P>SOLUTION: A cell library is prepared containing a plurality of kinds of standard cells is prepared where upper/lower boundaries of a threshold value adjusting pattern are overlapped on upper/lower boundaries of a cell frame to define distances between right/left boundaries of the pattern and right/left boundaries of the cell frame. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a standard cell library including a plurality of types of standard cells, a method for designing a semiconductor integrated circuit using the standard cells, a semiconductor integrated circuit pattern including a circuit block in which a plurality of types of standard cells are arranged, and the semiconductor integrated circuit The present invention relates to a semiconductor integrated circuit in which a pattern is formed on a semiconductor substrate.

  In designing a semiconductor integrated circuit using standard cells, a plurality of types of standard cells having various logic functions are prepared in a library. In these standard cells, a pattern of multiple layers is formed in a cell frame having a constant height and a width that is an integral multiple of the unit width to form transistors and the like necessary to realize each function. The Then, cells necessary for realizing the required specifications are selected from the plurality of types of standard cells, and they are arranged vertically and horizontally so that the boundaries of the cell frames touch each other. Such a standard cell structure and arrangement method are disclosed in Patent Document 1, for example.

  On the other hand, in order to realize a necessary operation speed while suppressing generation of excessive leakage current, it is becoming common to configure a semiconductor integrated circuit using transistors having different threshold voltages. That is, high-threshold transistors with low speed but low leakage current are used for circuits and signal paths that do not require high-speed operation, while high leakage current is required for circuits and signal paths that require high-speed operation. A low threshold transistor capable of operation is used.

For example, in FIG. 15 of Patent Document 2, it is proposed to add a process of adding and distributing impurities under the gate electrode of a high threshold transistor. As a result, the threshold voltage of the MOSFET constituting the logic gate at an arbitrary location of the semiconductor integrated circuit can be freely changed.
JP 2005-72133 A JP 2004-172627 A

  However, when the technique of forming transistors having different thresholds by adding impurities as described in Patent Document 2 is applied to the standard cell as a result of the study by the present inventors, there is a case where restrictions are imposed on the arrangement of the standard cell. Became clear.

  FIG. 12 is a layout diagram of an example of a conventional standard cell. In FIG. 12, a plurality of layers of patterns necessary for obtaining the function of the standard cell 110 are arranged in a cell frame 112 indicated by a solid line. The standard cell 110 shown in FIG. 12 has an inverter function. In the figure, the N well 114, the active regions 116 and 118, the gate 120, and the pattern of each layer of the P channel threshold adjustment 122 and the N channel threshold adjustment 124 are illustrated. It is shown. Illustration of the pattern of the other layers was omitted.

  An N-well pattern 114 is provided on the upper side of FIG. The N-well pattern 114 extends from the inside of the cell frame 112 to the outside of the upper boundary 112a and the left and right boundaries 112c and 112d of the cell frame. The portion extending outward from the boundary of the cell frame 112 is integrated when a plurality of standard cells are arranged so that the boundary of the cell frame is in contact with each other to form a circuit block.

  A first active region pattern 116 is provided in the N well pattern 114, and a gate electrode pattern 120 penetrating therethrough in the vertical direction is disposed. These are patterns for forming a P-channel MOS transistor (PMOS transistor) 140 on a semiconductor substrate. That is, the channel region 142 of the PMOS transistor 140 is formed in the portion where the first active region pattern 116 and the gate electrode pattern 120 overlap. Further, the source region 144 and the drain region 146 of the PMOS transistor 140 are formed on both sides of the gate electrode pattern 120 of the first active region pattern 116.

  In FIG. 12, a P well is formed in a region outside the N well pattern 114, that is, a region on the lower side of the figure. That is, doping of the P well impurity is performed using a mask formed by data obtained by inverting the N well pattern 114. An N channel MOS transistor (NMOS transistor) 150 is formed by the second active region pattern 118 disposed on the lower side of FIG. 12 and the gate electrode pattern 120 penetrating therethrough in the vertical direction. A channel region 152 of the NMOS transistor is formed in a portion where the second active region pattern 118 and the gate electrode pattern 120 overlap. A source region 154 and a drain region 156 of the NMOS transistor 150 are formed on both sides of the gate electrode pattern 120 of the second active region pattern 118.

  Here, the threshold voltages of the PMOS transistor 140 and the NMOS transistor 150 are determined by the impurity concentration of each channel region. For example, the threshold voltage increases as the concentration of P-type and N-type impurities in each channel region increases.

  The standard cell 110 shown in FIG. 12 includes a first threshold adjustment pattern 122 and a second threshold adjustment pattern 124 for adjusting the threshold voltage by adding impurities to the channel region. The first threshold adjustment pattern 122 is a pattern for forming a mask for adjusting the threshold voltage by adding an impurity to the channel region 142 of the PMOS transistor 140. The second threshold adjustment pattern 124 is a pattern for forming a mask for adjusting the threshold voltage by adding an impurity to the channel region 152 of the NMOS transistor 150.

  Actually, the only difference is whether or not the first and second threshold adjustment patterns 122 and 124 are provided, and two types of standard cells common to other patterns are prepared. Although these cells have a common function, the threshold voltages of the transistors 140 and 150 are different from each other.

  In the standard cell shown in FIG. 12, the dimension and position of the pattern of each layer are determined so as to satisfy the design rule. The threshold adjustment patterns 122 and 124 need to surround the corresponding channel regions 142 and 152 and widen by a dimension determined outside thereof. On the other hand, the channel region may be extended to the vicinity of the upper and lower boundaries 112 a and 112 b of the cell frame 112 in order to increase the driving capability of the transistors 144 and 154.

  FIG. 12 shows an example in which the upper end of the P channel region 142 is extended to the vicinity of the upper boundary 112a of the cell frame, and the lower end of the N channel region 152 is extended to the vicinity of the lower boundary 112b of the cell frame. As a result, the distance between the upper boundary of the first threshold adjustment pattern 122 and the upper boundary 112a of the cell frame, and the lower boundary of the second threshold adjustment pattern 124 and the lower boundary of the cell frame The distance to 112b is small.

  FIG. 13 is a layout diagram showing a part of a circuit block 170 formed by arranging the standard cells 110 of FIG. 12 together with a plurality of other types of standard cells. In FIG. 13, a plurality of standard cells 110 shown in FIG. 12 are arranged adjacent to each other in the left-right direction in two columns R11, R12 adjacent in the vertical direction. In the lower column R11 shown in FIG. 13, the standard cells 110 shown in FIG. 12 are arranged in the layout shown in FIG. On the other hand, in the upper column R12, the standard cells shown in FIG. 12 are arranged in a layout inverted in the vertical direction.

  In each row, the left and right boundaries 112c and 112d of the frame 112 of the standard cell 110 adjacent to the left and right are arranged so as to contact each other. Further, the upper boundary 112a of the frame 112 of the standard cell 110 is arranged so as to be in contact with each other at the boundary between two columns R11 and R12 that are vertically adjacent to each other.

  Here, as described above, in the standard cell 110 shown in FIG. 12, the distance between the upper boundary 122a of the first threshold adjustment pattern 122 and the upper boundary 112a of the cell frame 112 is extremely small. ing. As a result, in the circuit block 170 shown in FIG. 13, the distance between the first threshold adjustment patterns 122 of the two standard cells 110 adjacent in the vertical direction becomes extremely small. This distance may be less than the minimum distance between adjacent threshold adjustment patterns determined by the design rule. That is, there is a possibility of causing a design rule violation.

  Although omitted in FIG. 13, a similar rule violation occurs between the standard cells arranged in the lower column R11 shown in FIG. 13 and the standard cells arranged in the lower column. May occur. That is, there is a possibility that the distance between the second threshold adjustment patterns 124 is less than the minimum value.

  In order to prevent such a rule violation from occurring, it is necessary to limit the arrangement of standard cells, for example, to “prohibit standard cells having a threshold adjustment pattern from being adjacent to each other vertically”. However, in this case, the standard cell having the threshold adjustment pattern cannot be arranged at an optimum position in order to optimize the performance and dimensions of the circuit block 170. As a result, the performance of the formed circuit block 170 is reduced and the size is increased.

  Alternatively, rule violation can also be prevented by increasing the vertical dimension of the standard cell frame 112 and increasing the distance between the boundary of the threshold adjustment patterns 122 and 124 and the boundary of the cell frame 112. it can. However, in this case, the size of the standard cell 110 is increased, and the size of the circuit block 170 is increased. As a result, the cost of the semiconductor integrated circuit is increased.

  Further, after the standard cell 110 is arranged as shown in FIG. 13, a dummy threshold value adjustment is performed so that a space below the minimum dimension is formed between the threshold value adjustment patterns 122 and 124 so as to fill the space. It is also possible to add patterns. However, generation of such a dummy pattern requires a large amount of arithmetic processing, which increases the time and cost required for designing a semiconductor integrated circuit.

  The present invention provides a standard cell library and a semiconductor integrated circuit that can arrange standard cells including transistors having different threshold voltages at arbitrary positions without causing an increase in area or design cost. It is an object to provide a design method. In addition, a semiconductor integrated circuit pattern in which standard cells including transistors having different threshold voltages are arranged at an arbitrary position without causing an increase in area or design cost, and a semiconductor integrated circuit in which such a pattern is formed It is an issue to provide.

  In order to solve the above problems, the standard cell library of the present invention has a plurality of layers of patterns arranged in a cell frame having a constant height and a width that is an integral multiple of the unit width Wu. A standard cell library including a plurality of types of standard cells for forming a semiconductor integrated circuit by arranging the boundaries so as to be in contact with each other, wherein the plurality of types of standard cells are arranged on an upper side in the cell frame. A pattern for forming a first conductivity type transistor, a pattern for forming a second conductivity type transistor disposed on the lower side in the cell frame, and an upper boundary overlapping the upper boundary of the cell frame; A first threshold adjustment pattern for adding an impurity for adjusting a threshold value of the first conductivity type transistor, and a lower boundary of the cell frame. Each having a lower boundary and left and right boundaries, and a second threshold adjustment pattern for adding an impurity for adjusting a threshold of the second conductivity type transistor, A distance D1 between the left boundary and the left boundary of the cell frame, a distance D2 between the right boundary of the first threshold adjustment pattern and the right boundary of the cell frame, and the second threshold adjustment A distance D3 between the left boundary of the pattern and the left boundary of the cell frame, and a distance D4 between the right boundary of the second threshold adjustment pattern and the right boundary of the cell frame, respectively Di = Wu × ni / 2 (i = 1, 2, 3, 4, ni is an integer greater than or equal to 0), and includes the first plurality of types of standard cells, and is defined by the design rule of the semiconductor integrated circuit. First and second threshold adjustment patterns that Wu ≧ Wmin and Wu ≧ Smin with respect to the minimum permissible width Wmin and the minimum permissible space Smin between the first and second threshold adjustment patterns, and the first plurality of standards In the whole cell, both n1 and n2 are even or both are odd, and both n3 and n4 are even or both are odd.

  In another standard cell library of the present invention, D1, D2, D3, and D4 are Di = di + Wu × ni / 2 (i = 1, 2, 3, 4, −Wu / 2 <di <Wu / 2, ni, respectively). Is an integer greater than or equal to 0), the minimum allowable width Wmin of each of the first and second threshold adjustment patterns determined by the design rule of the semiconductor integrated circuit, and each of the first and second threshold adjustment patterns Wu ≧ Wmin and Wu ≧ Smin, and both n1 and n2 are even or both are odd in the whole of the first plurality of standard cells, and n3 And n4 are both even or both are odd, and the values of d1, d2, d3, and d4 are the same throughout the first plurality of standard cells. Wu + (d1 + d2) ≧ Smin and Wu− (d1 + d2) ≧ Wmin, Wu + (d3 + d4) ≧ Smin and Wu− (d3 + d4) ≧ Wmin, and d1 + d2 ≦ 0 when n1 = n2 = 0. , N3 = n4 = 0, d3 + d4 ≦ 0.

  Here, it is preferable that d1 = d2 and d3 = d4. Moreover, it is preferable that d1 + d2 = d3 + d4. Furthermore, it is preferable that all of n1, n2, n3, and n4 are even in all the first plurality of standard cells, or that all of n1, n2, n3, and n4 are odd.

  Furthermore, it is preferable that Wu <Wmin × 2 and Wu <Smin × 2.

  In order to solve the above problems, a design method of a semiconductor integrated circuit according to the present invention includes a plurality of types of standard cells in which a plurality of patterns are arranged in a cell frame having a common height and an integral multiple of a unit width Wu. A standard cell library is prepared, at least a part of the plurality of types of standard cells is selected, the upper and lower boundaries of the cell frame are in contact with each other along the arrangement grid, and are alternately inverted in the vertical direction. A design method of a semiconductor integrated circuit including a step of forming a circuit block by arranging the arrangement grid, wherein a horizontal pitch of the arrangement grid is Ph, and the plurality of types of standard cells are arranged on an upper side in the cell frame. A pattern for forming the first conductivity type transistor disposed; and a pattern for forming the second conductivity type transistor disposed on the lower side in the cell frame; A first threshold adjustment pattern for adding an impurity that adjusts a threshold value of the first conductivity type transistor, and has an upper boundary that overlaps an upper boundary of the cell frame and a left and right boundary; A second threshold adjustment pattern for adding an impurity for adjusting a threshold value of the second conductivity type transistor, which has a lower boundary that overlaps with the lower boundary and left and right boundaries; A distance D1 between a left boundary of the first threshold adjustment pattern and a left boundary of the cell frame; a distance D2 between a right boundary of the first threshold adjustment pattern and a right boundary of the cell frame; A distance D3 between the left boundary of the second threshold adjustment pattern and the left boundary of the cell frame, and between the right boundary of the second threshold adjustment pattern and the right boundary of the cell frame Distances D4 are Di = Ph × the first and second standard cells defined by the design rule of the semiconductor integrated circuit, including a first plurality of standard cells that are ni / 2 (i = 1, 2, 3, 4, ni is an integer of 0 or more). Ph ≧ Wmin and Ph ≧ Smin with respect to the minimum allowable width Wmin of each of the two threshold adjustment patterns and the minimum allowable space Smin between the first and second threshold adjustment patterns, In the plurality of kinds of standard cells, both n1 and n2 are even or odd, and both n3 and n4 are even or both odd.

  In another semiconductor integrated circuit design method of the present invention, D1, D2, D3, and D4 are represented by Di = di + Ph × ni / 2 (i = 1, 2, 3, 4, −Ph / 2 <di <Ph / 2 and ni are integers of 0 or more), the minimum allowable width Wmin of each of the first and second threshold adjustment patterns determined by the design rule of the semiconductor integrated circuit, and the first and second thresholds With respect to the minimum allowable space Smin between the adjustment patterns, Ph ≧ Wmin and Ph ≧ Smin. In the first plurality of standard cells, both n1 and n2 are even or both are odd. And both n3 and n4 are even or both are odd, and the values of d1, d2, d3, and d4 are the same in the whole of the first plurality of standard cells. Ph + (d1 + d2) ≧ Smin and Ph− (d1 + d2) ≧ Wmin, Ph + (d3 + d4) ≧ Smin and Ph− (d3 + d4) ≧ Wmin, and d1 + d2 ≦ 0 when n1 = n2 = 0. , N3 = n4 = 0, d3 + d4 ≦ 0.

  Here, with respect to the first and second threshold adjustment patterns in the formed circuit block, prepared in advance in a step of performing a violation check against the design rule and a violation occurrence location where a violation is detected by the violation check It is preferable that the method further includes a step of eliminating the violation by arranging the violation elimination pattern.

  In order to solve the above problems, the semiconductor integrated circuit pattern of the present invention includes a plurality of types of standard cells in which a plurality of layers of patterns are arranged in a cell frame having a common height and a width that is an integral multiple of the unit width Wu. A pattern of a semiconductor integrated circuit including circuit blocks arranged along the placement grid, in contact with the upper, lower, left, and right boundaries of the cell frame and alternately inverted in the vertical direction, the horizontal direction of the placement grid And the plurality of types of standard cells have a pattern for forming a first conductivity type transistor arranged on the upper side in the cell frame, and a second type arranged on the lower side in the cell frame. An impurity for adjusting a threshold value of the first conductivity type transistor, having a pattern for forming a two conductivity type transistor, an upper boundary overlapping the upper boundary of the cell frame, and a left and right boundary; An impurity addition for adjusting a threshold value of the second conductivity type transistor having a first threshold adjustment pattern for performing addition, a lower boundary overlapping with a lower boundary of the cell frame, and a left and right boundary; A second threshold adjustment pattern to be performed, a distance D1 between a left boundary of the first threshold adjustment pattern and a left boundary of the cell frame, and a right side of the first threshold adjustment pattern Distance D2 between the boundary of the cell frame and the right boundary of the cell frame, distance D3 between the left boundary of the second threshold adjustment pattern and the left boundary of the cell frame, and the second threshold The distances D4 between the right boundary of the adjustment pattern and the right boundary of the cell frame are Di = Ph × ni / 2 (i = 1, 2, 3, 4, ni is an integer of 0 or more), respectively. A semiconductor integrated circuit including a first plurality of types of standard cells; With respect to the minimum allowable width Wmin of each of the first and second threshold adjustment patterns and the minimum allowable space Smin between each of the first and second threshold adjustment patterns defined by the circuit design rule, Ph ≧ Wmin and Ph ≧ Smin, and in the first plurality of standard cells, both n1 and n2 are even or odd, and both n3 and n4 are even or both are odd. It is characterized by being.

  In another semiconductor integrated circuit pattern of the present invention, D1, D2, D3, and D4 are Di = di + Ph × ni / 2 (i = 1, 2, 3, 4, −Ph / 2 <di <Ph / 2, ni is an integer greater than or equal to 0), the minimum allowable width Wmin of each of the first and second threshold adjustment patterns determined by the design rule of the semiconductor integrated circuit, and the first and second threshold adjustment patterns Ph ≧ Wmin and Ph ≧ Smin with respect to the minimum allowable space Smin between each other, and in the first plurality of types of standard cells, both n1 and n2 are even or both are odd, and , N3 and n4 are both even or both are odd, and the values of d1, d2, d3, and d4 are the same throughout the first plurality of standard cells, h + (d1 + d2) ≧ Smin and Ph− (d1 + d2) ≧ Wmin, Ph + (d3 + d4) ≧ Smin and Ph− (d3 + d4) ≧ Wmin, and d1 + d2 ≦ 0 when n1 = n2 = 0. , N3 = n4 = 0, d3 + d4 ≦ 0.

  Here, a plurality of violations that have caused violations of the design rules of the first and second threshold adjustment patterns arranged by arranging the first plurality of types of standard cells in the circuit block. It is preferable that the same violation elimination pattern is arranged at the occurrence location and the violation is eliminated.

  In the standard cell library of the present invention, the positional relationship causing the design rule violation when the first plurality of types of standard cells having the threshold adjustment pattern are arranged next to each other is specified and can be easily eliminated. . Accordingly, the first plurality of types of standard cells having the threshold adjustment pattern can be arranged at arbitrary positions.

  In the semiconductor integrated circuit design method of the present invention, since such a standard cell library is used, a semiconductor integrated circuit in which cells having threshold adjustment patterns are arranged at arbitrary positions without causing an increase in area or cost. A circuit can be obtained.

  In the semiconductor integrated circuit pattern of the present invention, by using such a standard cell library, a cell having a threshold adjustment pattern can be arranged at an arbitrary position without causing an increase in area or design cost. it can.

  In the semiconductor integrated circuit of the present invention, cells having a threshold adjustment pattern can be arranged at any position without causing an increase in area or design cost, and both the operation speed and the leakage current can be optimized. .

  FIG. 1 is a layout diagram showing a pattern arrangement of each layer of an example of a standard cell included in the cell library according to the embodiment of the present invention.

  The standard cell 10 shown in FIG. 1 has the same function as the conventional standard cell 110 shown in FIG. The dimensions of the cell frame 12 are the same as the dimensions of the cell frame 112 of the conventional standard cell 110. Further, the pattern of each layer of the N well 14, the first active region 16, the second active region 18, and the gate 20 is the same as that of the conventional standard cell 110 shown in FIG. Therefore, in the manufactured semiconductor integrated circuit, a P-channel MOS transistor (PMOS transistor) 40 including a channel region 42, a source region 44 and a drain region 46 is formed in the N well 14 above the standard cell 10. . On the other hand, an N channel MOS transistor (NMOS transistor) 50 including a channel region 52, a source region 54, and a drain region 56 is formed in a P well (not shown) below the standard cell 10.

  Then, similarly to the conventional standard cell 110, the first threshold adjustment pattern 22 for adding an additional impurity to the channel region 42 of the PMOS transistor 40 and the additional impurity addition to the channel region 52 of the NMOS transistor 50 are added. There is a second threshold adjustment pattern 24 for performing. However, the shapes of the first and second threshold adjustment patterns 22 and 24 are different from those of the conventional standard cell 110 shown in FIG.

  Specifically, the upper boundary 22 a of the first threshold adjustment pattern 22 overlaps the upper boundary 12 a of the cell frame 12. Further, the lower boundary 24 b of the second threshold adjustment pattern 24 overlaps the lower boundary 12 b of the cell frame 12. This prevents the formation of a minute space that does not satisfy the design rule between the first or second threshold adjustment patterns of the standard cells arranged adjacent to each other up and down, except in specific cases. Can do.

  The threshold voltage can be increased or decreased depending on the conductivity type of the impurity added additionally using the mask formed by the threshold adjustment patterns 22 and 24. In the present specification, description will be made on the assumption that the threshold voltage of the MOS transistor is increased by the additional addition by the threshold adjustment patterns 22 and 24. Therefore, as shown in FIG. 1, the cell having the threshold adjustment patterns 22 and 24 is a cell having a MOS transistor having a relatively high threshold, and is therefore called a “high threshold cell”. On the other hand, a cell that does not have the threshold adjustment patterns 22 and 24 is a cell having a MOS transistor having a relatively low threshold value, and is therefore called a “low threshold cell”.

  In the method for designing a semiconductor integrated circuit according to the embodiment of the present invention, a plurality of types of standard cells including the standard cell 10 shown in FIG. 1 are arranged along the vertical and horizontal layout grids. FIG. 2 is a layout diagram showing a state where the standard cells shown in FIG. 1 are arranged along the horizontal arrangement grid Gh and the vertical arrangement grid Gv.

  As shown in FIG. 2, the standard cell 10 is arranged such that the upper, lower, left, and right boundaries of the cell frame follow the vertical and horizontal arrangement grids. The height of the standard cell 10 (distance between the upper and lower boundaries 12a and 12b of the cell frame 12) is an integral multiple of the pitch Pv in the vertical direction of the arrangement grid (14 times in the example of FIG. 2), and the width of the standard cell 10 (cell The distance between the left and right boundaries 12c and 12d of the frame 12) is an integral multiple (8 times in the example of FIG. 2) of the horizontal pitch Ph of the arrangement grid.

  In the example shown in FIG. 2, the distance (D1) between the left boundary 22c of the first threshold adjustment pattern 22 of the standard cell 10 and the left boundary 12c of the cell frame 12, the first threshold adjustment. The distance (D2) between the right boundary 22d of the pattern 22 and the right boundary 12d of the cell frame 12, and the distance between the left boundary 24c of the second threshold adjustment pattern 24 and the left boundary 12c of the cell frame 12. The distance (D3) and the distance (D4) between the right boundary 24d of the second threshold adjustment pattern 24 and the right boundary 12d of the cell frame 12 are all equal, and the horizontal pitch Ph of the arrangement grid is 1/2 times.

  In the cell library according to the embodiment of the present invention, each of these distances D1, D2, D3, and D4 is kept in a fixed relationship among a plurality of types of standard cells to be prepared. As a result, it is possible to identify a case where a design rule violation occurs between the threshold adjustment patterns of standard cells arranged adjacent to each other in the vertical direction, and to easily solve the case.

  FIG. 3 is a flowchart showing an example of an embodiment of a method for designing a semiconductor integrated circuit according to the present invention. In FIG. 3, “preparation of violation elimination pattern” and “arrangement of violation elimination pattern” shown in bold are steps characterizing an embodiment of the design method of the present invention that is not present in the conventional design method of a semiconductor integrated circuit. These steps will be described later, and other steps will be described here.

  First, a standard cell library used for designing a semiconductor integrated circuit is prepared. That is, including a standard cell 10 shown in FIG. 1, a plurality of types of standard cells having various patterns that realize various functions are prepared and registered in the cell library (ST1).

  Next, the specifications required for the semiconductor integrated circuit are read, for example, in the form of a net list (ST3). Then, a plurality of types of standard cells required to satisfy this specification are selected from a plurality of types of standard cells prepared in the library (ST4). Subsequently, a necessary number of selected standard cells are respectively arranged along the arrangement grid (ST5). As a result, a circuit block in which a plurality of types of standard cells are arranged vertically and horizontally is formed.

  Thereafter, it is checked whether or not the pattern of each layer of the formed circuit block has a portion that violates various rules defined in the design rule (ST6). If there is no violation, wiring is also arranged along the arrangement grid and the standard cells are connected (ST8). As a result, a pattern of the semiconductor integrated circuit including one or a plurality of circuit blocks necessary for satisfying the specifications is formed.

  The above procedure is performed using a well-known CAD system. That is, the cell library prepared in step ST1 is provided on the storage device of the CAD system, and the pattern of the semiconductor integrated circuit is also formed as computer-readable data stored on the storage device of the CAD system. Then, a mask for each layer is created based on the data of the formed semiconductor integrated circuit pattern, and a semiconductor integrated circuit is manufactured on the semiconductor substrate using the mask. As a result, the semiconductor integrated circuit in which the pattern of the semiconductor integrated circuit designed by the procedure of FIG. 3 is formed on the semiconductor substrate is manufactured.

  FIG. 4 is a conceptual diagram showing a configuration of an example of an embodiment of the cell library of the present invention prepared in step ST1 of the design method of FIG. In the cell library 60, a plurality of types of high threshold cells 62 and low threshold cells 64 are registered. As the plurality of types of high threshold cells, a cell 10 having an inverter function as shown in FIG. 1 and cells having various functions such as NAND and NOR are registered. Further, for each function, a plurality of types of cells having different driving capabilities and different cell frame widths are registered.

  Similarly, as the low threshold cell, a plurality of types of cells having various functions and driving capabilities such as an inverter, NAND, and NOR are registered. At least some of the low threshold cells have the same pattern as the corresponding high threshold cells placed in the same size cell frame, except for the difference between having and not having the first and second threshold adjustment patterns. It is a thing. This low threshold cell has the same function as the corresponding high threshold cell. However, the operation speed and the leakage current are different due to the difference in the threshold value of the transistors to be configured.

  Here, in the present embodiment, each of the high threshold cells included in the cell library 60 has the first and second threshold adjustment patterns similar to the standard cell 10 shown in FIGS. The layout of these threshold adjustment patterns is the same as that of the standard cell 10. That is, the upper boundary 22a of the first threshold adjustment pattern 22 and the lower boundary 24b of the second threshold adjustment pattern 24 overlap the upper and lower boundaries 12a and 12b of the cell frame 12, respectively. And distances D1, D2, D3, and D4 between the left and right boundaries 22c, 22d, 24c, and 24d of the second threshold adjustment patterns 22 and 24 and the left and right boundaries 12c and 12d of the cell frame are all arranged. It is assumed that it is 1/2 of the horizontal pitch Ph of the grid.

  In this way, by making the layout of the threshold adjustment pattern of a plurality of high threshold cells included in the cell library constant, a design rule violation occurs when a circuit block is formed by arranging these high threshold cells. It is possible to make the state constant and easily eliminate it. However, with respect to the distance between the left and right boundaries of the threshold adjustment pattern and the left and right boundaries of the cell frame, it is not always necessary to have a single rule even though it is necessary to satisfy a certain rule.

  FIG. 5 is a layout diagram schematically showing an example 70 of a circuit block formed by arranging a plurality of types of standard cells including the standard cell 10 shown in FIG. 1 and other standard cells. This circuit block 70 is an example of a circuit block included in the semiconductor integrated circuit pattern of the present invention. FIG. 5 is also a layout diagram showing an example of a circuit block included in a semiconductor integrated circuit pattern formed on a semiconductor substrate in the semiconductor integrated circuit of the present invention.

  In FIG. 5, what is indicated as H8 is the high threshold cell 10 shown in FIG. 1, in which the width of the cell frame is eight times the horizontal pitch Ph of the arrangement grid. Similarly, H9, H10, and H12 are high threshold cells whose cell frame width is 9 times, 10 times, and 12 times that of Ph, respectively. On the other hand, L6, L7, L8, L9, and L13 are low threshold cells whose cell frame width is 6, 7, 8, 9, and 13 times that of Ph. Although omitted in FIG. 5, these standard cells are arranged along the arrangement grids Gh and Gv shown in FIG. In other words, the upper, lower, left and right boundaries of the cell frames of the standard cells are arranged so as to overlap the arrangement grid.

  More specifically, a plurality of standard cells are arranged in the horizontal direction of FIG. 5 so that the left and right boundaries of the cell frame are in contact with each other, and the standard cell rows R1, R2, R3. . . These standard cell rows R1, R2, R3. . . Are arranged so that the upper and lower boundaries of the cell frames of the standard cells included therein are in contact with each other to form the circuit block 70. At this time, the standard cells are alternately inverted in the vertical direction. That is, for example, odd-numbered columns R1, R3. . . For example, as shown in FIG. 1, the standard cells arranged in (1) are arranged in a layout in which the N well 14 is located on the upper side. On the other hand, even-numbered columns R2. . . In this case, the layout as shown in FIG. 1 is inverted in the vertical direction, and the N well 14 is arranged in a lower position.

In the circuit block 70 arranged in this way, the two high threshold cells arranged adjacent to each other in the vertical direction have one of the following three positional relationships.
(1) Both cell frames touch at a corner (for example, position A in FIG. 5).
(2) Both cell frames are in contact with each other over a width that is twice or more than the horizontal pitch Ph of the arrangement grid (for example, position B in FIG. 5).
(3) Both cell frames are in contact with each other over the horizontal pitch Ph of the arrangement grid (for example, position C in FIG. 5).

  In the high threshold cell 10 shown in FIG. 2, the upper boundary 22a of the first threshold adjustment pattern 22 and the lower boundary 24b of the second threshold adjustment pattern 24 are respectively above and below the cell frame 12. It overlaps the side boundaries 12a, 12b. Further, distances D1, D2, D3, and D4 between the left and right boundaries 22c, 22d, 24c, and 24d of the first and second threshold adjustment patterns 22 and 24 and the left and right boundaries 12a and 12b of the cell frame are: In both cases, the pitch is 1/2 of the horizontal pitch Ph of the arrangement grid. When high threshold cells having such a threshold adjustment pattern layout are arranged, in the cases (1) and (2) above, the threshold adjustment patterns of the high threshold cells adjacent to each other in the upper and lower sides cause a design rule violation. There is nothing. In the case of (3), the threshold adjustment patterns of the high threshold cells adjacent in the vertical direction cause a design rule violation, but this can be solved by a simple process.

  Each of these cases will be described with reference to FIGS. FIG. 5 shows a case where the same high threshold cell 10 is adjacent to each other in the vertical direction. Similarly, in FIGS. 6, 7, 8, and 9, an example in which the same high threshold cell 10 is vertically adjacent will be described. However, in the cell library 60 of this embodiment, the layout of the threshold adjustment pattern is the same as that of the high threshold cell 10 shown in FIG. Therefore, even when other types of high threshold standard cells are arranged next to each other or when different types of high threshold standard cells are arranged next to each other, the positions of the threshold adjustment patterns The relationship is similar.

  FIG. 6 is a layout diagram showing the arrangement of standard cells around the position A in FIG.

  In the lower right and upper left of FIG. 6, two high threshold cells 10 arranged adjacent to each other in the vertical direction with the corner of the cell frame in the position A are shown. Among these, the lower right high threshold cell 10 is arranged in the layout shown in FIG. On the other hand, the high threshold cell 10 at the upper left is arranged in a layout that is vertically inverted from that shown in FIG. In the lower left and upper right of FIG. 6, two low threshold cells L7 and L9 that are in contact with the corner of the cell frame at the position A are arranged. In FIG. 6, for these low threshold cells, only the cell frame is shown, and the display of the internal pattern is omitted.

  In FIG. 6, arrangement grids Gh and Gv for arranging these cells are further displayed. However, in order to prevent complication, the arrangement grid is displayed only in the area outside the four cells illustrated.

  As shown in FIG. 2, in the standard cell 10, distances D1 and D2 between the left and right boundaries 22c and 22d of the first threshold adjustment pattern 22 and the left and right boundaries 12c and 12d of the cell frame 12 are arranged. It is 1/2 times the horizontal pitch Ph of the grid. Therefore, when the frames of the high threshold cells 10 arranged adjacent to each other at the top and bottom touch each other at the corner, a space S1 equal to Ph is formed between the first threshold adjustment patterns 22 of the cells adjacent to each other vertically.

  Here, in the 130 nm node semiconductor integrated circuit, the minimum space Smin allowed between the first threshold adjustment patterns defined by the design rule is, for example, 0.31 μm. On the other hand, the horizontal pitch Ph of the arrangement grid is, for example, 0.41 μm. That is, the horizontal pitch Ph of the arrangement grid and the minimum space Smin have a relationship of Ph ≧ Smin. Accordingly, no design rule violation occurs between the first threshold adjustment patterns 22.

  5A, the standard cell 10 arranged in a layout obtained by inverting the layout shown in FIG. 1 vertically is adjacent to the upper side of the standard cell 10 arranged in the layout shown in FIG. Arranged. Therefore, as shown in FIG. 6, the first threshold adjustment patterns 22 of the standard cells 10 that are vertically adjacent to each other are arranged adjacent to each other. On the other hand, when the standard cell 10 arranged in the layout shown in FIG. 1 is adjacent to the upper side of the standard cell 10 arranged in the layout obtained by inverting the layout shown in FIG. The threshold adjustment patterns 24 are arranged adjacent to each other in the vertical direction.

  In the high threshold cell 10 shown in FIG. 2, the distances D3 and D4 between the left and right boundaries 24c and 24d of the second threshold adjustment pattern 24 and the left and right boundaries 12c and 12d of the cell frame 12 are also 1 of Ph. / 2 times. Therefore, even when the second threshold value adjustment patterns 24 of the standard cells arranged adjacent to each other in contact with each other at the corner of the cell frame are arranged adjacent to each other, a Ph space is formed between them. .

  Here, a minimum space that is the same as the minimum space allowed between the first threshold adjustment patterns is generally allowed between the second threshold adjustment patterns. Therefore, the design rule violation does not occur even when the second threshold value adjustment patterns 24 of the standard cells arranged adjacent to each other at the corners of the cell frame are arranged adjacent to each other.

  Various values set in the design rule vary depending on the manufacturing process to be used. In general, however, the pitch Ph of the arrangement grid is the minimum space between the threshold adjustment patterns (if the first threshold adjustment pattern and the second threshold adjustment pattern are set to different values, the larger value is used. ) Smin or higher is set. Accordingly, as shown in FIG. 6, a space S1 that is equal to or larger than the minimum space defined by the design rule is provided between the first or second threshold adjustment patterns 22 of cells adjacent to each other in the vertical direction by touching one corner. Is formed.

  Here, with reference to FIG. 6, the relationship between the dimensions of the cell frames of a plurality of types of standard cells included in the standard cell library of the present embodiment and the pitch of the arrangement grid will be further described.

  As described above, the plurality of types of standard cells included in the cell library have the same height. Specifically, the example shown in FIG. 6 has a height that is 14 times the vertical pitch Pv of the arrangement grid. Also, as described above, the width of the plurality of types of standard cells is an integral multiple of the unit width Wu (more precisely, a positive integer multiple). Specifically, the high threshold cell 10 has a width 8 times Wu, and the low threshold cells L7 and L9 have a width 7 times and 9 times Wu, respectively.

  Here, in the example shown in FIG. 6, the horizontal pitch Ph of the arrangement grid is equal to the unit width Wu of the standard cell. Therefore, in the high threshold cell 10, the left and right boundaries 22c and 22d of the first threshold adjustment pattern 22, the left and right boundaries 24c and 24d of the second threshold adjustment pattern 24, and the left and right boundaries 12c of the cell frame 12, The distances D1, D2, D3, and D4 with respect to 12d are ½ times the unit width Wu. The unit width Wu has a relationship of Wu ≧ Smin with the minimum space Smin between the threshold adjustment patterns determined by the design rule.

  Next, FIG. 7 is a layout diagram showing the arrangement of standard cells around the position B in FIG.

  In the lower right and upper left of FIG. 7, two high threshold cells 10 that are adjacent to each other at the position B and in contact with the cell frame over the width twice the horizontal pitch Ph of the arrangement grid are shown. Among these, the lower right high threshold cell 10 is arranged in the layout shown in FIG. On the other hand, the high threshold cell 10 at the upper left is arranged in a layout that is vertically inverted from that shown in FIG. In the lower left and upper right of FIG. 7, two low threshold threshold cells L7 having a width seven times the unit width Wu are arranged. As in the case of FIG. 6, only the frame is shown for these low threshold cells, and the display of the internal pattern is omitted.

  As shown in FIG. 2, in the high threshold cell 10 included in the cell library 60 of the present embodiment, the upper boundary 22 a of the first threshold adjustment pattern 22 overlaps the upper boundary 12 a of the cell frame 12. . For this reason, when the frames of the high threshold cells 10 adjacent in the vertical direction touch each other over a width that is twice or more the grid pitch Ph, the upper boundaries 12a of the threshold adjustment patterns 22 of the cells adjacent in the vertical direction touch each other. In this way, the threshold adjustment patterns 22 of the upper and lower cells are integrated at a place where they are in contact with each other, and a minute space that violates the design rule does not occur between them.

  Furthermore, in the high threshold cell 10 included in the cell library of the present embodiment, the distance D1, between the left and right boundaries 22c and 22d of the first threshold adjustment pattern 22 and the left and right boundaries 12c and 12d of the cell frame 12 is set. D2 is ½ times the grid pitch Ph (or the unit width Wu of the standard cell). For this reason, when the frames of the high threshold cells 10 adjacent in the vertical direction touch each other over a width of twice or more the grid pitch Ph, the upper boundary 12a of the threshold adjustment pattern 22 of the cells adjacent in the vertical direction is the grid pitch Ph (or unit). It contacts over a width W1 that is at least one time the width Wu). That is, in the portion B, the pattern in which the threshold adjustment patterns 22 of vertically adjacent cells are integrated has a width equal to or greater than the grid pitch Ph (or unit width Wu).

  In the design rule of the 0.13 μm node semiconductor integrated circuit, the minimum value Wmin allowed for the width of the first and second threshold adjustment patterns is usually equal to each other, for example, 0.31 μm. That is, the relationship of Ph ≧ Wmin (or Wu ≧ Wmin) is established. Accordingly, at the position B, the first threshold value adjustment pattern does not violate the design rule with respect to its width.

  Similarly, in the case where the second threshold adjustment patterns of the high threshold cells adjacent to each other in the vertical direction are arranged adjacent to each other over a width more than twice the grid pitch Ph, the design rule is also violated. Will not cause.

  The value defined in the design rule varies depending on the manufacturing process to be used. However, generally, the pitch Ph (or unit width Wu) of the arrangement grid is a minimum value of the threshold adjustment pattern width (when the first threshold adjustment pattern and the second threshold adjustment pattern are set to different values). Is set to a larger value) Wmin or more. Accordingly, at the position B, neither the first threshold adjustment pattern nor the second threshold adjustment pattern causes a design rule violation.

  Further, FIG. 8 is a layout diagram showing the arrangement of standard cells around the position C in FIG.

  In the lower right and upper left of FIG. 8, two high threshold cells 10 that are adjacent to each other at the position C and in contact with the cell frame over the width of the pitch Ph in the horizontal direction of the arrangement grid are shown. Among these, the lower right high threshold cell 10 is arranged in the layout shown in FIG. On the other hand, the high threshold cell 10 at the upper left is arranged in a layout that is vertically inverted from that shown in FIG. In the lower left and upper right of FIG. 8, two low threshold threshold cells L8 having a width eight times the unit width Wu are arranged. As in the case of FIGS. 6 and 7, only the frame is shown for these low threshold cells, and the display of the internal pattern is omitted.

  As shown in FIG. 2, in the high threshold cell 10 included in the cell library of the present embodiment, the upper boundary 22 a of the first threshold adjustment pattern 22 overlaps the upper boundary 12 a of the cell frame 12. The distances D1 and D2 between the left and right boundaries 22c and 22d of the first threshold value adjustment pattern 22 and the left and right boundaries 12c and 12d of the cell frame 12 are the horizontal pitch Ph (or standard cell) of the arrangement grid. Of the unit width Wu). For this reason, when the frames of the high threshold cells 10 adjacent in the vertical direction touch each other over the width of the grid pitch Ph, the threshold adjustment patterns 22 of the cells adjacent in the vertical direction touch each other at one corner. That is, at the position C, the threshold adjustment pattern 22 has a width W2.

  This width W2 is less than the minimum value Wmin determined by the design rule, and a design rule violation occurs. However, the rule violation that occurs at position C can be easily resolved by the procedure shown in FIG.

  Here, returning to FIG. 3, the design method of the present embodiment will be further described. As shown in bold in FIG. 3, in the semiconductor integrated circuit pattern design method of this embodiment, a violation elimination pattern is prepared in advance to be additionally arranged to eliminate the design rule violation (ST2). ). Then, the violation elimination pattern prepared in ST2 is arranged at the violation location found in the design rule violation check (ST6), that is, at the position C shown in FIG. 8 (ST7).

  In the present embodiment, the occurrence of the design rule violation is limited to the position C, and the occurrence state (the width or space dimension that does not satisfy the design rule occurring at the violation location) is constant. Therefore, in step ST2 for preparing a violation elimination pattern, only one type of violation elimination pattern having a certain shape and size is prepared for the first and second threshold adjustment patterns, respectively.

  FIG. 9 is a layout diagram showing a state in which a violation elimination pattern is arranged at the position C shown in FIG.

  In the example shown in the figure, the violation elimination pattern 32 is a rectangle (a square in the case of Pv = Ph) whose vertical and horizontal sides have dimensions twice the vertical and horizontal grid pitches Pv and Ph, respectively. is there. The violation elimination pattern 32 is arranged with one side of the corner where the threshold adjustment patterns of adjacent cells in the vertical direction are in contact with each other and the sides parallel to the horizontal and vertical grids. In the layout data, the violation elimination pattern 32 is integrated with the threshold adjustment patterns 22 of the two adjacent high threshold cells 10. The minimum width (the length W3 of the arrow shown in FIG. 9) around the position C of the integrated threshold adjustment pattern is Ph × √2≈Ph × 1.4. This value is larger than the minimum width Wmin determined by the design rule. This eliminates the design rule violation.

  In addition, even when the second threshold adjustment patterns of the high threshold cells adjacent to each other in the vertical direction are arranged so that the cell frames are in contact with each other over the width of the grid pitch Ph, similarly, only one corner point is used. A contact is made and a design rule violation occurs. Even when such a design rule violation occurs with respect to the second threshold adjustment pattern, it can be easily resolved by the same procedure.

  Here, among the steps shown in FIG. 3, the design rule check of ST6 has been performed conventionally. On the other hand, the arrangement of the violation elimination pattern 32 in ST7 is a newly required procedure by arranging cells having different threshold voltages. However, the actual processing is simply placing the prepared pattern 32 at the position where the design rule violation has occurred. That is, it is not necessary to generate a violation elimination pattern or set the arrangement position of the generated pattern according to the pattern shape of each design rule violation location.

  Moreover, in the plurality of types of high threshold standard cells included in the cell library of the present embodiment, not only when the high threshold cells 10 shown in FIG. 1 are arranged one above the other, but also other types of high threshold standard cells. The positional relationship between the threshold adjustment patterns is the same even when two or different types of high threshold standard cells are arranged one above the other. That is, when two high threshold cells are arranged adjacent to each other in the vertical direction with their cell frames in contact with each other over the width of the grid pitch Ph, the threshold adjustment patterns are in contact with each other only at one corner. The design rule violation that occurs in the threshold adjustment pattern of the high threshold cell arranged in this way is caused by the same processing, that is, the same violation elimination pattern is placed at a fixed position (at the corner where the threshold adjustment patterns touch each other). Can be solved by arranging them together.

  The amount of calculation required for such a design rule violation elimination process is small, and the addition does not significantly increase the time and cost required for designing the semiconductor integrated circuit pattern.

  Note that it is not always essential for the present invention that the violation elimination pattern 32 is a square whose one side is twice the grid pitches Pv and Ph. Smaller dimensions may be used as long as the design rule violation can be resolved. Specifically, the dimension of the violation elimination pattern can be reduced within a range in which the width W3 indicated by the arrow in FIG. 9 does not fall below the minimum width Wmin determined by the design rule.

  On the other hand, for example, when the high threshold cell is also arranged at the lower left of the position C in FIG. 5, the horizontal dimension of the violation elimination pattern 32 is 2 of the grid pitch Ph in order to realize the elimination of the design rule violation. It is preferable that it is double or more.

  FIG. 10 is a layout diagram around the position C when the high threshold cell 10 is arranged at the lower left.

  In the lower right and upper left of FIG. 10, as in FIG. 8, two high-threshold cells 10 that are adjacent to each other at the position C and in contact with the cell frame over the width of the horizontal pitch Ph of the arrangement grid are shown. It is. Further, in FIG. 10, the same high threshold cell 10 is also arranged at the lower left. As shown in FIG. 2, in the standard cell 10 included in the library of the present embodiment, the distance between the left and right boundaries 22c and 22d of the first threshold value adjustment pattern 22 and the left and right boundaries 12c and 12d of the cell frame. Is 1/2 times the grid pitch Ph. Therefore, a space S2 that is the same as the grid pitch Ph is formed between the first threshold adjustment patterns 22 of the two high threshold cells 10 arranged in the horizontal direction on the lower side of FIG. This space is not less than the minimum space Smin defined by the design rule and satisfies the design rule.

  Here, if the horizontal dimension of the violation elimination pattern 32 arranged at the position C is inappropriate, the first threshold adjustment pattern 22 and the violation elimination pattern 32 of the high threshold cell 10 arranged at the lower left of the figure. A small space remains between and the design rule violation occurs.

  On the other hand, in FIG. 10, the horizontal dimension of the violation elimination pattern 32 is twice that of Ph, and the centers of the two high threshold cells 10 arranged at the lower right and upper left of the figure are One threshold adjustment pattern 22 is arranged so as to coincide with a point where the corners are in contact with each other. For this reason, the space S <b> 2 between the first threshold adjustment patterns 22 of the two high threshold cells 10 arranged adjacent to each other on the lower side of the figure is just filled with the violation elimination pattern 32. Therefore, a minute space that causes a design rule violation does not remain between the threshold adjustment patterns 22 of the high threshold cells 10 adjacent to the left and right.

  In this way, when the threshold adjustment patterns of the high threshold cells adjacent to each other at the top and bottom are in contact with each other at the corner and the high threshold cell is adjacent to the left and right at the position C where the design rule violation occurs, the violation occurs. The horizontal dimension of the cancellation pattern 32 is preferably twice the grid pitch Ph or more.

  The cell library, the semiconductor integrated circuit design method, the semiconductor integrated circuit pattern, and the semiconductor integrated circuit of the present invention have been described above by taking one embodiment as an example. In the above example, the distances D1, D2, D3, D4 between the left and right boundaries of the first and second threshold adjustment patterns of the plurality of high threshold cells included in the cell library and the left and right boundaries of the cell frame. However, all are constant at 1/2 times the horizontal pitch Ph (or standard cell unit width Wu) of the arrangement grid. In this case, the design rule violation occurs between the threshold adjustment patterns of the high threshold cells adjacent to each other in the vertical and horizontal directions. The position of C in FIG. 5, that is, the two high threshold cells are arranged in the horizontal direction of the arrangement grid. This is limited to the case where the cell frames are in contact with each other up and down over the width of the pitch Ph. In addition, at that position, the design rule violation occurs in a certain state in which the threshold adjustment patterns are in contact with each other at a corner. Therefore, the same violation eliminating pattern 32 having a predetermined shape and size prepared in advance can be easily eliminated.

  In FIG. 5 and FIGS. 6, 7, 8, 9, and 10, a plurality of types of standard cells are arranged while being inverted in the vertical direction, but are arranged without being inverted in the horizontal direction. However, it is also possible to arrange it in the left-right direction as well as the up-down direction while reversing as necessary.

  Thus, it is not always essential for the present invention that the distances D1, D2, D3, and D4 between the left and right boundaries of the threshold adjustment pattern and the left and right boundaries of the cell frame are constant. For example, part or all of these distances can be changed in units of 1/2 times the horizontal pitch Ph of the arrangement grid (or 1/2 times the unit width Wu of the standard cell). is there.

  FIG. 11 shows an example of the layout when D1, D2, D3, and D4 are all set to 1.5 times the horizontal pitch Ph (or the unit cell width Wu of the standard cell).

  FIG. 11 shows three high threshold cells 80 where D1 = D2 = D3 = D4 = Ph × 1.5 = Wu × 1.5. That is, in the lower right and upper left of FIG. 11, the upper boundary 12 a of the cell frame 12 is touched on the upper and lower sides over a width three times the horizontal pitch Ph (that is, the unit cell width Wu of the standard cell). Two high threshold cells 80 are shown. In the lower left of FIG. 11, the third high threshold cell 80 further includes the upper boundary 12 a or the right boundary 12 d of the cell frame 12, and the upper boundary 12 a of the cell frame 12 of the other high threshold cell 80 or Arranged in contact with the left boundary 12c.

  At this time, the threshold adjustment patterns 22 of the two high threshold cells 80 arranged at the lower right and upper left are in contact with each other at the corners, and a design rule violation occurs. However, the state of occurrence of this design rule violation is the same as that shown in FIG. 8 (threshold adjustment patterns are in contact at the corners). Therefore, similarly to the case shown in FIG. 9, it is possible to easily solve the problem by arranging one kind of violation eliminating pattern 32 prepared in advance.

  When D1 = D2 = Ph × 1.5, the horizontal direction of the arrangement grid is between the threshold adjustment patterns 22 of the high threshold cells 80 arranged adjacent to each other on the lower side in FIG. A space S3 that is three times the pitch Ph is formed. Therefore, as shown in FIG. 11, even if the violation elimination pattern 32 having a width twice as large as the grid pitch Ph is arranged, a space S4 that is twice as large as Ph remains and a design rule violation occurs. There is nothing.

  FIG. 11 shows the case where the first threshold adjustment patterns 22 are arranged next to each other vertically, but the same applies to the case where the second threshold adjustment patterns are arranged next to each other vertically. It is.

  Although not shown, when D1 = D2 = D3 = D4 = Ph × 1.5 = Wu × 1.5, except in the case shown in FIG. 11, the threshold adjustment patterns of the high threshold cells adjacent to each other vertically Design rule violations do not occur between each other. For example, the high threshold cells adjacent to each other in the upper and lower sides touch each other at the corner of the cell frame, or the cells have a width that is 1 or 2 times the horizontal pitch Ph (or the standard cell unit width Wu) of the arrangement grid. When touching the frame, the state is as shown in FIG. That is, a space of 1 or more times the grid pitch Ph is formed between the threshold adjustment patterns of the high threshold cells adjacent in the vertical direction. Further, FIG. 7 shows a case where the high threshold cells adjacent in the vertical direction touch the cell frame over a width of four times or more the horizontal pitch Ph (or standard cell unit width Wu) of the arrangement grid. It becomes a state like this. That is, the threshold adjustment patterns of the high threshold cells adjacent in the vertical direction are in contact with each other over a width of 1 or more times the grid pitch Ph and are integrated.

  Further, for example, all of D1, D2, D3, and D4 can be set to zero. In this case, when the cell frames of the high threshold cells arranged adjacent to each other at the top and bottom touch each other at the corner, the threshold setting patterns touch each other at the corner, causing a design rule violation. Also in this case, the design rule violation can be resolved by adding the same violation resolution pattern 32 shown in FIG. In this case, the threshold adjustment patterns of the high threshold cells adjacent to the left and right are in contact with each other at the right or left boundary of the cell frame and integrated. Therefore, a minute space that does not satisfy the design rule is not formed between the threshold adjustment patterns of the high threshold cells adjacent to the left and right.

  As described above, the distances D1, D2, D3, and D4 between the left and right boundaries of the threshold adjustment pattern and the left and right boundaries of the cell frame are the horizontal pitch Ph (or the standard cell unit width Wu) of the arrangement grid. Not only in the case of 1/2 times, but also in the case of n / 2 times, it is easily resolved by limiting the state where the design rule violation occurs between the threshold adjustment patterns of the high threshold cells adjacent to each other in the vertical direction In addition, it is possible to prevent a design rule violation from occurring between the threshold adjustment patterns of the high threshold cells adjacent to the left and right. Here, n is an integer of 0 or more.

  In this case, the value of n does not have to be the same for all of the plurality of types of high threshold cells included in the cell library. Further, it is not necessary that the value of n is the same for all of D1, D2, D3, and D4 for each high threshold cell. That is, D1 = Ph × n1 / 2 (or D1 = Wu × n2 / 2), D2 = Ph × n2 / 2 (or D2 = Wu × n2 / 2), D3 = Ph × n3 / 2 (or When expressed as D3 = Wu × n3 / 2), D4 = Ph × n4 / 2 (or D4 = Wu × n4 / 2), ni (i = 1, 2, 3, 4) is a plurality of types. High threshold cell and an integer greater than or equal to 0 that can be different for each i.

  When ni is not constant, the positional relationship between the high threshold cells adjacent in the vertical direction is not constant when the design rule violation occurs between the threshold adjustment patterns. However, the design method shown in FIG. 3 can be implemented no matter what positional relationship causes the design rule violation. That is, the position where the design rule violation is caused in ST6 is specified by the design rule violation check, and the violation elimination pattern is arranged in that position in ST7 to eliminate the violation.

  However, it is preferable that n1 and n2 are both even or both are odd. It is preferable that both n3 and n4 are even numbers or both are odd numbers. For example, when n1 = 1 and n2 = 2, the first threshold adjustment patterns of the high threshold cells adjacent in the vertical direction do not touch each other at the corner. However, a Ph × 1/2 space is formed between the first threshold adjustment patterns of the high threshold cells adjacent to each other in the vertical direction with their cell frames in contact with each other over the width of Ph. Further, the first threshold adjustment patterns of the high threshold cells adjacent to each other in the vertical direction with the cell frames in contact with each other over the width of Ph × 2 are in contact with each other over the width of Ph × 1/2. In the example of the 130 nm node semiconductor integrated circuit (Ph = 0.41 μm, Smin = Wmin = 0.31 μm), a design rule violation occurs in both of these high threshold cell arrangement relationships. As a result, the amount of calculation processing necessary for eliminating the violation increases.

  By setting Ph ≧ Smin × 2 or Ph ≧ Wmin × 2, it is possible to prevent the occurrence of a design rule violation in at least one of the above arrangement relationships. However, when the pitch of the arrangement grid is increased in this way, the area of the formed circuit block is increased. Therefore, the relationship between Smin and Wmin (usually the same value for the first and second threshold adjustment patterns, but the smaller value when set to different values) and Ph , Ph <Smin × 2 and Ph <Wmin × 2 enables the circuit block area to be reduced, and the left and right boundaries of the first and second threshold adjustment patterns and the left and right boundaries of the cell frame Between the high threshold cells where the above rule (n1 and n2 are both even or both are odd and both n3 and n4 are even or both are odd) and the design rule violation occurs It is preferable to limit the arrangement relationship.

  In the actual circuit block formation, arbitrary high threshold cells selected from a plurality of types of high threshold cells included in the standard cell library are arranged adjacent to each other in the vertical direction. Therefore, it is preferable that both n1 and n2 are even or odd in all of the plurality of types of high threshold cells included in the standard cell library, and both n3 and n4 are even or both are odd.

  It is also preferable that all of n1, n2, n3, and n4 are even or all are odd in all of the plurality of types of high threshold cells included in the library. In this case, the relative position of the design rule violation occurrence location with respect to the vertical arrangement grid can be made the same in the first threshold adjustment pattern and the second threshold adjustment pattern. Thereby, the violation can be solved more easily.

  Furthermore, it is not necessarily essential for the present invention that D1, D2, D3, and D4 are n / 2 times Ph. Here, the distance between the left and right boundaries of the threshold setting pattern and the left and right boundaries of the cell frame is considered as Di = di + Ph × ni / 2 (or Di = di + Wu × ni / 2). However, -Ph / 2 <di <Ph / 2 (or -Wu / 2 <di <Wu / 2).

  First, FIG. 6 shows a case where n1 = n2 = 1 and d1 = d2 = 0, and the first threshold adjustment pattern 22 of two high threshold cells 10 arranged adjacent to each other in the vertical direction. The distance between them is S1 = Ph = Wu. This distance is Ph + (d1 + d2) = Wu + (d1 + d2) when either or both of d1 and d2 are not zero. However, if it is within the range of Ph + (d1 + d2) ≧ Smin (or Wu + (d1 + d2) ≧ Smin), a small space that is less than Smin and violates the design rule is formed between the first threshold adjustment patterns 22. It will never be done. For example, when Ph = Wu = 0.41 μm and Smin = 0.31 μm as described above, a range of (d1 + d2) ≧ −0.1 μm is allowed.

  The same applies to the second threshold adjustment patterns 24. That is, as long as it is within the range of Ph + (d3 + d4) ≧ Smin (or Wu + (d3 + d4) ≧ Smin), the design is performed even at the position where the second threshold adjustment patterns are arranged adjacent to each other in the relationship shown in FIG. There is no rule violation.

  Next, FIG. 7 shows the case where n1 = n2 = 1 and d1 = d2 = 0, and the first threshold adjustment pattern of two high threshold cells 10 arranged adjacent to each other in the vertical direction. 22 touch each other over the width of W1 = Ph = Wu. This width is Ph- (d1 + d2) = Wu- (d1 + d2) when either or both of d1 and d2 are not zero. However, if it is within the range of Ph− (d1 + d2) ≧ Wmin (or Wu− (d1 + d2) ≧ Wmin), a portion with a width that violates the design rule is less than Wmin between the first threshold adjustment patterns. Never formed. For example, when Ph = Wu = 0.41 μm and Wmin = 0.31 μm as described above, a range of (d1 + d2) ≦ 0.1 μm is allowed.

  The same applies to the second threshold adjustment pattern 24. That is, if it is within the range of Ph− (d3 + d4) ≧ Wmin (or Wu− (d3 + d4) ≧ Wmin), the second threshold value adjustment pattern is positioned adjacent to the relationship shown in FIG. There is no design rule violation.

  Further, at the position shown in FIG. 9, when d1 + d2 is not 0, the first threshold adjustment patterns 22 of the high threshold cells adjacent in the vertical direction do not come into contact with each other at the corner. When d1 + d2> 0, the first threshold adjustment patterns 22 are in contact with each other over the width of d1 + d2. On the other hand, when d1 + d2 <0, a space equal to the absolute value of d1 + d2 is formed between the first threshold adjustment patterns 22. As described above, Smin ≦ Ph <Smin × 2 and Wmin ≦ Ph <Wmin × 2 and d1 + d2 is violated in the design rule at the position shown in FIGS. If it is within the range that does not occur, a design rule violation occurs at the position shown in FIG.

  However, if the position where the design rule violation occurs is limited, it can be easily eliminated by arranging the violation elimination pattern. The same applies to the second threshold adjustment pattern. Depending on the value of d1 + d2, it is necessary to adjust the dimension of the violation elimination pattern to be arranged. However, if the value of d1 + d2 is known in advance, in step ST2 of FIG. 3, if a violation resolution pattern having an appropriate dimension is prepared, in step ST7, it is easy only by arranging the prepared violation resolution pattern. The rule violation can be resolved.

  However, if the values of d1, d2, d3, and d4 are different among multiple types of high-threshold cells included in the standard cell library, a small space or width that does not satisfy the rule formed at the design rule violation location The dimensions change. In this case, it is necessary to prepare rule violation elimination patterns of various dimensions in step ST2 of FIG. 3, and in step ST7, it is necessary to select an appropriate dimension out of a plurality of rule violation elimination patterns. In order to avoid an increase in the amount of calculation processing due to such processing, it is preferable that the values of d1, d2, d3, and d4 are the same in the plurality of types of high threshold cells included in the cell library.

  It is also preferable that d1 = d2 and d3 = d4. In this case, even when the high threshold cell is allowed to be reversed in the left-right direction, the size of a minute space or width that does not satisfy the rule formed at the design rule violation location can be made constant. As a result, it is easy to violate by placing the same violation resolution pattern with a certain shape and size at multiple rule violation occurrence locations formed by arranging multiple types of high threshold cells in the circuit block. Can be resolved.

  It is also preferable that d1 + d2 = d3 + d4. In this case, the design rule violation state in the first threshold value adjustment pattern (the size of the minute space or width that does not satisfy the rule that occurs at the violation point) and the design rule violation state in the second threshold value adjustment pattern are the same. Become. For this reason, the violation elimination pattern of the same shape and dimension can be utilized for elimination of the rule violation between the first threshold adjustment pattern and the second threshold adjustment pattern.

  Furthermore, in order to prevent a design rule violation between the threshold setting patterns of the high threshold cells adjacent to the left and right, it is preferable that d1 + d2 ≦ 0 when n1 = n2 = 0. If d1 + d2> 0 when n1 = n2 = 0, a space of d1 + d2 is formed between the first threshold adjustment patterns of the high threshold cells adjacent to the left and right. Therefore, if Smin ≦ Ph <Smin × 2 and Wmin ≦ Ph <Wmin × 2, and d1 + d2 is a value that does not cause a design rule violation at the position shown in FIGS. 6 and 7, a design rule violation occurs. . Similarly, when n3 = n4 = 0, it is preferable to satisfy d3 + d4 ≦ 0.

  As described above, in the standard cell having the threshold adjustment pattern included in the cell library of the embodiment of the present invention, the upper boundary of the first threshold adjustment pattern and the lower boundary of the second threshold adjustment pattern 4 Are superimposed on the upper and lower boundaries of the cell frame, respectively. Then, the distances between the left and right boundaries of the threshold adjustment pattern and the left and right boundaries of the cell frame are appropriately set.

  In the design method according to the embodiment of the present invention, when such a standard cell is arranged to form a circuit block, the threshold value of the adjacent standard cell is obtained unless the standard cell is arranged in a limited positional relationship. It is possible to prevent design rule violations between adjustment patterns. A design rule violation that occurs in the case of being arranged in such a limited positional relationship can be easily eliminated by arranging a violation elimination pattern prepared in advance. Thereby, it is possible to design a semiconductor integrated circuit pattern in which cells including transistors having different thresholds are arranged at arbitrary positions without causing an increase in time and cost.

  Then, by using the semiconductor integrated circuit pattern designed in this way, it is possible to obtain a semiconductor integrated circuit in which cells including transistors having different thresholds are arranged at arbitrary locations and both the operation speed and the leakage current are optimized. it can.

  In the above description, the standard cell having the threshold adjustment pattern is the high threshold cell. However, conversely, as described above, the standard cell having the threshold adjustment pattern can be a low threshold cell.

  In an actual standard cell, patterns of other layers omitted in FIG. 1 and the like are also arranged. For example, a wiring pattern for forming an input terminal at the gate 20, a wiring pattern for connecting the drain 46 of the PMOS transistor 40 and the drain 56 of the NMOS transistor 50, and forming an output terminal of the inverter, the Vdd potential, A power supply wiring pattern or the like for supplying the GND potential is not shown in FIG. Also, a contact hole pattern for connecting these wirings to corresponding portions of the transistors 40 and 50 is not shown in FIG. Further, with respect to the pattern of the active layer, in addition to the portion shown in FIG. 1, in fact, the portion for supplying the Vdd potential to the source region 44 of the PMOS transistor 40 and the source region of the N-channel MOS transistor 54 is provided with a portion for supplying a GND potential.

  The Vdd power supply wiring pattern is provided over the entire width of the cell 10 along the upper boundary 12 a of the cell frame 12, and the GND power supply wiring pattern is provided along the lower boundary 12 b of the cell frame 12. When the standard cells are arranged as shown in FIG. 5 to form the circuit block 70, the power supply wiring patterns of the cells arranged on the left and right and top and bottom are integrated. As a result, Vdd and GND power supply wirings having lengths extending over the entire horizontal dimension of the circuit block are alternately arranged at the boundary between the respective cell columns. That is, the Vdd power supply wiring and the GND power supply wiring are alternately arranged in the vertical direction of the circuit block 70.

  Similarly, the N well and P well patterns are also integrated when the circuit block 70 is formed. N well and P well patterns having dimensions over the entire horizontal dimension of the circuit block 70 are alternately arranged in the vertical direction.

  By providing the Vdd and GND power supply wiring patterns in the second layer or higher metal layer, the active layer pattern and the gate pattern can be extended to the vicinity of the upper and lower boundaries of the cell frame. . As a result, the driving capability of the transistor can be increased. In such a case, it is necessary to extend the threshold adjustment pattern to the vicinity of the upper and lower boundaries of the cell frame. The present invention can be particularly suitably applied to standard cells having such a layout.

  In the standard cell 10 illustrated in FIG. 1, both the first and second threshold adjustment patterns 22 and 24 have a rectangular shape. However, this is not necessarily essential to the present invention. Other shapes can be employed. In this case, the left and right boundaries of the threshold adjustment pattern may be divided into a plurality.

  In this way, when the left and right boundaries of the threshold adjustment pattern are divided into multiple parts, the positional relationship of the standard cells that cause a design rule violation between the standard adjustment threshold patterns adjacent to the top and bottom can be limited and easily resolved In order to make this possible, the distance between the upper and lower boundaries of the threshold adjustment pattern and the left and right boundaries of the portion connected to the upper and lower boundaries of the cell frame should be set appropriately. It is necessary to determine. That is, with respect to the threshold adjustment pattern arranged on the upper side of the standard cell, the left and right boundaries of the portion connected to the upper boundary of the cell frame and the portion overlapping the upper boundary of the cell frame are It is necessary to set the distance appropriately. For the threshold adjustment pattern placed below the standard cell, the left and right borders of the cell frame are the same as the left and right borders of the part that is connected to the part of the lower border that overlaps the lower border of the cell frame. It is necessary to set the distance appropriately.

  On the other hand, in order not to cause a design rule violation between the threshold adjustment patterns of cells arranged adjacent to the left and right, the distance between the left and right boundaries of the cell frame is appropriately set for each of the divided left and right boundaries. Must be set.

  The standard cell library, semiconductor integrated circuit design method, semiconductor integrated circuit pattern, and semiconductor integrated circuit of the present invention have been described in detail above. However, the present invention is not limited to the above embodiment, and various improvements and changes can be made without departing from the spirit of the present invention.

It is a layout diagram of an example of a standard cell included in the cell library of the embodiment of the present invention. FIG. 2 is a layout diagram showing a state in which the standard cells shown in FIG. 1 are arranged along an arrangement grid. It is a flowchart which shows an example of embodiment of the design method of the semiconductor integrated circuit of this invention. It is a conceptual diagram which shows the structure of an example of embodiment of the cell library of this invention. It is a layout figure showing typically an example of a circuit block contained in a semiconductor integrated circuit pattern of the present invention. FIG. 6 is a layout diagram illustrating an arrangement of standard cells around a position A in FIG. 5. FIG. 6 is a layout diagram showing the arrangement of standard cells around the position B in FIG. 5. FIG. 6 is a layout diagram showing an arrangement of standard cells around a position C in FIG. 5. It is a layout figure which shows the state which has arrange | positioned the violation elimination pattern in the position of C shown in FIG. FIG. 6 is a layout diagram showing another arrangement of standard cells around the position C in FIG. 5. FIG. 6 is a layout diagram in which another high threshold cell is arranged. It is a layout figure of an example of the conventional standard cell. FIG. 13 is a layout diagram showing a part of a circuit block formed by arranging the standard cells of FIG. 12.

Explanation of symbols

10, 110 Standard cell 12, 112 Frame 16, 18, 116, 118 Active region pattern 20, 120 Gate pattern 40, 140 PMOS transistor 50, 150 NMOS transistor 22, 122 First threshold adjustment pattern 24, 124 Second threshold Adjustment pattern 32 Violation elimination pattern 60 Standard cell library 70, 170 Circuit block H8, H9, H10, H12 High threshold cell L6, L7, L8, L9, L13 Low threshold cell Gh, Gv Arrangement grid

Claims (22)

In order to form a semiconductor integrated circuit by arranging a plurality of patterns in a cell frame having a certain height and a width that is an integral multiple of the unit width Wu, and arranging the cell frame so that the upper, lower, left, and right boundaries touch each other. A standard cell library including a plurality of types of standard cells,
The plurality of types of standard cells are
A pattern for forming a first conductivity type transistor disposed on the upper side in the cell frame; and a pattern for forming a second conductivity type transistor disposed on the lower side in the cell frame;
A first threshold adjustment pattern for performing an impurity addition for adjusting a threshold value of the first conductivity type transistor, the first threshold adjustment pattern having an upper boundary and a left and right boundary overlapping with an upper boundary of the cell frame; Each having a lower boundary and a left and right boundary overlapping with the lower boundary, and a second threshold adjustment pattern for adding an impurity for adjusting the threshold of the second conductivity type transistor,
A distance D1 between a left boundary of the first threshold adjustment pattern and a left boundary of the cell frame; a distance between a right boundary of the first threshold adjustment pattern and a right boundary of the cell frame; D2, a distance D3 between the left boundary of the second threshold adjustment pattern and the left boundary of the cell frame, and the right boundary of the second threshold adjustment pattern and the right boundary of the cell frame Includes a plurality of first standard cells each having a distance D4 between Di = Wu × ni / 2 (i = 1, 2, 3, 4, ni is an integer of 0 or more),
The minimum allowable width Wmin of each of the first and second threshold adjustment patterns determined by the design rule of the semiconductor integrated circuit, and the minimum allowable space Smin between the first and second threshold adjustment patterns. On the other hand, Wu ≧ Wmin and Wu ≧ Smin, and in the first plurality of types of standard cells, both n1 and n2 are even or both odd, and both n3 and n4 are even or both A standard cell library characterized by an odd number. In order to form a semiconductor integrated circuit by arranging a plurality of patterns in a cell frame having a certain height and a width that is an integral multiple of the unit width Wu, and arranging the cell frame so that the upper, lower, left, and right boundaries touch each other. A standard cell library including a plurality of types of standard cells,
The plurality of types of standard cells are
A pattern for forming a first conductivity type transistor disposed on the upper side in the cell frame; and a pattern for forming a second conductivity type transistor disposed on the lower side in the cell frame;
A first threshold adjustment pattern for performing an impurity addition for adjusting a threshold value of the first conductivity type transistor, the first threshold adjustment pattern having an upper boundary and a left and right boundary overlapping with an upper boundary of the cell frame; Each having a lower boundary and a left and right boundary overlapping with the lower boundary, and a second threshold adjustment pattern for adding an impurity for adjusting the threshold of the second conductivity type transistor,
A distance D1 between a left boundary of the first threshold adjustment pattern and a left boundary of the cell frame; a distance between a right boundary of the first threshold adjustment pattern and a right boundary of the cell frame; D2, a distance D3 between the left boundary of the second threshold adjustment pattern and the left boundary of the cell frame, and the right boundary of the second threshold adjustment pattern and the right boundary of the cell frame The first plurality of distances D4 are Di = di + Wu × ni / 2 (i = 1, 2, 3, 4, −Wu / 2 <di <Wu / 2, ni is an integer of 0 or more). Including a standard cell of seeds,
The minimum allowable width Wmin of each of the first and second threshold adjustment patterns determined by the design rule of the semiconductor integrated circuit, and the minimum allowable space Smin between the first and second threshold adjustment patterns. On the other hand, Wu ≧ Wmin and Wu ≧ Smin, in the first plurality of standard cells, both n1 and n2 are even or both odd, and both n3 and n4 are even or both Is an odd number
The respective values of d1, d2, d3, and d4 are the same throughout the first plurality of types of standard cells, Wu + (d1 + d2) ≧ Smin and Wu− (d1 + d2) ≧ Wmin, and Wu + (d3 + d4) ≧ Smin Wu− (d3 + d4) ≧ Wmin, d1 + d2 ≦ 0 when n1 = n2 = 0, and d3 + d4 ≦ 0 when n3 = n4 = 0. .   3. The standard cell library according to claim 2, wherein d1 = d2 and d3 = d4.   4. The standard cell library according to claim 2, wherein d1 + d2 = d3 + d4.   All of n1, n2, n3, and n4 are even numbers in all of the first plurality of standard cells, or all of n1, n2, n3, and n4 are odd numbers. 4. The standard cell library according to any one of 4.   6. The standard cell library according to claim 1, wherein Wu <Wmin × 2 and Wu <Smin × 2. A standard cell library including a plurality of types of standard cells in which a plurality of patterns are arranged in a cell frame having a common height and an integral multiple of the unit width Wu is prepared, and at least a part of the plurality of types of standard cells A method of designing a semiconductor integrated circuit including a step of selecting and arranging circuit blocks by vertically and alternately inverting the cell frame along the arrangement grid and in contact with the upper, lower, left, and right boundaries of the cell frame. There,
The horizontal pitch of the arrangement grid is Ph;
The plurality of types of standard cells are
A pattern for forming a first conductivity type transistor disposed on the upper side in the cell frame; and a pattern for forming a second conductivity type transistor disposed on the lower side in the cell frame;
A first threshold adjustment pattern for performing an impurity addition for adjusting a threshold value of the first conductivity type transistor, the first threshold adjustment pattern having an upper boundary and a left and right boundary overlapping with an upper boundary of the cell frame; Each having a lower boundary and a left and right boundary overlapping with the lower boundary, and a second threshold adjustment pattern for adding an impurity for adjusting the threshold of the second conductivity type transistor,
A distance D1 between a left boundary of the first threshold adjustment pattern and a left boundary of the cell frame; a distance between a right boundary of the first threshold adjustment pattern and a right boundary of the cell frame; D2, a distance D3 between the left boundary of the second threshold adjustment pattern and the left boundary of the cell frame, and the right boundary of the second threshold adjustment pattern and the right boundary of the cell frame Includes a first plurality of types of standard cells each having a distance D4 between Di = Ph × ni / 2 (i = 1, 2, 3, 4, ni is an integer of 0 or more);
The minimum allowable width Wmin of each of the first and second threshold adjustment patterns determined by the design rule of the semiconductor integrated circuit, and the minimum allowable space Smin between the first and second threshold adjustment patterns. On the other hand, Ph ≧ Wmin and Ph ≧ Smin, and in the first plurality of standard cells, both n1 and n2 are even or both odd, and both n3 and n4 are even or both A method for designing a semiconductor integrated circuit, characterized in that is an odd number. A standard cell library including a plurality of types of standard cells in which a plurality of patterns are arranged in a cell frame having a common height and an integral multiple of the unit width Wu is prepared, and at least a part of the plurality of types of standard cells A method of designing a semiconductor integrated circuit including a step of selecting and arranging circuit blocks by vertically and alternately inverting the cell frame along the arrangement grid and in contact with the upper, lower, left, and right boundaries of the cell frame. There,
The horizontal pitch of the arrangement grid is Ph;
The plurality of types of standard cells are
A pattern for forming a first conductivity type transistor disposed on the upper side in the cell frame; and a pattern for forming a second conductivity type transistor disposed on the lower side in the cell frame;
A first threshold adjustment pattern for performing an impurity addition for adjusting a threshold value of the first conductivity type transistor, the first threshold adjustment pattern having an upper boundary and a left and right boundary overlapping with an upper boundary of the cell frame; Each having a lower boundary and a left and right boundary overlapping with the lower boundary, and a second threshold adjustment pattern for adding an impurity for adjusting a threshold of the second conductivity type transistor,
A distance D1 between a left boundary of the first threshold adjustment pattern and a left boundary of the cell frame; a distance between a right boundary of the first threshold adjustment pattern and a right boundary of the cell frame; D2, a distance D3 between the left boundary of the second threshold adjustment pattern and the left boundary of the cell frame, and the right boundary of the second threshold adjustment pattern and the right boundary of the cell frame The first plurality of distances D4 are Di = di + Ph × ni / 2 (i = 1, 2, 3, 4, −Ph / 2 <di <Ph / 2, ni is an integer of 0 or more). Including a standard cell of seeds,
The minimum allowable width Wmin of each of the first and second threshold adjustment patterns determined by the design rule of the semiconductor integrated circuit, and the minimum allowable space Smin between the first and second threshold adjustment patterns. On the other hand, Ph ≧ Wmin and Ph ≧ Smin, in the first plurality of standard cells, both n1 and n2 are even or both odd, and both n3 and n4 are even or both Is an odd number,
The respective values of d1, d2, d3, and d4 are the same throughout the first plurality of types of standard cells, Ph + (d1 + d2) ≧ Smin and Ph− (d1 + d2) ≧ Wmin, and Ph + (d3 + d4) ≧ Smin And Ph− (d3 + d4) ≧ Wmin, d1 + d2 ≦ 0 when n1 = n2 = 0, and d3 + d4 ≦ 0 when n3 = n4 = 0. Design method.   9. The method of designing a semiconductor integrated circuit according to claim 8, wherein d1 = d2 and d3 = d4.   10. The method of designing a semiconductor integrated circuit according to claim 8, wherein d1 + d2 = d3 + d4.   All of n1, n2, n3, and n4 are even numbers or all of n1, n2, n3, and n4 are odd numbers in the whole of the first plurality of standard cells. 10. A method for designing a semiconductor integrated circuit according to any one of 10 above. A step of performing a violation check against the design rule for the first and second threshold adjustment patterns in the formed circuit block;
12. The method further comprising the step of resolving the violation by arranging a prepared violation resolution pattern at a violation occurrence location where the violation is detected by the violation check. A method for designing a semiconductor integrated circuit according to claim 1.   13. The method for designing a semiconductor integrated circuit according to claim 7, wherein Ph <Wmin × 2 and Ph <Smin × 2.   14. The method for designing a semiconductor integrated circuit according to claim 7, wherein Wu = Ph. A plurality of types of standard cells in which a pattern of a plurality of layers is arranged in a cell frame having a common height and an integral multiple of the unit width Wu are connected to each other along upper, lower, left, and right boundaries of the cell frame along the arrangement grid. A pattern of a semiconductor integrated circuit including circuit blocks arranged while being alternately inverted in the vertical direction,
The horizontal pitch of the arrangement grid is Ph;
The plurality of types of standard cells are
A pattern for forming a first conductivity type transistor disposed on the upper side in the cell frame; and a pattern for forming a second conductivity type transistor disposed on the lower side in the cell frame;
A first threshold adjustment pattern for performing an impurity addition for adjusting a threshold value of the first conductivity type transistor, the first threshold adjustment pattern having an upper boundary and a left and right boundary overlapping with an upper boundary of the cell frame; Each having a lower boundary and a left and right boundary overlapping with the lower boundary, and a second threshold adjustment pattern for adding an impurity for adjusting the threshold of the second conductivity type transistor,
A distance D1 between a left boundary of the first threshold adjustment pattern and a left boundary of the cell frame; a distance between a right boundary of the first threshold adjustment pattern and a right boundary of the cell frame; D2, a distance D3 between the left boundary of the second threshold adjustment pattern and the left boundary of the cell frame, and the right boundary of the second threshold adjustment pattern and the right boundary of the cell frame Includes a first plurality of types of standard cells each having a distance D4 between Di = Ph × ni / 2 (i = 1, 2, 3, 4, ni is an integer of 0 or more);
The minimum allowable width Wmin of each of the first and second threshold adjustment patterns determined by the design rule of the semiconductor integrated circuit, and the minimum allowable space Smin between the first and second threshold adjustment patterns. On the other hand, Ph ≧ Wmin and Ph ≧ Smin, and in the first plurality of standard cells, both n1 and n2 are even or both odd, and both n3 and n4 are even or both Is an odd-numbered semiconductor integrated circuit pattern. A plurality of types of standard cells in which a pattern of a plurality of layers is arranged in a cell frame having a common height and an integral multiple of the unit width Wu are connected to each other along upper, lower, left, and right boundaries of the cell frame along the arrangement grid. A pattern of a semiconductor integrated circuit including circuit blocks arranged while being alternately inverted in the vertical direction,
The horizontal pitch of the arrangement grid is Ph;
The plurality of types of standard cells are
A pattern for forming a first conductivity type transistor disposed on the upper side in the cell frame; and a pattern for forming a second conductivity type transistor disposed on the lower side in the cell frame;
A first threshold adjustment pattern for performing an impurity addition for adjusting a threshold value of the first conductivity type transistor, the first threshold adjustment pattern having an upper boundary and a left and right boundary overlapping with an upper boundary of the cell frame; Each having a lower boundary and a left and right boundary overlapping with the lower boundary, and a second threshold adjustment pattern for adding an impurity for adjusting the threshold of the second conductivity type transistor,
A distance D1 between a left boundary of the first threshold adjustment pattern and a left boundary of the cell frame; a distance between a right boundary of the first threshold adjustment pattern and a right boundary of the cell frame; D2, distance D3 between the left boundary of the second threshold adjustment pattern and the left boundary of the cell frame, and the boundary between the right boundary of the second threshold adjustment pattern and the right side of the cell frame The distance D4 between the first and the second is Di = di + Ph × ni / 2 (i = 1, 2, 3, 4, −Ph / 2 <di <Ph / 2, ni is an integer of 0 or more) Includes multiple types of standard cells,
The minimum allowable width Wmin of each of the first and second threshold adjustment patterns determined by the design rule of the semiconductor integrated circuit, and the minimum allowable space Smin between the first and second threshold adjustment patterns. On the other hand, Ph ≧ Wmin and Ph ≧ Smin, and in the first plurality of standard cells, both n1 and n2 are even or both odd, and both n3 and n4 are even or both Is an odd number,
The respective values of d1, d2, d3, and d4 are the same throughout the first plurality of types of standard cells, Ph + (d1 + d2) ≧ Smin and Ph− (d1 + d2) ≧ Wmin, and Ph + (d3 + d4) ≧ Smin And Ph− (d3 + d4) ≧ Wmin, d1 + d2 ≦ 0 when n1 = n2 = 0, and d3 + d4 ≦ 0 when n3 = n4 = 0. pattern.   17. The semiconductor integrated circuit pattern according to claim 16, wherein d1 = d2 and d3 = d4.   18. The semiconductor integrated circuit pattern according to claim 16, wherein d1 + d2 = d3 + d4.   16. All of n1, n2, n3, and n4 are even numbers or all of n1, n2, n3, and n4 are odd numbers in all the first plurality of standard cells. The semiconductor integrated circuit pattern according to any one of 18.   In each of the first and second threshold adjustment patterns arranged by arranging the first plurality of types of standard cells in the circuit block, a plurality of violation occurrence locations causing violations of the design rule. 20. The semiconductor integrated circuit pattern according to claim 15, wherein the same violation elimination pattern is arranged to eliminate the violation.   21. The semiconductor integrated circuit pattern according to claim 15, wherein Ph <Wmin × 2 and Ph <Smin × 2.   22. A semiconductor integrated circuit, wherein the semiconductor integrated circuit pattern according to claim 15 is formed on a semiconductor substrate.

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