JP2007103459A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which can reduce on-state resistance through a gate electrode (MOS gate) with a trench electrode structure expanding in the depth direction (vertical direction) of a substrate, and can suppress a leak current even if wiring is formed on the surface of the substrate with an interlayer insulating film between, and to provide its manufacturing method. <P>SOLUTION: As a structure applicable to a MOSFET (field effect transistor) provided with a gate electrode G (MOS gate) of a trench electrode structure, a p-type diffused layer SP having a higher concentration than a p-type base area BS is formed around the surface of a substrate in a p-type base area BS. Furthermore, the concentration of a diffused layer SP is set higher than that of a source area S within a range not exceeding the solid solubility of conductive impurities relating to the diffused layer SP. <P>COPYRIGHT: (C)2007,JPO&amp;INPIT

Description

  The present invention relates to a semiconductor device constituting a MOS device (semiconductor element using a MOS structure) and a method for manufacturing the same, and particularly to a semiconductor device useful for a power device such as a power MOSFET, IGBT, or thyristor (MCT). And a manufacturing method thereof.

  As is well known, as this type of semiconductor device, for example, a transistor having a DMOS (double diffusion MOS) structure is well known. However, this DMOS transistor has a high on-resistance in a low withstand voltage to medium withstand voltage (about 50 V to 300 V) region, and development and practical use of a semiconductor device that can obtain a lower on-resistance in the same region are serious. It is desired.

  Therefore, in recent years, as described in Patent Document 1, for example, a gate electrode (MOS) that controls a current between a source and a drain in order to form a channel whose depth direction (longitudinal direction) is a channel width direction is used. A so-called three-dimensional power MOSFET (field effect transistor) that employs a trench electrode structure extending in the substrate depth direction has been proposed. Hereinafter, an outline of an example of such a three-dimensional power MOSFET will be described with reference to FIGS.

  First, the structure of this three-dimensional power MOSFET will be described with reference to FIGS. 15 and 16. FIG. 15 is a plan view showing a schematic structure of this transistor, and FIG. 16 is a perspective view showing the structure in more detail by cutting out a region U indicated by a one-dot chain line in FIG.

  As shown in FIG. 15, a substrate (for example, a silicon substrate) serving as a base material of this transistor has trenches T1 formed continuously at a predetermined interval (isolation between trenches T1 (elements). (Separation) is not shown). When the inner and outer structures of the trench T1 are examined in detail, as shown in FIG. 16, the transistors are provided so as to face each other (specifically, facing the Y direction and the Z direction in the figure). The n-type source region S (inside the trench T1) and the n-type drain region D (outside the trench T1) are also provided. Further, a p-type base region BS is extended from the surface of the substrate so as to surround the adjacent source region S. Furthermore, an n-type drift region DF having a lower concentration than the drain region D is provided between the base region BS and the drain region D. A trench T is provided so as to penetrate the source region S and the base region BS in the depth direction of the substrate (Z direction in the drawing), and a gate made of, for example, silicon oxide is further provided inside the trench T. A gate electrode G made of, for example, polycrystalline silicon is formed through the insulating film GI. Note that the source region S, the drain region D, and the gate electrode G are led to terminals (for example, pads) SE, DE, and GE through predetermined wirings as shown in FIG. Similarly to the source region S, the base region BS is also electrically connected to the terminal SE.

  With this configuration, in this transistor, with the application of a voltage (gate voltage) to the gate electrode G, a predetermined portion of the base region BS adjacent to the gate electrode G (specifically, the gate electrode G and In the channel width direction in the Z direction and the Y direction in the figure. That is, the output current of the transistor flows between the terminals SE and DE (between the source and drain) in the Y direction and the Z direction in the drawing, respectively. Further, in order to obtain a large current as the output current, such gate electrodes G are formed continuously at a predetermined interval, and as shown in FIG. A voltage (gate voltage) is applied to each of the signals almost simultaneously.

  Next, a method for manufacturing the three-dimensional power MOSFET will be described with reference to FIGS. FIGS. 17A to 23A are cross-sectional views taken along the line AA ′ in FIG. 15, and FIGS. 17B to 23B are BB in FIG. It is sectional drawing along a line.

  In manufacturing this transistor, first, as shown in FIG. 17, a semiconductor substrate 1 made of, for example, n-type silicon is prepared, and on this substrate 1, for example, oxidation or CVD (chemical vapor) of a silicon substrate is prepared. By the phase growth, a mask material M1 for trench formation made of, for example, silicon oxide is formed, and the mask material M1 is patterned through an appropriate photolithography process and further an etching process (dry or wet).

  Next, as shown in FIG. 18, trenches T <b> 1 (FIG. 15) are formed in the substrate 1 by performing etching (dry or wet) using the mask material M <b> 1 as a mask from the surface side of the substrate 1. The dimensions of the trench T1 are set, for example, to a depth (Z direction) “10 to 100 (μm)” and a width (Y direction) “10 to 100 (μm)”. Here, the mask material M1 is intentionally left, but the mask material M1 may be removed by etching when the trench T1 is formed.

Further, as shown in FIG. 19, this time, in order to bury the inside of the trench T1, the semiconductor film 2 made of n-type (n ⁻ -type) silicon having a concentration lower than that of the substrate 1 is formed by, for example, epitaxial growth. A semiconductor film 3 made of silicon and a semiconductor film 4 made of n-type silicon (or polycrystalline silicon) are sequentially deposited on the surface of the substrate 1. Then, for example, the surface of the substrate 1 is flattened as shown in FIG. 20 by performing the flattening polishing using the mask material M1 as a stopper, the removal of the mask material M1, and the final polishing. Subsequently, in order to form isolation (element isolation) between the trenches T1 (FIG. 15), the surface of the substrate 1 is subjected to, for example, LOCOS (LOCal Oxidation of Silicon) oxidation, and then, for example, by CVD, for example, silicon oxide. A trench forming mask material M2 is formed. Then, as shown in FIG. 21, the mask material M2 is patterned through, for example, a photolithography process and an subsequent etching process (dry or wet).

  Next, as shown in FIG. 22, by performing etching (dry or wet) using the mask material M2 as a mask from the surface side of the substrate 1, a trench T (FIG. 15) is formed in the substrate 1, and this Simultaneously with the formation of the trench T (or separately), the mask material M2 is removed by etching.

Next, for example, the inner wall portion of the trench T is oxidized to form a gate insulating film GI (FIG. 15) made of, for example, silicon oxide, and further, for example, n-type (n ^A gate electrode G (FIG. 15) made of polycrystalline silicon of ⁺ type is formed. Then, the surface of the substrate 1 is planarized by, for example, etch back. Furthermore, after this planarization, various wirings (electrodes) including a gate wiring for the gate electrode G through a normal manufacturing process (such as a photolithography process or an etching process (dry or wet)) of a semiconductor device, By forming a protective film or the like, this transistor is completed as shown in FIG. That is, the substrate 1 becomes the drain region D, the semiconductor film 2 becomes the drift region DF, the semiconductor film 3 becomes the base region BS, and the semiconductor film 4 becomes the source region S.

  FIG. 24 shows specific data regarding the relationship between the on-resistance and withstand voltage of two types of power devices including such a three-dimensional power MOSFET, with these elements taken on the vertical axis (on-resistance) and the horizontal axis (withstand voltage). The trend (characteristic) of each device is shown as a graph based on (theoretical limit data of a vertical DMOS transistor and simulation data of a three-dimensional power MOSFET).

As shown in FIG. 24, in the region of low withstand voltage to medium withstand voltage (about 50V to 300V), the three-dimensional power MOSFET tends to obtain lower on-resistance than the vertical DMOS transistor. . For example, if the gate electrode G having a trench electrode structure is formed to a depth of “30 (μm)”, the theoretical limit of the normalized on-resistance of the vertical DMOS transistor is limited in the region of the breakdown voltage “300 (V)”. It becomes possible to fall below. Incidentally, the adjustment and setting of the on-resistance and withstand voltage are usually performed through the setting of the width (thickness) of the drift region. That is, for example, when it is desired to keep the on-resistance small, the width of the drift region is set to be narrow. On the other hand, when it is desired to ensure a large withstand voltage, the width of the drift region is set wide.
Japanese Patent No. 3356162

  By the way, as shown in FIG. 25 (cross-sectional views corresponding to FIGS. 17 (a) to 23 (a)), such a transistor usually has an interlayer made of an appropriate insulating material (for example, silicon oxide) on the substrate surface. The wiring L (for example, source wiring) made of an appropriate wiring material (for example, aluminum) is used with the insulating film SI interposed therebetween. For this reason, a MOS structure is parasitically formed on the substrate surface by the wiring L, the interlayer insulating film SI, and the base region BS. For example, the wiring is caused by the influence of a disturbance (surge or the like) or disconnection (short). When a positive potential (voltage) is applied to L, electrons that are minority carriers gather on the surface of the p-type base region BS, and an unintended channel (inversion layer) is formed. The channel (inversion layer) thus generated acts to leak an unnecessary current even when the transistor is not operating, and as a result, a so-called leakage current is increased.

  The present invention has been made in view of the above circumstances, and it is possible to reduce the on-resistance through a gate electrode (MOS gate) having a trench electrode structure extending in the substrate depth direction (longitudinal direction), while providing an interlayer on the substrate surface. An object of the present invention is to provide a semiconductor device and a method for manufacturing the same that can suppress leakage current even when wiring is formed through an insulating film.

  In order to achieve such an object, the invention according to claim 1 uses a MOS structure such as a MOS device (eg, MOSFET, IGBT, thyristor (MCT), etc.) in a substrate which is a base material of the semiconductor device. A first impurity region and a second impurity region each having an arbitrary conductivity type provided so as to face each other to form a semiconductor element), and a surface of the substrate so as to surround the second impurity region. Extending in the depth direction of the substrate so as to constitute the MOS device together with a base region having a conductivity type different from that of the second impurity region and the first and second impurity regions. A gate electrode embedded in the trench through a gate insulating film and forming a channel in a predetermined portion of the base region according to an applied voltage. As conductor devices, in the vicinity of the substrate surface of at least the base region, the high diffusion layer density than the base region of the same conductivity type are provided structure.

  Thus, by providing a high-concentration diffusion layer, at least near the substrate surface of the base region, the number of majority carriers (for example, holes if the base region conductivity type is p-type) increases, Along with this, the number of minority carriers (for example, electrons if the conductivity type of the base region is p-type) decreases conversely. Therefore, even when a wiring is formed on the substrate surface via an interlayer insulating film and an inversion potential (inversion voltage) is applied to the wiring (see FIG. 25), minority carriers are less likely to collect near the substrate surface, As a result, the inversion layer is hardly formed near the surface of the substrate (in other words, the applied voltage required to form the inversion layer is increased). That is, according to such a structure as a semiconductor device, interlayer insulation is provided on the substrate surface while reducing on-resistance through a gate electrode (MOS gate) having a trench electrode structure extending in the substrate depth direction (longitudinal direction). Even when the wiring is formed through the film, it is difficult to form an unintended current path (inversion layer) near the substrate surface, and as a result, the leakage current is suppressed.

  In the semiconductor device according to claim 1, although the concentration of the high concentration diffusion layer provided in the base region needs to be set higher than that of the base region, the conductivity of the diffusion layer is not limited. If this is set so high that it exceeds the solid solubility of the type impurity (maximum density of impurities that are dissolved without being precipitated), the generation of defects may be caused by the precipitated impurities. Therefore, it is desirable that the concentration of the high-concentration diffusion layer is set within a range not exceeding the solid solubility of the conductive impurities related to the high-concentration diffusion layer.

  The inventor further suggests here that in addition to the above-described leakage current mechanism (generation principle), the diffusion (especially thermal diffusion) of the second impurity region may contribute to the leakage current. That is, in the conventional semiconductor device shown in FIGS. 15 and 16, when a post-process heat treatment (for example, heat treatment for impurity activation or recrystallization) is performed, a broken line in FIG. As indicated by, there is a concern that the conductive type impurity (n-type impurity) in the source region S (second impurity region) may diffuse into the p-type base region BS. When such diffusion is performed, the number of minority carriers (electrons in this example) increases near the substrate surface of the base region BS, and an inversion layer is easily formed here, or It is conceivable that the channel length (length of the inversion layer) contributing to current leakage is shortened by completely reversing and part of the base region BS becoming the source region S substantially. FIG. 26 shows a concentration profile (concentration of p-type impurity) of the base region BS after the heat treatment as a result of the inventor's simulation. As shown in FIG. 26, the concentration in the vicinity of the substrate surface is certainly reduced.

  Thus, it is considered that the diffusion (particularly thermal diffusion) of the second impurity region (for example, the source region S) also contributes to the leakage current. Therefore, according to the invention described in claim 3, in the semiconductor device according to claim 1 or 2, the concentration of the high concentration diffusion layer provided in the base region is set to the concentration of the second impurity region. The second impurity region is less likely to diffuse into the base region. For example, even when a predetermined heat treatment is performed in a later step, diffusion into the base region (thermal diffusion) Will be suppressed. That is, according to the structure of the third aspect, the leakage current can be further suppressed.

  Such diffusion occurs particularly actively in the vicinity of an unstable substrate surface with many dangling bonds (unbonded hands). In this respect, according to the invention described in claim 4, in the semiconductor device according to claim 3, the high-concentration diffusion layer provided in the base region is extended to the second impurity region in the vicinity of the substrate surface. If extended, diffusion near the substrate surface is more efficiently suppressed by this high concentration (higher concentration than the second impurity region) diffusion layer.

  Further, according to the invention described in claim 5, in the semiconductor device according to any one of claims 1 to 4, the high-concentration diffusion layer provided in the base region has a depth of the substrate. If it is formed so as to extend in the direction, the diffusion is suppressed not only near the surface of the substrate but also deeper.

  Further, in this case, as in the sixth aspect of the invention, the high-concentration diffusion layer provided in the base region is extended along the interface between the second impurity region and the base region. Then, it can be easily formed by, for example, ion implantation from an oblique direction of the substrate surface.

  Further, here, the concentration profile of the high-concentration diffusion layer provided in the extended manner has a constant concentration region in the vicinity of the substrate surface as in the invention according to claim 7, and from there If the concentration becomes lower as the substrate proceeds in the depth direction, the concentration of the entire diffusion layer is increased without causing impurities to precipitate, for example, by setting a constant concentration region close to the solid solubility. In other words, it is possible to increase the concentration of the diffusion layer within a range not exceeding the solid solubility of impurities (see FIG. 4 for details). Such a concentration profile can also be easily formed, for example, by ion implantation from an oblique direction of the substrate surface.

  Further, since the above-described problem (leakage current) appears particularly prominently in a MOSFET (field effect transistor) (and adversely affects the transistor operation), the invention according to any one of claims 1 to 7 is provided. According to another aspect of the present invention, the first impurity region and the second impurity region are a drain region (first impurity region) and a source region (second impurity) having the same conductivity type. This is particularly effective when applied to the case where the MOS device is a MOSFET. In addition, as described above, it is desired to develop and put into practical use a semiconductor device having a lower on-resistance in a low breakdown voltage to medium breakdown voltage (about 50 V to 300 V) region.

  Further, in the semiconductor device according to claim 8, as in the invention according to claim 9, between the base region and the drain region, the same conductivity type having a lower concentration than the drain region is used. It is effective to have a structure in which a drift region is interposed. As described above, if such a drift region is provided, it is possible to easily perform adjustment and setting of on-resistance and withstand voltage, for example, through setting of the dimension (for example, width) of the drift region. Become.

  By the way, a three-dimensional MOSFET that employs a gate electrode (MOS gate) having a trench electrode structure parasitically causes a bipolar transistor (the source region and the gate region) due to the resistance component (potential distribution) of the base region formed deep in the substrate. (Parasitic bipolar formed by the drain region and the base region) is easily generated.

  In this regard, in the invention according to claim 10, in the semiconductor device according to claim 9, the high-concentration diffusion layer provided in the base region extends to the drift region in the vicinity of the substrate surface. I have to. As described above, the width (thickness) of the drift region affects on-resistance and breakdown voltage. Specifically, if the width of the drift region is set wide (large), the breakdown voltage increases (increases). In the structure according to the tenth aspect, since the width (thickness) of the drift region in the vicinity of the substrate surface is selectively narrowed by the high-concentration diffusion layer, the width of the drift region and the breakdown voltage can be reduced. As a result, a break point (a place where it is easy to make a break) is formed here. Further, since the width (thickness) of the drift region is selectively narrowed in the vicinity of the substrate surface, a sharp curve of the potential distribution (equipotential line) is also formed here. This portion (the narrow portion of the drift region) can easily be plunged by concentration. And, since the parasitic bipolar will not operate (transistor operation) even if it is made to break before the operation in this way, the undesired operation of the parasitic bipolar is also affected by the width of the high-concentration diffusion layer (more precisely, It is possible to more easily suppress (prevent) the diffusion layer by setting the degree to which the diffusion layer erodes the drift region.

  Further, in this case, as in the eleventh aspect of the invention, the high-concentration diffusion layer provided in the base region is extended to the drift region so as to protrude at least toward the drain region from the gate electrode. If this is done, the electric field concentration at the corners (corner portions) of the gate electrode (trench electrode) is relaxed, so that the reliability of the electrode is reduced due to the electric field concentration (details). This also suitably suppresses the deterioration of the electrode material and the life (for example, TDDB) (see FIG. 12 for details).

  Further, as described above, in obtaining a large current as an output current, as in the invention according to claim 12, in the semiconductor device according to any one of claims 1 to 11, the gate electrode is It is desirable that they are formed continuously at a predetermined interval and are electrically connected to each other in parallel.

  Further, as described above, the leakage current caused by the inversion layer near the substrate surface is caused by the semiconductor according to any one of the above claims 1 to 12, as in the invention according to claim 13. This is particularly noticeable when the device has a structure in which predetermined wiring is formed on the surface of the substrate via an interlayer insulating film (see FIG. 25). That is, the invention described in any one of claims 1 to 12 is particularly effective when applied to such a structure (structure described in claim 13).

  On the other hand, as a method for manufacturing a semiconductor device, a process for forming a trench at a desired location on a semiconductor substrate having a first impurity region of a predetermined conductivity type, as in the invention according to claim 14, Forming a suitable semiconductor film in the trench so as to form a base region having a conductivity type different from that of the first impurity region; and forming the base region formed on at least an inner wall portion of the trench. On the other hand, a step of ion-implanting a predetermined conductivity type impurity from an oblique direction on the surface of the semiconductor substrate, and an appropriate semiconductor film is further embedded in the trench so as to completely fill the trench. Forming a second impurity region of a conductivity type, in addition to the first impurity region, the second impurity region, and the base region Further, by forming a gate electrode embedded in a trench extending in the depth direction of the semiconductor substrate via a gate insulating film and forming a channel in a predetermined portion of the base region, these are formed. A method of causing each element to function as a MOS device is effective. According to such a method, this can be easily realized even with the structure according to any one of claims 5 to 7.

  Further, in this case, according to the invention described in claim 15, if the method further includes a heat treatment step after the ion implantation step to thermally diffuse the ion-implanted conductive impurities, the ion implantation step is performed. It is possible to suitably recover (recrystallize) crystal defects and the like generated along with the execution.

  Further, according to the invention described in claim 16, the method according to claim 14 or 15 is similar to the invention according to claim 8 in that the first impurity region and the second impurity region. Are a drain region (first impurity region) and a source region (second impurity region) having the same conductivity type, and are particularly effective when applied to the case where the MOS device is a MOSFET.

  When the drift region is formed, the semiconductor film according to the base region is formed in the formed trench as a step prior to the step of forming the base region. Forming an appropriate semiconductor film as a lower layer of the semiconductor layer, and the semiconductor film formed through this process is formed of the same conductivity type having a lower concentration than the drain region, and the base region and the drain region. A method of using a drift region interposed between the two is particularly effective.

(First embodiment)
A first embodiment of a semiconductor device and a method for manufacturing the same according to the present invention will be described below with reference to FIGS. In the semiconductor device of this embodiment as well, as in the semiconductor device illustrated in FIG. 15, the current between the source and the drain is formed in order to form a channel in which the depth direction of the substrate is the channel width direction. A so-called three-dimensional power MOSFET is assumed that employs a trench electrode structure extending in the substrate depth direction for a gate electrode (MOS gate) to be controlled.

  1 is a plan view showing a schematic structure of the transistor, FIG. 2A is a cross-sectional view taken along line AA ′ in FIG. 1, and FIG. 2B is a cross-sectional view taken along line BB in FIG. FIG. 2C is a cross-sectional view taken along the line CC ′ in FIG. 1. Here, only a part of the plan view shown in FIG. 15 is shown in an enlarged manner, and the schematic structure of the entire apparatus, which is a part equivalent to the apparatus shown in FIG. Yes. However, also in the transistor according to this embodiment, the trench T1 (epi-trench) is continuously formed on the base material (for example, a silicon substrate) with a predetermined interval (here, equal intervals). In addition, various elements (components of the transistor) formed in the trench T1 are used by being connected in parallel between the trenches T1 (in the end, For example, “1 to 10 (mm)” corners are cut out as chips and subjected to a sealing / inspection process and the like, and then a finished product (product). Further, the manner of pulling out (connecting) the terminals SE, DE, and GE is basically the same as the device illustrated in FIG. 15 (and FIG. 16). Further, wiring made of a suitable wiring material (for example, aluminum) is formed on the surface of the substrate through an interlayer insulating film made of a suitable insulating material (for example, silicon oxide), as in the apparatus illustrated in FIG. Has been.

  As shown in FIGS. 1 and 2, this transistor is also basically configured to have a structure according to the semiconductor device illustrated in FIG. However, here, a p-type diffusion layer SP having a concentration higher than that of the base region BS is further provided in the vicinity of the substrate surface of the base region BS, so that an inversion layer (channel) is formed in this portion, and a leakage current is generated. I try to suppress it.

  That is, also in this transistor, n-type source region S (second impurity region) and drain region D (first region) facing each other (specifically, facing the Y direction and Z direction in the figure) are formed inside the substrate. 1 impurity region) is provided, and a p-type base region BS extends from the surface of the substrate so as to surround the adjacent source region S. Between the base region BS and the drain region D, an n-type drift region DF having a lower concentration than the drain region D is provided. However, a p-type diffusion layer SP having a higher concentration than the base region BS is further provided near the substrate surface of the base region BS as described above.

Incidentally, in this embodiment, the dimensions and concentrations of these elements are set as follows.
Drain region D (conductivity type: n ⁺ ): width (Y direction) is set to “2 to 20 (μm)” and impurity concentration is set to “1 × 10 ¹⁸ to 1 × 10 ²⁰ (atoms / cm ³ )” Has been.
Source region S (conductivity type: n ⁺ ): width (Y direction) set to “1 to 20 (μm)” and impurity concentration set to “1 × 10 ¹⁸ to 1 × 10 ²¹ (atoms / cm ³ )” Has been.
Drift region DF (conductivity type: n ⁻ ): width (Y direction) set to “2 to 30 (μm)” and impurity concentration set to “1 × 10 ¹⁴ to 1 × 10 ¹⁶ (atoms / cm ³ )” Has been.
Base region BS (conductivity type: p): width (Y direction) is “0.5 to 4 (μm)” and impurity concentration is “1 × 10 ¹⁶ to 1 × 10 ¹⁸ (atoms / cm ³ )”. Is set.
Diffusion layer SP (conductivity type: p ⁺ ): The depth (Z direction) is “5 (μm)” or less, or “20 (%)” or less of the depth of the base region BS (this depth is The width (Y direction) is set to “0.5 to 4 (μm)” (however, it falls within the base region BS (the same width is also used)). Including)) range). The impurity concentration is higher than that of the base region BS and the source region S and does not exceed the solid solubility of the conductive impurity related to the diffusion layer SP, for example, “1 × 10 ¹⁶ −1”. × 10 ²¹ (atoms / cm ³ ) ”(however, considering the concentrations of the base region BS and the source region S, a more preferable range is“ 1 × 10 ¹⁸ to 1 × 10 ²⁰ (atoms / cm ³ ) ”. Is set).

  Here, the concentration profile of the drain region D, the source region S, the drift region DF, and the base region BS is a profile (distribution) that makes the concentration uniform in the depth direction of the substrate.

  Also in this transistor, as in the device illustrated in FIG. 15, a trench T is provided so as to penetrate the source region S and the base region BS in the depth direction of the substrate (Z direction in the drawing). A gate electrode G made of, for example, polycrystalline silicon is embedded in the trench T via a gate insulating film GI made of, for example, silicon oxide. That is, also in this transistor, as a voltage (gate voltage) is applied to the gate electrode G, a predetermined portion of the base region BS adjacent to the gate electrode G (specifically, a portion adjacent to the gate electrode G) is applied. Channels having the Z direction and Y direction in the figure as the channel width direction are formed, and currents flow in the Y direction and Z direction in the figure, respectively. Further, in order to obtain a large current as an output of the transistor, such gate electrodes G are continuously formed at a predetermined interval, and these are electrically connected in parallel as shown in FIG. A voltage (gate voltage) is applied to each of the signals almost simultaneously.

  Note that such a transistor can also be basically manufactured by a method similar to the method illustrated in FIGS. However, since the diffusion layer SP is newly provided in this transistor, when manufacturing this transistor, for example, after the planarization step (FIG. 20) after the formation of the semiconductor films 2 to 4 described above, or the gate After the planarization (etchback) step (FIG. 23) after the electrode G is formed, a step for forming such a diffusion layer SP is newly required. That is, for example, after ion implantation is performed on the vicinity of the substrate surface of the base region BS, the implanted conductivity type impurity (p-type) is activated (appropriate heat treatment is performed), and the like. An SP is formed.

Then, according to the semiconductor device and the manufacturing method thereof according to this embodiment described above, the following excellent effects can be obtained.
(1) The three-dimensional power MOSFET (field effect transistor) has a structure in which a p-type diffusion layer SP having a concentration higher than that of the base region BS is provided near the substrate surface of the p-type base region BS. Thus, by providing the high-concentration diffusion layer SP, the number of minority carriers (here, electrons) decreases at least near the substrate surface of the base region. As a result, a wiring is formed on the substrate surface via an interlayer insulating film, and even when an inversion potential (inversion voltage) is applied to the wiring (see FIG. 25), minority carriers are less likely to collect near the substrate surface. This makes it difficult to form the inversion layer near the surface of the substrate (in other words, the applied voltage required to form the inversion layer increases). That is, the above-described leakage current is suitably suppressed while reducing the on-resistance through the gate electrode G having a trench electrode structure extending in the substrate depth direction.

  (2) The gate electrode G having a trench electrode structure is formed so as to penetrate both the source region S and the base region BS in the depth direction of the substrate. As a result, channels are formed not only in one direction but also in two directions (the Y direction and the Z direction in FIG. 1), and a larger current can be controlled.

  (3) The concentration of the diffusion layer SP is set in a range that does not exceed the solid solubility of the conductive impurities related to the diffusion layer SP. As a result, it is possible to appropriately prevent the generation of defects caused by the precipitation of impurities.

  (4) Further, the concentration of the diffusion layer SP is set higher than the concentration of the source region S (second impurity region). As a result, the source region S is less likely to diffuse into the base region BS, and diffusion (thermal diffusion) into the base region BS is suppressed even when, for example, a predetermined heat treatment is performed in a subsequent process. That is, by doing so, the resistance against the above-described leakage current is further enhanced (for details, see also the simulation result of FIG. 26).

  (5) Among the MOS-based devices, the semiconductor device is configured as a MOSFET (field effect transistor). This makes it possible to operate the semiconductor device (transistor) with a lower on-resistance even in the above-described low breakdown voltage to medium breakdown voltage (about 50 V to 300 V) region (see FIG. 24).

  (6) The n-type drift region DF having a lower concentration than the drain region D is interposed between the p-type base region BS and the n-type drain region D. Thereby, it becomes possible to adjust and set the on-resistance and the breakdown voltage more easily through the setting of the dimension (for example, width) of the drift region DF.

  (7) The concentration profile of the drain region D, the source region S, the drift region DF, and the base region BS is a profile (distribution) that makes the concentration uniform in the depth direction of the substrate. As a result, the current flowing through the channel when the transistor is operated becomes constant without being biased in the depth direction. For this reason, it is possible to reduce the channel resistance and hence the on-resistance. In addition, it is possible to suppress the operation (ON drive) of the parasitic transistor, and the punch-through is less likely to occur by suppressing the extension of the depletion layer.

  (8) The gate electrode G having a trench electrode structure is formed continuously at a predetermined interval, and is electrically connected to each other in parallel. Thereby, a large current can be obtained as the output of the transistor.

  (9) Further, a predetermined wiring is formed on the surface of the substrate through an interlayer insulating film. Even in such a structure, if the present invention is applied, the above-described leakage current (see FIG. 25) can be greatly suppressed.

(Second Embodiment)
Next, with reference to FIGS. 3 to 5, a semiconductor device and a manufacturing method thereof according to a second embodiment of the invention will be described. However, as shown in FIG. 3 (a cross-sectional view corresponding to FIG. 2A), the apparatus according to this embodiment also basically has a structure similar to that of the apparatus of the first embodiment. Therefore, for the sake of convenience, description of the common structure (or operation) is omitted. That is, here, the difference from the apparatus of the first embodiment will be mainly described.

  First, the structure of this transistor will be described in detail with reference to FIGS. 3 is a cross-sectional view showing the schematic structure of this transistor (the same elements as those shown in FIGS. 1 and 2 are given the same reference numerals), and FIG. 4 is a diffusion layer. It is a graph which shows the density | concentration profile of SP. 4A shows the concentration profile of the diffusion layer SP according to the device of the first embodiment, and FIG. 4B shows the device according to the device of the second embodiment. The concentration profile of the diffusion layer SP is shown.

  As shown in FIG. 3, in this embodiment, the high-concentration diffusion layer SP is provided so as to extend in the depth direction of the substrate. Specifically, it extends along the interface between the p-type base region BS and the n-type source region S. That is, this suppresses diffusion (particularly thermal diffusion) of the source region S not only near the surface of the substrate but also deeper.

  Moreover, as shown in FIG. 4B, the concentration profile of the diffusion layer SP has a constant concentration region in the vicinity of the substrate surface, and tends to become lower as the depth of the substrate advances from there. (Characteristics)

  Specifically, in the apparatus of the first embodiment, as shown in FIG. 4A, the diffusion layer SP has a concentration profile having a relatively steep peak (maximum degree) near the substrate surface. It has become. On the other hand, in the apparatus according to the second embodiment, as shown in FIG. 4B, the diffusion layer SP has a concentration profile having a constant concentration region near the substrate surface. In other words, in this concentration profile, no peak exists or the peak is flat. For this reason, by setting this constant concentration region close to the solid solubility, the concentration of the entire diffusion layer SP can be increased within a range not exceeding the solid solubility of the impurity (without depositing impurities). It becomes possible.

  Next, with reference to FIGS. 5A to 5E, a method of manufacturing the semiconductor device according to this embodiment will be described in detail. 5A to 5E are also cross-sectional views corresponding to FIG. 2A.

  As shown in FIG. 5 (a), when manufacturing this device, first, a semiconductor substrate 1 made of, for example, n-type silicon is prepared, and after steps similar to the steps shown in FIGS. After forming the trench T1, a semiconductor film 2 made of n-type silicon having a lower concentration than the substrate 1 and a semiconductor film 3 made of p-type silicon are sequentially deposited on the surface of the substrate 1. However, in this embodiment, prior to the formation of the semiconductor film 4 (FIG. 19), as shown in FIG. 5B, the base region BS formed in the trench T1 (particularly the trench in the region BS) From the oblique direction of the substrate surface (for convenience, only one direction is shown) from the T1 inner wall portion, a high concentration (p) that implants ions of a predetermined conductivity type impurity (for example, boron) and extends in the depth direction of the substrate. Type) diffusion layer D1. At this time, the direction of ion implantation with respect to the substrate 1 is set to a desired angle, for example, by tilting the substrate 1.

  Further, in order to thermally diffuse the ion-implanted conductive impurities, an appropriate heat treatment (for example, at a temperature of “800 to 1000” ° C. for “5 to 20” minutes) is performed, and then shown in FIG. Thus, in order to completely fill the trench T1, the semiconductor film 4 made of, for example, n-type silicon (or polycrystalline silicon) is formed. Then, through a step according to the step shown in FIG. 20, the surface of the substrate 1 is flattened as shown in FIG.

  Then, through a process similar to the process shown in FIGS. 21 to 23, a trench T, a gate electrode G, various wirings (electrodes), a protective film, and the like are formed. This transistor is completed as shown in e). That is, even in the manufacturing process (manufacturing method) according to this embodiment, the substrate 1 becomes the drain region D, the semiconductor film 2 becomes the drift region DF, the semiconductor film 3 becomes the base region BS, and the semiconductor film 4 becomes the source region S. Further, the diffusion layer D1 becomes the diffusion layer SP.

  As described above, according to the semiconductor device and the manufacturing method thereof according to the present embodiment, in addition to the effects similar to the effects (1) to (9) according to the first embodiment or effects equivalent thereto. In addition, the following effects can be obtained.

  (10) The high concentration diffusion layer SP is formed so as to extend in the depth direction of the substrate. As a result, the diffusion of the source region S described above (see FIGS. 25 and 26 for details) is suppressed not only near the surface of the substrate but also deeper.

(11) Moreover, since the diffusion layer SP extends along the interface between the p-type base region BS and the n-type source region S, the formation thereof is easy.
(12) Further, the concentration profile of the diffusion layer SP has a region where the concentration is constant near the substrate surface, and becomes lower as the substrate proceeds in the depth direction (FIG. 4B). reference). This makes it possible to increase the concentration of the entire diffusion layer SP (to increase the concentration) within a range that does not exceed the solid solubility of the impurities (without depositing impurities).

  (13) Further, as a method for manufacturing the semiconductor device (MOSFET), a method (manufacturing process) as shown in FIG. 5 was adopted. This facilitates formation of the diffusion layer SP having the above-described form.

  (14) Further, as a step prior to the step of forming the semiconductor film 3 (base region BS), the semiconductor film 2 (drift region DF) which is the lower layer of the semiconductor film 3 (base region BS) is formed. Thus, the drift region DF can be easily formed.

  (15) In order to thermally diffuse the conductive impurities introduced into the substrate in the previous ion implantation step (see FIG. 5B), a heat treatment step is provided after the ion implantation step. As a result, it is possible to suitably recover (recrystallize) crystal defects and the like generated with the execution of the ion implantation.

(Third embodiment)
Next, with reference to FIG. 6 and FIG. 7, a third embodiment embodying the semiconductor device and the manufacturing method thereof according to the present invention will be described. However, as shown in FIGS. 6 and 7 (a plan view and a cross-sectional view corresponding to FIGS. 1 and 2), the apparatus according to this embodiment is basically the same as the first embodiment. Since it has a structure similar to that of the apparatus of the embodiment, description of common parts is omitted for convenience. That is, here, the difference from the apparatus of the first embodiment will be mainly described.

  Hereinafter, the outline of the transistor will be described in detail with reference to FIGS. 6 is a plan view showing a schematic structure of the transistor, FIG. 7A is a cross-sectional view taken along the line AA ′ in FIG. 6, and FIG. FIG. 7C is a cross-sectional view taken along line CC ′ in FIG. 6. In these drawings, the same elements as those shown in FIGS. 1 and 2 are denoted by the same reference numerals.

  As shown in FIGS. 6 and 7, in this embodiment, the high concentration diffusion layer SP is extended to the source region S in the vicinity of the substrate surface. As a result, the diffusion of the source region S described above (refer to FIG. 25 and FIG. 26 for details) is actively and efficiently suppressed especially near the active substrate surface.

Incidentally, in this embodiment, the dimension of the diffusion layer SP is set as follows (the concentration and the concentration profile are the same as those in the first embodiment).
Diffusion layer SP (conductivity type: p ⁺ ): The depth (Z direction) is “5 (μm)” or less, or “20 (%)” or less of the depth of the base region BS (this depth is The width (Y direction) is set to “1.0 to 10 (μm)” (however, the diffusion layer SP is also included in the source region S). The range is set.

  As described above, according to the semiconductor device and the manufacturing method thereof according to the present embodiment, in addition to the effects similar to the effects (1) to (9) according to the first embodiment or effects equivalent thereto. In addition, the following effects can be obtained.

  (16) The high concentration diffusion layer SP is extended to the source region S in the vicinity of the substrate surface, so that the diffusion in the vicinity of the substrate surface (specifically, the diffusion of the source region S) is caused by this high concentration (source The diffusion layer SP having a higher concentration than the region S is more efficiently suppressed.

(Fourth embodiment)
Next, with reference to FIG. 8 and FIG. 9, a fourth embodiment embodying the semiconductor device and the manufacturing method thereof according to the present invention will be described. However, as shown in FIGS. 8 and 9 (a plan view and a cross-sectional view corresponding to FIGS. 1 and 2), the apparatus according to this embodiment is basically the same as the first embodiment. Since it has a structure similar to that of the apparatus of the embodiment, description of common parts is omitted for convenience. That is, here, the difference from the apparatus of the first embodiment will be mainly described.

  The outline of this transistor will be described in detail below with reference to FIGS. 8 is a plan view showing a schematic structure of the transistor, FIG. 9A is a cross-sectional view taken along the line AA ′ in FIG. 8, and FIG. 9B is a cross-sectional view along B in FIG. FIG. 9C is a cross-sectional view taken along the line CC ′ in FIG. 8. In these drawings, the same elements as those shown in FIGS. 1 and 2 are denoted by the same reference numerals.

  As shown in FIGS. 8 and 9, in this embodiment, the high concentration diffusion layer SP is extended to the drift region DF in the vicinity of the substrate surface. As a result, the width (thickness) of the drift region DF in the vicinity of the substrate surface is selectively narrowed by the diffusion layer SP, and a break point (a place where it is easy to make a break) is formed here. In addition, since the width (thickness) of the drift region DF is selectively narrowed in the vicinity of the substrate surface, a sharp curve of the potential distribution is also formed here. This portion (the narrow portion of the drift region) can be easily plunged.

  Thus, in the semiconductor device (transistor) according to this embodiment, a break point is formed between the diffusion layer SP and the drift region DF (boundary) in the vicinity of the substrate surface. For this reason, the undesired operation of the parasitic bipolar (the parasitic bipolar formed by the source region S, the drain region D, and the base region BS) (see the description of “Means for Solving the Problems” for details) By setting the width of the diffusion layer SP (more precisely, the extent to which the diffusion layer SP erodes the drift region DF), it is possible to more easily suppress (prevent) the diffusion layer SP.

Incidentally, in this embodiment, the dimension of the diffusion layer SP is set as follows (the concentration and the concentration profile are the same as those in the first embodiment).
Diffusion layer SP (conductivity type: p ⁺ ): The depth (Z direction) is “5 (μm)” or less, or “20 (%)” or less of the depth of the base region BS (this depth is The width (Y direction) is set to “1.0 to 10 (μm)” (however, the diffusion layer SP is also included in the drift region DF). The range is set.

  As described above, according to the semiconductor device and the manufacturing method thereof according to the present embodiment, in addition to the effects similar to the effects (1) to (9) according to the first embodiment or effects equivalent thereto. In addition, the following effects can be obtained.

  (17) The above-described high-concentration diffusion layer SP is extended to the drift region DF in the vicinity of the substrate surface, so that the undesired operation of the above-mentioned parasitic bipolar (see “Means for Solving the Problems” in detail) (See description) can be more easily suppressed (prevented) by setting the width of the diffusion layer SP (more precisely, the extent to which the diffusion layer SP erodes the drift region DF). .

(Fifth embodiment)
Next, with reference to FIGS. 10 and 11, a fifth embodiment of the semiconductor device and the method for manufacturing the same according to the present invention will be described. However, as shown in FIGS. 10 and 11 (a plan view and a cross-sectional view corresponding to FIGS. 1 and 2), the apparatus according to this embodiment is basically the same as the fourth embodiment. Since it has a structure similar to that of the apparatus of the embodiment, description of common parts is omitted for convenience. That is, here, the difference from the apparatus of the fourth embodiment will be mainly described.

  The outline of this transistor will be described in detail below with reference to FIGS. 10 is a plan view showing a schematic structure of the transistor, FIG. 11A is a cross-sectional view taken along the line AA ′ in FIG. 10, and FIG. 11B is a cross-sectional view along B in FIG. FIG. 11C is a cross-sectional view taken along the line CC ′ in FIG. 10. In these drawings, the same elements as those shown in FIGS. 1 and 2 are denoted by the same reference numerals.

  As shown in FIGS. 10 and 11, in this embodiment, the high-concentration diffusion layer SP protrudes at least from the gate electrode G (trench protruding position) to the drain region D side, and the substrate surface. It extends to the drift region DF in the vicinity. Thereby, the electric field concentration at the corner (corner portion) of the gate electrode G (trench electrode) is relaxed.

  FIG. 12 is a plan view schematically showing the potential distribution in the vicinity of the gate electrode G with equipotential lines. In FIG. 12, (a) shows the potential distribution of the device according to the fourth embodiment, and (b) shows the potential distribution of the device according to the fifth embodiment. Yes.

  As shown in FIG. 12A, in the device of the fourth embodiment, the potential distribution (equipotential line) is curved along the trench T (gate electrode G). A sharp curve is formed at the corner (corner portion) of G (trench electrode). In contrast, in the apparatus of the fifth embodiment, as shown in FIG. 12B, the potential distribution (equipotential lines) in the vicinity of the gate electrode G is a straight line parallel to the drain region D. (In detail, it is formed so that straight lines are continuous). For this reason, the electric field concentration at the corner (corner portion) of the gate electrode G is alleviated (the break point is formed in the drift region DF), and the reliability of the electrode G is reduced due to the electric field concentration ( Specifically, deterioration of the electrode material and a decrease in lifetime (for example, TDDB) are suppressed.

In this embodiment, the dimensions of the diffusion layer SP are set as follows (the concentration and the concentration profile are the same as those in the first embodiment).
Diffusion layer SP (conductivity type: p ⁺ ): The depth (Z direction) is “5 (μm)” or less, or “20 (%)” or less of the depth of the base region BS (this depth is The width (Y direction) is set to “1.0 to 10 (μm)” (however, the diffusion layer SP is drained more than the gate electrode G). It is set to a range that protrudes toward the region D and is also located in the drift region DF.

  As described above, according to the semiconductor device and the manufacturing method thereof according to this embodiment, the same effects as the effects (1) to (9) and (17) according to the first and fourth embodiments. Or in addition to the effect according to it, the following effect can be obtained.

  (18) The high-concentration diffusion layer SP is extended to at least the drift region DF in the vicinity of the substrate surface in such a manner as to protrude at least toward the drain region D from the gate electrode G. The deterioration of the property (specifically, the deterioration of the electrode material and the life (for example, TDDB)) can be suitably suppressed.

(Other embodiments)
Each of the above embodiments may be modified as follows.
-You may make it implement combining each form of the said diffusion layer SP shown in said each embodiment. That is, for example, as shown in FIGS. 13 and 14 (a plan view and a cross-sectional view corresponding to FIGS. 1 and 2), this diffusion layer SP extends to both the source region S and the drift region DF in the vicinity of the substrate surface. It is also possible to have a structured. Or about the diffusion layer SP of each form shown in the said 3rd-5th embodiment, it can also be set as the structure extended in the depth direction of the board | substrate.

  In each of the above embodiments, the concentration profile of the drain region D, the source region S, the drift region DF, and the base region BS is a profile (distribution) that makes the concentration uniform in the depth direction of the substrate. This is not an essential configuration, and an arbitrary density profile can be adopted for each region.

  The isolation (element isolation) between the trenches T1 employed in each of the above embodiments is not an essential configuration, and the formation thereof can be omitted as appropriate according to the convenience of element design, for example.

  The present invention can be similarly applied to a structure in which the conductivity type of each element constituting the semiconductor device (transistor) is reversed, that is, a structure in which p-type and n-type are interchanged. However, in the case of an n-channel transistor like the transistors according to the above embodiments, carriers become electrons, so that the drift speed is increased and the on-resistance is also decreased.

  In each of the above embodiments, the gate electrode G having a trench electrode structure is formed so as to penetrate both the source region S and the base region BS in the depth direction of the substrate. However, the gate electrode G may be formed so as to stop in the source region S without penetrating these regions. However, in this case, current flows only in one direction (for example, the Y direction in FIG. 1).

  In each of the above embodiments, the gate electrodes G having a trench electrode structure are formed continuously at a predetermined interval, and are connected electrically in parallel with each other. However, this is not an essential configuration. Also, the application timing of the gate voltage to each gate electrode G is arbitrary, and for example, these may be sequentially turned on according to the traveling direction of the output current. Furthermore, the number of the gate electrodes G is completely arbitrary, and in an extreme case, one gate electrode is sufficient.

  In each of the above embodiments, a three-dimensional power MOSFET (field effect transistor) is illustrated as an example of a MOS device, but the present invention can be similarly applied to an arbitrary MOS device. For example, the present invention can be applied to an IGBT (Insulated Gate Bipolar Transistor) or a thyristor (MCT) in which the drain region D is changed to a p-type semiconductor region (collector region).

  The concentration of the diffusion layer SP (the same conductivity type as that of the base region BS) is arbitrary as long as it is higher than the base region BS. That is, even if the concentration of the diffusion layer SP exceeds the solid solubility of the conductive impurities related to the diffusion layer SP, it is possible to obtain the effect (1).

  The method for manufacturing the semiconductor device is not limited to the method illustrated in FIGS. 17 to 23 and is basically arbitrary. For example, with respect to the planarization process illustrated in FIG. 20, the degree of polishing of other elements (for example, a monitor element provided separately) can be seen by measuring the polishing time without using a stopper. As a result, a desired amount of polishing, and thus accurate planarization can be performed.

The top view which shows schematic structure of this semiconductor device (transistor) about 1st Embodiment of the semiconductor device which concerns on this invention, and its manufacturing method. 1A is a cross-sectional view taken along the line AA ′ in FIG. 1, FIG. 1B is a cross-sectional view taken along the line BB ′ in FIG. 1, and FIG. A cross-sectional view along the line C ′. Sectional drawing which shows schematic structure of this semiconductor device (transistor) about 2nd Embodiment of the semiconductor device which concerns on this invention, and its manufacturing method. (A) is a graph showing the concentration profile of the high concentration diffusion layer according to the device of the first embodiment, and (b) is the concentration profile of the high concentration diffusion layer according to the device of the second embodiment. Graph showing. (A)-(e) is sectional drawing which shows the manufacturing process about the manufacturing method of the semiconductor device of the said 2nd Embodiment. The top view which shows schematic structure of this semiconductor device (transistor) about 3rd Embodiment of the semiconductor device which concerns on this invention, and its manufacturing method. 6A is a cross-sectional view taken along line AA ′ in FIG. 6, FIG. 6B is a cross-sectional view taken along line BB ′ in FIG. 6, and FIG. A cross-sectional view along the line C ′. The top view which shows schematic structure of this semiconductor device (transistor) about 4th Embodiment of the semiconductor device which concerns on this invention, and its manufacturing method. 8A is a cross-sectional view taken along the line AA ′ in FIG. 8, FIG. 8B is a cross-sectional view taken along the line BB ′ in FIG. 8, and FIG. A cross-sectional view along the line C ′. The top view which shows schematic structure of this semiconductor device (transistor) about 5th Embodiment of the semiconductor device which concerns on this invention, and its manufacturing method. 10A is a cross-sectional view taken along the line AA ′ in FIG. 10, FIG. 10B is a cross-sectional view taken along the line BB ′ in FIG. 10, and FIG. A cross-sectional view along the line C ′. Regarding the potential distribution near the gate electrode, (a) shows the potential distribution of the device according to the fourth embodiment, and (b) shows the potential distribution of the device according to the fifth embodiment. The top view typically shown with a line. The top view which shows typically the modification of the form about the high concentration diffusion layer provided in the base region. (A) is a cross-sectional view taken along the line AA ′ in FIG. 13, (b) is a cross-sectional view taken along the line BB ′ in FIG. 13, and (c) is a cross-sectional view taken along the line C—B in FIG. A cross-sectional view along the line C ′. The top view which shows the outline | summary about an example of the conventional semiconductor device (transistor). The perspective view which cuts out the area | region U shown by the dashed-dotted line in FIG. 15, and shows the structure in detail. (A) And (b) is sectional drawing which shows the example of a manufacturing process about the manufacturing method of the conventional semiconductor device. (A) And (b) is sectional drawing which shows the example of a manufacturing process about the manufacturing method of the conventional semiconductor device. (A) And (b) is sectional drawing which shows the example of a manufacturing process about the manufacturing method of the conventional semiconductor device. (A) And (b) is sectional drawing which shows the example of a manufacturing process about the manufacturing method of the conventional semiconductor device. (A) And (b) is sectional drawing which shows the example of a manufacturing process about the manufacturing method of the conventional semiconductor device. (A) And (b) is sectional drawing which shows the example of a manufacturing process about the manufacturing method of the conventional semiconductor device. (A) And (b) is sectional drawing which shows the example of a manufacturing process about the manufacturing method of the conventional semiconductor device. Regarding the relationship between on-resistance and breakdown voltage of two types of power devices, a graph showing the tendency (characteristics) of each device based on specific data with these elements on the vertical axis (on-resistance) and horizontal axis (withstand voltage) . Sectional drawing which shows an example of the usage condition of a transistor (especially power MOSFET) for the example of the conventional semiconductor device (power MOSFET). The graph which shows the density | concentration profile (concentration of a p-type impurity) of the base area | region after heat processing as an inventor's simulation result.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 2-4 ... Semiconductor film | membrane, BS ... Base region, D ... Drain region, D1 ... Diffusion layer, DE, GE, SE ... Terminal, DF ... Drift region, G ... Gate electrode, GI ... Gate insulating film , S ... source region, SP ... diffusion layer, T, T1 ... trench.

Claims (17)

In the substrate that is the base material of the semiconductor device,
A first impurity region and a second impurity region each having an arbitrary conductivity type provided to face each other to form a MOS-based device;
A base region extending from the surface of the substrate so as to surround the second impurity region, and having a conductivity type different from that of the second impurity region;
In order to form the MOS device together with the first and second impurity regions, the base is buried in a trench extending in the depth direction of the substrate via a gate insulating film, and the base according to an applied voltage. A gate electrode that forms a channel in a predetermined portion of the region;
In a semiconductor device comprising:
A semiconductor device, wherein a diffusion layer having the same conductivity type and a higher concentration than the base region is formed at least near the substrate surface of the base region. The semiconductor device according to claim 1, wherein the concentration of the high-concentration diffusion layer provided in the base region is set in a range that does not exceed the solid solubility of the conductive impurity related to the high-concentration diffusion layer. The semiconductor device according to claim 1, wherein the concentration of the high-concentration diffusion layer provided in the base region is set to be higher than the concentration of the second impurity region. The semiconductor device according to claim 3, wherein the high-concentration diffusion layer provided in the base region extends to the second impurity region in the vicinity of the substrate surface. The semiconductor device according to claim 1, wherein the high-concentration diffusion layer provided in the base region is provided in a form extending in a depth direction of the substrate. The semiconductor device according to claim 5, wherein a high-concentration diffusion layer provided in the base region extends along an interface between the second impurity region and the base region. The concentration profile of the high-concentration diffusion layer provided in the extended mode has a constant concentration region near the substrate surface, and decreases from there toward the depth direction of the substrate. 6. The semiconductor device according to 6. The first impurity region and the second impurity region are a drain region and a source region having the same conductivity type, and the MOS device is a MOSFET. Semiconductor device. The semiconductor device according to claim 8, wherein a drift region having the same conductivity type and having a concentration lower than that of the drain region is interposed between the base region and the drain region. The semiconductor device according to claim 9, wherein the high-concentration diffusion layer provided in the base region extends to the drift region in the vicinity of the substrate surface. 11. The semiconductor device according to claim 10, wherein the high-concentration diffusion layer provided in the base region extends to the drift region in such a manner that the diffusion layer protrudes at least toward the drain region from the gate electrode. The semiconductor device according to claim 1, wherein the gate electrodes are continuously formed at a predetermined interval and are electrically connected to each other in parallel. The semiconductor device according to claim 1, wherein predetermined wiring is formed on a surface of the substrate via an interlayer insulating film. Forming a trench at a desired location of a semiconductor substrate having a first impurity region of a predetermined conductivity type;
Forming a base region having a conductivity type different from that of the first impurity region by forming an appropriate semiconductor film in the formed trench;
A step of ion-implanting a predetermined conductivity type impurity from an oblique direction of the surface of the semiconductor substrate to the base region formed in at least an inner wall portion of the trench;
Forming a second impurity region of a predetermined conductivity type by further burying an appropriate semiconductor film in the trench to completely fill the trench;
In addition to the first impurity region, the second impurity region, and the base region, the trench is further extended in a trench extending in the depth direction of the semiconductor substrate via a gate insulating film, A method for manufacturing a semiconductor device, comprising: forming a gate electrode for forming a channel in a predetermined portion of the base region, thereby causing each of these elements to function as a MOS-based device. The method of manufacturing a semiconductor device according to claim 14, further comprising a heat treatment step after the ion implantation step to thermally diffuse the ion-implanted conductive impurities. The semiconductor device according to claim 14 or 15, wherein the first impurity region and the second impurity region are a drain region and a source region having the same conductivity type, and the MOS device is a MOSFET. Method. As a step prior to the step of forming the base region,
Forming an appropriate semiconductor film as a lower layer of the semiconductor film in the base region in the formed trench;
The semiconductor film formed through this step is a drift region made of the same conductivity type having a lower concentration than the drain region and interposed between the base region and the drain region. The manufacturing method of the semiconductor device of description.

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