JP2007102056A - Display controller - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a display controller which is enabled to secure a bypass function when a fast serial interface for fast data communication with a host computer is employed. <P>SOLUTION: This display controller 10 can operate in normal mode or bypass mode. In the normal mode, an LCD interface 14 etc., operates based upon a first clock according to the normal mode. In the bypass mode, a bypass circuit 16 operates based upon a second clock according to the bypass mode. Then data output from the LCD interface 14 are transmitted to a display driver 40 in the normal mode and data output from the bypass circuit 16 are transmitted to the display driver 40 in the bypass mode. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

The present invention relates to a display control apparatus that is applied to a liquid crystal display or the like and is provided between a host computer and a display driver.

Conventionally, as a display control device applied to a liquid crystal display, for example, a device described in Patent Document 1 is known.
The display control device includes a normal mode for performing a normal display operation, and a bypass mode for operating as if the host computer and the display driver are directly connected.
Here, the bypass mode may be required to transmit a small amount of data discontinuously (intermittently) from the host computer to the display driver, and is used in such a case.

By the way, if the circuit related to the bypass mode is configured only by an asynchronous circuit that does not require any clock, it is not necessary to activate the PLL circuit included in the display control device and generating the system clock when using the bypass mode.
As such an advantage, for example, in a display device such as a mobile phone, only a clock display is 1
When it is desired to update every second, there is no need to start / stop the PLL circuit each time, there is no impact on the performance and processing complexity of the host computer, and the current consumption is reduced. Can do.
JP 2005-10638 A

By the way, the interface between the host computer and the display control device is changed from a parallel interface or a serial interface (9-bit to 3-wire system, 8-bit to 4-wire system, etc.) to a high-speed serial interface (high speed, low amplitude, difference). It is conceivable to shift to a data transfer specification based on a packet method using a moving signal.
As described above, when the interface between the host computer and the display control device shifts to the high-speed serial interface, the above-described bypass mode (bypass function) cannot be utilized and the above-described advantages cannot be expected. As a result, the following problems can be considered.

(1) When the display update by the high-speed serial interface is discontinuously performed, it is necessary to repeatedly start / stop the PLL circuit each time.
(2) When the command to be transferred to the display driver is in the initial state of lighting, for example, when it exceeds 100 events, the packet header and CRC are added to the command one event at a time.
Etc., and the total transfer performance is high-speed serial
As a result, the interface does not meet the initial expectations.

In view of the above, an object of the present invention is to provide a display control device that can ensure a bypass function when a high-speed serial interface that performs high-speed data communication with a host computer is employed. It is in.

In order to solve the above problems and achieve the object of the present invention, each invention has the following configuration.
That is, the first invention is a display control device provided between a host computer and a display driver, which performs high-speed data communication with the host computer and interprets data from the host computer. A high-speed serial interface that outputs data according to the interpretation, and a display interface that operates according to the normal mode according to the first clock when the data interpreted by the high-speed serial interface is in the normal mode. When the data interpreted by the high-speed serial interface is in the bypass mode, a bypass circuit that operates according to the bypass mode according to the second clock, and in the normal mode, from the display interface Data to the display driver and the bypass mode Case, and a, and transmitting means for transmitting the data from the bypass circuit to the display driver.

In a second aspect based on the first aspect, the transmission means selectively transmits the transmission circuit that transmits data to the display driver, and the output data from the display interface or the output data from the bypass circuit. And a selection circuit for outputting to the circuit.
A third invention further includes an asynchronous register for setting whether the mode is a normal mode or a bypass mode according to data interpreted by the high-speed serial interface according to the second invention, and according to the setting contents of the asynchronous register The selection circuit is controlled.

According to the present invention having such a configuration, a bypass function can be ensured when a high-speed serial interface that performs high-speed data communication with a host computer is employed.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
(Configuration of the embodiment)
The configuration of the embodiment of the display control apparatus of the present invention will be described with reference to the block diagram of FIG.
As shown in FIG. 1, the display control apparatus 10 according to this embodiment is provided between the host computer 30 and the display driver 40, and can perform high-speed serial communication with the host computer 30. The conventional serial communication or parallel communication can be performed.

The display control device 10 operates in a normal mode or a bypass mode based on an instruction from the host computer 30 and is necessary for displaying an LCD panel (not shown) with respect to the display driver 40 according to the operation mode. Data is provided.
Here, the normal mode is a mode in which normal display control is performed for display on an LCD panel (not shown) driven by the display driver 40.

On the other hand, the bypass mode is a mode for performing display control when it is desired to intermittently change a part of the display, such as a clock display on the LCD panel.
For this purpose, as shown in FIG. 1, the display control device 10 includes a high-speed serial interface 11, a synchronous register unit 12, an asynchronous register unit 13, an LCD interface (display interface) 14, a VRAM 15, and a bypass circuit. 16, a selection circuit 17, an input / output cell (I / O cell) 18, an input / output terminal 19, a selection circuit 20, and an input / output cell (I / O cell)
Cell) 21 and an input / output terminal 22.

As shown in FIG. 1, the synchronization register unit 12, the LCD interface 14, and the VRAM 15 operate synchronously with a system clock SCLK generated inside the display control device 10 and a pixel transfer clock PCLK that is a divided clock thereof. It consists of a synchronization circuit.
The system clock SCLK is generated by the PLL circuit 24 using the clock CLKI supplied to the clock input terminal 23. The frequency divider (divider) 25 includes a PLL circuit 2.
4 divides the system clock SCLK generated in step 4 to obtain a desired pixel transfer clock PCL.
K is generated. The generated pixel transfer clock PCLK is supplied to the clock selection circuit 26.
And supplied to the LCD interface 14.

Here, the frequency of the clock CLKI is, for example, 32 [KHz], the frequency of the system clock SCLK is, for example, 60 [MHz], and the frequency of the pixel transfer clock PCLK is, for example, several [MHz].
The bypass circuit 16 includes a synchronization circuit that operates in synchronization with the clock CLK selected by the clock selection circuit 26. Here, the clock C selected by the clock selection circuit 26
The frequency of LK is relatively lower than the frequency of the system clock SCLK.

The clock selection circuit 26 uses the clock CLKI supplied to the clock input terminal 23 or the pixel transfer clock PCLK from the frequency divider 25 as the clock CL of the bypass circuit 16.
K is selectively output. The clock selection circuit 26 outputs a ground potential when the bypass circuit 16 is not used (in the normal mode).

Furthermore, the clock selection circuit 26 can also use the pixel transfer clock PCLK from the frequency divider 5 when the PLL circuit 24 is activated.
Other than these synchronous circuits, a high-speed serial interface 11, an asynchronous register unit 13,
The selection circuit 17, the input / output cell 18, the selection circuit 20, and the input / output cell 21 operate asynchronously without using a clock.

Next, the configuration of each part in FIG. 1 will be described.
The high-speed serial interface 11 performs high-speed data communication with the host computer 30 by, for example, a packet method using a low amplitude differential signal. The high-speed serial interface 11 interprets data from the host computer 30 and outputs data corresponding to the interpretation.

The synchronous register unit 12 temporarily stores data corresponding to the interpretation of the high-speed serial interface 11, and includes a plurality of register groups that store the data.
The asynchronous register unit 13 temporarily stores data corresponding to the interpretation of the high-speed serial interface 11, and includes a plurality of register groups for storing each data as will be described later.

The LCD interface 14 operates in accordance with an instruction from the register of the synchronous register unit 12 in the normal mode. The VRAM 15 is an LCD interface 1
4 can read and write display data. Also pixel transfer clock
Sends and receives data in the PCLK cycle to the display driver.
The bypass circuit 16 operates in accordance with an instruction from the register of the asynchronous register unit 13 in the bypass mode.

The selection circuit 17 receives the parallel data from the LCD interface 14 and the bypass circuit 1.
6 is selectively output according to the register setting of the asynchronous register unit 13.
The input / output cell 18 transmits parallel data output from the selection circuit 17 to the display driver 40 or receives parallel data from the display driver 40 to receive the bypass circuit 16.
The selection is made according to the register setting of the asynchronous register unit 13.

The selection circuit 20 receives the serial data from the LCD interface 14 and the bypass circuit 1.
6 is selectively output according to the register setting of the asynchronous register section 13.
The input / output cell 21 transmits serial data output from the selection circuit 20 to the display driver 40 or receives serial data from the display driver 40 and receives the bypass circuit 16.
The selection is made according to the register setting of the asynchronous register section 13.

(Outline of operation in each mode of embodiment)
Next, an outline of the operation of the embodiment having such a configuration will be described with reference to FIG.
First, a case where the display control apparatus 10 operates in the normal mode based on an instruction from the host computer 30 will be described.
In this case, when the high-speed serial interface 11 receives an instruction to operate in the normal mode from the host computer 30, the instruction is set in the operation mode setting register of the asynchronous register unit 13.

As a result, the PLL circuit 24 starts operation by the control signal S1, and the system clock S
The CLK and the pixel transfer clock PCLK are generated, and the synchronization register unit 12, the LCD interface 14, and the VRAM 15 have their system clock (first clock) SC.
Synchronous operation is possible with LK and the pixel transfer clock PCLK.
In the normal mode, the selection circuit 17 outputs parallel data from the LCD interface 14 according to the setting of the parallel / serial mode setting register of the asynchronous register unit 13.
Alternatively, the selection circuit 20 outputs serial data from the LCD interface 14 or its use is set. At this time, the use of the input / output cells 18 and 21 is set according to the setting of the use of the selection circuits 17 and 20.

With the operation of the LCD interface 14, parallel data or serial data is output from the LCD interface 14 as data to be transferred to the display driver 40. At this time, if the use of the selection circuit 17 is set, parallel data is output and input to the input / output cell 18. When use of the selection circuit 20 is set, serial data is output and input to the input / output cell 21.

The parallel data input to the input / output cell 18 is transmitted to the display driver 40 in the form of parallel data. The serial data input to the input / output cell 20 is transmitted to the display driver 40 in the form of serial data.
Next, a case where the display control apparatus 10 operates in the bypass mode based on an instruction from the host computer 30 will be described.

In this case, when the high-speed serial interface 11 receives an instruction to operate in the bypass mode from the host computer 30, the instruction is set in the operation mode setting register of the asynchronous register unit 13.
As a result, the clock selection circuit 26 selects a clock by the clock selection signal S2,
The bypass circuit 16 can operate in synchronization with the selected clock (second clock) CLK.

At this time, the bypass circuit 16 is connected to the input / output terminal 19 or the input / output terminal 22.
The bypass circuit 16 transfers data to the display driver 40 or receives data from the display driver 40.

(Details of operation in bypass mode)
Next, detailed operation of the display control apparatus 10 when it operates in the bypass mode will be described.
Here, since the bypass mode further includes a write mode and a read mode, the operation in the write mode will be described first.
In this case, when the high-speed serial interface 11 receives an instruction to operate in the bypass mode and the write mode from the host computer 30, the instruction is set in the register group of the asynchronous register unit 13.

According to the setting, the clock selection circuit 26 selects a clock by the clock selection signal S2, and the bypass circuit 16 can perform a synchronous operation by the selected clock CLK.
Further, according to the setting, the operation of the input / output cells 18 and 21 sets to select the output / bypass circuit, and also sets to use one of the selection circuits 17 and 20.
Next, data is written into the bypass transfer data register of the asynchronous register unit 13.
Here, when the data in the bypass transfer data register is read, the transfer status can be referred to. After the data is written, the transfer status becomes active to indicate that fact.

Next, transfer data and a transfer trigger (level signal) are sent from the bypass transfer data register of the asynchronous register unit 13 to the bypass circuit 16.
Thereafter, when the selection circuit 17 and the input / output cell 18 are set to be usable, parallel data is output from the bypass circuit 16 at the cycle of the clock CLK. For this reason,
Since the parallel data is output to the input / output cell 18 via the selection circuit 17, the input / output cell 18 transmits the parallel data to the display driver 40 in parallel.

On the other hand, when the selection circuit 20 and the input / output cell 21 are set to be usable, serial data is output from the bypass circuit 16 at the cycle of the clock CLK. Therefore, since the serial data is output to the input / output cell 21 via the selection circuit 20, the input / output cell 21 transmits the serial data to the display driver 40 in series.
When transmission of all data is completed, the bypass circuit 16 sends an end signal (pulse) to a predetermined register of the asynchronous register unit 13.

As a result, the transfer status of the bypass transfer data register of the asynchronous register unit 13 becomes inactive. The transfer trigger is also deactivated.
Next, the operation in the read mode will be described.
In this case, when the high-speed serial interface 11 receives an instruction to operate in the bypass mode and the read mode from the host computer 30, the instruction is set in the register group of the asynchronous register unit 13.

According to the setting, the clock selection circuit 26 selects a clock by the clock selection signal S2, and the bypass circuit 16 can perform a synchronous operation by the selected clock CLK.
Further, according to the setting, the operation of the input / output cells 18 and 21 is set to select the input / bypass circuit.
Next, “1” is written in the trigger bit of the bypass trigger register of the asynchronous register unit 13. After the trigger bit is written, the transfer status becomes active.

Thereafter, a read operation trigger (level signal) is sent from the bypass transfer data register of the asynchronous register unit 13 to the bypass circuit 16.
Next, when the input / output cell 18 is set to be usable, parallel data transmitted in parallel from the display driver 40 is received by the input / output cell 18, and the received parallel data is read from the bypass circuit 16. Captured into the buffer. This reception operation is performed in the cycle of the clock CLK that drives the bypass circuit 16.

On the other hand, when the input / output cell 21 is set to be usable, serial data transmitted in series from the display driver 40 is received by the input / output cell 21, and the received serial data is read by the read buffer of the bypass circuit 16. Is taken in.
The bypass circuit 16 sends an end signal (pulse) to a predetermined register of the asynchronous register unit 13 when all data has been captured.

As a result, the transfer status of the bypass transfer data register of the asynchronous register unit 13 becomes inactive. Also, the read operation trigger is deactivated.
Thereafter, the data taken into the read buffer of the bypass circuit 16 is transferred to the high-speed serial interface 11 via the asynchronous register unit 13.
As described above, according to this embodiment, when the high-speed serial interface 11 that performs high-speed data communication with the host computer 30 is provided, the bypass function can be utilized.

Therefore, a large amount of data can be efficiently transferred to and from the host computer 30 by the high-speed serial interface 11. Furthermore, by the bypass function, fine settings for the display driver 40 and partial changes of the image data can be smoothly performed while ensuring reduction of power consumption.
(Other)
In the above embodiment, the transfer data register in the asynchronous register unit 13 has been described, but the specific configuration or the like has not been particularly described.

However, if the asynchronous register unit 13 has a plurality of transfer data registers in parallel and the read buffer in the bypass circuit 16 has a FIFO (First In First Out) structure, a single command / parameter transfer can be integrated. This can be performed continuously, and the above problem (2) can be solved.

It is a block diagram which shows the structure of embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Display control apparatus, 11 ... High-speed serial interface, 12 ... Synchronous register part, 13 ... Asynchronous register part, 14 ... LCD interface (display interface), 15 ... VRAM, 16: Bypass circuit, 17, 20 ... Selection circuit, 18, 21 ... Input / output cells (I / O cells), 19, 22 ... Input / output terminals

Claims (3)

A display control device provided between a host computer and a display driver,
A high-speed serial interface that performs high-speed data communication with the host computer, interprets data from the host computer, and outputs data according to the interpretation;
When the data interpreted by the high-speed serial interface is in a normal mode, a display interface that operates according to the normal mode according to a first clock;
When the data interpreted by the high-speed serial interface is in the bypass mode, a bypass circuit that operates according to the bypass mode according to the second clock;
Transmitting means for transmitting data from the display interface to the display driver in the normal mode, and transmitting data from the bypass circuit to the display driver in the bypass mode;
A display control apparatus comprising: The transmission means includes
A transmission circuit for transmitting data to the display driver;
A selection circuit that selectively outputs output data from the display interface or output data from the bypass circuit to the transmission circuit;
The display control apparatus according to claim 1, further comprising: An asynchronous register for setting whether the mode is a normal mode or a bypass mode according to data interpreted by the high-speed serial interface;
The display control apparatus according to claim 2, wherein the selection circuit is controlled in accordance with setting contents of the asynchronous register.

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