JP2007096150A - Esd protection circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an ESD protection circuit capable of realizing an ESD protective operation suitable for multifarious ESD phenomena, and of protecting an internal circuit from a breakage caused by the ESD phenomena. <P>SOLUTION: The ESD protection circuit is equipped with an ESD discharge circuit 11 which is arranged between a first node N1 and a second node N2; and a plurality of trigger circuits 12A, 12B which are arranged between the first node N1 and the ESD discharge circuit 11, and are constituted by different kinds of circuit components. The trigger circuits 12A, 12B supply a trigger current to the ESD discharge circuit 11. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an ESD protection circuit that prevents a current from flowing into a semiconductor integrated circuit or the like due to an electrostatic discharge (hereinafter referred to as ESD) phenomenon.

  In recent years, in the semiconductor integrated circuit, as the generation of transistors progresses, the gate insulating film is made thinner, and the insulating film withstand voltage of the internal circuit formed in the semiconductor integrated circuit is lowered. Furthermore, the operating voltage of the internal circuit is lowered due to the miniaturization of the elements. As a result, ESD destruction modes are complicated and diversified, and an ESD protection circuit having more flexible operation characteristics is demanded.

  In general, MOS field effect transistors (hereinafter referred to as MOSFETs), bipolar transistors (BJT), thyristors (SCR), or the like are widely used in ESD protection circuits. However, the single element constituting the ESD protection circuit has a high operating voltage and is difficult to control when a surge current is input due to an ESD phenomenon, and it is difficult to protect a fine device. Thus, an ESD protection circuit having a trigger circuit for operating the ESD protection circuit has been proposed. For example, Patent Documents 1 and 2 describe an ESD protection device including an ESD protection element and a trigger element as an example. With these techniques, it is possible to control the operating voltage of the ESD protection device.

However, the surge current generated by the actual ESD phenomenon is various. The breakdown voltage of the insulating film depends on the pulse width of the voltage due to the ESD phenomenon (for example, see Non-Patent Document 1), and the operating voltage of the internal circuit depends on the rise time of the voltage pulse due to the ESD phenomenon (for example, see Non-Patent Document 2). ). For this reason, in the conventional ESD protection circuit using a single trigger circuit, it is difficult to protect the internal circuit from destruction due to the ESD phenomenon.
US Pat. No. 5,629,545 JP 2002-43533 A EOS / ESD Symposium96, pp.85-94 AZHWang, "On-chip ESD Protection for Integrated Circuit", p.110

  An object of the present invention is to provide an ESD protection circuit that can realize an ESD protection operation suitable for various ESD phenomena and can protect an internal circuit from destruction due to the ESD phenomenon.

  An ESD protection circuit according to a first embodiment of the present invention includes an ESD discharge circuit disposed between a first node and a second node, and disposed between the first node and the ESD discharge circuit. And a plurality of trigger circuits each composed of different circuit elements, wherein the trigger circuit supplies a trigger current to the ESD discharge circuit.

  An ESD protection circuit according to a second embodiment of the present invention includes a plurality of ESD discharge circuits arranged between a first node and a second node, each of which is composed of different circuit elements, And a trigger circuit disposed between the node and the ESD discharge circuit, wherein the trigger circuit supplies a trigger current to the ESD discharge circuit.

  An ESD protection circuit according to a third embodiment of the present invention includes a plurality of ESD discharge circuits that are arranged between a first node and a second node, each composed of different circuit elements, A plurality of trigger circuits which are arranged between a node and the ESD discharge circuit, each of which is composed of different circuit elements, wherein the trigger circuit supplies a trigger current to the ESD discharge circuit, To do.

  According to the present invention, it is possible to provide an ESD protection circuit capable of realizing an ESD protection operation suitable for various ESD phenomena and capable of protecting an internal circuit from destruction due to the ESD phenomenon.

  Embodiments of the present invention will be described below with reference to the drawings. In the description, common parts are denoted by common reference symbols throughout the drawings.

[First Embodiment]
First, an ESD protection circuit according to a first embodiment of the present invention will be described. In the first embodiment, an ESD protection circuit is configured by one ESD discharge circuit and two trigger circuits.

  FIG. 1 is a schematic diagram showing the configuration of the ESD protection circuit of the first embodiment. The ESD protection circuit includes one ESD discharge circuit 11 and two trigger circuits 12A and 12B. An ESD discharge circuit 11 is disposed between the first node N1 and the second node N2, and trigger circuits 12A and 12B are disposed between the first node N1 and the ESD discharge circuit 11.

  FIG. 2 shows an example of the circuit configuration of the ESD protection circuit of the first embodiment. Here, a case where a thyristor is used as the ESD discharge circuit and an N-channel MOS transistor and a diode are used as the trigger circuit is shown. A thyristor (SCR) composed of bipolar transistors BT1 and BT2 is connected as an ESD discharge circuit 11 between the first node N1 and the second node N2. More specifically, the emitter of the bipolar transistor BT1 is connected to the first node N1, and the collector of the bipolar transistor BT1 is connected to the base of the bipolar transistor BT2. Further, the base of the bipolar transistor BT1 is connected to the collector of the bipolar transistor BT2, and the emitter of the bipolar transistor BT2 is connected to the second node N2.

  Between the first node N1 and the second node N2, diodes D1, D2, D3, D4 and a resistor R1 connected in series are connected as a trigger circuit 12A, and an N channel is further connected as a trigger circuit 12B. A MOS transistor NT1 and a resistor R2 are connected. Further, the base of the bipolar transistor BT2 constituting the thyristor is connected to a connection point between the diode D4 and the resistor R1, and a connection point between the N-channel MOS transistor NT1 and the resistor R2.

  In the ESD protection circuit having such a configuration, when a surge current is applied to the first node N1, the trigger current flows to the ESD discharge circuit 11 through the trigger circuit 12A or 12B. As a result, the thyristor constituting the ESD discharge circuit 11 is turned on, and a surge current flows into the second node N2 via the thyristor. In this way, the surge current generated by the ESD phenomenon or the like is prevented from flowing into the internal circuit, and the internal circuit is prevented from being destroyed.

  Next, the operation of the trigger circuit in the ESD protection circuit will be described. Here, the internal circuit includes a MOSFET. 3 and 4 show the breakdown voltage of the internal circuit. As shown in FIG. 3, the thermal breakdown voltage of the MOSFET in the internal circuit exceeds the breakdown voltage of the gate insulating film of the MOSFET. For this reason, the lower voltage of the thermal breakdown voltage in the MOSFET of the internal circuit or the breakdown voltage of the gate insulating film becomes the breakdown voltage of the internal circuit. Therefore, in order to protect the internal circuit, it is necessary to operate the trigger circuit at a voltage lower than the breakdown voltage of the internal circuit shown in FIG.

  FIG. 5 shows the operating voltage of the trigger circuit 12B using a MOSFET. In this case, the operating voltage of the trigger circuit 12B depends on the rise time of the surge current. FIG. 6 shows the operating voltage of the trigger circuit 12A using a diode, and the operating voltage of the trigger circuit 12A does not depend on the rise time of the surge current. Note that if the operating voltage of the trigger circuit is lowered and the operating voltage of the ESD protection circuit is made too low, the leakage current increases, and cannot be excessively lowered. Therefore, by using the trigger circuit 12B composed of a MOSFET and the trigger circuit 12A composed of a diode, as shown in FIG. 7, the operating voltage of the trigger circuit is lower than the breakdown voltage of the internal circuit and is set to the breakdown voltage. Set to change along. As a result, the internal circuit can be protected and the leakage current can be minimized.

  In the first embodiment, by using the trigger circuit 12B including a MOSFET that depends on the rise time of the surge current and the trigger circuit 12A including a diode that does not depend on the rise time of the surge current, various ESD phenomena, for example, It is possible to cope with surge currents with different rises and lengths, and a protection circuit with high ESD protection capability can be formed. For example, during the transportation of a semiconductor integrated circuit in a chip state or a packaged LSI, a surge current that rises quickly is often applied (A), although it depends on the handling environment. In addition, in the process of mounting a semiconductor integrated circuit in a chip state or a packaged LSI on a wiring board, a surge current having a slow rise may be applied (B). Furthermore, during the manufacture of a semiconductor integrated circuit, a surge current having a rise approximately in the middle of the two states described above is often applied (C). The ESD protection circuit of the first embodiment is particularly effective in the cases (A) and (C).

  FIG. 8 shows the ESD protection circuit of the first embodiment between the power supply voltage VDD terminal and the input / output I / O terminal, between the input / output I / O terminal and the reference potential Vss terminal, and between the power supply voltage VDD terminal and the reference potential Vss. An example of arrangement between terminals is shown. When such a circuit configuration is formed, even when a surge current due to an ESD phenomenon or the like is input to the power supply voltage VDD terminal or the input / output I / O terminal, the surge current input to the power supply voltage VDD terminal or the input / output I / O terminal. Can be passed through the reference potential Vss terminal to prevent surge current from flowing into the internal circuit. Thereby, destruction of the internal circuit due to the surge current can be reduced. In the case shown in FIG. 8, a protective element that causes a surge current to flow from the reference potential Vss terminal to the power supply voltage VDD terminal (for example, a diode alone when the power supply voltage VDD terminal is always higher in voltage than the reference potential Vss terminal). May be provided if necessary.

  In the first embodiment, the case where the ESD protection circuit is configured by one ESD discharge circuit and two trigger circuits has been described. However, the ESD protection circuit is configured by one ESD discharge circuit and three or more trigger circuits. It may be configured. In addition, a commonly used discharge circuit such as a MOSFET may be used as the ESD discharge circuit. Further, as the trigger circuit, a generally used trigger circuit such as a reverse diode, a MOS capacitor, or an RC circuit can be used.

[Second Embodiment]
Next, an ESD protection circuit according to a second embodiment of the present invention will be described. In the second embodiment, an ESD protection circuit is configured by two ESD discharge circuits and one trigger circuit.

  FIG. 9 is a schematic diagram showing the configuration of the ESD protection circuit of the second embodiment. The ESD protection circuit includes two ESD discharge circuits 11A and 11B and one trigger circuit 12. ESD discharge circuits 11A and 11B are arranged between the first node N1 and the second node N2, and a trigger circuit 12 is arranged between the first node N1 and the ESD discharge circuits 11A and 11B. Yes.

  FIG. 10 shows an example of the circuit configuration of the ESD protection circuit of the second embodiment. Between the first node N1 and the second node N2, as the ESD discharge circuit 11A, a thyristor (SCR) composed of bipolar transistors BT1 and BT2, and a bipolar transistor (NPN transistor) as the ESD discharge circuit 11B BT3 is connected in parallel. More specifically, the emitter of the bipolar transistor BT1 is connected to the first node N1, and the collector of the bipolar transistor BT1 is connected to the base of the bipolar transistor BT2. Further, the base of the bipolar transistor BT1 is connected to the collector of the bipolar transistor BT2, and the emitter of the bipolar transistor BT2 is connected to the second node N2. The collector of the bipolar transistor BT3 is connected to the first node N1, and the emitter of the bipolar transistor BT3 is connected to the second node N2.

  Between the first node N1 and the second node N2, diodes D1, D2, D3, D4 and a resistor R1 connected in series are connected as the trigger circuit 12. Further, the base of the bipolar transistor BT2 constituting the thyristor is connected to the connection point between the diode D4 and the resistor R1 and the base of the bipolar transistor BT3.

  In the ESD protection circuit having such a configuration, when a surge current is applied to the first node N1, the trigger current flows through the trigger circuit 12 to the ESD discharge circuits 11A and 11B. As a result, the thyristor constituting the ESD discharge circuit 11A is turned on, the bipolar transistor BT3 constituting the ESD discharge circuit 11B is turned on, and a surge current flows into the second node N2 via the thyristor and the bipolar transistor BT3. In this way, surge current generated by an ESD discharge phenomenon or the like is prevented from flowing into the internal circuit, and the internal circuit is prevented from being destroyed.

  In the second embodiment, the case where the ESD protection circuit is configured by two ESD discharge circuits and one trigger circuit has been described. However, the ESD protection circuit is configured by three or more ESD discharge circuits and one trigger circuit. It may be configured. In addition, a commonly used discharge circuit such as a MOSFET may be used as the ESD discharge circuit. Further, as the trigger circuit, a generally used trigger circuit such as a reverse diode, a MOS capacitor, or an RC circuit can be used.

[Third Embodiment]
Next explained is an ESD protection circuit according to the third embodiment of the invention. In the third embodiment, an ESD protection circuit is configured by two ESD discharge circuits and two trigger circuits.

  FIG. 11 is a schematic diagram showing the configuration of the ESD protection circuit of the third embodiment. The ESD protection circuit includes two ESD discharge circuits 11A and 11B and two trigger circuits 12A and 12B. ESD discharge circuits 11A and 11B are arranged between the first node N1 and the second node N2, and trigger circuits 12A and 12B are arranged between the first node N1 and the ESD discharge circuits 11A and 11B. Has been.

  FIG. 12 shows an example of the circuit configuration of the ESD protection circuit of the third embodiment. Between the first node N1 and the second node N2, as the ESD discharge circuit 11A, a thyristor (SCR) composed of bipolar transistors BT1 and BT2, and a bipolar transistor (NPN transistor) as the ESD discharge circuit 11B BT3 is connected in parallel. More specifically, the emitter of the bipolar transistor BT1 is connected to the first node N1, and the collector of the bipolar transistor BT1 is connected to the base of the bipolar transistor BT2. Further, the base of the bipolar transistor BT1 is connected to the collector of the bipolar transistor BT2, and the emitter of the bipolar transistor BT2 is connected to the second node N2. The collector of the bipolar transistor BT3 is connected to the first node N1, and the emitter of the bipolar transistor BT3 is connected to the second node N2.

  Between the first node N1 and the second node N2, diodes D1, D2, D3, D4 and a resistor R1 connected in series are connected as a trigger circuit 12A, and an N channel is further connected as a trigger circuit 12B. A MOS transistor NT1 and a resistor R2 are connected. Further, the base of the bipolar transistor BT2 constituting the thyristor is connected to the connection point between the diode D4 and the resistor R1, the connection point between the N-channel MOS transistor NT1 and the resistor R2, and the base of the bipolar transistor BT3.

  In the ESD protection circuit having such a configuration, when a surge current is applied to the first node N1, the trigger current flows to the ESD discharge circuits 11A and 11B through the trigger circuits 12A and 12B. As a result, the thyristor constituting the ESD discharge circuit 11A is turned on and the bipolar transistor BT3 constituting the ESD discharge circuit 11B is also turned on, so that a surge current flows into the second node N2 via the thyristor and the bipolar transistor BT3. In this way, surge current generated by an ESD discharge phenomenon or the like is prevented from flowing into the internal circuit, and the internal circuit is prevented from being destroyed.

  In the third embodiment, the case where the ESD protection circuit is configured by two ESD discharge circuits and two trigger circuits has been described. However, the ESD protection is performed by three or more ESD discharge circuits and three or more trigger circuits. A circuit may be configured. In addition, a commonly used discharge circuit such as a MOSFET may be used as the ESD discharge circuit. Further, as the trigger circuit, a generally used trigger circuit such as a reverse diode, a MOS capacitor, or an RC circuit can be used.

  In addition, each of the above-described embodiments can be implemented not only independently but also in an appropriate combination. Furthermore, the above-described embodiments include inventions at various stages, and the inventions at various stages can be extracted by appropriately combining a plurality of constituent elements disclosed in the embodiments.

It is the schematic which shows the structure of the ESD protection circuit of 1st Embodiment of this invention. It is a circuit diagram of the ESD protection circuit of the first embodiment. It is a figure which shows the breakdown voltage of the internal circuit containing MOSFET. It is a figure which shows the breakdown voltage of the internal circuit containing MOSFET. It is a figure which shows the operating voltage of the trigger circuit containing MOSFET. It is a figure which shows the operating voltage of the trigger circuit containing a diode. It is a figure which shows the operating voltage of the trigger circuit in the ESD protection circuit of 1st Embodiment, and the breakdown voltage of an internal circuit. It is a circuit diagram which shows the example which has arrange | positioned the ESD protection circuit of 1st Embodiment between several terminals. It is the schematic which shows the structure of the ESD protection circuit of 2nd Embodiment of this invention. It is a circuit diagram of the ESD protection circuit of the second embodiment. It is the schematic which shows the structure of the ESD protection circuit of 3rd Embodiment of this invention. It is a circuit diagram of the ESD protection circuit of 3rd Embodiment.

Explanation of symbols

  11, 11A, 11B ... ESD discharge circuit, 12, 12A, 12B ... trigger circuit, N1 ... first node, N2 ... second node.

Claims (5)

An ESD discharge circuit disposed between the first node and the second node;
A plurality of trigger circuits disposed between the first node and the ESD discharge circuit, each composed of different circuit elements;
The ESD protection circuit, wherein the trigger circuit supplies a trigger current to the ESD discharge circuit. A plurality of ESD discharge circuits disposed between the first node and the second node, each configured of different circuit elements;
A trigger circuit disposed between the first node and the ESD discharge circuit;
The ESD protection circuit, wherein the trigger circuit supplies a trigger current to the ESD discharge circuit. A plurality of ESD discharge circuits disposed between the first node and the second node, each configured of different circuit elements;
A plurality of trigger circuits disposed between the first node and the ESD discharge circuit, each composed of different circuit elements;
The ESD protection circuit, wherein the trigger circuit supplies a trigger current to the ESD discharge circuit.   The plurality of trigger circuits include a first trigger circuit and a second trigger circuit, the first trigger circuit includes a diode, and the second trigger circuit includes a MOS field effect transistor. Item 4. The ESD protection circuit according to Item 1 or 3.   The plurality of ESD discharge circuits include a first ESD discharge circuit and a second ESD discharge circuit, the first ESD discharge circuit includes a thyristor, and the second ESD discharge circuit includes a bipolar transistor. The ESD protection circuit according to claim 2 or 3, characterized in that

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