JP2007095744A - Semiconductor light-emitting element and manufacturing method thereof, and luminaire using the same - Google Patents

Semiconductor light-emitting element and manufacturing method thereof, and luminaire using the same Download PDF

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JP2007095744A
JP2007095744A JP2005279500A JP2005279500A JP2007095744A JP 2007095744 A JP2007095744 A JP 2007095744A JP 2005279500 A JP2005279500 A JP 2005279500A JP 2005279500 A JP2005279500 A JP 2005279500A JP 2007095744 A JP2007095744 A JP 2007095744A
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semiconductor layer
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light emitting
gallium nitride
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Masaharu Yasuda
正治 安田
Nobuyuki Takakura
信之 高倉
Takayoshi Takano
隆好 高野
Hideo Kawanishi
英雄 川西
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Panasonic Electric Works Co Ltd
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Matsushita Electric Works Ltd
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Abstract

<P>PROBLEM TO BE SOLVED: To increase luminous efficiency in a semiconductor light-emitting element, where at least an n-type nitride semiconductor layer, a luminous layer, and a p-type nitride semiconductor layer are laminated on a substrate, and an irregular structure is provided on an upper surface. <P>SOLUTION: On a sapphire substrate 2, a buffer layer 3 is formed for film of an n-type gallium nitride compound semiconductor layer 4, the luminous layer 5, and a p-type gallium nitride compound semiconductor layer 6 at a film-forming temperature of 1,000°C. A mask having an opening is formed, the temperature is decreased to 800°C, and a p-type gallium nitride compound semiconductor layer is grown again, thus forming a projection 7 in a square pole shape having a tip in a rectangular pyramid shape, improving the extraction efficiency of light generated by the luminous layer 5 by the projection 7, setting the thickness of the p-type gallium nitride compound semiconductor layer 6 to the minimum required value, reducing resistance, and realizing a blue or ultraviolet light-emitting diode 1 having high luminous efficiency. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、青色または紫外の光を発生することができる窒化ガリウム系化合物半導体発光素子の素子構造に関し、詳しくはp型窒化ガリウム系化合物半導体層上に凹凸構造を形成して、発光層から発生する光を効率良く外部に取出す方法に関する。   The present invention relates to a device structure of a gallium nitride-based compound semiconductor light-emitting device capable of generating blue or ultraviolet light, and more specifically, is generated from a light-emitting layer by forming an uneven structure on a p-type gallium nitride-based compound semiconductor layer. The present invention relates to a method for efficiently extracting light to the outside.

前記窒化ガリウム系化合物半導体発光素子では、窒化ガリウム系化合物半導体層と光を取出す空気層との屈折率が大きく異なるので、発光層から発生した光がそれらの界面においてある角度以上で入射した場合には、全反射してしまい、空気層側へ取出せなくなる。このため、従来から、発光層内で発生する光の全反射を低減して発光効率が高い青色または紫外の半導体発光素子を実現するために、特許文献1〜3で示されるように、光取出し面を粗面化する方法が用いられている。   In the gallium nitride compound semiconductor light emitting device, the refractive index of the gallium nitride compound semiconductor layer and the air layer from which the light is extracted are greatly different. Therefore, when light generated from the light emitting layer is incident on the interface at an angle or more. Is totally reflected and cannot be taken out to the air layer side. Therefore, conventionally, in order to realize a blue or ultraviolet semiconductor light emitting device having high luminous efficiency by reducing total reflection of light generated in the light emitting layer, as shown in Patent Documents 1 to 3, light extraction is performed. A method of roughening the surface is used.

特許文献1では、光取出し面となるp型またはn型窒化ガリウム系化合物半導体層上に絶縁性の光散乱層を新たに形成しており、その光散乱層はSiOをウェットエッチングして成り、表面は凹凸構造を有し、凸部は球形の粒子の一部から構成されていたり、取出し面上に島状に凸部を形成した例が記載されている。 In Patent Document 1, an insulating light scattering layer is newly formed on a p-type or n-type gallium nitride compound semiconductor layer serving as a light extraction surface, and the light scattering layer is formed by wet etching of SiO 2. The surface has a concavo-convex structure, and the convex part is composed of a part of spherical particles, or an example in which the convex part is formed in an island shape on the extraction surface is described.

また、特許文献2では、光取出し面となるp型窒化ガリウム系化合物半導体層上に最小寸法が発光波長λの1/4となる開口部を設けており、p型窒化ガリウム系化合物半導体層上にレジストを積層してそのレジストにパターン形成を行った後、レジストをマスクとして、開口部をイオン・ミリング法によって形成するプロセスが記載されている。   In Patent Document 2, an opening having a minimum dimension of 1/4 of the emission wavelength λ is provided on the p-type gallium nitride compound semiconductor layer serving as a light extraction surface, and the p-type gallium nitride compound semiconductor layer is formed on the p-type gallium nitride compound semiconductor layer. A process is described in which a resist is stacked and a pattern is formed on the resist, and then an opening is formed by ion milling using the resist as a mask.

さらにまた、特許文献3では、光取り出し面となるp型窒化ガリウム系化合物半導体層の表面、またはp型窒化ガリウム系化合物半導体層上に形成した透明電極表面に、前記イオン・ミリング法やRIEなどのエッチング手法を用いて、凹凸構造を形成することが記載されている。詳しくは、レジストなどによってパターン形成を行い、そのレジストをマスクとして開口部をイオン・ミリング法によりエッチングを行うことで、前記p型窒化ガリウム系化合物半導体層上やp型窒化ガリウム系化合物半導体層上に形成した透明電極表面に凹凸構造を形成するプロセスが記載されている。
特開平10−163525号公報 特開2000−91639号公報 特開2000−196152号公報
Furthermore, in Patent Document 3, the ion milling method, RIE, or the like is applied to the surface of the p-type gallium nitride compound semiconductor layer serving as the light extraction surface or the transparent electrode surface formed on the p-type gallium nitride compound semiconductor layer. It is described that the concavo-convex structure is formed by using the etching method. Specifically, a pattern is formed with a resist or the like, and the opening is etched by an ion milling method using the resist as a mask, so that the p-type gallium nitride compound semiconductor layer or the p-type gallium nitride compound semiconductor layer is formed. A process for forming a concavo-convex structure on the surface of the transparent electrode formed in the above is described.
JP-A-10-163525 JP 2000-91639 A JP 2000-196152 A

前記特許文献1の従来技術では、光取出し面上に新たに光散乱層を設けているので、散乱層内での光吸収が発生する。また、SiOは、GaNよりも屈折率が小さい(SiOが約1.7、GaNが約2.5)ので、屈折率の大きいGaNから小さいSiOへ、発光層からの光がある入射角度以上にて進む場合には、GaN側へ全反射するエスケープコーンが存在する。さらにまた、光取出し面と光散乱層との密着性が悪いときには、前記のような屈折率差を有する材料間の界面で反射が生じる。以上のようなことから、光取出し効率の向上が充分でないという問題がある。 In the prior art disclosed in Patent Document 1, since a light scattering layer is newly provided on the light extraction surface, light absorption occurs in the scattering layer. In addition, since SiO 2 has a smaller refractive index than GaN (SiO 2 is about 1.7 and GaN is about 2.5), light from the light emitting layer is incident on GaN having a large refractive index to small SiO 2 . When traveling at an angle or more, there is an escape cone that totally reflects to the GaN side. Furthermore, when the adhesion between the light extraction surface and the light scattering layer is poor, reflection occurs at the interface between the materials having the refractive index difference as described above. As described above, there is a problem that the light extraction efficiency is not sufficiently improved.

一方、特許文献2では、光取出し面となるp型窒化ガリウム系化合物半導体層上に直接開口部を設けているので、光散乱効果を発揮する深さ(0.1μm以上)を有する開口部を形成しようとすれば、p型窒化ガリウム系化合物半導体層を厚くする必要がある。しかしながら、p型窒化ガリウム系化合物半導体層は、一般的に、10Ω/cm程度の抵抗値を持っており、n型窒化ガリウム系化合物半導体層と比べて、高抵抗である。そのため、前記開口部の底部から半導体層までの抵抗値は小さいものの、大面積の前記開口部以外の上面から半導体層までの抵抗値は高く、あまりp型窒化ガリウム系化合物半導体層を厚くすると、素子の動作電圧が高くなり、発光効率の低下を招くなどの問題がある。 On the other hand, in Patent Document 2, since the opening is provided directly on the p-type gallium nitride compound semiconductor layer serving as the light extraction surface, the opening having a depth (0.1 μm or more) that exhibits the light scattering effect is provided. In order to form it, it is necessary to increase the thickness of the p-type gallium nitride compound semiconductor layer. However, the p-type gallium nitride compound semiconductor layer generally has a resistance value of about 10 6 Ω / cm 2, and has a higher resistance than the n-type gallium nitride compound semiconductor layer. Therefore, although the resistance value from the bottom of the opening to the semiconductor layer is small, the resistance value from the upper surface other than the large-area opening to the semiconductor layer is high, and if the p-type gallium nitride compound semiconductor layer is too thick, There is a problem that the operating voltage of the element is increased and the luminous efficiency is lowered.

さらにまた、特許文献3のように、RIEやイオン・ミリング法などにより、p型窒化ガリウム系化合物半導体層の一部をエッチングにより除去してp型窒化ガリウム系化合物半導体層表面に凹凸構造を形成した場合には、p型窒化ガリウム系化合物半導体層へダメージを与えてしまい、p型窒化ガリウム系化合物半導体層とp型の電極材料とのオーミック性が低下する。その結果、上記と同様に窒化ガリウム系化合物からなる半導体発光素子の動作電圧が高くなるなどの問題がある。   Furthermore, as in Patent Document 3, a part of the p-type gallium nitride compound semiconductor layer is removed by etching by RIE or ion milling to form a concavo-convex structure on the surface of the p-type gallium nitride compound semiconductor layer. In this case, the p-type gallium nitride compound semiconductor layer is damaged, and the ohmic property between the p-type gallium nitride compound semiconductor layer and the p-type electrode material is lowered. As a result, there is a problem that the operating voltage of a semiconductor light emitting device made of a gallium nitride compound is increased as described above.

本発明の目的は、p型窒化ガリウム系化合物半導体層とp型の電極材料とのオーミック性を低下させることなく、p型窒化ガリウム系半導体層上に凹凸構造を形成して、光取出し効率の向上を一層進めることができる半導体発光素子およびそれを用いる照明装置ならびに半導体発光素子の製造方法を提供することである。   An object of the present invention is to form a concavo-convex structure on a p-type gallium nitride semiconductor layer without reducing the ohmic property between the p-type gallium nitride compound semiconductor layer and the p-type electrode material, thereby improving the light extraction efficiency. To provide a semiconductor light-emitting element that can be further improved, a lighting device using the same, and a method for manufacturing the semiconductor light-emitting element.

本発明の半導体発光素子は、基板上に、少なくともn型窒化物半導体層、発光層およびp型窒化物半導体層を積層して成り、前記p型窒化物半導体層上に凹凸構造を有する半導体発光素子において、前記凹凸構造を、前記p型窒化物半導体層からエピタキシャル成長させたp型ドーパントを含む先端が四角錐状で四角柱状の凸部から成ることを特徴とする。   The semiconductor light-emitting device of the present invention includes a semiconductor light-emitting device in which at least an n-type nitride semiconductor layer, a light-emitting layer, and a p-type nitride semiconductor layer are stacked on a substrate, and has a concavo-convex structure on the p-type nitride semiconductor layer. In the element, the concavo-convex structure has a quadrangular pyramid-shaped convex portion with a tip including a p-type dopant epitaxially grown from the p-type nitride semiconductor layer.

上記の構成によれば、p型窒化物半導体層を所望とする厚さに形成した後、開口部を有するマスク形成を行い、前記p型窒化物半導体層から、p型ドーパントを含み、先端が四角錐状で四角柱状の凸部を低温でエピタキシャル成長させることで、回折による光取出し効率を向上する凹凸を作成する。   According to the above configuration, after the p-type nitride semiconductor layer is formed to a desired thickness, a mask having an opening is formed, and the p-type nitride semiconductor layer contains the p-type dopant, and the tip is Concavities and convexities that improve the light extraction efficiency by diffraction are created by epitaxially growing quadrangular pyramidal and quadrangular columnar projections at low temperatures.

したがって、前記凸部を、回折による光取出し効率を向上することができる充分な高さに形成することができる。また、p型窒化物半導体層は必要最小限の厚さとして、低抵抗化を図ることができる。また、前記マスクを除去するエッチングはp型窒化物半導体層を彫るものではなく、ダメージも小さく、また凸部にp型ドーパントを含むことから、p型の電極材とオーミックコンタクトすることができる。これらによって、発光効率が高い青色または紫外の発光ダイオードを実現することができる。   Therefore, the convex portion can be formed at a sufficient height that can improve the light extraction efficiency by diffraction. In addition, the p-type nitride semiconductor layer can be reduced in resistance by setting the minimum necessary thickness. In addition, the etching for removing the mask does not carve the p-type nitride semiconductor layer, causes little damage, and includes a p-type dopant in the convex portion, so that ohmic contact can be made with the p-type electrode material. By these, a blue or ultraviolet light emitting diode with high luminous efficiency can be realized.

また、本発明の半導体発光素子は、前記凸部の最表層の組成を、InGa1−yN(0<y≦1)とすることを特徴とする。 In the semiconductor light emitting device of the present invention, the composition of the outermost surface layer of the convex portion is In y Ga 1-y N (0 <y ≦ 1).

上記の構成によれば、凸部の最表層の組成をInGa1−yN(0<y≦1)とすることで、p型ドーパントの活性化エネルギーが低く、低抵抗なp型窒化物半導体層を形成できるので、p型窒化物半導体層とp型の電極材とのオーミック性が良好になり、動作電圧を低減し、一層発光効率が高い青色または紫外の半導体発光素子を実現することができる。 According to the arrangement, the composition of the outermost layer of the convex portion by the In y Ga 1-y N ( 0 <y ≦ 1), the activation energy of the p-type dopant is low, a low-resistance p-type nitride Since an oxide semiconductor layer can be formed, the ohmic property between the p-type nitride semiconductor layer and the p-type electrode material is improved, the operating voltage is reduced, and a blue or ultraviolet semiconductor light emitting device with higher luminous efficiency is realized. be able to.

さらにまた、本発明の照明装置は、前記の半導体発光素子を用いることを特徴とする。   Furthermore, the lighting device of the present invention is characterized by using the semiconductor light emitting element.

上記の構成によれば、半導体発光素子に凹凸を形成することによる光取出し効率を一層向上することができる照明装置を実現することができる。   According to said structure, the illuminating device which can further improve the light extraction efficiency by forming an unevenness | corrugation in a semiconductor light-emitting device is realizable.

また、本発明の半導体発光素子の製造方法は、基板上に、少なくともn型窒化物半導体層、発光層およびp型窒化物半導体層を積層して成り、前記p型窒化物半導体層上に凹凸構造を有する半導体発光素子の製造方法において、前記p型窒化物半導体層を予め定める規定の膜厚に成長させた後に、開口部を有するマスク形成を行い、前記p型窒化物半導体層から、p型ドーパントを含み、先端が四角錐状で四角柱状の凸部を低温でエピタキシャル成長させることを特徴とする。   The method for manufacturing a semiconductor light-emitting device according to the present invention includes a substrate on which at least an n-type nitride semiconductor layer, a light-emitting layer, and a p-type nitride semiconductor layer are stacked, and an unevenness is formed on the p-type nitride semiconductor layer. In the method of manufacturing a semiconductor light emitting device having a structure, after the p-type nitride semiconductor layer is grown to a predetermined film thickness, a mask having an opening is formed, and the p-type nitride semiconductor layer is formed from the p-type nitride semiconductor layer. And a quadrangular prism-shaped convex portion including a type dopant and having a tip thereof formed into a quadrangular pyramid shape, and is epitaxially grown at a low temperature.

上記の構成によれば、p型窒化物半導体層を所望とする厚さに形成した後、開口部を有するマスク形成を行い、温度を低下させて再び結晶成長を行わせると、該結晶は通常の成長のような面方向に拡がった成長をせず、先ず四角錐状に核成長し、その後、先端を四角錘として、前記開口の内周面に沿って、四角柱状に成長してゆく。   According to the above configuration, when a p-type nitride semiconductor layer is formed to a desired thickness, a mask having an opening is formed, and the crystal is grown again at a reduced temperature. The growth is not carried out in the plane direction as in the case of the above growth, but is first grown in a quadrangular pyramid shape, and then grows in a quadrangular prism shape along the inner peripheral surface of the opening with the tip as a quadrangular pyramid.

したがって、前記マスクを除去すると、p型窒化物半導体層上に、p型ドーパントを含み、先端が四角錐状で四角柱状の凸部から成る凹凸構造を形成することができる。   Therefore, when the mask is removed, a concavo-convex structure including a p-type dopant, a quadrangular pyramidal tip, and a quadrangular columnar projection can be formed on the p-type nitride semiconductor layer.

さらにまた、本発明の半導体発光素子の製造方法では、前記マスクは、NiOもしくはSnOの金属酸化膜、シリコン酸化膜、シリコン窒化膜、またはサファイアから成ることを特徴とする。 Furthermore, in the method for manufacturing a semiconductor light emitting device of the present invention, the mask is made of a metal oxide film of NiO 2 or SnO 2 , a silicon oxide film, a silicon nitride film, or sapphire.

上記の構成によれば、マスク材がエピタキシャル成長中に用いる成長ガスに対して腐食されることがなく、所定の形状をもつp型ドーパントを含む凸部の形成を容易に行うことができる。   According to said structure, the mask material is not corroded with respect to the growth gas used during epitaxial growth, and the convex part containing the p-type dopant which has a predetermined shape can be formed easily.

また、本発明の半導体発光素子の製造方法は、前記凸部のエピタキシャル成長後に、酸素原子を含む雰囲気下で熱処理を行うことを特徴とする。   In addition, the method for manufacturing a semiconductor light-emitting device according to the present invention is characterized in that heat treatment is performed in an atmosphere containing oxygen atoms after epitaxial growth of the convex portion.

上記の構成によれば、凸部を含むp型窒化物半導体層内のドーパントが活性化されて低抵抗になるので、p型窒化物半導体層とp型の電極材とのオーミック性は良好となり、発光効率が高い半導体発光素子を実現できる。   According to said structure, since the dopant in the p-type nitride semiconductor layer containing a convex part is activated and becomes low resistance, the ohmic property of a p-type nitride semiconductor layer and a p-type electrode material becomes favorable. A semiconductor light emitting device with high luminous efficiency can be realized.

本発明の半導体発光素子およびその製造方法は、以上のように、基板上に、少なくともn型窒化物半導体層、発光層およびp型窒化物半導体層を積層して成り、前記p型窒化物半導体層上に凹凸構造を有する半導体発光素子において、p型窒化物半導体層を所望とする厚さに形成した後、開口部を有するマスク形成を行い、前記p型窒化物半導体層から、p型ドーパントを含み、先端が四角錐状で四角柱状の凸部を低温でエピタキシャル成長させることで、回折による光取出し効率を向上する凹凸を作成する。   As described above, the semiconductor light-emitting device and the method for manufacturing the same according to the present invention are formed by laminating at least an n-type nitride semiconductor layer, a light-emitting layer, and a p-type nitride semiconductor layer on a substrate. In a semiconductor light emitting device having a concavo-convex structure on a layer, a p-type nitride semiconductor layer is formed to a desired thickness, then a mask having an opening is formed, and a p-type dopant is formed from the p-type nitride semiconductor layer. In addition, the convex and concave portions having a quadrangular pyramid shape and a rectangular column shape are epitaxially grown at a low temperature, thereby creating irregularities that improve the light extraction efficiency by diffraction.

それゆえ、前記凸部を、回折による光取出し効率を向上することができる充分な高さに形成することができる。また、p型窒化物半導体層は必要最小限の厚さとして、低抵抗化を図ることができる。また、前記マスクを除去するエッチングはp型窒化物半導体層を彫るものではなく、ダメージも小さく、また凸部にp型ドーパントを含むことから、p型の電極材とオーミックコンタクトすることができる。これらによって、発光効率が高い青色または紫外の発光ダイオードを実現することができる。   Therefore, the convex portion can be formed at a sufficient height that can improve the light extraction efficiency by diffraction. In addition, the p-type nitride semiconductor layer can be reduced in resistance by setting the minimum necessary thickness. In addition, the etching for removing the mask does not carve the p-type nitride semiconductor layer, causes little damage, and includes a p-type dopant in the convex portion, so that ohmic contact can be made with the p-type electrode material. By these, a blue or ultraviolet light emitting diode with high luminous efficiency can be realized.

さらにまた、本発明の照明装置は、以上のように、前記の半導体発光素子を用いる。   Furthermore, the illumination device of the present invention uses the semiconductor light emitting element as described above.

それゆえ、半導体発光素子に凹凸を形成することによる光取出し効率を一層向上することができる照明装置を実現することができる。   Therefore, it is possible to realize an illumination device that can further improve the light extraction efficiency by forming irregularities in the semiconductor light emitting element.

図1は、本発明の実施の一形態に係る窒化ガリウム系化合物半導体発光素子である発光ダイオード1の断面図である。この発光ダイオード1では、サファイア基板2上に、AlNとGaNとのペア層が積層されたバッファ層3、n型窒化ガリウム化合物半導体層4、発光層5およびp型窒化ガリウム化合物半導体層6が順に積層される。注目すべきは、本発明では、前記p型窒化ガリウム化合物半導体層6に続けて、該p型窒化ガリウム化合物半導体層6上に分散して、p型ドーパントを含む先端が四角錐状で四角柱状の凸部7が結晶成長されていることである。その凸部7を含むp型窒化ガリウム化合物半導体層6上には、導電膜8が積層され、さらにその導電膜8上にメタル層が積層されてp型電極9となる。一方、この発光ダイオード1の一部分、たとえば矩形の隅角部の1箇所は、エッチングによって前記n型窒化ガリウム化合物半導体層4まで彫り込まれ、その上にn型電極10が形成される。   FIG. 1 is a cross-sectional view of a light-emitting diode 1 that is a gallium nitride-based compound semiconductor light-emitting element according to an embodiment of the present invention. In this light-emitting diode 1, a buffer layer 3, an n-type gallium nitride compound semiconductor layer 4, a light-emitting layer 5 and a p-type gallium nitride compound semiconductor layer 6 in which a pair layer of AlN and GaN is stacked on a sapphire substrate 2 are sequentially arranged. Laminated. It should be noted that in the present invention, the p-type gallium nitride compound semiconductor layer 6 is followed by the p-type gallium nitride compound semiconductor layer 6 and is dispersed on the p-type gallium nitride compound semiconductor layer 6 so that the tip containing the p-type dopant has a quadrangular pyramid shape. That is, the projection 7 is crystal-grown. A conductive film 8 is stacked on the p-type gallium nitride compound semiconductor layer 6 including the convex portion 7, and a metal layer is further stacked on the conductive film 8 to form the p-type electrode 9. On the other hand, a part of the light emitting diode 1, for example, one corner of a rectangular corner is carved up to the n-type gallium nitride compound semiconductor layer 4 by etching, and an n-type electrode 10 is formed thereon.

この発光ダイオード1では、サファイア基板2を支持基板として用いているが、基板はサファイアに限定されず、基板側から光取出しを行う場合には、該基板は発光波長に対して透光性を持つものであればよいことは言うまでもない。またその場合、導電膜8およびp型電極9は光を反射する材料となるけれども、基板がSiであったり、前記サファイア基板2側からYAGレーザを照射することによって該サファイア基板2を除去し、前記バッファ層3上に導電膜を形成してn型電極とする場合には、導電膜8およびp型電極9は光を透過する材料として、p型電極9側から光を取出すようにしてもよい。   In this light emitting diode 1, the sapphire substrate 2 is used as a support substrate. However, the substrate is not limited to sapphire, and when performing light extraction from the substrate side, the substrate has translucency with respect to the emission wavelength. It goes without saying that anything is acceptable. In that case, although the conductive film 8 and the p-type electrode 9 are materials that reflect light, the substrate is Si or the sapphire substrate 2 is removed by irradiating the YAG laser from the sapphire substrate 2 side. In the case where a conductive film is formed on the buffer layer 3 to form an n-type electrode, the conductive film 8 and the p-type electrode 9 are made of materials that transmit light, and light may be extracted from the p-type electrode 9 side. Good.

前記バッファ層3は、たとえばAlNとGaNとから成るペア層が1nmの厚みで積層されて成り、前記n型窒化ガリウム化合物半導体層4は、たとえばAl0.3Ga0.7N層が2.2μmの厚みで積層されて成り、前記発光層5は、たとえばAl0.2Ga0.8N層が3nmの厚みで積層されて成り、前記p型窒化ガリウム化合物半導体層6は、たとえばp型の電気伝導を示すドーパントMgを含むAl0.3Ga0.7N層が0.1μmの厚みで積層されて成る。一方、前記凸部7は、たとえばp型ドーパントMgを含むAl0.3Ga0.7Nが0.1μmの厚みで積層されて成る。ただし、この凸部7の最表層は、InGa1−yN(0<y≦1)で形成される。 The buffer layer 3 is formed by stacking, for example, a pair layer of AlN and GaN with a thickness of 1 nm, and the n-type gallium nitride compound semiconductor layer 4 is, for example, an Al 0.3 Ga 0.7 N layer of 2. The light emitting layer 5 is formed by stacking, for example, an Al 0.2 Ga 0.8 N layer with a thickness of 3 nm, and the p-type gallium nitride compound semiconductor layer 6 is formed, for example, by a p-type layer. An Al 0.3 Ga 0.7 N layer containing a dopant Mg exhibiting electrical conduction is laminated with a thickness of 0.1 μm. On the other hand, the convex part 7 is formed by laminating, for example, Al 0.3 Ga 0.7 N containing a p-type dopant Mg with a thickness of 0.1 μm. However, the outermost layer of the convex portion 7 is formed of In y Ga 1-y N (0 <y ≦ 1).

前記各層4,5,6および凸部7において、AlGa1−xN(0<x≦1)の成分xおよびその厚さは、上記の値に限らず、所望とする電気的特性を得ることができる範囲で、適宜変化されてもよい。本発明の半導体発光素子では、前記n型窒化ガリウム化合物半導体層4、発光層5、p型窒化ガリウム化合物半導体層6および凸部7の組成は、AlInGa1−x−yN(0<x≦1、0≦y≦1)で表すことができ、上記の例は、凸部7の最表層を除き、y=0である。 In each of the layers 4, 5, 6 and the protrusion 7, the component x of Al x Ga 1-x N (0 <x ≦ 1) and the thickness thereof are not limited to the above values, and desired electrical characteristics are obtained. It may be appropriately changed within a range where it can be obtained. In the semiconductor light emitting device of the present invention, the composition of the n-type gallium nitride compound semiconductor layer 4, the light emitting layer 5, the p-type gallium nitride compound semiconductor layer 6, and the protrusion 7 is Al x In y Ga 1-xy N ( 0 <x ≦ 1, 0 ≦ y ≦ 1). In the above example, y = 0 except for the outermost layer of the convex portion 7.

以下に、上述のように構成される発光ダイオード1の結晶成長方法を説明する。成長に用いるガスは、キャリアガスとして、水素ガス(H)、窒素ガス(N)、成長に係わるガスとして、アンモニア(NH)、トリメチルガリウム(Ga(CH、以下TMGと略す)、トリメチルアルミニウム(Al(CH、以下TMAと略す)、シラン(SiH)、シクロペンタジエニルマグネシウム(Mg(C)である。 Below, the crystal growth method of the light emitting diode 1 comprised as mentioned above is demonstrated. The gas used for the growth is hydrogen gas (H 2 ), nitrogen gas (N 2 ) as a carrier gas, and ammonia (NH 3 ), trimethyl gallium (Ga (CH 3 ) 3 , hereinafter abbreviated as TMG as gases related to the growth. ), Trimethylaluminum (Al (CH 3 ) 3 , hereinafter abbreviated as TMA), silane (SiH 4 ), and cyclopentadienyl magnesium (Mg (C 5 H 5 ) 2 ).

先ず、サファイア基板2を有機および酸溶液にて洗浄を行う。そして、Hを2(L/分)流しながら温度を1100℃に上昇させ、サファイア基板2を気相エッチングする。次に、800℃まで温度を低下させて、Hを20(L/分)およびNHを10(L/分)流しながら、1.8×10−5(モル/分)のTMAと1.1×10−5(モル/分)のTMGとを交互に供給して、合計で前記1nmの厚みとしたAlNとGaNとから成るペア層が積層されたバッファ層3をサファイア基板2上に結晶成長させる。 First, the sapphire substrate 2 is washed with an organic and acid solution. Then, the temperature is raised to 1100 ° C. while flowing H 2 at 2 (L / min), and the sapphire substrate 2 is vapor-phase etched. Next, the temperature was lowered to 800 ° C., and 1.8 × 10 −5 (mol / min) TMA and 1 were added while flowing H 2 at 20 (L / min) and NH 3 at 10 (L / min). 1 × 10 −5 (mol / min) TMG is alternately supplied to form a buffer layer 3 on which a pair layer of AlN and GaN having a total thickness of 1 nm is stacked on the sapphire substrate 2 Crystal growth.

こうして基板処理が終わると半導体層の作成に移り、温度を1000℃に上げて、Hを20(L/分)およびNHを10(L/分)流しながら、1.8×10−5(モル/分)のTMAと1.1×10−5(モル/分)のTMGとを交互に供給して、さらにシランを導入して、前記2.2μmの厚みとし、n型ドーパントとしてSiを含むAl0.3Ga0.7N層を、前記n型窒化ガリウム化合物半導体層4としてバッファ層3上に結晶成長させる。 When the substrate processing is completed in this manner, the semiconductor layer is formed, the temperature is raised to 1000 ° C., and H 2 is supplied at 20 (L / min) and NH 3 is supplied at 10 (L / min), and 1.8 × 10 −5. (Mol / min) of TMA and 1.1 × 10 −5 (mol / min) of TMG are alternately supplied, and silane is further introduced to the thickness of 2.2 μm, and the n-type dopant is Si. An Al 0.3 Ga 0.7 N layer containing N is grown on the buffer layer 3 as the n-type gallium nitride compound semiconductor layer 4.

引続き、温度を1000℃に保ち、Hを20(L/分)およびNHを10(L/分)流しながら、1.8×10−5(モル/分)のTMAと1.1×10−5(モル/分)のTMGとを交互に供給して、さらにシランを導入して、前記3nmの厚みとしたAl0.2Ga0.8N層を、前記発光層5としてn型窒化ガリウム化合物半導体層4上に結晶成長させる。 Subsequently, while maintaining the temperature at 1000 ° C. and flowing H 2 at 20 (L / min) and NH 3 at 10 (L / min), 1.8 × 10 −5 (mol / min) TMA and 1.1 × 10 −5 (mol / min) of TMG is alternately supplied, and silane is further introduced to form the Al 0.2 Ga 0.8 N layer having a thickness of 3 nm as the light emitting layer 5 in the n-type. Crystals are grown on the gallium nitride compound semiconductor layer 4.

さらに、温度を1000℃に保ち、Hを20(L/分)およびNHを10(L/分)流しながら、1.8×10−5(モル/分)のTMAと1.1×10−5(モル/分)のTMGとを交互に供給して、さらにシクロペンタジエニルマグネシウムを導入して、前記0.1μmの厚みとしたp型Al0.3Ga0.7N層を、前記p型窒化ガリウム化合物半導体層6として発光層5上に結晶成長させる。 Furthermore, while maintaining the temperature at 1000 ° C. and flowing H 2 at 20 (L / min) and NH 3 at 10 (L / min), 1.8 × 10 −5 (mol / min) TMA and 1.1 × The p-type Al 0.3 Ga 0.7 N layer having a thickness of 0.1 μm was prepared by alternately supplying 10 −5 (mol / min) TMG and further introducing cyclopentadienyl magnesium. Then, crystals are grown on the light emitting layer 5 as the p-type gallium nitride compound semiconductor layer 6.

こうして、窒化ガリウム化合物半導体層が積層されると、注目すべきは、本発明では、イオンビーム蒸着方法にて、図2(a)に示すように、前記p型窒化ガリウム化合物半導体層6上に、シリコン酸化膜11が、厚さが0.3μmとなるように蒸着が行われ、その上に、図2(b)で示すように、レジスト12が全面に塗布され、図2(c)のように所定のパターンを有するマスク13越しに露光を行い、レジスト12の現像処理を行うことで、図2(d)に示すように目的とするレジストパターンが形成される。   Thus, when the gallium nitride compound semiconductor layer is laminated, it should be noted that, in the present invention, as shown in FIG. Then, the silicon oxide film 11 is vapor-deposited so as to have a thickness of 0.3 μm, and a resist 12 is applied on the entire surface as shown in FIG. 2B, and the silicon oxide film 11 shown in FIG. Thus, exposure is performed through the mask 13 having a predetermined pattern, and the resist 12 is developed to form a target resist pattern as shown in FIG.

その後、図2(e)で示すように、レジスト12の開口部のシリコン酸化膜11をBHFによりエッチングを行い、さらに図2(f)で示すように、アセトンによりパターン形成しているレジストを除去して、シリコン酸化膜11をp型窒化ガリウム化合物半導体層6上にパターン形成している。   Thereafter, as shown in FIG. 2 (e), the silicon oxide film 11 in the opening of the resist 12 is etched by BHF, and the resist patterned with acetone is removed as shown in FIG. 2 (f). The silicon oxide film 11 is patterned on the p-type gallium nitride compound semiconductor layer 6.

このシリコン酸化膜11のパターンを用いて、温度を800℃に低下させて再び結晶成長を行い、Hを20(L/分)およびNHを10(L/分)流しながら、1.8×10−5(モル/分)のTMAと1.1×10−5(モル/分)のTMGとを交互に供給して、さらにシクロペンタジエニルマグネシウムを導入して、図2(g)で示すように、前記0.1μmの厚みとしたp型Al0.3Ga0.7Nから成る先端が四角錐状で四角柱状の凸部7を、p型窒化ガリウム化合物半導体層6上に、前記シリコン酸化膜11の開口14内に結晶成長させる。前記開口14の形状は、円でも多角形でもよく、p型窒化ガリウム化合物半導体層6上に、低温で結晶核成長させると、先ず前記開口14に内接するように四角錘が形成され、その四角錘から、開口14の内周面に沿って、四角柱が成長してゆき、先端が前記四角錐状になる。 Using this pattern of the silicon oxide film 11, the temperature is lowered to 800 ° C. and crystal growth is performed again. While H 2 is supplied at 20 (L / min) and NH 3 is supplied at 10 (L / min), 1.8% 2 × 10 −5 (mol / min) TMA and 1.1 × 10 −5 (mol / min) TMG were alternately supplied, and cyclopentadienyl magnesium was further introduced. As shown in FIG. 4, the tip 7 made of p-type Al 0.3 Ga 0.7 N having a thickness of 0.1 μm has a quadrangular pyramid-shaped quadrangular columnar projection 7 on the p-type gallium nitride compound semiconductor layer 6. Then, crystals are grown in the openings 14 of the silicon oxide film 11. The shape of the opening 14 may be a circle or a polygon. When crystal nuclei are grown on the p-type gallium nitride compound semiconductor layer 6 at a low temperature, a square weight is first formed so as to be inscribed in the opening 14. From the weight, a quadrangular column grows along the inner peripheral surface of the opening 14, and the tip becomes the shape of the quadrangular pyramid.

そして、最表層には、温度を680℃に低下させてそのまま結晶成長を行い、Hを10(L/分)およびNHを20(L/分)流しながら、1.8×10−5(モル/分)のTMAと3.1×10−5(モル/分)のTMGとを交互に供給して、さらにシクロペンタジエニルマグネシウムを導入して、0.1μmの厚みとしたp型In0.2Ga0.8Nを形成する。 Then, on the outermost layer, the temperature is lowered to 680 ° C. and crystal growth is performed as it is, and 1.8 × 10 −5 while flowing H 2 at 10 (L / min) and NH 3 at 20 (L / min). (Mol / min) TMA and 3.1 × 10 −5 (mol / min) TMG are alternately supplied, and cyclopentadienylmagnesium is further introduced to a thickness of 0.1 μm. In 0.2 Ga 0.8 N is formed.

その後、BHFなどを用いて前記シリコン酸化膜11を除去し、酸素原子を含む雰囲気下で熱処理を行い、前記導電膜8およびp型電極9ならびにn型電極10が形成されると、前記図1のようになる。   Thereafter, the silicon oxide film 11 is removed using BHF or the like, and heat treatment is performed in an atmosphere containing oxygen atoms, whereby the conductive film 8, the p-type electrode 9, and the n-type electrode 10 are formed. become that way.

前記凸部7の成長にあたって、650℃程度では前記四角錐状の凸部7は形成されず、窒化物半導体層の通常の成膜温度である1000℃以上であれば、シリコン酸化膜11のパターン上で面方向にも成長してしまう。したがって、700〜900℃、特に上記800℃で成長させることが好ましい。   When the convex portion 7 is grown, the quadrangular pyramid-shaped convex portion 7 is not formed at about 650 ° C., and the pattern of the silicon oxide film 11 is not less than 1000 ° C. which is a normal film forming temperature of the nitride semiconductor layer. It will also grow in the surface direction. Therefore, it is preferable to grow at 700 to 900 ° C., particularly at the above 800 ° C.

このようにエピタキシャル成長時にマスクとなるシリコン酸化膜11のパターンを用い、柱状の凸部7を形成することで、該凸部7は、回折による光取出し効率を充分に向上することができる高さ(たとえば、発光波長λ=460nmの1/4の前記0.1μm以上)とし、p型窒化ガリウム化合物半導体層6は必要最小限の厚さ(たとえば、前記0.1μm程度)として、低抵抗化を図ることができる。また、BHFによるエッチングはp型窒化ガリウム化合物半導体層6を彫るものではなく、前記シリコン酸化膜11を除去するものであり、ダメージも小さく、また凸部7にp型ドーパントを含むことから、導電膜8とオーミックコンタクトすることができる。これらによって、発光効率が高い青色または紫外の発光ダイオードを実現することができる。   Thus, by using the pattern of the silicon oxide film 11 which becomes a mask at the time of epitaxial growth and forming the columnar convex portion 7, the convex portion 7 has a height that can sufficiently improve the light extraction efficiency by diffraction ( For example, the emission wavelength λ is ¼ of 460 nm, which is 0.1 μm or more), and the p-type gallium nitride compound semiconductor layer 6 has a necessary minimum thickness (for example, about 0.1 μm), thereby reducing the resistance. Can be planned. Etching with BHF does not carve the p-type gallium nitride compound semiconductor layer 6 but removes the silicon oxide film 11 and causes little damage. Since the convex portion 7 contains a p-type dopant, the conductive layer is conductive. The film 8 can be in ohmic contact. By these, a blue or ultraviolet light emitting diode with high luminous efficiency can be realized.

また、凸部7の最表層の組成をInGa1−yN(0<y≦1)とすることで、p型ドーパントの活性化エネルギーが低く、低抵抗なp型窒化ガリウム化合物半導体層6を形成できるので、該p型窒化ガリウム化合物半導体層6と導電膜8とのオーミック性が良好になり、動作電圧を低減し、一層発光効率が高い青色または紫外の半導体発光素子を実現することができる。 Further, the composition of the outermost layer of the convex portion 7 is In y Ga 1-y N (0 <y ≦ 1), so that the activation energy of the p-type dopant is low and the p-type gallium nitride compound semiconductor layer has low resistance. 6 can be formed, the ohmic property between the p-type gallium nitride compound semiconductor layer 6 and the conductive film 8 is improved, the operating voltage is reduced, and a blue or ultraviolet semiconductor light emitting device with higher luminous efficiency is realized. Can do.

さらにまた、前記凸部7のエピタキシャル成長後に、酸素原子を含む雰囲気下で熱処理を行うことで、該凸部7を含むp型窒化ガリウム化合物半導体層6内のドーパントが活性化されて(GaN中に取込まれているp型ドーパントMgは、エピタキシャル成長をさせた状態では水素と結合しているために活性化していないが、酸素雰囲気下で熱処理を行うことで、Mgと水素との結合が切れて(水素と酸素とが結合して水蒸気になり)、p型ドーパントMgが活性化する)低抵抗になるので、p型窒化ガリウム化合物半導体層6と導電膜8とのオーミック性は良好となり、より一層発光効率を向上することができる。   Furthermore, after the epitaxial growth of the convex portion 7, by performing a heat treatment in an atmosphere containing oxygen atoms, the dopant in the p-type gallium nitride compound semiconductor layer 6 including the convex portion 7 is activated (in GaN). The incorporated p-type dopant Mg is not activated because it is bonded to hydrogen in an epitaxially grown state, but by performing heat treatment in an oxygen atmosphere, the bond between Mg and hydrogen is broken. (Hydrogen and oxygen combine to form water vapor), and the p-type dopant Mg is activated.) The ohmic property between the p-type gallium nitride compound semiconductor layer 6 and the conductive film 8 is improved, and more Luminous efficiency can be further improved.

前記シリコン酸化膜11に代えて、NiOまたはSnOの金属酸化膜、シリコン窒化膜、もしくはサファイアをマスクとして用いることができ、これらの材料も、エピタキシャル成長中に用いる成長ガスに対して腐食されることがなく、所定の形状をもつp型ドーパントを含む凸部7の形成を容易に行うことができる。たとえば、シリコン窒化膜を用いる場合には、前記BHFによるエッチングに代えて、Arのプラズマによるエッチングを行うようにすればよい。 Instead of the silicon oxide film 11, a metal oxide film of NiO 2 or SnO 2 , a silicon nitride film, or sapphire can be used as a mask, and these materials are also corroded by a growth gas used during epitaxial growth. In other words, the projection 7 containing the p-type dopant having a predetermined shape can be easily formed. For example, when a silicon nitride film is used, etching with Ar plasma may be performed instead of etching with BHF.

上述のように構成される発光ダイオード1を照明装置に用いることで、同じ光束(輝度、照度)を得るにも、小型で低消費電力な照明装置を実現することができる。   By using the light-emitting diode 1 configured as described above for the lighting device, it is possible to realize a small-sized and low power consumption lighting device to obtain the same luminous flux (luminance, illuminance).

本発明の実施の一形態に係る窒化ガリウム系化合物半導体発光素子である発光ダイオードの断面図である。It is sectional drawing of the light emitting diode which is a gallium nitride type compound semiconductor light emitting element concerning one Embodiment of this invention. 本発明の発光ダイオードの製造方法を説明するための断面図である。It is sectional drawing for demonstrating the manufacturing method of the light emitting diode of this invention.

符号の説明Explanation of symbols

1 発光ダイオード
2 サファイア基板
3 バッファ層
4 n型窒化ガリウム化合物半導体層
5 発光層
6 p型窒化ガリウム化合物半導体層
7 凸部
8 導電膜
9 p型電極
10 n型電極
11 シリコン窒化膜
12 レジスト
14 開口
DESCRIPTION OF SYMBOLS 1 Light emitting diode 2 Sapphire substrate 3 Buffer layer 4 N-type gallium nitride compound semiconductor layer 5 Light emitting layer 6 P-type gallium nitride compound semiconductor layer 7 Convex part 8 Conductive film 9 P-type electrode 10 N-type electrode 11 Silicon nitride film 12 Resist 14 Opening

Claims (6)

基板上に、少なくともn型窒化物半導体層、発光層およびp型窒化物半導体層を積層して成り、前記p型窒化物半導体層上に凹凸構造を有する半導体発光素子において、
前記凹凸構造を、前記p型窒化物半導体層からエピタキシャル成長させたp型ドーパントを含む先端が四角錐状で四角柱状の凸部から成ることを特徴とする半導体発光素子。
In a semiconductor light emitting device comprising at least an n-type nitride semiconductor layer, a light emitting layer, and a p type nitride semiconductor layer on a substrate, and having a concavo-convex structure on the p type nitride semiconductor layer,
A semiconductor light emitting device comprising a convex portion having a quadrangular pyramid shape with a tip including a p-type dopant obtained by epitaxially growing the concavo-convex structure from the p-type nitride semiconductor layer.
前記凸部の最表層の組成を、InGa1−yN(0<y≦1)とすることを特徴とする請求項1記載の半導体発光素子。 2. The semiconductor light emitting element according to claim 1, wherein the composition of the outermost layer of the convex portion is In y Ga 1-y N (0 <y ≦ 1). 前記請求項1または2記載の半導体発光素子を用いることを特徴とする照明装置。   An illumination device using the semiconductor light emitting device according to claim 1. 基板上に、少なくともn型窒化物半導体層、発光層およびp型窒化物半導体層を積層して成り、前記p型窒化物半導体層上に凹凸構造を有する半導体発光素子の製造方法において、
前記p型窒化物半導体層を予め定める規定の膜厚に成長させた後に、開口部を有するマスク形成を行い、前記p型窒化物半導体層から、p型ドーパントを含み、先端が四角錐状で四角柱状の凸部を低温でエピタキシャル成長させることを特徴とする半導体発光素子の製造方法。
In a method for manufacturing a semiconductor light emitting device, comprising at least an n-type nitride semiconductor layer, a light emitting layer, and a p type nitride semiconductor layer on a substrate, and having a concavo-convex structure on the p type nitride semiconductor layer.
After the p-type nitride semiconductor layer is grown to a predetermined film thickness, a mask having an opening is formed, the p-type nitride semiconductor layer includes a p-type dopant, and the tip has a quadrangular pyramid shape. A method for manufacturing a semiconductor light-emitting device, characterized by epitaxially growing a quadrangular columnar convex portion at a low temperature.
前記マスクは、NiOもしくはSnOの金属酸化膜、シリコン酸化膜、シリコン窒化膜、またはサファイアから成ることを特徴とする請求項4記載の半導体発光素子の製造方法。 5. The method of manufacturing a semiconductor light emitting device according to claim 4, wherein the mask is made of a metal oxide film of NiO 2 or SnO 2 , a silicon oxide film, a silicon nitride film, or sapphire. 前記凸部のエピタキシャル成長後に、酸素原子を含む雰囲気下で熱処理を行うことを特徴とする請求項4または5記載の半導体発光素子の製造方法。   6. The method for manufacturing a semiconductor light-emitting element according to claim 4, wherein heat treatment is performed in an atmosphere containing oxygen atoms after epitaxial growth of the convex portion.
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