JP2007088495A - Organic insulating film and method of manufacturing same, and semiconductor device using organic insulating film and method of manufacturing same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an organic insulating film which is efficient and has a low dielectric constant, and a semiconductor device using the organic insulating film. <P>SOLUTION: Disclosed are the organic insulating film which is formed by using organic silane which has at least a ≥5 C/Si ratio and a ≥100 molecular weight, and made of SiOCH, SiCNH, and SiCH, and the semiconductor device using the organic insulating film, especially, a semiconductor device having a groove structure. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an organic insulating film and a semiconductor device using the same, and in particular, a low dielectric constant organic insulating film and a manufacturing method thereof, and a semiconductor device having a multilayer wiring structure using a low dielectric constant organic insulating film as an interlayer insulating film, and It relates to the manufacturing method.

  In the field of manufacturing ICs, device design rules are being reduced as devices become faster and more integrated. As the device size is reduced and the wiring size and the wiring interval are miniaturized, the wiring resistance and the capacitance between the wirings tend to increase in inverse proportion. If the wiring resistance or the capacitance between the wirings increases, the RC time constant increases, which causes a decrease in signal propagation speed, which is a problem in increasing the device speed.

  For this reason, reduction of wiring resistance and inter-wiring capacitance has become important in promoting device speedup. As a method for reducing the wiring resistance, a technique and a product using Cu, which has a lower specific resistance than Al, which has been widely used as a wiring material, have become widespread.

In addition, the capacitance between wirings is proportional to the area of the wiring and the dielectric constant of the insulating film between the wirings, and increases in inverse proportion to the wiring spacing. Therefore, as a method of reducing the wiring capacitance without changing the device design. For example, an insulating film having a dielectric constant lower than that of a conventional oxide film (SiO ₂ ) or nitride film (SiN) has been studied.

  When Cu is used as a wiring material, a damascene wiring structure as shown in FIG. 1 is generally widely used because it is difficult to finely process Cu by a dry etching technique.

In the damascene wiring formation method, first, an etching stopper SiN insulating film 0003 having excellent etching selectivity with respect to the SiO ₂ wiring groove interlayer film 0002 formed thereafter is formed on the SiO ₂ base interlayer insulating film 0001 with SiH ₄ and NH. _A film is formed to a thickness of 50 to 150 nm by a parallel plate type plasma CVD method using ₃ and N ₂ , and then a SiO ₂ wiring interlayer insulating film 0002 is formed to a thickness of about 400 to 1000 nm. Then, a groove pattern is formed by photolithography and dry etching technology, and the resist pattern is removed by O ₂ dry ashing technology and wet stripping technology. Then, the trench pattern is filled with Cu and a barrier metal for preventing diffusion of Cu such as Ta and TaN by using a sputtering technique and a plating technique, and excess Cu and barrier metal on the SiO ₂ wiring interlayer insulating film 0002 are formed by CMP. The Cu wiring 0007 is formed by removing.

When an interlayer insulating film is formed after the damascene wiring is formed, since Cu reacts and diffuses easily with SiO ₂ , SiH ₄ , NH ₃ and N ₂ are usually used as a diffusion preventing insulating film (barrier insulating film). After the SiN film 0012 by the parallel plate type plasma CVD used is formed on Cu to a thickness of about 50 to 100 nm, the SiO ₂ via interlayer insulating film 0010 is formed.

In this case, SiN is not only for preventing diffusion of Cu, but also when etching Cu grooves, and when opening a via hole on Cu damascene wiring, the Cu surface is etched by SiO ₂ or O ₂ resist ashing. In order to prevent exposure to the atmosphere, it also serves as a SiO ₂ etching stop layer. Thus, SiN is required to prevent diffusion and function as an etching stop layer.

In recent years, in order to further reduce the parasitic capacitance between the wirings, an organic insulating film such as SiOF or SiOC having a relative dielectric constant lower than that of the conventional SiO ₂ relative dielectric constant 4.1 is also used. Organic insulating films with a relative dielectric constant of about 4.5 to 5 such as SiC and SiCN by parallel plate plasma CVD using 4MS (tetramethylsilane) or 3MS (trimethylsilane) as raw materials having a lower relative dielectric constant are widely studied. It is coming.

  FIGS. 15A to 16C are conventional examples using a SiC film or a SiCN film formed by using conventional 3MS as a source gas.

After forming the first Cu wiring 805, a second SiCN film 806 was formed with the above gas. Next, a second SiOC film 807, a third SiCN film 808 similarly formed by the above gas, a third SiOC film 809 thereon, and a second SiO ₂ film 810 are formed.

As shown in FIG. 15A, the second SiO ₂ film 810, the third SiOC film 809, the third SiCN film 808, and the second SiOC film are formed using the photoresist having the via resist pattern as a mask. 807 is etched, and the etching is stopped on the second SiCN film 806.

  However, the etching selectivity between SiOC and SiCN is small, and there are cases in which the etching is lost on the underlying wiring as shown in FIG. After that, ashing was performed with oxygen gas in order to peel off the photoresist. In this case, a copper oxide layer 831 is formed in the Cu wiring at the location removed by etching. The same applies to the cases of SiOC and SiC.

  Next, as shown in FIG. 15C, after applying an antireflection film, a second resist pattern 819 for trench wiring was formed by a photoresist 818.

As shown in FIG. 15D, the second SiO ₂ film 810 and the third SiC film 808 were etched using the photoresist 818 as a mask. Thereafter, the photoresist 818 was peeled off by oxygen ashing. Here, the Cu oxide layer 831 was further oxidized, and thereafter organic peeling was performed.

As shown in FIG. 16A, the entire SiC back film 806 was etched by etching back the entire surface. Next, a second Ta / TaN film was formed as shown in FIG. 16B, and then a second Cu film was formed. Metal other than the trench wiring was removed by CMP to form a second Cu wiring. A fourth SiCHN film was formed thereon as shown in FIG.
Special Table 2002-526916

  Currently, SiC and SiCN by parallel plate plasma CVD using 4MS (tetramethylsilane) and 3MS (trimethylsilane) as raw materials, which are generally studied, have a relative dielectric constant of about 4.5 to 5, and SiOC is 2.8. To about 3.0.

  As the device size is further reduced and the wiring size and the wiring interval are further miniaturized, further reduction of the dielectric constant is required.

In addition, since the etching selectivity ratio between SiOC and SiCN and SiC is small, when SiCN and SiC are used as the etching stopper film, the surface of the metal wiring layer is oxidized when the photoresist is removed, and the connection resistance is reduced. There is a problem of becoming higher.

  The present invention relates to an organic insulating film having a low dielectric constant that is effective when used in a semiconductor device and a semiconductor device using the organic insulating film.

  The organic insulating film having a low dielectric constant according to the present invention is an organic insulating film formed using an organic silane having a C / Si ratio of 5 or more and a molecular weight of 100 or more as a raw material. This organic insulating film is formed by plasma CVD using organic silane having a molecular weight of 100 or more as a raw material.

  The organic silane is desirably one or more organic silanes selected from the group consisting of triethylvinylsilane, dimethyldivinylsilane, diethyldivinylsilane, methyltrivinylsilane, ethyltrivinylsilane, tetravinylsilane, tetraethylsilane, and triethylsilane.

  Furthermore, the organic insulating film desirably has a C═C bond, and the one having a vinyl group has better heat resistance.

  In this case, the organic silane used as a raw material preferably has a vinyl group at least partially. The organic silane having a vinyl group at least in part is one or more organic compounds selected from the group consisting of trimethylvinylsilane, triethylvinylsilane, dimethyldivinylsilane, diethyldivinylsilane, methyltrivinylsilane, ethyltrivinylsilane, and tetravinylsilane. Silane is desirable.

In particular, in the case of a SiOCH film, the source gas requires an organic silane having at least a C / Si ratio of 5 or more and a molecular weight of 100 or more, an oxidizing agent, and an inert gas. The inert gas may be any of helium, argon, and xenon, and the oxidant may be any of O ₂ , O ₃ , H ₂ O, CO, and CO ₂ .

  The oxidizing agent may be an oxidizing gas containing nitrogen, but is not suitable for currently used novolak photoresists.

  The raw material organic silane may be one or more organic silanes selected from the group consisting of triethylvinylsilane, dimethyldivinylsilane, diethyldivinylsilane, methyltrivinylsilane, ethyltrivinylsilane, tetravinylsilane, tetraethylsilane, and triethylsilane. However, it is better to have a vinyl group in terms of improving heat resistance.

  In the case of the SiCH film, the source gas is an inert gas that is an organic silane having a C / Si ratio of 5 or more and a molecular weight of 100 or more and helium, argon, or xenon. Again, the organosilane can be one or more organosilanes selected from the group consisting of triethylvinylsilane, dimethyldivinylsilane, diethyldivinylsilane, methyltrivinylsilane, ethyltrivinylsilane, tetravinylsilane, tetraethylsilane, and triethylsilane. In particular, heat resistance can be improved by having a vinyl group.

The SiCHN film is an inert gas whose source gas is one of organic silane, nitrogen-containing gas, helium, argon, and xenon having a C / Si ratio of 5 or more and a molecular weight of 100 or more. Nitrogen-containing gases include ammonia, N ₂ and hydrazine. The organic silane may be one or more organic silanes selected from the group consisting of triethylvinylsilane, dimethyldivinylsilane, diethyldivinylsilane, methyltrivinylsilane, ethyltrivinylsilane, tetravinylsilane, tetraethylsilane, and triethylsilane. The one part having a vinyl group can improve the heat resistance.

In a conventional semiconductor device, a SiOCH film can be used as a substitute for the SiO ₂ film, and a SiCH film or a SiCHN film can be used as a substitute for the SiN film.

As the semiconductor device, a semiconductor integrated circuit device having a multilayer structure is suitable, and in particular, a semiconductor device having a trench wiring structure which has been adopted in recent years with miniaturization.

  The structure and manufacturing method of the organic insulating film according to the embodiment of the present invention will be described.

  In order to reduce the relative dielectric constant of the organic insulating film, it is necessary to make the C / Si composition ratio in the film larger than that of conventional SiC, SiCN, or SiOC. It is necessary to use a source gas having a large C / Si composition ratio.

  On the other hand, when the C / Si ratio in the film is increased, a C—C bond is formed in the film. The bond energy of the C—C bond is higher than the bond energy of Si—O, Si—C, Si—N, and the like. Since it is small and easily decomposed, it becomes a film having low heat resistance. In order to improve heat resistance, it is effective to form a film having a C═C bond having a binding energy larger than that of C—C.

  An organic insulating film having a C = C bond can also be controlled by controlling the power of plasma CVD, but it is also effective to use a source gas having a vinyl group bond in the source gas.

  As one of the methods for reducing the dielectric constant of SiCH, SiCHN, and SiOCH, it is effective to reduce the film density. In order to reduce the film density, a raw material gas having a molecular weight higher than that of 4MS (tetramethylsilane) or 3MS (trimethylsilane) is used, and the plasma gas density is suppressed in order to suppress decomposition of the raw material gas in the gas phase. It is necessary to reduce the film thickness.

  The present invention provides a SiCH, SiCHN, or SiOCH film having a lower dielectric constant than the conventionally obtained SiCH, SiCHN, or SiOCH film based on the above knowledge.

  Furthermore, the present invention relates to a semiconductor device using a low dielectric constant SiCH, SiCHN, or SiOCH film, and particularly to a semiconductor layer having a trench structure.

  A parallel plate type plasma CVD apparatus used in the present invention will be described with reference to FIG.

  The apparatus has an upper electrode 1 and a lower electrode 2 in a vacuum chamber, a substrate 3 is installed on the lower electrode, and a high frequency generated from a high frequency power source 4 is applied to the upper electrode. The lower electrode can be heated by a heater. The apparatus is connected to a gas introduction part 5 for introducing a raw material gas and a gas exhaust part 6. In the raw material introduction part, a cylinder of raw material gas is connected via a sealing valve and a mass flow controller, and the introduction part piping is structured to be heated to 300 ° C. In addition, when using a liquid raw material for a raw material, it supplies with a liquid vaporization supply device instead of a mass flow controller.

In addition to parallel plate type plasma CVD, it has been confirmed that an equivalent film can be obtained by using ECR excitation plasma CVD, helicon wave excitation, and inductively coupled plasma CVD.

The SiOCH film according to the first embodiment of the present invention will be described in detail.

In the SiOCH film according to the first embodiment, a Si wafer is placed in a parallel plate plasma CVD (hereinafter abbreviated as PECVD) apparatus, heated to 150 ° C. to 400 ° C., trimethylvinylsilane (TMVS) as a source gas, O ₂ and He are introduced into the PECVD apparatus at a flow rate of 200 to 2000 sccm, 50 to 1000 sccm, and 50 to 500 sccm, respectively. The pressure in the chamber is set to 133 to 1330 Pa, and RF power of 200 to 1000 W is applied.

The SiOCH film formed under the above conditions had a C / Si composition ratio of 0.8 to 1.3 and a film density of 1.1 to 1.2 g / cm ³ . This value is compared with a SiOCH film (C / Si composition ratio 0.7, film density 1.3 g / cm ³ ) using trimethylsilane (3MS), which has been used as a conventional wiring interlayer insulating film, as a source gas. , C / Si ratio is large and film density is small. For this reason, the relative dielectric constant is 2.2 to 2.7, which is lower than the relative dielectric constant (2.8 to 3.0) of the SiOC film using trimethylsilane (3MS) as a source gas. Under the above conditions, the refractive index varies between 1.3 and 1.45.

  The SiOCH film formed at an RF power of 400 W or more has a C / Si composition ratio of 0.8 or more and less than 1.0, and in this case, a C—C bond is formed in the film, so that it is thermally unstable. The film thickness is reduced by about 5% by heat treatment at 400 ° C. for 30 minutes. On the other hand, in the range of RF power 200 W to 400 W, C═C bonds are formed in the film, so that the heat resistance is improved and the film thickness reduction by heat treatment at 400 ° C. for 30 minutes is 1% or less.

  In the first embodiment, trimethylvinylsilane is used as the source gas. For example, any one of dimethyldivinylsilane, diethyldivinylsilane, methyltrivinylsilane, ethyltrivinylsilane, tetravinylsilane, tetraethylsilane, and triethylsilane is used. Or a combination thereof.

  In particular, any of trimethylvinylsilane, dimethyldivinylsilane, diethyldivinylsilane, methyltrivinylsilane, ethyltrivinylsilane, and tetravinylsilane having a vinyl group is preferable.

When a gas such as N ₂ O or NO ₂ is used as the oxidizing gas, a minute amount of N is present in the SiOCH film, and an amine group is formed. If an amine group is present in the film, in the case of a novolak-type photoresist, the photoresist and the amine group react with each other and exposure failure occurs, so that these oxidizing gases containing N cannot be used.

Next, the SiCH film which is the 2nd Embodiment of this invention is demonstrated.

  In this embodiment, a parallel plate type plasma CVD apparatus is used.

  The flow rate is controlled by a mass flow controller, and 300 sccm of trimethylvinylsilane is allowed to flow, and simultaneously 1000 sccm of He is allowed to flow. The pressure during film formation is 133 Pa to 1330 Pa, high frequency power 100 to 400 W, and substrate temperature 350 ° C.

  When the relative dielectric constant of the film prepared under the above conditions was measured, the value varied depending on the deposition pressure, and the relative dielectric constant of the film formed at 133 to 1330 Pa with the relative dielectric constant of 3.3 to 1330 Pa. Continuously changed between.

  The dielectric constant can be made lower than that of a film deposited using 3MS or 4MS (each having a relative dielectric constant of 4.5).

Further, under the above film forming conditions, the C / Si composition ratio in the film changed from 0.9 to 1.4, and the film density changed from 0.9 to 1.4 g / cm ³ . That is, the density is lower than that of the SiCH film (C / Si composition ratio 0.8, density 1.5 g / cm ³ ) prepared by 3MS. Therefore, it is considered that the relative dielectric constant has been reduced.

Moreover, the refractive index changed between 1.70-1.85 on the said conditions. As a result of measurement by FT-IR (Fourier transform infrared spectroscopy), Si—C, Si—CH ₃ and Si—H bonds exist in the film. On the other hand, no Si—OH bond due to moisture was detected in the film.

  The Cu barrier property was also good, and Cu diffusion was not observed even when a Cu diffusion acceleration test was performed by applying a bias voltage when heated at 450 ° C. That is, it has been found that the film has the same properties as those of a conventional SiCH film deposited using 3MS.

The above example is an example in the case of using trimethylvinylsilane as a raw material. In addition, triethylvinylsilane, which is a raw material having a molecular weight of 100 or more and a C / Si ratio of the raw material of 5 or more, It was confirmed that an equivalent film was formed when dimethyldivinylsilane, diethyldivinylsilane, methyltrivinylsilane, ethyltrivinylsilane, tetravinylsilane, tetraethylsilane, or triethylsilane was used. FIG. 20 shows the relationship between the molecular weight of the raw material compound, the density of the deposited film, and the C / Si composition ratio when the above raw materials are used. By using a raw material having a molecular weight of 100 or more and a C / Si ratio of 5 or more, the film density is 1.0 or more and 1.4 g / cm ³ or less, and the C / Si composition ratio is 0.9 or more and 1.3. It was confirmed that the following films can be deposited.

In addition to parallel plate type plasma CVD, it has been confirmed that an equivalent film can be obtained by using ECR excitation plasma CVD, helicon wave excitation, and inductively coupled plasma CVD.

Subsequently, a SiCH film containing a vinyl group in a SiCH film which is a modification of the second embodiment will be described.

  In order to contain a vinyl group in the film, it is necessary to prevent dissociation of the raw material by plasma as much as possible. Therefore, the flow rate of trimethylvinylsilane was increased to 300 sccm or more, and the plasma power was deposited at a lower power of 50 to 100 W.

  In order to confirm whether vinyl groups are contained in the film, an infrared absorption spectrum was measured, and it was found that absorption caused by vinyl groups appeared from a sample deposited at a high flow rate and high frequency power of 50 to 100 W. It was. This is because in the case of weak energy plasma, the structure of the raw material is taken into the film without being destroyed.

  As described above, it has been found that a SiCH film containing a vinyl group can be manufactured by using a raw material in which a vinyl group is bonded to a raw material gas and suppressing decomposition of the raw material. The amount of vinyl group incorporated into the film can be controlled by varying the plasma power. When the power was increased to 100 W or more, the vinyl group was no longer contained.

  As a result of conducting a heat resistance test on the structure in which vinyl groups are present in the film, the film shrinkage is within 0.1% after heating at 450 ° C. for 1 hour in a nitrogen atmosphere, and there is almost no change in other film characteristics. I couldn't see it. That is, it has been clarified that vinyl group incorporation into the film significantly improves the heat resistance of the film.

The relative dielectric constant changes depending on the film forming pressure as in the case where the vinyl group is not included, and is between the relative dielectric constant 3.2 of the film formed at 133 Pa and the relative dielectric constant 4.2 of the film formed at 1330 Pa. It turns out that it changes continuously. That is, the relative dielectric constant hardly changed with or without vinyl groups in the film. Also, the C / Si composition ratio of the film changes from 0.9 to 1.4, while the film density changes from 0.9 to 1.4 g / cm ³ and the refractive index changes from 1.70 to 1.85. did. That is, there was no change with respect to the presence or absence of vinyl groups in the film.

  The Cu barrier property was also good, and Cu diffusion was not observed even when a Cu diffusion acceleration test was performed by applying a bias voltage when heated at 450 ° C. That is, it has been found that the film has the same properties as those of a conventional SiCH film deposited using 3MS.

  The above example is an example in the case of using trimethylvinylsilane as a raw material. In addition, triethylvinylsilane, which is a raw material having a molecular weight of 100 or more and a C / Si ratio of the raw material of 5 or more, It was confirmed that an equivalent film was formed when dimethyldivinylsilane, diethyldivinylsilane, methyltrivinylsilane, ethyltrivinylsilane, tetravinylsilane, tetraethylsilane, or triethylsilane was used.

In addition to parallel plate type plasma CVD, it has been confirmed that an equivalent film can be obtained by using ECR excitation plasma CVD, helicon wave excitation, and inductively coupled plasma CVD.

A SiCHN film according to the third embodiment will be described.

  In this embodiment, the flow rate is controlled by a mass flow controller, and 300 sccm of trimethylvinylsilane and 300 sccm of ammonia are allowed to flow, and at the same time, 1000 sccm of He is allowed to flow. The pressure during film formation is 133 Pa to 1330 Pa, high frequency power 100 to 400 W, and substrate temperature 350 ° C.

  When 300 sccm of ammonia is introduced, nitrogen is introduced into the film and a SiCHN film is formed.

The relative dielectric constant changes depending on the deposition pressure, and continuously changes between the relative dielectric constant of 3.8 to 1330 Pa of the film formed at 133 Pa. Under the above film forming conditions, the C / Si composition ratio of the film is 1.0-1.3, and the carbon content is larger than that of silicon, while the film density is 1.4-1.6 g / cm ^3. The density is lower than that of the SiCHN film (density 1.7 g / cm ³ ) prepared by 3MS.

The refractive index changes between 1.77 and 1.90. As a result of FT-IR measurement, Si—C, Si—CH ₃ and Si—H bonds existed in the film, while no Si—OH bond due to moisture in the film was detected.

  The Cu barrier property was also good, and Cu diffusion was not observed even when a Cu diffusion acceleration test was performed by applying a bias voltage when heated at 450 ° C. That is, it was found that the film has the same properties as those of a conventional SiCHN film deposited using 3MS.

  The above examples are examples where trimethylvinylsilane is used as a raw material, but in addition, triethylvinylsilane which is an organosilane having a molecular weight of 100 or more and a raw material having a C / Si ratio of 5 or more, When dimethyldivinylsilane, diethyldivinylsilane, methyltrivinylsilane, ethyltrivinylsilane, tetravinylsilane, tetraethylsilane, or triethylsilane is used, an equivalent film can be formed by using other nitriding sources such as hydrazine instead of ammonia. I was sure that.

In addition to parallel plate type plasma CVD, it has been confirmed that an equivalent film can be obtained by using ECR excitation plasma CVD, helicon wave excitation, and inductively coupled plasma CVD.

As a modification of the third embodiment, a SiCHN film containing a vinyl group will be described.
It contained vinyl groups. Similar to the second embodiment, trimethylvinylsilane (300 sccm) was increased to 300 sccm or more, and the plasma power was reduced to 50-100 W and deposited.

  In order to confirm whether vinyl groups are contained in the film, an infrared absorption spectrum was measured, and it was found that absorption caused by vinyl groups appeared from a sample deposited at a high flow rate and high frequency power of 50 to 100 W. It was. This is because even in the SiCHN film, the structure of the raw material is taken into the film without being destroyed by the weak energy plasma.

It was also found that Si—C, Si—CH ₃ and Si—H bonds were present in the film at the same time. On the other hand, Si—OH bonds due to moisture in the film were not detected.

On the other hand, when the power was increased to 100 W or more, the absorption due to the vinyl group disappeared, and only Si—C, Si—CH ₃ and Si—H bonds were detected from the film.

  As described above, it was found that a SiCHN film containing a vinyl group can be manufactured by using a raw material in which a vinyl group is bonded to a raw material gas and suppressing the decomposition of the raw material. It was also found that the amount of vinyl group incorporated into the film can be controlled by varying the plasma power.

  Furthermore, as a result of conducting a heat resistance test on a structure in which a vinyl group is present in the film, the film characteristics did not change even after heating at 450 ° C. for 1 hour in a nitrogen atmosphere. That is, it has been clarified that vinyl group incorporation into the film significantly improves the heat resistance of the film. The relative dielectric constant continuously changed between the relative dielectric constant 3.8 of the film formed at 133 Pa and the relative dielectric constant 4.7 of the film formed at 1330 Pa.

Also, the C / Si composition ratio of the film is 1.0-1.3, and the carbon content changes in a range higher than that of silicon, while the film density is in the range of 1.4-1.6 g / cm ³ and the refractive index. Changed between 1.77 and 1.90. That is, there was no change with respect to the presence or absence of vinyl groups in the film. That is, it has been found that the vinyl group in the film has the effect of improving the heat resistance of the barrier film without causing a significant increase in the dielectric constant. The Cu barrier property was also good, and Cu diffusion was not observed even when a Cu diffusion acceleration test was performed by applying a bias voltage when heated at 450 ° C. That is, it has been found that the film has the same properties as those of a conventional SiCH film deposited using 3MS.

  In this embodiment, trimethylvinylsilane is used as a raw material, but triethylvinylsilane and dimethyldisilane, which are organic silanes having a molecular weight of 100 or more and having a C / Si ratio of 5 or more, are also used. It was confirmed that an equivalent film was formed when vinylsilane, diethyldivinylsilane, methyltrivinylsilane, ethyltrivinylsilane, tetravinylsilane, tetraethylsilane, or triethylsilane was used.

  In addition to parallel plate type plasma CVD, it has been confirmed that an equivalent film can be obtained by using ECR excitation plasma CVD, helicon wave excitation, and inductively coupled plasma CVD.

18 and 19 are SiOCH films and SiC films formed using 3MS and 4M, and SiOCH films formed using TMVS or DMVS having a source molecular weight of 100 or more and a C / Si ratio of 5 or more. It shows the relative dielectric constant of the film and the SiCH film. The SiOC film formed using 3MS and 4MS has a relative dielectric constant of 2.9, but TMVS shows 2.6 and DMVS shows 2.4. It was verified that a film having a low relative dielectric constant can be formed by using a source having a large molecular weight.

  Embodiments in which an organic insulating film according to an embodiment of the present invention is applied to a semiconductor device will be described below with reference to the drawings.

Example 1
FIG. 2 is a partial cross-sectional view of a semiconductor device having a single damascene configuration according to the first embodiment.

  The semiconductor device shown in FIG. 2 includes a first etching stopper film 202, a first SiOCH film 203, and a first hard mask film on a base insulating film 201 that covers an element such as a MOS transistor formed on a Si substrate. 204, the first barrier insulating film 211, the second SiOCH film 212, the second hard mask film 213, the second etching stopper film 214, the third SiOC 217, the third hard mask film 218, and the second A barrier insulating film 223 is sequentially stacked.

  The first copper wiring 210, the second copper wiring 224, and the copper plug 228 that connects the first copper wiring 210 and the second copper wiring 224 are formed in the laminated insulating film.

  The first copper wiring 210 is formed in a laminated insulating film made up of the first etching stopper 202, the first SiOCH film 203, and the first hard mask film 204, which are sequentially laminated on the base insulating film 201. .

  The second copper wiring 224 is formed in a laminated insulating film composed of the second etching stopper 214, the third SiOCH film 217, and the third hard mask film 218.

  The copper plug 228 connecting the second copper wiring 224 serving as the upper wiring and the first copper wiring 210 serving as the lower wiring serves as a different barrier insulating film that separates the upper wiring from the lower wiring. The insulating film 211, the second SiOCH film 212, and the second hard mask film 213 are formed in a laminated film.

  A part of the first copper wiring 210 may bite into the base insulating film 201.

  Of the interlayer films configured as described above, the first and second barrier insulating films, the first and first etching stoppers are either SiCH films or SiCHN films, or a stack of SiCH films and SiCHN films. It may be a membrane.

  Next, a manufacturing method of the above-described semiconductor device will be described with reference to process cross-sectional views of FIGS. 3 (a) to 6 (d).

  First, as shown in FIG. 3A, a first etching stopper film 302, a first SiOCH film 303, and a first hard mask film 304 were sequentially formed on the base insulating film 301.

The first etching stopper film 302 is a SiCH film or a SiCHN film and is formed with a thickness of 30 nm to 150 nm by a parallel plate plasma CVD method. The first SiOCH film 303 is formed with a thickness of about 200 to 1000 nm. The first hard mask film 304 is one of SiO ₂ , SiN, and SiON, and is formed with a thickness of about 50 nm to 200 nm.

  A first photoresist 305 was formed on them on the first hard mask film 304, and a groove pattern 306 was formed by photolithography.

  Subsequently, as shown in FIG. 3B, the first hard mask film 304 and the first SiOCH film 303 are formed by dry etching using the first photoresist film 305 patterned with the groove pattern 306 as a mask. After etching and removing the photoresist 305, the first etching stopper 302 was removed by etching by etching the entire surface to form a first wiring groove pattern 307.

  Here, when the first etching stopper 302 is removed by etching, a part of the base insulating film is removed by etching, but there is no problem.

  The first etching stopper film 302 may be omitted. In this case, the first hard mask 304 and the first SiOCH film 303 may be removed by etching using the first photoresist as a mask.

  Next, as shown in FIG. 3C, a first barrier metal film 308 and a first conductor film 309 were formed.

  The first barrier metal film 308 is a film made of Ta, TaN, TiN or the like, and is formed by a sputtering method or a CVD method. The first conductor film 309 is a Cu film or a Cu alloy film, and can be formed by a sputtering method, a CVD method, or a plating method.

  Thereafter, as shown in FIG. 3D, the barrier metal film 308 and the first conductor film 309 on the hard mask film were removed by CMP to form the first wiring 310.

  Next, as shown in FIG. 4A, a first barrier insulating film 311, a second SiOCH film 312 and a second hard mask film 313 were sequentially formed.

  Next, as shown in FIG. 4B, a via resist pattern 316 using a photoresist 315 was formed on them by photolithography as described above.

  Next, the second hard mask film 313 and the second SiOCH film 312 are etched by a dry etching technique, and the photoresist 316 is peeled off (FIG. 4C).

  Thereafter, the first barrier insulating film 311 is removed by overall etch back to form a via pattern.

  Next, as shown in FIG. 4D, a second barrier metal film 326 and a second conductor film 327 were formed.

  The second barrier metal film 326 is a film made of Ta, TaN, TiN or the like, and is formed by a sputtering method or a CVD method. The second conductor film 327 is a Cu film or a Cu alloy film, and is formed by a sputtering method, a CVD method, or a plating method.

  Thereafter, as shown in FIG. 5A, the barrier metal film 326 and the second conductor film 327 on the hard mask film were removed by CMP to form a first conductor plug 328.

  Thereafter, as shown in FIG. 5B, a second etching stopper 314 is formed thereon.

  Further, as shown in FIG. 5C, a third SiOCH film 317 was formed, and a third hard mask film 318 was formed thereon. An antireflection film 325 was formed thereon, and a second wiring groove resist pattern 320 was formed thereon with a third photoresist 319.

  As shown in FIG. 5D, the third hard mask film 318 and the third SiOCH film 317 are etched using the photoresist mask 319, and after removing the third photoresist 319, the entire surface is etched back. The wiring pattern of the etching stopper 314 of 2 was removed.

  Also in this case, the second etching stopper film 314 can be omitted. In this case also, the third photoresist 319 may be used as a mask. However, in this case, if ashing with oxygen is used to remove the photoresist, the surface of copper is oxidized, so an organic solvent must be used.

Subsequently, as shown in FIG. 6A, a third barrier metal 321 was formed, and a third conductor film 322 was formed.
As shown in FIG. 6B, the barrier metal film 321 and the third conductor film 322 on the hard mask film were removed by CMP to form the second wiring 324.

  A second barrier insulating film 323 was formed as shown in FIG.

  A multilayer wiring can be formed by sequentially repeating FIG. 4A to FIG. 6C.

  In this embodiment, the upper layer wiring, the lower layer wiring, and the connection plug that connects the upper layer wiring and the lower layer wiring are all formed of a Cu film or a Cu alloy film, but are not necessarily Cu or Cu alloy. Silver or a silver-containing alloy may be used. Furthermore, at least one of the upper layer wiring, the lower layer wiring, and the connection plug that connects the upper layer wiring and the lower layer wiring may be formed of a Cu film or a Cu alloy film.

  The Cu-containing alloy is one or more selected from the group consisting of Si, Al, Ag, W, Mg, Be, Zn, Pd, Cd, Au, Hg, Pt, Zr, Ti, Sn, Ni, and Fe. These metals may be contained.

  The barrier metal layer is made of one or more barrier metals of the group consisting of Ti, TiN, TiSiN, Ta, TaN, and TaSiN.

The same applies to the dual damascene structure described below.

(Example 2)
Next, as a second embodiment, a dual damascene structure will be described with reference to a partial sectional view of FIG.

  In this semiconductor device, a first etching stopper 402 is formed on a base insulating film 401 covering an element such as a MOS transistor formed on a Si substrate by 30 nm to 150 nm, and a first SiOCH film 403 is formed thereon by 200 to 500 nm. A first hard mask film 404 is formed thereon with a first copper wiring 410 formed in a laminated insulating layer of 50 to 200 nm, and a second barrier insulating film 411 is formed so as to cover the upper portion of the copper wiring. 30 nm to 150 nm are formed. A second SiOCH film 412 is formed thereon as a 200-500 nm different interlayer insulating film. Further, a second etching stopper 413 is formed in a thickness of 30 to 150 nm, a third SiOCH film 414 is formed in a thickness of 200 to 500 nm, and a second hard mask film 417 is formed in a thickness of 50 to 200 nm. A second copper wiring 422 is formed on the laminated insulating film, and a second barrier insulating film 423 is formed thereon with a thickness of 30 nm to 150 nm.

  The upper layer is repeated to form a multilayer wiring having a dual damascene structure.

  In the dual damascene structure, the etching stopper film can be omitted as in the single damascene structure.

  Next, a method for manufacturing the dual damascene structure of FIG. 7 will be described with reference to the drawings.

  FIG. 8A to FIG. 9C are process sectional views showing a manufacturing method by the via first method.

  FIG. 10A to FIG. 11D are process cross-sectional views illustrating a manufacturing method based on the middle first method.

  FIG. 12A to FIG. 14A are process cross-sectional views showing a manufacturing method by the trench first method.

  A method of manufacturing a dual damascene structure by the via first method will be described with reference to FIGS.

As in FIGS. 3A to 3D, the first Cu wiring 510 was formed. Next, as shown in FIG. 8A, a second SiCHN film 511 is formed, on which a second SiOCH film 512, a third SiCHN film 513, a third SiOCH film 514, and a second SiOCH are formed. _Two films 515 were formed, and an antireflection film 516 was formed thereon. The photoresist 517 was exposed and developed to form a via resist pattern 518.

Next, using the photoresist 517 as a mask, the second SiO ₂ film 515, the third SiOCH film 514, the third SiCHN film 513, and the second SiOCH film 512 are removed by etching, and the second SiCHN film 511 is removed. Etch stop. Thereafter, the photoresist 517 was peeled off (FIG. 8B).

  As shown in FIG. 8C, an antireflection film 519 was applied, and then the photoresist 520 was applied, exposed, and developed to form a second resist pattern 521 for trench wiring.

As shown in FIG. 8D, the second SiO ₂ film 515 and the third SiOCH film 514 were etched using the photoresist 520 as a mask. Then, etch stop was performed with the third SiCHN film 513. Thereafter, the photoresist 520 was removed and etched back again, and the second SiCHN film 511 and the third SiCHN film 513 were etched. Since the etching at this time is slightly over-etched, part of the second SiOCH is also removed by etching.

  Then, as shown in FIG. 9A, a second Ta / TaN film 522 was formed, and then a second Cu film 523 was formed.

  As shown in FIG. 9B, CMP was performed to remove metals other than the trench wiring, and a second Cu wiring 523 was formed.

  Next, as shown in FIG. 9C, a fourth SiCHN film 525 was formed.

  Next, a method for manufacturing a dual damascene structure by the middle-first method will be described with reference to FIGS.

  Similar to FIGS. 3A to 3D, the first Cu wiring 610 was formed. Next, a second SiCH film 611 was formed thereon, and a second SiOCH film 612 was further formed. A third SiCH film 613 was formed thereon (FIG. 10A).

  As shown in FIG. 10B, a photoresist 614 of a via resist pattern 615 was formed on the third SiCH film 613.

As shown in FIG. 10C, the third SiCH film 613 was etched using the photoresist 614 as a mask, and then ashing and organic peeling were performed. A third SiOCH film 616 and a third SiO ₂ film 617 were formed thereon.

  Next, as shown in FIG. 10D, a photoresist 618 was formed on the second trench wiring resist pattern 619.

As shown in FIG. 11A, the second SiOCH film 612 is processed using the photoresist 618 as a mask and the third SiO ₂ film 617, the third SiOCH film 616, and the third SiCH film 613 as a mask. did. Thereafter, the second SiCH film 611 was etched by etch back.

  A second Ta / TaN film 620 was formed as shown in FIG. Further, a second Cu film 621 was formed. Thereafter, as shown in FIG. 11C, the metal other than the trench wiring is removed by CMP to form the second Cu wiring 623, and then the fourth SiCH film 622 is formed as shown in FIG. Formed.

  Next, a method for manufacturing a dual damascene structure by the trench first method will be described with reference to FIGS.

  As in FIGS. 3A to 3D, a first-layer Cu wiring 710 was formed.

Next, as shown in FIG. 12A, a second SiCH film 711, a second SiOCH film 712, a third SiCHN film 713, a third SiOCH film 716, and a first SiO ₂ film 717 are formed. did. An antireflection film 725 was formed thereon, and a photoresist 718 was formed thereon as a second groove wiring resist pattern 719.

As shown in FIG. 12B, the first SiO ₂ film 717 and the third SiOCH film 716 are etched using the photoresist mask, the etching is stopped by the third SiCH film 713, and then the photoresist is ashed. And removed by organic peeling.

  As shown in FIG. 12C, the entire surface was etched back, and the third SiCH film 713 was etched.

  Next, as shown in FIG. 12D, a photoresist 714 is formed on the via resist pattern 715.

  As shown in FIG. 13A, the second SiOCH film 716 was etched using the photoresist 714 as a mask, the etch stop was performed with the second SiCH film 713, the photoresist was ashed, and organic peeling was performed. Thereafter, as shown in FIG. 13B, the entire surface was etched back, and the second SiCH film 711 was removed.

  As shown in FIG. 13C, a second Ta / TaN film 720 was formed, and then a second Cu film 721 was formed. Then, after removing the metal other than the second copper wiring 723 by CMP as shown in FIG. 13D, a SiCH film 722 was formed thereon as shown in FIG.

In the first and second embodiments, SiCH and SiCHN are equivalent and no problem occurs even if they are replaced.

(Example 3)
Example 3 in the case where SiCH and SiCHN insulating films are applied as a barrier insulating film of a semiconductor device will be described.

  SiCH was applied as the insulating films 202, 211, 214, and 223 of the semiconductor device shown in FIG.

  As the SiCH film, a film having a relative dielectric constant of 3.8 containing a vinyl group was used. When the obtained laminated structure was examined for heat resistance up to 450 ° C., it showed extremely good characteristics without deterioration of via yield even when heated at 450 ° C. In addition, the effective relative permittivity was reduced by 10% compared to the semiconductor device using SiCH having a relative permittivity of 4.5 deposited using 3MS.

  SiCHN which is the third embodiment is applied as the insulating films 202, 211, 214, and 223 of the semiconductor device shown in FIG.

A SiCHN film having a relative dielectric constant of 4.2 containing a vinyl group was used. When the obtained laminated structure was examined for heat resistance up to 450 ° C., it showed very good characteristics without deterioration in via yield even after heating at 450 ° C. In addition, the effective relative permittivity was reduced by 10% compared to the semiconductor device using SiCH having a relative permittivity of 5 deposited using 3MS.

  The present invention provides a method for producing a low-dielectric constant and high-quality SiOCH film. Further, by applying the SiOCH film to a low dielectric constant insulating film of a multilayer wiring of a semiconductor device, a structure with a small effective relative dielectric constant can be provided while maintaining the reliability of the wiring.

  The present invention provides a method for producing a low dielectric constant and high quality SiCH and SiCHN barrier insulating film. Further, by applying the SiCH and SiCHN films to the barrier insulating film of the multilayer wiring of the semiconductor device, it is possible to provide a structure with a small effective relative dielectric constant while maintaining the reliability of the wiring.

  Furthermore, since the completed film quality contains more carbon than the conventional SiC film and SiCN film, a high etching selectivity can be obtained with respect to the SiOC film and the SiOCH film as shown in FIG.

FIG. 21 shows data on the etching selectivity of the SiOCH / SiCHN film of the prior art and the present invention. As the etching gas, a CF-based gas was used. The SiCN film formed with 3MS, NH ₃ , and He had a low carbon content in the film, and the etching selectivity with respect to the SiOC film was 8, which was not sufficiently obtained. In contrast, the SiCHN film using TMVS has a sufficient etching selectivity of about 15. FIG. 22 shows the yield of 500K chains with 0.2 μm via diameter at that time.

  FIG. 22 shows the via yield of the dual damascene wiring formed by the via first method. In the conventional SiCN film formed by 3MS, the via yield was about 80%, whereas in SiCHN formed by TMVS. A yield of about 98% was obtained.

  Here, the via yield data of DD by the via first method is shown. However, the high yield of the SiCH film by TMVS of the present invention was also obtained by DD by middle first.

  Furthermore, FIG. 23 shows the wiring resistance in the DD wiring by trench first.

The effect was confirmed by variation in the layer resistance in the film structure of SiCHN using TMVS of the present invention. The reduction in the variation in the layer resistance is also due to the improvement in the etching selectivity of the etching stopper film. As shown in FIG. 23, the etching stopper for the SiCHN film using the conventional 3MS varies between 75 and 90Ω. However, the SiCHN film using TMVS of the present application was suppressed to about half of the variation.

Explanatory drawing of damascene structure. The 1st Embodiment figure of this invention. Explanatory drawing (1) of the process flow of the single damascene of this invention. Explanatory drawing (2) of the process flow of the single damascene of this invention. Explanatory drawing (3) of the process flow of the single damascene of this invention. Explanatory drawing (4) of the process flow of the single damascene of this invention. Second embodiment of the present invention Explanatory drawing (1) of the via first process flow of the dual damascene of this invention. Explanatory drawing (2) of the via first process flow of the dual damascene of this invention. Explanatory drawing (1) of the middle first process flow of the dual damascene of this invention. Explanatory drawing (2) of the middle first process flow of the dual damascene of this invention. Explanatory drawing (1) of the trench first process flow of the dual damascene of this invention. Explanatory drawing (2) of the trench first process flow of the dual damascene of this invention. Explanatory drawing (3) of the trench first process flow of the dual damascene of this invention. Explanatory drawing (1) of the via first process flow of the conventional dual damascene. Explanatory drawing (2) of the via first process flow of the conventional dual damascene. The block diagram of parallel plate type plasma CVD used by this invention. Relative permittivity of SiOCH film by various gases. Dielectric constant of SiCH film by various gases. The figure which shows the relationship between source gas molecular weight and the density and composition of a SiCH film | membrane. Etching selectivity of SiOCH and SiCHN films. Comparison of via chain yield between the present invention and the prior art. Comparison of wiring resistance variation between the present invention and the prior art.

Explanation of symbols

0001 SiO ₂ base interlayer insulating film 0002 SiO ₂ wiring trench interlayer film 0003 Etching stopper SiN insulating film 0007 Cu wiring 0012 SiN film (diffusion prevention insulating film)
0010 Insulating film
1 Upper electrode
2 Lower electrode
4 High frequency power supply
5 Gas introduction part
6 Gas exhaust part 201 Underlying insulating film 202 First etching stopper film 203 First SiOCH film 204 First hard mask film 210 First copper wiring 211 First barrier insulating film 212 Second SiOCH film 213 Second Hard mask film 214 second etching stopper film 217 third SiOCH film 218 third hard mask film 223 second barrier insulating film 224 second copper wiring 228 copper plug 301 base insulating film 302 first etching stopper Film 303 first SiOCH film 304 first hard mask film 305 first photoresist 306 groove pattern 307 first wiring groove pattern 308 first barrier metal film 309 first conductor film 310 first copper wiring 311 First barrier insulating film 312 Second SiOCH film 313 Second Hard mask film 314 Second etching stopper 315 Photoresist 316 Via resist pattern 317 Third SiOCH film 318 Third hard mass 319 Third photoresist 320 Second wiring groove resist pattern 321 Third barrier metal 322 3rd conductor film 323 2nd barrier insulating film 324 2nd wiring 325 Antireflection film 326 2nd barrier metal film 327 2nd conductor film 328 1st conductor plug 401 Base insulating film 402 1st etching stopper 403 first SiOCH film 404 first hard mask film 410 first copper wiring 411 second barrier insulating film 412 second SiOCH film 413 second etching stopper 414 third SiOCH film 417 second hard mask Film 422 Second copper wiring 423 Second barrier insulating film 510 first Cu interconnection 511 second SiCHN film 512 second SiOCH film 513 third SiCHN film 514 third SiOCH film 515 second SiO ₂ film 516 antireflection film 517 photoresist 518 Via resist pattern 519 Antireflection film 520 Photo resist 521 Second trench wiring resist pattern 522 Second Ta / TaN film 523 Second Cu film 524 Second Cu wiring 525 Fourth SiCHN film 610 First Cu wiring 611 Second SiCH film 612 Second SiOCH film 613 Third SiCH film 614 Photoresist 615 Via resist pattern 616 Third SiOCH film 617 Third SiO ₂ film 618 Photoresist 619 Second groove wiring Resist pattern 620 second T / TaN film 621 Second Cu film 622 Fourth SiCH film 623 Second Cu wiring 710 First copper wiring 711 Second SiCH film 712 Second SiOCH film 713 Third SiCH film 714 Photoresist 715 Via Resist pattern 716 Third SiOCH film 717 First SiO ₂ film 718 Photoresist 719 Second groove wiring resist pattern 720 Second Ta / TaN film 721 Second Cu film 723 Second copper wiring 725 Antireflection Film 801 Lower insulating film 802 First SiC film 803 Second SiOCH film 804 First SiO ₂ film 805 First copper wiring 806 Second SiCN film 807 Second SiOC film 808 Third SiCN film 809 First 3 SiOC film 810 Second SiO ₂ film 811 Antireflection film 812 Photoresist 813 Resist for via pattern 818 Photoresist 819 Second resist pattern for trench wiring 825 Antireflection film 831 Copper oxide film

Claims (73)

An organic insulating film formed from an organic silane having a C / Si ratio of 5 or more and a molecular weight of 100 or more as a raw material. The organic silane is one or more organic silanes selected from the group consisting of trimethylvinylsilane, triethylvinylsilane, dimethyldivinylsilane, diethyldivinylsilane, methyltrivinylsilane, ethyltrivinylsilane, tetravinylsilane, tetraethylsilane, and triethylsilane. The organic insulating film according to claim 1. The organic insulating film according to claim 1, wherein the organosilane has a vinyl group at least partially. The organic silane having a vinyl group at least partially is one or more organic silanes selected from the group consisting of trimethylvinylsilane, triethylvinylsilane, dimethyldivinylsilane, diethyldivinylsilane, methyltrivinylsilane, ethyltrivinylsilane, and tetravinylsilane. The organic insulating film according to claim 3. The organic insulating film according to claim 1, wherein the organic insulating film has a C═C bond. 6. The organic insulating film according to claim 5, which has a vinyl group. The organic insulating film according to claim 1, wherein the organic insulating film is a SiCH film, a SiCHN film, or a SiOCH film. The organic insulating film according to claim 7, wherein the SiCH film is made of Si, C, and H elements and has a C / Si composition ratio of 0.9 or more. The organic insulating film according to claim 7, wherein the SiCH film has a density of less than 1.4 g / cm ³ . 8. The organic insulating film according to claim 7, wherein the SiCHN film is made of Si, C, H, and N elements and has a C / Si composition ratio of 1.0 or more. 11. The organic insulating film according to claim 7, wherein the SiCHN film has a density of less than 1.6 g / cm ³ . The organic insulating film according to claim 7, wherein the SiOCH film is made of at least Si, C, O, and H elements, and has a C / Si composition ratio of 0.8 or more. The organic insulating film according to claim 7, wherein the SiOCH film has a density of less than 1.2 g / cm ³ . An organic insulating film characterized by being a film-forming method by plasma CVD, wherein the source gas is an organic silane having at least a C / Si ratio of 5 or more and a molecular weight of 100 or more, an oxidizing agent, and an inert gas Manufacturing method. The method of manufacturing an organic insulating film according to claim 14, wherein the inert gas is one of helium, argon, and xenon. The method for producing an organic insulating film according to claim 14, wherein the oxidizing agent is any one of O ₂ , O ₃ , H ₂ O, CO, and CO ₂ . The organic silane is one or more organic silanes selected from the group consisting of trimethylvinylsilane, triethylvinylsilane, dimethyldivinylsilane, diethyldivinylsilane, methyltrivinylsilane, ethyltrivinylsilane, tetravinylsilane, tetraethylsilane, and triethylsilane. The organic insulating film according to claim 14. The organic insulating film according to claim 14, wherein the organosilane has a vinyl group at least partially. The organic silane having a vinyl group at least partially is one or more organic silanes selected from the group consisting of trimethylvinylsilane, triethylvinylsilane, dimethyldivinylsilane, diethyldivinylsilane, methyltrivinylsilane, ethyltrivinylsilane, and tetravinylsilane. The organic insulating film according to claim 18. 15. The method of manufacturing an organic insulating film according to claim 14, wherein the organic insulating film is a SiOCH film made of at least Si, C, H, and O elements. It is a film-forming method by a plasma CVD method, and the source gas is an inert gas having an organic silane having a C / Si ratio of 5 or more and a molecular weight of 100 or more and helium, argon, or xenon. A method for producing an organic insulating film. The organic silane is one or more organic silanes selected from the group consisting of trimethylvinylsilane, triethylvinylsilane, dimethyldivinylsilane, diethyldivinylsilane, methyltrivinylsilane, ethyltrivinylsilane, tetravinylsilane, tetraethylsilane, and triethylsilane. The organic insulating film according to claim 21. The organic insulating film according to claim 21, wherein the organosilane has a vinyl group at least partially. The organosilane having a vinyl group at least partially is one or more organic silanes selected from the group consisting of trimethylvinylsilane, triethylvinylsilane, dimethyldivinylsilane, diethyldivinylsilane, methyltrivinylsilane, ethyltrivinylsilane, and tetravinylsilane. The organic insulating film according to claim 24. The method of manufacturing an organic insulating film according to claim 21, wherein the organic insulating film is a SiCH film made of Si, C, and H elements. A plasma CVD method for forming a film, wherein the source gas is an inert gas having a C / Si ratio of 5 or more, an organic silane having a molecular weight of 100 or more, a nitrogen-containing gas, and helium, argon, or xenon A method for producing an organic insulating film, wherein It said nitrogen-containing gas, ammonia, N _2, the manufacturing method of the organic insulating film according to claim 26 is any one of hydrazine. The organic silane is one or more organic silanes selected from the group consisting of trimethylvinylsilane, triethylvinylsilane, dimethyldivinylsilane, diethyldivinylsilane, methyltrivinylsilane, ethyltrivinylsilane, tetravinylsilane, tetraethylsilane, and triethylsilane. The manufacturing method of the organic insulating film of Claim 26. 27. The method for producing an organic insulating film according to claim 26, wherein the organosilane has a vinyl group at least partially. The organic silane having a vinyl group at least partially is one or more organic silanes selected from the group consisting of trimethylvinylsilane, triethylvinylsilane, dimethyldivinylsilane, diethyldivinylsilane, methyltrivinylsilane, ethyltrivinylsilane, and tetravinylsilane. 30. The method for producing an organic insulating film according to claim 29. 27. The method of manufacturing an organic insulating film according to claim 26, wherein the organic insulating film is a SiCHN film made of at least Si, C, H, and N elements. In a semiconductor device having at least one insulating film of an interlayer insulating film, an etching stopper film, or a metal barrier insulating film,
6. The semiconductor device according to claim 1, wherein the insulating film, the etching stopper film, or the metal barrier insulating film is the organic insulating film according to claim 1. The semiconductor device according to claim 32, wherein the semiconductor device has a trench wiring structure. A first insulating film formed on the insulating film formed on the semiconductor substrate;
A first trench wiring formed in the first insulating film;
A second insulating film;
A third insulating film;
A second trench wiring formed in the third insulating film;
In a semiconductor device having a groove wiring structure formed in the second insulating film and having a connection plug connecting the first groove wiring and the second groove wiring.
8. The semiconductor device according to claim 7, wherein the first insulating film, the second insulating film, and the third insulating film are made of at least the SiOCH film according to claim 7. 35. The semiconductor device according to claim 34, wherein the first insulating film is a laminated film including the SiOCH film and a hard mask film. The first insulating film is a laminated film composed of an etching stopper film, the SiOCH film, and a hard mask film,
The semiconductor device according to claim 34, wherein the etching stopper film is the SiCH film or the SiCHN film according to claim 7. The second insulating film is a laminated film comprising a barrier insulating film, the SiOCH film according to claim 7, and a hard mask film.
The semiconductor device according to claim 34, wherein the barrier insulating film is the SiCH film or the SiCHN film according to claim 7. The second insulating film is a laminated film composed of a barrier insulating film and the SiOCH film,
The semiconductor device according to claim 34, wherein the barrier insulating film is the SiCH film or the SiCHN film according to claim 7. The second insulating film is a laminated film including a barrier insulating film, the SiOCH film, and an etching stopper film.
The semiconductor device according to claim 34, wherein the barrier insulating film and the etching stopper film are the SiCH film or the SiCHN film according to claim 7. 35. The semiconductor device according to claim 34, wherein the third insulating film is a laminated film including the SiOCH film and a hard mask film. The third insulating film is a laminated film composed of an etching stopper film, the SiOCH film, and a hard mask film.
The semiconductor device according to claim 34, wherein the etching stopper film is the SiCH film or the SiCHN film according to claim 7. The upper part of the second trench wiring is covered with a barrier insulating film,
The semiconductor device according to claim 34, wherein the barrier insulating film is a SiCH film or a SiCHN film according to claim 7. The semiconductor device according to any one of claims 36, 39, and 41, wherein the etching stopper film is a laminated film of the SiCH film and the SiCHN film according to claim 7. The semiconductor device according to any one of claims 37, 38, 39, and 42, wherein the barrier insulating film is a laminated film of the SiCH film and the SiCHN film according to claim 7. 35. The semiconductor device according to claim 34, wherein at least one of the trench wiring or the connection plug is made of copper or a copper-containing metal. The copper-containing metal is one or more selected from the group consisting of Si, Al, Ag, W, Mg, Be, Zn, Pd, Cd, Au, Hg, Pt, Zr, Ti, Sn, Ni, and Fe. 46. The semiconductor device according to claim 45, comprising a metal. 35. The semiconductor device according to claim 34, wherein the trench wiring and the connection plug include one or more barrier metal layers of the group consisting of Ti, TiN, TiSiN, Ta, TaN, and TaSiN. In a method of manufacturing a semiconductor device having at least one insulating film of an interlayer insulating film, an etching stopper film, or a metal barrier insulating film,
The method for manufacturing a semiconductor device, wherein the insulating film, the etching stopper film, or the metal barrier insulating film is the organic insulating film according to claim 7. 49. The method of manufacturing a semiconductor device according to claim 48, wherein the semiconductor device has a trench wiring structure. In a method for manufacturing a semiconductor device having a trench wiring structure,
Forming a first insulating film on the semiconductor substrate;
Selectively etching the first insulating film to form a first wiring groove pattern;
Burying the first wiring groove pattern with metal to form a first groove wiring;
Forming a second insulating film;
Forming a connection hole reaching the upper surface of the first trench wiring by selectively etching the second insulating film;
Burying a metal in the connection hole to form a connection plug;
Forming a third insulating film;
Selectively etching the third insulating film to form a second groove pattern that reaches at least a part of the upper surface of the connection plug;
Burying the second wiring groove pattern with metal to form a second groove wiring;
Forming a barrier insulating film, and a method of manufacturing a semiconductor device,
8. The method of manufacturing a semiconductor device according to claim 7, wherein at least one of the first, second, and third insulating films is made of SiOCH. 51. The method of manufacturing a semiconductor device according to claim 50, wherein the first insulating film is a laminated film including the SiOCH film and a hard mask film. The first insulating film is a laminated film composed of an etching stopper film, the SiOCH film, and a hard mask film,
51. The method of manufacturing a semiconductor device according to claim 50, wherein the etching stopper film is the SiCH film or the SiCHN film according to claim 5. The second insulating film is a laminated film composed of a barrier insulating film, the SiOCH film, and a hard mask film,
46. The method of manufacturing a semiconductor device according to claim 45, wherein the barrier insulating film is the SiCH film or the SiCHN film according to claim 7. 51. The method of manufacturing a semiconductor device according to claim 50, wherein the third insulating film is a laminated film including the SiOCH film and a hard mask film. The third insulating film is a laminated film composed of an etching stopper film, the SiOCH film, and a hard mask film.
The method for manufacturing a semiconductor device according to claim 50, wherein the etching stopper film is the SiCH film or the SiCHN film according to claim 7. In a method for manufacturing a semiconductor device having a trench wiring structure,
Forming a first insulating film on the semiconductor substrate;
Selectively etching the first insulating film to form a first wiring groove pattern;
Burying the first wiring groove pattern with metal to form a first groove wiring;
Forming a second insulating film and a third insulating film;
Selectively etching the second insulating film and the third insulating film to form a connection hole reaching the upper surface of the first insulating film;
A step of selectively etching the third insulating film to form a second wiring groove reaching the upper surface of the second insulating film;
Burying the connection hole and the second wiring groove with metal;
In a method for manufacturing a semiconductor device including a step of forming a fourth insulating film,
8. The method of manufacturing a semiconductor device according to claim 7, wherein at least one of the first, second, and third insulating films is made of SiOCH. In a method for manufacturing a semiconductor device having a trench wiring structure,
Forming a first insulating film on the semiconductor substrate;
Selectively etching the first insulating film to form a first wiring groove pattern;
Burying the first wiring groove pattern with metal to form a first groove wiring;
Forming a second insulating film and a third insulating film;
Selectively etching the third insulating film to form a second wiring groove reaching the upper surface of the second insulating film;
Selectively etching a part of the bottom of the second wiring trench to form a connection hole reaching the top of the first insulating film;
Burying the connection hole and the second wiring groove with metal;
In a method for manufacturing a semiconductor device including a step of forming a fourth insulating film,
8. The method of manufacturing a semiconductor device according to claim 7, wherein at least one of the first, second, and third insulating films is made of SiOCH. 58. The method of manufacturing a semiconductor device according to claim 56, wherein the first insulating film is a laminated film including the SiOCH film and a hard mask film. The first insulating film is a laminated film composed of an etching stopper film, the SiOCH film, and a hard mask film,
58. The method of manufacturing a semiconductor device according to claim 56, wherein the etching stopper film is the SiCH film or the SiCHN film according to claim 7. The second insulating film is a laminated film composed of a barrier insulating film and the SiOCH film,
58. The method of manufacturing a semiconductor device according to claim 56, wherein the barrier insulating film is a SiCH film or a SiCHN film according to claim 7. The second insulating film is a laminated film including a barrier insulating film, the SiOCH film, and an etching stopper film.
58. The method of manufacturing a semiconductor device according to claim 56 or 57, wherein the barrier insulating film and the etching stopper film are the SiCH film or the SiCHN film according to claim 7. 58. The method of manufacturing a semiconductor device according to claim 56, wherein the third insulating film is a laminated film including the SiOCH film and a hard mask film. The third insulating film is a laminated film composed of an etching stopper film, the SiOCH film, and a hard mask film.
58. The method of manufacturing a semiconductor device according to claim 56, wherein the etching stopper film is the SiCH film or the SiCHN film according to claim 7. In a method for manufacturing a semiconductor device having a trench wiring structure,
Forming a first insulating film on the semiconductor substrate;
Selectively etching the first insulating film to form a first wiring groove pattern;
Burying the first wiring groove pattern with metal to form a first groove wiring;
Forming a second insulating film;
Forming an etching stopper film;
Selectively opening holes in the etching stopper film;
Forming a third insulating film;
The third insulating film is selectively etched to form a second wiring groove reaching the upper surface of the second insulating film, and a connection hole reaching the upper portion of the first wiring through the opening Forming, and
Burying the connection hole and the second wiring groove with metal;
In a method for manufacturing a semiconductor device including a step of forming a fourth insulating film,
At least one of the first, second, and third insulating films is made of SiOCH according to claim 7, and the etching stopper film is made of SiCH or SiCHN according to claim 7. A method for manufacturing a semiconductor device. The method of manufacturing a semiconductor device according to claim 64, wherein the first insulating film is a laminated film including the SiOCH film and a hard mask film. The first insulating film is a laminated film composed of an etching stopper film, the SiOCH film, and a hard mask film,
The method for manufacturing a semiconductor device according to claim 64, wherein the etching stopper film is the SiCH film or the SiCHN film according to claim 7. The second insulating film is a laminated film composed of a barrier insulating film and the SiOCH film,
The method for manufacturing a semiconductor device according to claim 64, wherein the barrier insulating film is the SiCH film or the SiCHN film according to claim 7. The method of manufacturing a semiconductor device according to claim 64, wherein the third insulating film is a laminated film including the SiOCH film and a hard mask film. The third insulating film is a laminated film composed of an etching stopper film, the SiOCH film, and a hard mask film.
The method for manufacturing a semiconductor device according to claim 64, wherein the etching stopper film is the SiCH film or the SiCHN film according to claim 7. The method for manufacturing a semiconductor device according to claim 64, wherein the barrier insulating film is the SiCH film or the SiCHN film according to claim 7. The semiconductor device according to claim 64, wherein at least one of the trench wiring or the connection plug is made of a copper-containing metal. The copper-containing metal is one or more selected from the group consisting of Si, Al, Ag, W, Mg, Be, Zn, Pd, Cd, Au, Hg, Pt, Zr, Ti, Sn, Ni, and Fe. 65. The method of manufacturing a semiconductor device according to any one of claims 56, 57, and 64, comprising a metal. The groove wiring or the connection plug has one or more barrier metals of the group consisting of Ti, TiN, TiSiN, Ta, TaN, and TaSiN. The manufacturing method of the semiconductor device as described in 2 ..

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