JP2007086762A - Display device and driving method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce a false contour which is generated when displaying in a time grayscale system. <P>SOLUTION: A pixel is divided into m (m is an integer of m≥2) sub-pixels, and an area ratio of an s-th (s is an integer of 1 to m) sub-pixel is to be 2<SP>s-1</SP>. Also, k (k is an integer of k≥2) sub-frame groups including a plurality of sub-frames are provided in one frame, along with dividing one frame into n (n is an integer of n≥2) sub-frames, so that a ratio of a lighting period length of a t-th (t is an integer of 1 to n) sub-frame is 2<SP>(t-1)m</SP>. Further, each of the n sub-frames is divided into k sub-frames each having a lighting period length that is about 1/k of each of the n sub-frames, and one of these is provided in each of the k sub-frame groups. At this time, in the k sub-frame groups, the sub-frames are arranged so that an appearance order of the sub-frame may become the same. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

The present invention relates to a display device and a driving method thereof, and more particularly to a display device to which an area gray scale method is applied and a driving method thereof.

In recent years, so-called self-luminous display devices in which pixels are formed by light-emitting elements such as light-emitting diodes (LEDs) have attracted attention. As a light-emitting element used in such a self-luminous display device, an organic light-emitting diode (also referred to as an OLED (Organic Light Emitting Diode), an organic EL element, or an electroluminescence (EL) element) attracts attention. It has been used for EL displays and the like. Since light-emitting elements such as OLEDs are self-luminous, there are advantages such as higher pixel visibility than a liquid crystal display, no need for a backlight, and high response speed. The luminance of the light emitting element is controlled by the value of the current flowing through the light emitting element.

There are a digital gradation method and an analog gradation method as driving methods for controlling the light emission gradation of such a display device. In the digital gradation method, gradation is expressed by turning on and off the light emitting element by digital control. On the other hand, the analog gray scale method includes a method in which the light emission intensity of the light emitting element is controlled in analog and a method in which the light emission time of the light emitting element is controlled in analog.

In the digital gradation method, since there are only two states of light emission and non-light emission, only two gradations can be expressed as it is. In view of this, multi-gradation is being achieved by combining different methods. As a technique for increasing the number of gradations, an area gradation method or a time gradation method is often used.

The area gradation method is a method of expressing gradation by controlling the area of a lighted portion. That is, one pixel is divided into a plurality of sub-pixels, and the number and area of the lit sub-pixels are controlled to express gradation (see, for example, Patent Document 1 and Patent Document 2). A disadvantage of the area gradation method is that it is difficult to increase the resolution and increase the number of gradations because the number of subpixels cannot be increased.

The time gray scale method is a method of expressing a gray scale by controlling the length of a light emitting period and the number of times of light emission. In other words, one frame is divided into a plurality of subframes, and each subframe is weighted such as the number of times of light emission and the time of light emission. Is used to express gradation. When such a time gray scale method is used, it is known that a display defect called pseudo contour (or false contour) or the like is caused, and countermeasures thereof are being studied (for example, see Patent Documents 3 to 9). ).

However, various methods for reducing pseudo contours have been proposed, but the effect of reducing pseudo contours has not been sufficiently obtained.

For example, refer to FIG. The pixel A represents the gradation 127, and the adjacent pixel B represents the gradation 128. FIG. 60 shows a lighting / non-lighting state in each subframe in that case. For example, FIG. 60A shows a case where only the pixel A or only the pixel B is viewed without moving the line of sight. In this case, a pseudo contour does not occur. This is because the brightness of the place where the line of sight passes is summed and the eyes feel bright. Therefore, the pixel A feels that the gradation is 127 (= 1 + 2 + 4 + 8 + 16 + 32 + 32 + 32), and the pixel B feels that the gradation is 128 (= 32 + 32 + 32 + 32). That is, the eyes feel the correct gradation.

On the other hand, it is assumed that the line of sight moves from the pixel A to the pixel B or from the pixel B to the pixel A. This case is shown in FIG. In this case, depending on how the line of sight moves, in some cases, the gradation may be 96 (= 32 + 32 + 32), and in other cases, the gradation may be 159 (= 1 + 2 + 4 + 8 + 16 + 32 + 32 + 32 + 32). Originally, the gradation should be 127 and 128, but the gradation appears to be 96 or 159, and a pseudo contour is generated.

FIG. 60 shows the case of 8-bit gradation (256 gradations). Next, FIG. 61 shows a case of 6-bit gradation (64 gradations). Similarly, depending on how the line of sight moves, the gray level is felt 16 (= 16) in some cases, and the gray level is felt 47 (= 1 + 2 + 4 + 8 + 16 + 16) in some cases. Originally, the gradation should be visible as 31 and 32, but the gradation appears as 16 or 47, and a pseudo contour is generated.
Japanese Patent Laid-Open No. 11-73158 JP 2001-125526 A Japanese Patent No. 2903984 Japanese Patent No. 3075335 Japanese Patent No. 2639311 Japanese Patent No. 3322809 JP-A-10-307561 Japanese Patent No. 3585369 Japanese Patent No. 348684

In this way, it is difficult to achieve high resolution and multi-gradation only with the conventional area gradation method, and with the conventional time gradation method alone, a pseudo contour is generated, and it is not sufficient to suppress deterioration in image quality. There wasn't.

In view of such problems, the present invention provides a display device that can display multi-tones and can be reduced in the number of subframes and can reduce pseudo contours, and a driving method using the display device. Objective.

One aspect of the present invention is a driving method of a display device including a plurality of pixels including m sub-pixels (m is an integer of m ≧ 2) provided with light-emitting elements, and the area ratio of the m sub-pixels is determined. 2 ⁰ : 2 ¹ : 2 ² ...: 2 ^m−3 : 2 ^m−2 : 2 ^m−1, and a plurality of subframes are formed in one frame in the lighting period of m subpixels. K (k is an integer of k ≧ 2) sub-frame groups, and in each of the k sub-frame groups, the ratio of the lengths of the lighting periods is 2 ⁰ : 2 ^m : 2 ^2m : ..: 2 ^{(n-3) m} : 2 ^{(n-2) m} : 2 ^(n-1) n (n is an integer of n ≧ 2) subframes are provided, and each of k subframes In the frame group, arrange the subframes with the same lighting period length so that the appearance order of the subframes is almost the same. Thus, the gradation of the pixel is expressed by selecting the lighting state or the non-lighting state of the m sub-pixels.

One aspect of the present invention is a driving method of a display device including a plurality of pixels including m sub-pixels (m is an integer of m ≧ 2) provided with light-emitting elements, and the area ratio of the m sub-pixels is determined. ^{2 0: 2 1: 2 2} : ····: 2 m-3: 2 m-2: 2 and ^m-1, the lighting period of the m sub-pixels, in one frame, composed of a plurality of sub-frame K (k is an integer of k ≧ 2) sub-frame groups, and the ratio of the lengths of lighting periods of one frame is 2 ⁰ : 2 ^m : 2 ^2m :...: 2 ^{(n− 3) m} : 2 ^{(n-2) m} : 2 ^(n-1) divided into n (n is an integer of n ≧ 2) first subframes, and n first subframes Is divided into k second subframes having a lighting period of approximately 1 / k of the first subframe, and n first subframes are divided. In each of the frames, each of the k subframe groups is divided into k subframe groups so that the appearance order of the second subframes having the same lighting period length is substantially the same. The gray level of each pixel is expressed by selecting the lighting state or non-lighting state of m subpixels in each second subframe.

One aspect of the present invention is a driving method of a display device including a plurality of pixels including m sub-pixels (m is an integer of m ≧ 2) provided with light-emitting elements, and the area ratio of the m sub-pixels is determined. 2 ⁰ : 2 ¹ : 2 ² ...: 2 ^m−3 : 2 ^m−2 : 2 ^m−1, and a plurality of subframes are formed in one frame in the lighting period of m subpixels. K (k is an integer of k ≧ 2) sub-frame groups, and the ratio of the lengths of lighting periods of one frame is 2 ⁰ : 2 ^m : 2 ^2m :...: 2 ^{(n− 3) m} : 2 ^{(n-2) m} : 2 ^(n-1) divided into n (n is an integer of n ≧ 2) first subframes, and n first subframes At least one of the first subframes is lighted with a length approximately 1 / (a × k) (a is an integer of a ≧ 2) of the first subframe. Are divided into (a × k) second subframes having a gap, and in the n first subframes, each of the second subframes divided into (a × k) is divided into k pieces A is arranged in each of the subframe groups, and each of the remaining first subframes of the n first subframes has a lighting period of approximately 1 / k length of the first subframe. Dividing into k second subframes, and arranging each of the second subframes divided into k in each of the remaining first subframes, one in each of the k subframe groups The second subframes arranged in a divided manner are arranged so that the appearance order of the second subframes having the same lighting period length is approximately the same in each of the k subframe groups, In each second subframe, the lighting state of m subpixels Or by selecting a non-lighting state is to represent the gray level of the pixel.

In the present invention, the subframe that divides the lighting period into (a × k) may be a subframe having the longest lighting period among n subframes.

In the present invention, in each of the k subframe groups, the subframes constituting each subframe group may be arranged in ascending order or descending order of the lighting periods. In addition, among the subframes constituting each subframe group, the order of at least one subframe having the longest lighting period and the subframe having the second longest lighting period is reversed. Also good.

In the driving method of the present invention, when the gradation is low, the relationship between the luminance of the pixel and the gradation is linear, and when the gradation is high, the relationship between the luminance of the pixel and the gradation is nonlinear. Also good.

The present invention is a display device that performs the driving method of the present invention, wherein each of the m sub-pixels includes a light emitting element, a signal line, a scanning line, a first power supply line, and a second power supply line. A selection transistor, and a drive transistor. The selection transistor has a first electrode electrically connected to the signal line and a second electrode electrically connected to the gate electrode of the drive transistor. The first electrode is electrically connected to the first power supply line, and the light-emitting element is configured such that the first electrode is electrically connected to the second electrode of the driving transistor, and the second electrode is the second electrode. A display device connected to a power supply line.

Note that in the display device of the present invention, the signal line, the scanning line, or the first power supply line may be shared by the m sub-pixels.

Note that in the display device of the present invention, the number of signal lines included in the pixel is 2 or more and m or less, and the selection transistor included in any one of the m sub-pixels is included in the other sub-pixels. The signal line different from the selection transistor may be electrically connected.

Note that in the display device of the present invention, the number of scanning lines included in the pixel is two or more, and the selection transistor included in any one of the m sub-pixels is different from the selection transistor included in the other sub-pixels. You may electrically connect with a different scanning line.

Note that in the display device of the present invention, the number of the first power supply lines included in the pixel is 2 or more and m or less, and the driving transistor included in any one of the m subpixels is connected to the other subpixels. The pixel may be electrically connected to a first power supply line different from the driving transistor included in the pixel.

Here, the subframe group refers to a group composed of a plurality of subframes. When a plurality of subframe groups are provided in one frame, the number of subframes constituting each subframe group is not limited. However, it is desirable to configure with approximately the same number of subframes. Further, there is no limitation on the length of the lighting period of each subframe group. However, it is desirable that the length of the lighting period be approximately equal in each subframe group.

Note that the division of subframes means to divide the length of the lighting period of the subframe.

In the present invention, one pixel represents one color element. Therefore, in the case of a color display device composed of R (red), G (green), and B (blue) color elements, the minimum unit of an image is composed of three pixels, an R pixel, a G pixel, and a B pixel. Shall be. Note that the color elements are not limited to three colors, and more than that may be used, or colors other than RGB may be used. For example, white (W) may be added to obtain RGBW. Further, RGB may be obtained by adding one or more colors such as yellow, cyan, and magenta. Further, for example, a similar color may be added for at least one color of RGB. For example, R, G, B1, and B2 may be used. B1 and B2 are both blue, but have different wavelengths. By using such color elements, it is possible to perform display closer to the real thing or to reduce power consumption. Note that the brightness of one color element may be controlled using a plurality of regions. In this case, one color element is one pixel, and each area for controlling the brightness is a sub-pixel. Thus, for example, when the area gradation method is used, there are a plurality of areas for controlling the brightness for each color element, and the gradation is expressed as a whole. Let it be a pixel. Therefore, in that case, one color element is composed of a plurality of sub-pixels. In that case, the size of the region contributing to display may be different depending on the sub-pixel. Further, in a plurality of brightness control areas for one color element, that is, in a plurality of sub-pixels constituting one color element, a signal supplied to each is slightly different so that a viewing angle is increased. You may make it expand.

In the present invention, the case where the pixels are arranged (arranged) in a matrix is included. Here, the arrangement (arrangement) of pixels in a matrix includes a case where pixels are arranged side by side in a vertical direction or a horizontal direction or a case where they are arranged on a jagged line. Therefore, for example, when full-color display is performed with three color elements (for example, RGB), the case where stripes are arranged and the case where dots of three color elements are arranged in a so-called delta are also included. Furthermore, the case where a Bayer is arranged is also included.

Note that in the present invention, various types of transistors can be used as a transistor. Thus, there is no limitation on the type of applicable transistor. Therefore, for example, a thin film transistor (TFT) including a non-single-crystal semiconductor film typified by amorphous silicon or polycrystalline silicon can be used. As a result, they can be manufactured even if the manufacturing temperature is not high, can be manufactured at low cost, can be manufactured on a large substrate, can be manufactured on a transparent substrate, and can manufacture a transistor that can transmit light. The transmission of light through the display element can be controlled using a transistor. In addition, a MOS transistor, a junction transistor, a bipolar transistor, or the like formed using a semiconductor substrate or an SOI substrate can be used. Accordingly, a transistor with little variation can be manufactured, a transistor with high current supply capability can be manufactured, a transistor with a small size can be manufactured, and a circuit with low power consumption can be configured. In addition, a transistor including a compound semiconductor such as ZnO, a-InGaZnO, SiGe, or GaAs, or a thin film transistor obtained by thinning them can be used. Accordingly, the transistor can be manufactured even at a low manufacturing temperature, can be manufactured at room temperature, or a transistor can be directly formed on a substrate having low heat resistance such as a plastic substrate or a film substrate. In addition, a transistor formed using an inkjet method or a printing method can be used. By these, it can manufacture at room temperature, can manufacture in a state with a low degree of vacuum, or can manufacture with a large sized board | substrate. Further, since the transistor can be manufactured without using a mask (reticle), the layout of the transistor can be easily changed. In addition, a transistor including an organic semiconductor or a carbon nanotube, or another transistor can be used. Thus, a transistor can be formed over a substrate that can be bent. Note that the non-single-crystal semiconductor film may contain hydrogen or halogen. In addition, various types of substrates on which the transistor is arranged can be used, and the substrate is not limited to a specific type. Therefore, for example, it can be placed on a single crystal substrate, an SOI substrate, a glass substrate, a quartz substrate, a plastic substrate, a paper substrate, a cellophane substrate, a stone substrate, a stainless steel substrate, a stainless steel substrate, a foil substrate, or the like. Alternatively, a transistor may be formed using a certain substrate, and then the transistor may be moved to another substrate and placed on another substrate. By using these substrates, a transistor with good characteristics, a transistor with low power consumption, a device that is not easily broken, or heat resistance can be provided.

In the present invention, being connected is synonymous with being electrically connected. Therefore, in the configuration disclosed by the present invention, in addition to a predetermined connection relationship, another element (for example, another element or a switch) that enables electrical connection may be disposed therebetween.

Note that various types of switches can be used as a switch shown in the present invention, and examples thereof include an electrical switch and a mechanical switch. In other words, any device can be used as long as it can control the flow of current, and it is not limited to a specific device, and various devices can be used. For example, it may be a transistor, a diode (for example, a PN diode, a PIN diode, a Schottky diode, a diode-connected transistor, or the like), a thyristor, or a logic circuit that combines them. Therefore, when a transistor is used as a switch, the transistor operates as a mere switch, and thus the polarity (conductivity type) of the transistor is not particularly limited. However, when it is desirable that the off-state current is small, it is desirable to use a transistor having a polarity with a small off-state current. As a transistor with low off-state current, there are a transistor provided with an LDD region and a transistor having a multi-gate structure. In addition, when the transistor operated as a switch operates at a source terminal potential close to a low potential side power supply (VSS, GND, 0 V, etc.), the N channel type is used. On the contrary, the source terminal potential is a high potential. When operating in a state close to a side power supply (VDD or the like), it is desirable to use a P channel type. This is because the absolute value of the voltage between the gate and the source can be increased, so that it can easily operate as a switch. Note that both N-channel and P-channel switches may be used as CMOS switches. When a CMOS switch is used, a current can flow when either the P-channel switch or the N-channel switch is turned on, so that the switch can easily function as a switch. For example, the voltage can be appropriately output regardless of whether the voltage of the input signal to the switch is high or low. Further, since the voltage amplitude value of the signal for turning on / off the switch can be reduced, the power consumption can be reduced.

In addition, in the present invention, it is formed on a certain object, or is formed on the top. It is not limited to being in direct contact with. This includes cases where they are not in direct contact, that is, cases where another object is sandwiched between them. Therefore, for example, when the layer B is formed on the layer A (or on the layer A), the case where the layer B is formed in direct contact with the layer A and the case where the layer B is formed In which another layer (for example, layer C or layer D) is formed in direct contact with layer B and layer B is formed in direct contact therewith. The same applies to the description of “above”, and it is not limited to being in direct contact with a certain object, and includes a case where another object is sandwiched therebetween. Therefore, for example, when the layer B is formed above the layer A, the case where the layer B is formed in direct contact with the layer A and the case where another layer is formed in direct contact with the layer A. (For example, the layer C or the layer D) is formed, and the layer B is formed in direct contact therewith. It should be noted that the same applies to the case of below or below, and includes the case of direct contact and the case of no contact.

Note that in the present invention, a semiconductor device refers to a device having a circuit including a semiconductor element (such as a transistor or a diode). In addition, any device that can function by utilizing semiconductor characteristics may be used. A display device refers to a device having a display element (such as a liquid crystal element or a light-emitting element). Note that a display panel body in which a plurality of pixels including a display element such as a liquid crystal element or an EL element and a peripheral driver circuit for driving these pixels are formed over a substrate may be used. Furthermore, a device to which a flexible printed circuit (FPC) or a printed wiring board (PWB) is attached (such as an IC, a resistor, a capacitor, an inductor, or a transistor) may also be included. Furthermore, an optical sheet such as a polarizing plate or a retardation plate may be included. Furthermore, a backlight (which may include a light guide plate, a prism sheet, a diffusion sheet, a reflection sheet, or a light source (such as an LED or a cold cathode tube)) may be included.

Note that the display device of the present invention can use various modes or have various display elements. For example, EL elements (organic EL elements, inorganic EL elements or EL elements containing organic and inorganic substances), electron-emitting elements, liquid crystal elements, electronic ink, grating light valves (GLV), plasma displays (PDP), digital micromirrors, etc. A display medium whose contrast is changed by an electromagnetic action, such as a device (DMD), a piezoelectric ceramic display, or a carbon nanotube, can be applied. Note that a display device using an EL element is an EL display, and a display device using an electron-emitting device is a liquid crystal display such as a field emission display (FED) or a SED type flat display (SED: Surface-conduction Electron-Emitter Display). A display device using the element includes a liquid crystal display, a transmissive liquid crystal display, a transflective liquid crystal display, a reflective liquid crystal display, and a display device using electronic ink includes electronic paper.

Note that a light-emitting element in this specification refers to an element whose display luminance can be controlled by a current value flowing through the element among display elements. Typically, it refers to an EL element. In addition to the EL element, for example, an electron emitting element is also included in the light emitting element.

Note that in this specification, a case where a light-emitting element is mainly used as a display element will be described as an example; however, in the content of the present invention, the display element is not limited to a light-emitting element. Various display elements described above can be applied.

In the present invention, by combining the area gray scale method and the time gray scale method, multi-tone display can be performed and pseudo contour can be reduced. Accordingly, the display quality is improved and a beautiful image can be seen. Further, the duty ratio (the ratio of the lighting period in one frame) can be improved as compared with the conventional time gray scale method, and the voltage applied to the light emitting element is reduced. Therefore, power consumption can be reduced and deterioration of the light emitting element is also reduced.

Embodiments of the present invention will be described below with reference to the drawings. However, the present invention can be implemented in many different modes, and those skilled in the art can easily understand that the modes and details can be variously changed without departing from the spirit and scope of the present invention. Is done. Therefore, the present invention is not construed as being limited to the description of this embodiment mode.

(Embodiment 1)
In this embodiment, an example in which the driving method of the present invention is applied to the case of 6-bit display (64 gradations) will be described.

In the driving method according to this embodiment, one pixel is divided into a plurality of sub-pixels, and an area gray scale method that expresses a gray scale by controlling the number and area of lighted sub-pixels and a plurality of one frame. Is divided into sub-frames, and each sub-frame is weighted such as the number of times of light emission and the light-emission time, and a time gray scale method that expresses a gray scale by differentiating the total weight for each gray scale is combined. . That is, one pixel is divided into m sub-pixel, the area ratio of the m sub-pixel ^{2 0: 2 1: 2 2} : ····: 2 m-3: 2 m-2: 2 ^{Let m-1} . In addition, k subframe groups (k is an integer of k ≧ 2) composed of a plurality of subframes are provided in one frame, and one frame is divided into n subframes. The ratio of the length of the lighting period is 2 ⁰ : 2 ^m : 2 ^2m :...: 2 ^{(n-3) m} : 2 ^{(n-2) m} : 2 ^{(n-1) m} . Further, each of the n subframes is divided into k subframes having a lighting period of approximately 1 / k of the subframe, and one subframe is arranged in each of the k subframe groups. At this time, the subframes are arranged so that the appearance order of the subframes is substantially the same in the k subframe groups. Then, gradation is expressed by controlling the lighting of the m sub-pixels in each sub-frame.

First, an expression method of each gradation, that is, how each sub-pixel is lit in each sub-frame in each gradation will be described. In the present embodiment, one pixel is divided into two subpixels (SP1, SP2) such that the area ratio of each subpixel is 1: 2, and two subframe groups (one frame) ( SFG1, SFG2) are provided, and one frame is divided into three subframes (SF1, SF2, SF3) so that the ratio of the lighting periods of each subframe is 1: 4: 16. I will explain. This example corresponds to m = 2, n = 3, and k = 2.

Here, the area of each sub-pixel is SP1 = 1, SP2 = 2, and the lighting period of each sub-frame is SF1 = 1, SF2 = 4, and SF3 = 16.

In this embodiment, each of the subframes (SF1 to SF3) obtained by dividing one frame into three so that the ratio of the lighting period is 1: 4: 16 is reduced to 1/2 of the subframe. Is further divided into two subframes having a lighting period of a length of. That is, SF1 having the lighting period 1 is divided into two subframes SF11 and SF21 having the lighting period 0.5. Similarly, SF2 having the lighting period 4 is divided into two subframes SF12 and SF22 having the lighting period 2, and SF3 having the lighting period 16 is divided into two subframes SF13 and SF23 having the lighting period 8. To divide. Then, SF11, SF12, and SF13 are arranged in subframe group 1 (SFG1), and SF21, SF22, and SF23 are arranged in subframe group 2 (SFG2). At this time, the appearance order of SF11, SF12, SF13 and SF21, SF22, SF23 is made the same in subframe group 1 and subframe group 2.

Thus, each of the two subframe groups is composed of three subframes, and the lighting period of each subframe is SF11 = 0.5, SF12 = 2, SF13 = 8, SF21 = 0.5, SF22 = 2, SF23 = 8.

A representation method of each gradation in this case is shown in FIG. In addition, as a way of viewing FIG. 1, in each subframe, the subpixels marked with ◯ are lit and the subpixels marked with x are not lit.

In the present invention, the product of the area of each sub-pixel and the lighting period of each sub-frame is considered as a substantial light emission intensity. For example, in SF11 having a lighting period of 0.5 in subframe group 1, the emission intensity when only subpixel 1 with area 1 is lit is 1 × 0.5 = 0.5, and subpixel 2 with area 2 The light emission intensity when only the light is on is 2 × 0.5 = 1. Similarly, in the SF 12 having the lighting period 2, the light emission intensity when only the sub-pixel 1 is lit is 2, and the light emission intensity when only the sub-pixel 2 is lit is 4. Similarly, in the SF 13 having the lighting period 8, the emission intensity when only the sub-pixel 1 is lit is 8, and the emission intensity when only the sub-pixel 2 is lit is 16. It should be noted that the emission intensity is similarly determined in the subframes constituting the subframe group 2. In this manner, different emission intensity can be created depending on the combination of the area of the sub-pixel and the lighting period of the sub-frame, and the gradation is expressed by the emission intensity.

Next, an example of a gradation expression method, that is, a method for selecting each subframe will be described. In particular, regarding subframes having the same lighting period length, it is desirable that the subframe selection has the following regularity.

For example, for the subframes SF11 and SF21 having the lighting period 0.5, the selected / non-selected states are matched, and the lighting / non-lit states of the subpixels are also matched. That is, if SF11 is selected, SF21 is also selected. If SF11 is not selected, SF21 is not selected. Further, for example, if the sub pixel 1 is lit in SF11, the sub pixel 1 is also lit in SF21. If the sub pixel 2 is lit in SF11, the sub pixel 2 is also lit in SF21. This is because it is originally a subframe with a lighting period of 1, and is only divided into SF11 and SF21. Similarly, the subframes SF12 and SF22 having the lighting period 2 are also matched in the selected / unselected state, and the lit / non-lit state of the sub-pixel is also matched. This is because SF12 and SF22 are originally divided subframes with a lighting period of 4. Similarly, the subframes SF13 and SF23 having the lighting period 8 also match the selected / non-selected state, and also match the lighting / non-lighting states of the sub-pixels. This is because SF13 and SF23 are originally divided sub-frames having a lighting period of 16.

For this reason, for example, when the gradation 1 is expressed, the sub-pixel 1 is turned on by SF11 and SF21. Further, in the case of expressing the gradation 2, the sub-pixel 2 is turned on with SF11 and SF21. Further, when expressing the gradation 3, the subpixel 1 and the subpixel 2 are turned on by SF11 and SF21. In the case of expressing the gradation 6, the subpixel 2 is turned on with SF11 and SF21, and the subpixel 1 is turned on with SF12 and SF22. Similarly, for the other gradations, each sub-pixel to be lit in each sub-frame is selected.

As described above, 6-bit gradation (64 gradations) can be expressed by selecting a subpixel to be lit in each subframe.

When the driving method of the present invention is used, the pseudo contour can be reduced. For example, in FIG. 1, it is assumed that gradation 31 is displayed in pixel A and gradation 32 is displayed in pixel B. FIG. 2 shows a lighting / non-lighting state of each sub-pixel in each sub-frame in that case.

Here, how to view FIG. 2 will be described. FIG. 2 is a diagram showing a state of lighting / non-lighting of pixels in one frame. The horizontal direction in FIG. 2 indicates time, and the vertical direction indicates the pixel position. The vertical length of the quadrangle shown in FIG. 2 indicates the area ratio of each sub-pixel, and the horizontal length indicates the ratio of the length of the lighting period of each sub-frame. Further, the area of each quadrangle depicted in FIG. 2 indicates the emission intensity.

For example, if the line of sight moves, depending on how the line of sight is followed, the gray level is felt 26 (= 2 + 8 + 16) in some cases, and the gray level is felt 29 (= 16 + 1 + 4 + 8) in some cases. Originally, the gradation should be seen as 31 and 32, but the gradation is seen as 26 or 29, and a pseudo contour is generated. However, since the gradation shift is smaller than that of the conventional driving method, the pseudo contour is reduced as compared with the case of using the conventional driving method.

In this embodiment, the length of the lighting period of the subframes (SF1, SF2, SF3) before being divided into the same number as the subframe group is 1, 4, and 16, but the present invention is not limited to this.

In this embodiment, each of the three subframes (SF1, SF2, SF3) having a lighting period ratio of 1: 4: 16 is further divided into two subframes (the same number of subframe groups). Although divided into SF11 to SF23), the number of divisions of each subframe may be different from the number of subframe groups.

For example, the ratio of the length of the lighting period is 2 ⁰ : 2 ^m : 2 ^2m :...: 2 ^{(n−3) m} : 2 ^{(n−2) m} : 2 ^{(n−1) m} At least one subframe of the subframes has (a × k) lighting periods having a lighting period of approximately 1 / (a × k) (a is an integer of a ≧ 2). Divide into subframes, arrange a in each of the k subframe groups, and divide the remaining subframes into k subframes having a lighting period of approximately 1 / k of the subframe. , One may be arranged in each of the k subframe groups. In particular, as a subframe that divides the lighting period into (a × k) subframes, a subframe having the longest lighting period among n subframes may be selected.

For example, one pixel is divided into two subpixels (SP1, SP2) such that the area ratio of each subpixel is 1: 2, and two subframe groups (SFG1, SFG2) are included in one frame. ) Is divided into three subframes (SF1, SF2, SF3) such that the ratio of the lighting period is 1: 4: 16, and the subframe having the longest lighting period 16 among them is selected. The sub-frame is divided into four sub-frames having a lighting period that is 1/4 of the sub-frame, and the remaining two sub-frames are 2 having a lighting period that is 1/2 the length of the sub-frame. An example in the case of dividing into subframes is shown in FIG. This example corresponds to m = 2, n = 3, k = 2, and a = 2.

Here, the area of each sub-pixel is SP1 = 1, SP2 = 2, and the lighting period of each sub-frame is SF1 = 1, SF2 = 4, and SF3 = 16.

In FIG. 3, among subframes obtained by dividing one frame into three so that the ratio of the lighting periods is 1: 4: 16, SF3 having the longest lighting period 16 is represented as 1 of the subframe. The sub-frames are divided into four subframes SF13, SF14, SF23, and SF24 having a lighting period 4 of / 4 length. Further, the remaining SF1 and SF2 are further divided into two subframes having a lighting period that is 1/2 the length of the subframe. That is, SF1 having the lighting period 1 is divided into two subframes SF11 and SF21 having the lighting period 0.5, and SF2 having the lighting period 4 is divided into two subframes SF12 and SF22 having the lighting period 2. Divide into Then, SF11, SF12, SF13, and SF14 are arranged in subframe group 1 (SFG1), and SF21, SF22, SF23, and SF24 are arranged in subframe group 2 (SFG2). At this time, the appearance order of SF11, SF12, SF13, SF14 and SF21, SF22, SF23, SF24 is the same in subframe group 1 and subframe group 2.

Thus, each of the two subframe groups is composed of four subframes, and the lighting periods of each subframe are SF11 = 0.5, SF12 = 2, SF13 = 4, SF14 = 4, SF21 = 0. 5, SF22 = 2, SF23 = 4, and SF24 = 4.

In FIG. 3, the product of the area of each sub-pixel and the lighting period of each sub-frame is considered as a substantial light emission intensity. For example, in SF11 having a lighting period of 0.5 in subframe group 1, the emission intensity when only subpixel 1 with area 1 is lit is 0.5, and when only subpixel 2 with area 2 is lit. The emission intensity is 1. Similarly, in the SF 12 having the lighting period 2, the light emission intensity when only the sub-pixel 1 is lit is 2, and the light emission intensity when only the sub-pixel 2 is lit is 4. Similarly, in SF13 and SF14 having the lighting period 4, the emission intensity when only the sub-pixel 1 is lit is 4, and the emission intensity when only the sub-pixel 2 is lit is 8. It should be noted that the emission intensity is similarly determined in the subframes constituting the subframe group 2. In this manner, different emission intensity can be created depending on the combination of the area of the sub-pixel and the lighting period of the sub-frame, and 6-bit gradation (64 gradations) is expressed with this emission intensity.

The pseudo contour can be reduced by using the driving method as shown in FIG. For example, in FIG. 3, it is assumed that gradation 31 is displayed in pixel A and gradation 32 is displayed in pixel B. FIG. 4 shows the lighting / non-lighting state of each sub-pixel in each sub-frame in that case. For example, if the line of sight moves, depending on how the line of sight is followed, the gray level is felt 22 (= 2 + 4 + 8 + 8) in some cases, and the gray level is felt 29 (= 8 + 8 + 1 + 4 + 4 + 4) in some cases. Originally, the gradation should appear as 31 and 32, but the gradation appears as 22 or 29, and a pseudo contour is generated. However, since the gradation shift is smaller than that in the conventional driving method, the pseudo contour is reduced as compared with the conventional driving method.

In this way, by shortening the lighting period of each sub-frame or increasing the number of sub-frame divisions, the eyes are misled so that the gradation shift when the line of sight moves is felt smaller than in the conventional driving method. It is. Therefore, the effect of reducing the pseudo contour is increased. Note that the subframe in which the lighting period is further divided into four is not limited to the subframe having the longest lighting period.

Note that, by shortening the lighting period of each subframe or increasing the number of divisions, the number of subpixel selection methods in each subframe for expressing the same gradation is increased. Therefore, the selection method of each sub-pixel in each sub-frame is not limited to this. For example, when the gradation 31 is expressed, in FIG. 3, the subpixel 1 is lit by SF13, SF14, SF23, and SF24, but the subpixel 2 may be lit by SF13 and SF23. An example of this case is shown in FIG.

Note that the pseudo contour can be reduced by using a driving method as shown in FIG. For example, in FIG. 5, it is assumed that gradation 31 is displayed in pixel A and gradation 32 is displayed in pixel B. FIG. 6 shows a lighting / non-lighting state of each sub-pixel in each sub-frame in that case. For example, if the line of sight moves, depending on how the line of sight is followed, the gray level is felt 26 (= 2 + 8 + 8 + 8) in some cases, and the gray level is felt 29 (= 8 + 8 + 1 + 4 + 8) in some cases. Originally, the gradation should be seen as 31 and 32, but the gradation is seen as 26 or 29, and a pseudo contour is generated. However, since the gradation shift is smaller than that in the conventional driving method, the pseudo contour is reduced as compared with the conventional driving method.

As described above, the effect of reducing the pseudo contour can be increased by selectively changing the selection method of the sub-pixels in each sub-frame with respect to the gradation in which the pseudo contour is particularly likely to appear.

Note that the order of the lighting periods of the subframes is not limited to this. For example, the lighting periods may be in ascending order or descending order in each subframe group. This is because the gradation shift when moving the line of sight can be made smaller than in the conventional driving method by setting the lighting period of each subframe in ascending or descending order of the lighting period. This is because the pseudo contour can be further reduced as compared with this driving method.

Alternatively, after arranging the lighting periods in ascending or descending order in each subframe group, the order of the subframe having the longest lighting period and the subframe having the second longest lighting period may be interchanged.

For example, FIG. 7 shows an example in which the order of the subframe having the longest lighting period and the subframe having the second longest lighting period in each subframe group is switched in FIG.

7, the order of the subframe having the longest lighting period 4 and the subframe having the second longest lighting period 2 in each subframe group in FIG. 5 is switched. That is, in subframe group 1, SF 13 having lighting period 4 and SF12 having lighting period 2 are interchanged, and in subframe group 2, SF23 having lighting period 4 and SF22 having lighting period 2 are interchanged. Yes.

Note that the pseudo contour can be reduced by using a driving method as shown in FIG. For example, in FIG. 7, it is assumed that gradation 31 is displayed in pixel A and gradation 32 is displayed in pixel B. FIG. 8 shows the lighting / non-lighting state of each sub-pixel in each sub-frame in that case. For example, if the line of sight moves, depending on how the line of sight is followed, the gray level is felt 28 (= 8 + 4 + 8 + 8) in some cases, and the gray level is felt 30 (= 8 + 8 + 8 + 4 + 2) in some cases. Originally, the gradation should be seen as 31 and 32, but the gradation appears as 28 or 30, and a pseudo contour is generated. However, since the gradation shift is smaller than that in the conventional driving method, the pseudo contour is reduced as compared with the conventional driving method.

In this way, by changing the order of the lighting periods of the sub-frames, it is possible to reduce the gray level shift when the eyes are misled and the line of sight moves. Therefore, the pseudo contour can be reduced.

Note that the subframes in which the order is switched after the lighting periods are arranged in ascending or descending order in each subframe group are not limited to the subframe having the longest lighting period and the subframe having the second longest lighting period. For example, the subframe having the longest lighting period and the subframe having the third longest lighting period may be interchanged, and the subframe having the second longest lighting period and the subframe having the third longest lighting period may be replaced. It may be replaced.

Note that the length of the lighting period varies depending on the total number of gradations (number of bits), the total number of subframes, and the like. Therefore, even if the length of the lighting period is the same, if the total number of gradations (number of bits) or the total number of subframes changes, the length of the actual lighting period (for example, how many μs it is) ) May change.

The lighting period is used when the lamp continues to be lit, and the lighting count is used when the lamp continues to flash within a certain time. A typical display using the number of times of lighting is a plasma display. A typical display using the lighting period is an organic EL display.

In this embodiment, the area ratio of each sub-pixel is 1: 2, but is not limited to this. For example, it may be divided into 1: 4 or 1: 8.

For example, if the area ratio of each sub-pixel is 1: 1, the light emission intensity is equal regardless of which sub-pixel emits light in the same sub-frame. Therefore, when expressing the same gradation, it may be switched which sub-pixel emits light. As a result, it is possible to prevent only specific sub-pixels from emitting light in a concentrated manner, and to prevent pixel burn-in.

Incidentally, the area ratio of the m sub-pixel ^{2 0: 2 1: 2 2} : ····: 2 m-3: 2 m-2: 2 and ^m-1, the lighting period of the n sub-frame By setting the length ratio to 2 ⁰ : 2 ^m : 2 ^2m :...: 2 ^{(n-3) m} : 2 ^{(n-2) m} : 2 ^{(n-1) m} , fewer subpixels More gradations can be expressed with a smaller number and a smaller number of subframes. In addition, since the gradation that can be expressed by this method has a constant gradation change rate, smoother gradation display is possible and image quality can be improved.

In the present embodiment, the number of sub-pixels is two, but the present invention is not limited to this.

For example, one pixel is divided into three subpixels (SP1, SP2, SP3) so that the area ratio of each subpixel is 1: 2: 4, and two subframe groups are included in one frame. FIG. 9 shows an example in which (SFG1, SFG2) is provided and one frame is divided into two subframes (SF1, SF2) such that the ratio of the lighting period of each subframe is 1: 8. Show. This example corresponds to m = 3, n = 2, and k = 2.

Here, the area of each subpixel is SP1 = 1, SP2 = 2, SP3 = 4, and the lighting period of each subframe is SF1 = 1 and SF2 = 8.

In FIG. 9, each of the subframes (SF1, SF2) obtained by dividing one frame into two so that the ratio of the lighting period is 1: 8 is represented by 1 / of the subframe (SF1, SF2). It is further divided into two subframes having a lighting period of 2 lengths. That is, SF1 having the lighting period 1 is divided into two subframes SF11 and SF21 having the lighting period 0.5. Similarly, SF2 having the lighting period 8 is divided into two subframes SF12 and SF22 having the lighting period 4. Then, SF11 and SF12 are arranged in subframe group 1 (SFG1), and SF21 and SF22 are arranged in subframe group 2 (SFG2). At this time, the subframe group 1 and the subframe group 2 have the same appearance order of SF11, SF12, SF21, and SF22.

Thus, each of the two subframe groups is composed of two subframes, and the lighting periods of each subframe are SF11 = 0.5, SF12 = 4, SF21 = 0.5, and SF22 = 4.

In FIG. 9, the product of the area of each sub-pixel and the lighting period of each sub-frame is considered as a substantial light emission intensity. For example, in SF11 having a lighting period of 0.5 in subframe group 1, the emission intensity when only subpixel 1 with area 1 is lit is 0.5, and when only subpixel 2 with area 2 is lit. The light emission intensity is 1, and the light emission intensity is 2 when only the sub-pixel 3 having the area 4 is turned on. Similarly, in the SF 12 having the lighting period 4, the light emission intensity when only the sub-pixel 1 is lit is 4, the light emission intensity when only the sub-pixel 2 is lit is 8, and when only the sub-pixel 3 is lit. The emission intensity is 16. It should be noted that the emission intensity is similarly determined in the subframes constituting the subframe group 2. In this manner, different emission intensity can be created depending on the combination of the area of the sub-pixel and the lighting period of the sub-frame, and 6-bit gradation (64 gradations) is expressed with this emission intensity.

The pseudo contour can be reduced by using the driving method as shown in FIG. For example, in FIG. 9, it is assumed that gradation 31 is displayed in pixel A and gradation 32 is displayed in pixel B. FIG. 10 shows the lighting / non-lighting state of each sub-pixel in each sub-frame in that case. For example, if the line of sight moves, depending on how the line of sight is followed, the gray level is felt 28.5 (= 0.5 + 4 + 8 + 16) in some cases, and the gray level is 30 (= 16 + 2 + 8 + 4) in some cases. Originally, the gradation should be seen as 31 and 32, but the gradation appears as 28.5 or 30, and a pseudo contour is generated. However, since the gradation shift is smaller than that of the conventional driving method, the pseudo contour is reduced as compared with the case of using the conventional driving method.

Further, in FIG. 9, one frame is divided into two subframes (SF1, SF2) so that the ratio of the lighting period is 1: 8, and the subframe having the longest lighting period 8 among them is The subframe is divided into four subframes having a lighting period that is 1/4 of the subframe, and the remaining subframes are divided into two subframes having a lighting period that is 1/2 the length of the subframe. It may be divided. An example of this case is shown in FIG. This example corresponds to m = 3, n = 2, k = 2, and a = 2.

Here, the area of each subpixel is SP1 = 1, SP2 = 2, SP3 = 4, and the lighting period of each subframe is SF1 = 1 and SF2 = 8.

In FIG. 11, among the subframes obtained by dividing one frame into two so that the ratio of the lighting periods is 1: 8, SF2 having the longest lighting period 8 is ¼ of the subframe. Is divided into four sub-frames SF12, SF13, SF22, and SF23 having a lighting period 2 of the length. Further, the remaining SF1 is further divided into two subframes SF11 and SF21 having a lighting period 0.5 that is ½ of the length of the subframe. Then, SF11, SF12, and SF13 are arranged in subframe group 1 (SFG1), and SF21, SF22, and SF23 are arranged in subframe group 2 (SFG2). At this time, the appearance order of SF11, SF12, SF13 and SF21, SF22, SF23 is made the same in subframe group 1 and subframe group 2.

Thus, each of the two subframe groups is composed of three subframes, and the lighting period of each subframe is SF11 = 0.5, SF12 = 2, SF13 = 2, SF21 = 0.5, SF22 = 2, SF23 = 2.

In FIG. 11, the product of the area of each sub-pixel and the lighting period of each sub-frame is considered as a substantial light emission intensity. For example, in SF11 having a lighting period of 0.5 in subframe group 1, the emission intensity when only subpixel 1 with area 1 is lit is 0.5, and when only subpixel 2 with area 2 is lit. The light emission intensity is 1, and the light emission intensity is 2 when only the sub-pixel 3 having the area 4 is turned on. Similarly, in SF12 and SF13 having the lighting period 2, the emission intensity when only the sub-pixel 1 is lit is 2, the emission intensity when only the sub-pixel 2 is lit is 4, and only the sub-pixel 3 is lit. In this case, the emission intensity is 8. It should be noted that the emission intensity is similarly determined in the subframes constituting the subframe group 2. In this manner, different emission intensity can be created depending on the combination of the area of the sub-pixel and the lighting period of the sub-frame, and 6-bit gradation (64 gradations) is expressed with this emission intensity.

The pseudo contour can be reduced by using the driving method as shown in FIG. For example, in FIG. 11, it is assumed that gradation 31 is displayed in pixel A and gradation 32 is displayed in pixel B. FIG. 12 shows a lighting / non-lighting state of each sub-pixel in each sub-frame in that case. For example, if the line of sight moves, depending on how the line of sight is followed, the gradation may be felt 22 (= 2 + 4 + 8 + 8) in some cases, and the gradation may be 28 (= 8 + 8 + 2 + 4 + 4 + 2) in some cases. Originally, the gradation should appear as 31 and 32, but the gradation appears as 22 or 28, and a pseudo contour is generated. However, since the gradation shift is smaller than that in the conventional driving method, the pseudo contour is reduced as compared with the conventional driving method.

In this way, by shortening the lighting period of each subframe or increasing the number of subframe divisions, the eyes become misleading and the gradation shift when the line of sight moves is smaller than in the conventional driving method. . Therefore, the effect of reducing the pseudo contour is increased. Note that the subframe in which the lighting period is further divided into four is not limited to the subframe having the longest lighting period.

Note that, by shortening the lighting period of each subframe or increasing the number of divisions, the number of subpixel selection methods in each subframe for expressing the same gradation is increased. Therefore, the selection method of each sub-pixel in each sub-frame is not limited to this. For example, in the case of expressing gradation 31, in FIG. 11, subpixel 1 and subpixel 2 are lit by SF12, SF13, SF22, and SF23, but subpixel 2 and subpixel 3 are lit by SF12 and SF22. May be. An example of this case is shown in FIG.

Note that the pseudo contour can be reduced by using a driving method as shown in FIG. For example, in FIG. 13, it is assumed that gradation 31 is displayed in pixel A and gradation 32 is displayed in pixel B. FIG. 14 shows the lighting / non-lighting state of each sub-pixel in each sub-frame in that case. For example, if the line of sight moves, depending on how the line of sight is followed, the gradation may be 28 (= 4 + 8 + 8 + 8) in some cases, and the gradation may be 30 (= 8 + 8 + 2 + 8 + 4) in some cases. Originally, the gradation should be seen as 31 and 32, but the gradation appears as 28 or 30, and a pseudo contour is generated. However, since the gradation shift is smaller than that in the conventional driving method, the pseudo contour is reduced as compared with the conventional driving method.

As described above, the effect of reducing the pseudo contour can be increased by selectively changing the selection method of the sub-pixels in each sub-frame with respect to the gradation in which the pseudo contour is particularly likely to appear.

Note that the correspondence between the subpixel number and the area is not limited to this. For example, in FIG. 11, the area of each sub-pixel is SP1 = 1, SP2 = 2, and SP3 = 4. However, SP1 = 1, SP2 = 4, and SP3 = 2 may be used, or SP1 = 2 and SP2 = 1. SP3 = 4, or SP1 = 4, SP2 = 2, or SP3 = 1.

In this manner, by using the driving method of the present invention, it is possible to reduce the pseudo contour or increase the number of gradations without increasing the number of subframes. In addition, since the number of subframes can be reduced as compared with the conventional time gray scale method, each subframe period can be provided longer. Thereby, the duty ratio can be improved and the voltage applied to the light emitting element is reduced. Therefore, power consumption can be reduced and deterioration of the light emitting element is also reduced.

Note that, in a certain gradation, the selection method of subpixels in each subframe may be changed in time or place. That is, the subpixel selection method in each subframe may be changed depending on the time, or the subpixel selection method in each subframe may be changed depending on the pixel. Further, it may be changed depending on the time and also depending on the pixel.

For example, when expressing a certain gradation, the selection method of the sub-pixels in each sub-frame may be changed depending on whether the number of frames is an odd number or an even number. For example, when the number of frames is an odd number, gradation is expressed by the subpixel selection method shown in FIG. 11, and when the number is even, the gradation is expressed by the subpixel selection method shown in FIG. May be. As described above, the pseudo contour can be reduced by changing the selection method of the sub-pixel for the gradation at which the pseudo contour is particularly likely to appear between the odd number and the even number.

Note that here, the subframe selection method is changed for gradations at which pseudo contours are particularly likely to appear, but the subpixel selection method may be changed for arbitrary gradations.

In addition, when expressing a certain gradation, a method of selecting a sub pixel in each sub frame may be changed depending on whether an odd row pixel is displayed or an even row pixel is displayed. In addition, when expressing a certain gradation, a method of selecting a sub pixel in each sub frame may be changed depending on whether an odd column pixel is displayed or an even column pixel is displayed.

Further, when expressing a certain gradation, the number of subframe divisions and the ratio of the lighting period may be changed depending on whether the number of frames is an odd number or an even number. For example, when the number of frames is an odd number, gradation is expressed by the subpixel selection method shown in FIG. 9, and when the number of frames is an even number, the gradation is expressed by the subpixel selection method shown in FIG. May be expressed.

Note that the order of the lighting periods of the sub-frames may change depending on the time. For example, the order of the lighting periods of the subframes may be changed between the first frame and the second frame. Further, the order of the lighting periods of the subframes may be changed depending on the place. For example, the order of the lighting periods of the subframes may be changed between the pixel A and the pixel B. Further, by combining them, the order of the lighting periods of the subframes may change depending on the time and change depending on the place. For example, in FIG. 11, when the number of frames is an odd number, the lighting period of each subframe is set to SF11 = 0.5, SF12 = 2, SF13 = 2, SF21 = 0.5, SF22 = 2, and SF23 = 2. When the number of frames is an even number, SF11 = 2, SF12 = 0.5, SF13 = 2, SF21 = 2, SF22 = 0.5, and SF23 = 2 may be set.

Heretofore, an example in which the number of subframe groups is two (k = 2) has been shown, but the number of subframe groups is not limited to this. For example, FIG. 15 shows an example in which four subframe groups are provided in one frame.

In FIG. 15, one pixel is divided into two subpixels (SP1, SP2) such that the area ratio of each subpixel is 1: 2, and four subframe groups (SFG1) are included in one frame. , SFG2, SFG3, SFG4), and one frame is divided into three subframes (SF1, SF2, SF3) so that the ratio of the lighting period of each subframe is 1: 4: 16. . This example corresponds to m = 2, n = 3, and k = 4.

Here, the area of each sub-pixel is SP1 = 1, SP2 = 2, and the lighting period of each sub-frame is SF1 = 1, SF2 = 4, and SF3 = 16.

In FIG. 15, each of the subframes (SF1 to SF3) divided into three so as to have a lighting period ratio of 1: 4: 16 has a lighting period having a length of 1/4 of the subframe. Further subdividing into four subframes. That is, SF1 having the lighting period 1 is divided into four subframes SF11, SF21, SF31, and SF41 having the lighting period 0.25. Similarly, SF2 having the lighting period 4 is divided into four subframes SF12, SF22, SF32, and SF42 having the lighting period 1, and SF3 having the lighting period 16 is divided into four subframes having the lighting period 4. The process is divided into SF13, SF23, SF33, and SF43. SF11, SF12, and SF13 are in subframe group 1 (SFG1), SF21, SF22, and SF23 are in subframe group 2 (SFG2), and SF31, SF32, and SF33 are in subframe group 3 (SFG3), and SF41, SF42. , SF43 are arranged in subframe group 4 (SFG4), respectively. At this time, the appearance order of SF11, SF12, SF13, and SF21, SF22, SF23, and SF31, SF32, SF33, and SF41, SF42, and SF43 is made the same in subframe group 1 to subframe group 4.

Thus, each of the four subframe groups is composed of three subframes, and the lighting period of each subframe is SF11 = 0.25, SF12 = 1, SF13 = 4, SF21 = 0.25, SF22 = 1, SF23 = 4, SF31 = 0.25, SF32 = 1, SF33 = 4, SF41 = 0.25, SF42 = 1, SF43 = 4.

In FIG. 15, the product of the area of each sub-pixel and the lighting period of each sub-frame is considered as a substantial light emission intensity. For example, in SF11 having a lighting period of 0.25 in subframe group 1, the emission intensity when only subpixel 1 of area 1 is lit is 0.25, and only subpixel 2 of area 2 is lit. The emission intensity is 0.5. Similarly, in SF12 having the lighting period 1, the light emission intensity is 1 when only the sub-pixel 1 is lit, and the light emission intensity is 2 when only the sub-pixel 2 is lit. Similarly, in the SF 13 having the lighting period 4, the emission intensity when only the sub-pixel 1 is lit is 4, and the emission intensity when only the sub-pixel 2 is lit is 8. Note that the emission intensity is similarly determined in the other subframe groups. In this manner, different emission intensity can be created depending on the combination of the area of the sub-pixel and the lighting period of the sub-frame, and 6-bit gradation (64 gradations) is expressed with this emission intensity.

Note that the pseudo contour can be reduced by using a driving method as shown in FIG. For example, in FIG. 15, it is assumed that gradation 31 is displayed in pixel A and gradation 32 is displayed in pixel B. FIG. 16 shows a lighting / non-lighting state of each sub-pixel in each sub-frame in that case. For example, if the line of sight moves, depending on how the line of sight is followed, the gray level is felt 22.5 (= 8 + 8 + 0.5 + 2 + 4) in some cases, and the gray level is 23.75 (= 0.25 + 1 + 4 + 0.5 + 2 + 8 + 8) in some cases. I feel. Originally, the gradation should be seen as 31 and 32, but the gradation appears as 22.5 or 23.75, and a pseudo contour is generated. However, since the gradation shift is smaller than that in the conventional driving method, the pseudo contour is reduced as compared with the conventional driving method.

In this embodiment, the case of 6-bit gradation (64 gradations) has been described as an example, but the number of gradations to be displayed is not limited to this. For example, 8-bit gradation (256 gradations) can be expressed. Examples of this case are shown in FIGS. 17 shows gradations 0 to 63, FIG. 18 shows gradations 64 to 127, FIG. 19 shows gradations 128 to 191 and FIG. 20 shows subpixel selection methods in gradations 192 to 255.

In FIGS. 17 to 20, one pixel is divided into two sub-pixels (SP1, SP2) so that the area ratio of each sub-pixel is 1: 2, and two sub-frames per frame. A group (SFG1, SFG2) is provided, and one frame is divided into four subframes (SF1 to SF4) such that the ratio of the lighting periods of each subframe is 1: 4: 16: 64. This example corresponds to m = 2, n = 4, and k = 2.

Here, the area of each subpixel is SP1 = 1, SP2 = 2, and the lighting period of each subframe is SF1 = 1, SF2 = 4, SF3 = 16, and SF4 = 64.

17 to 20, each of the subframes (SF1 to SF4) divided into four so that the ratio of the lighting period is 1: 4: 16: 64 is half the length of the subframe. Is further divided into two subframes having a lighting period of. That is, SF1 having the lighting period 1 is divided into two subframes SF11 and SF21 having the lighting period 0.5. Similarly, SF2 having the lighting period 4 is divided into two subframes SF12 and SF22 having the lighting period 2, and SF3 having the lighting period 16 is divided into two subframes SF13 and SF23 having the lighting period 8. The SF4 having the lighting period 64 is divided into two subframes SF14 and SF24 having the lighting period 32. Then, SF11, SF12, SF13, and SF14 are arranged in subframe group 1 (SFG1), and SF21, SF22, SF23, and SF24 are arranged in subframe group 2 (SFG2). At this time, the appearance order of SF11, SF12, SF13, SF14 and SF21, SF22, SF23, SF24 is the same in subframe group 1 and subframe group 2.

Thus, each of the two subframe groups is composed of four subframes, and the lighting periods of each subframe are SF11 = 0.5, SF12 = 2, SF13 = 8, Sf14 = 32, SF21 = 0. 5, SF22 = 2, SF23 = 8, and SF24 = 32.

17 to 20, the product of the area of each sub-pixel and the lighting period of each sub-frame is considered as a substantial light emission intensity. For example, in SF11 having a lighting period of 0.5 in subframe group 1, the emission intensity when only subpixel 1 with area 1 is lit is 0.5, and when only subpixel 2 with area 2 is lit. The emission intensity is 1. Similarly, in the SF 12 having the lighting period 2, the light emission intensity when only the sub-pixel 1 is lit is 2, and the light emission intensity when only the sub-pixel 2 is lit is 4. Similarly, in the SF 13 having the lighting period 8, the emission intensity when only the sub-pixel 1 is lit is 8, and the emission intensity when only the sub-pixel 2 is lit is 16. Similarly, in the SF 14 having the lighting period 32, the emission intensity when only the sub-pixel 1 is lit is 32, and the emission intensity when only the sub-pixel 2 is lit is 64. It should be noted that the emission intensity is similarly determined in the subframes constituting the subframe group 2. In this manner, different emission intensity can be created depending on the combination of the area of the sub-pixel and the lighting period of the sub-frame, and the 8-bit gradation (256 gradations) is expressed with this emission intensity.

Note that the number of gradations to be displayed, the ratio and number of subpixels, the ratio and number of subframe lighting periods, the number of subframe groups, and the method of selecting subframes and subpixels according to the gradation described above. The contents such as changing may be used in combination with each other.

(Embodiment 2)
In the first embodiment, the case where the lighting period increases linearly in proportion to the increase in gradation has been described. Therefore, in this embodiment, a case where gamma correction is performed will be described.

The gamma correction refers to a non-linear lighting period that increases as the gradation increases. Even if the luminance increases linearly in proportion, the human eye does not feel that it is brighter in proportion. The higher the brightness, the less the difference in brightness is felt. Therefore, in order for the human eye to feel a difference in brightness, it is necessary to make the lighting period longer, that is, to perform gamma correction as the gradation increases. When the gradation is x and the luminance is y, the relationship between the luminance and the gradation is expressed by the following equation (1).
y = A × x ^γ (1)
However, in the formula (1), A is a constant for normalizing the luminance y to 0 ≦ y ≦ 1. Here, γ which is an index of the gradation x is a parameter indicating the degree of gamma correction.

The simplest method is to enable display with a larger number of bits (number of gradations) than the actual number of bits (number of gradations) to be displayed. For example, when displaying with 6-bit gradation (64 gradations), an 8-bit gradation (256 gradations) is actually displayed. In actual display, 6-bit gradation (64 gradations) is displayed such that the gradation luminance is non-linear. Thereby, gamma correction can be realized.

As an example, a method of selecting a subpixel in each subframe when displaying 6-bit gradation (64 gradations) and performing gamma correction to display 5-bit gradation (32 gradations). It shows in FIG. FIG. 21 shows a selection method of sub-pixels in each sub-frame when displaying a 5-bit gradation (32 gradations) by performing gamma correction so that γ = 2.2 over all gradations. Note that the value of γ = 2.2 is the value that best compensates human visual characteristics, and even when the luminance is high, the most appropriate brightness difference can be felt. In FIG. 21, until the gradation of 5 bits with gamma correction up to 3, the light is actually turned on by the subframe selection method of gradation 0 of 6 bits. Similarly, when the gamma-corrected 5-bit gradation is 4, the display is actually 6-bit gradation 1, and when the gamma-corrected 5-bit gradation is 6, it is actually Is displayed with 6-bit gradation 2. A graph of gradation x and luminance y is shown in FIG. FIG. 22A shows the relationship between gradation x and luminance y at all gradations, and FIG. 22B shows a graph of gradation x and luminance y on the low gradation side. In this way, a correspondence table between the 5-bit gradation after gamma correction and the 6-bit gradation may be created and displayed accordingly. Thereby, gamma correction such that γ = 2.2 can be realized.

However, as can be seen from FIG. 22B, in the case of FIG. 21, gradations 0 to 3, gradations 4 to 5, and gradations 6 to 7 are displayed with the same luminance. become. This is because the difference in luminance cannot be expressed because the number of gradations is not sufficient in 6-bit display. The following two methods can be considered as countermeasures against this.

The first method is to further increase the number of bits that can be displayed. Instead of 6 bits, display should be made with 7 bits or more, preferably 8 bits or more. As a result, smooth display can be performed even in a low gradation region.

The second method is a method in which the relationship of γ = 2.2 is not satisfied in the low gradation region, but the luminance is linearly changed and displayed smoothly. FIG. 23 shows a subframe selection method in this case. In FIG. 23, the gradation up to 17 in 5 bits is the same as the gradation in 6 bits. However, when the gamma-corrected 5-bit gradation is 18, light is actually turned on by a 6-bit gradation 19 subframe selection method. Similarly, when the gradation with 5 bits after gamma correction is 19, it is actually displayed with gradation 21 with 6 bits, and when the gradation with 5 bits after gamma correction is 20, it is actually Is displayed with 6-bit gradation 24. A graph of gradation x and luminance y is shown in FIG. FIG. 24A shows the relationship between gradation x and luminance y in all gradations, and FIG. 24B shows a graph of gradation x and luminance y on the low gradation side. In the low gradation region, the luminance changes linearly. By performing such gamma correction, the low gradation side can be displayed more smoothly.

In other words, the low gradation area can be displayed more smoothly by changing the luminance to be linearly proportional and changing the luminance non-linearly for the other gradation areas. Become.

Note that the correspondence table between the gamma-corrected 5-bit gradation and the 6-bit gradation can be changed as appropriate. Therefore, the degree of gamma correction (that is, the value of γ) can be easily changed by changing the correspondence table. Therefore, it is not limited to γ = 2.2.

Also, how many bits (for example, p bits, where p is an integer) can be displayed, and how many bits (for example, q bits, where q is an integer) after gamma correction is displayed. It is not limited. When displaying with gamma correction, it is desirable to increase the number of bits p as much as possible in order to express gradation smoothly. However, if it is made too large, there will be adverse effects such as an increase in the number of subframes. Therefore, it is desirable that the relationship between the number of bits q and the number of bits p is q + 2 ≦ p ≦ q + 5. As a result, it is possible to realize that the number of subframes does not increase too much while the gradation is expressed smoothly.

Note that the description in this embodiment can be implemented in free combination with the content described in Embodiment 1.

(Embodiment 3)
In the present embodiment, one pixel is divided into two subpixels (SP1, SP2) such that the area ratio of each subpixel is 1: 2, and two subframe groups (one frame) ( SFG1, SFG2) are provided, and one frame is divided into three subframes (SF1, SF2, SF3) such that the ratio of the lighting periods of each subframe is 1: 4: 16 (FIG. 1) The operation of the display device will be described with reference to a timing chart.

Here, the area of each sub-pixel is SP1 = 1, SP2 = 2, and the lighting period of each sub-frame is SF1 = 1, SF2 = 4, and SF3 = 16.

First, FIG. 25 shows a timing chart in the case where a period for writing a signal to a pixel and a lighting period are separated. Note that the timing chart is a diagram illustrating the timing of light emission of pixels in one frame, where the horizontal direction indicates time and the vertical direction indicates a row in which the pixels are arranged.

First, in a signal writing period, a signal for one screen is input to all pixels. During this time, the pixels are not lit. After the signal writing period ends, the lighting period starts and the pixels are lit. The length of the lighting period at that time is 0.5. Next, the next subframe starts, and a signal for one screen is input to all pixels in the signal writing period. During this time, the pixels are not lit. After the signal writing period ends, the lighting period starts and the pixels are lit. The length of the lighting period at that time is two.

By repeating the same, the lighting periods are arranged in the order of 0.5, 2, 8, 0.5, 2, 8.

As described above, the driving method in which the signal writing period and the lighting period are separated from each other is preferably applied to the plasma display. In the case of using for a plasma display, an initialization operation or the like is required. However, it is omitted in FIG. 25 for simplicity.

In addition, this driving method is applied to EL displays (organic EL displays, inorganic EL displays, or displays composed of elements including inorganic and organic), field emission displays, displays using digital micromirror devices (DMD), and the like. It is also suitable to apply.

Here, FIG. 26 illustrates a pixel configuration for realizing a driving method in which a period in which a signal is written to a pixel and a lighting period are separated. FIG. 26 shows a configuration example in which gradation is expressed by providing a plurality of scanning lines, controlling which scanning line is selected, and changing the number of light emitting elements to emit light. In FIG. 26, the area of each sub-pixel is expressed by the number of light-emitting elements. Accordingly, one light-emitting element is described in the sub-pixel 1 and two light-emitting elements are described in the sub-pixel 2.

First, the configuration of the pixel shown in FIG. 26 will be described. The sub-pixel 1 includes a first selection transistor 2611, a first driving transistor 2613, a first storage capacitor 2612, a signal line 2615, a first power supply line 2616, a first scanning line 2617, and a first light emitting element 2614. And a second power supply line 2618.

The first selection transistor 2611 has a gate electrode connected to the first scan line 2617, a first electrode connected to the signal line 2615, and a second electrode connected to the second storage capacitor 2612. And the gate electrode of the first driving transistor 2613. The first storage capacitor 2612 has a first electrode connected to the first power supply line 2616. The first driver transistor 2613 has a first electrode connected to the first power supply line 2616 and a second electrode connected to the first electrode of the first light-emitting element 2614. The first light-emitting element 2614 has a second electrode connected to the second power supply line 2618.

The sub-pixel 2 includes a second selection transistor 2621, a second driving transistor 2623, a second storage capacitor 2622, a signal line 2615, a first power supply line 2616, a second scanning line 2627, and a second light emitting element 2624. And a third power supply line 2628. In addition, since the connection of each element and wiring of the subpixel 2 is the same as that of the subpixel 1, description thereof is omitted.

Next, the operation of the pixel shown in FIG. 26 will be described. Here, the operation of the sub-pixel 1 will be described. By increasing the potential of the first scan line 2617, the first scan line 2617 is selected, the first selection transistor 2611 is turned on, and a signal is input from the signal line 2615 to the first storage capacitor 2612. To do. Then, the current of the first driving transistor 2613 is controlled in accordance with the signal, and current flows from the first power supply line 2616 to the first light-emitting element 2614. Note that the operation of the sub-pixel 2 is the same as the operation of the sub-pixel 1, and thus the description thereof is omitted.

At this time, the number of light emitting elements that emit light varies depending on which scanning line is selected from the first and second scanning lines. For example, when only the first scanning line 2617 is selected, only the first selection transistor 2611 is turned on and the current of only the first driving transistor 2613 is controlled, so that only the first light-emitting element 2614 is controlled. Emits light. That is, only the sub-pixel 1 emits light. On the other hand, when only the second scanning line 2627 is selected, only the second selection transistor 2621 is turned on, and the current of only the second driving transistor 2623 is controlled. Therefore, only the second light-emitting element 2624 is controlled. Emits light. That is, only the sub-pixel 2 emits light. When both the first and second scanning lines 2617 and 2627 are selected, the first and second selection transistors 2611 and 2621 are turned on, and the currents of the first and second drive transistors 2613 and 2623 are controlled. Therefore, both the first and second light emitting elements 2614 and 2624 emit light. That is, both the subpixel 1 and the subpixel 2 emit light.

Note that in the signal writing period, voltage is not applied to the light-emitting elements 2614 and 2624 by controlling the potentials of the first power supply line 2616 and the second and third power supply lines 2618 and 2628. For example, the second and third power supply lines 2618 and 2628 may be floated. Alternatively, the potentials of the second and third power supply lines 2618 and 2628 may be lower than the potential of the signal line 2615 by the threshold voltage of the first and second driving transistors 2613 and 2623. Further, the potentials of the second and third power supply lines 2618 and 2628 may be approximately the same as or higher than the potential of the signal line 2615. As a result, the light-emitting elements 2614 and 2624 can be prevented from being lit during the signal writing period.

Note that the second power supply line 2618 and the third power supply line 2628 may be separate wirings or common wirings.

Note that in the case where one pixel is divided into m (m is an integer of m ≧ 2) sub-pixels, in order to realize the pixel configuration illustrated in FIG. The selection transistor included in at least one sub-pixel among the m sub-pixels may be connected to a scanning line different from the selection transistor included in the other sub-pixels.

FIG. 26 shows a configuration example in which gradation is expressed by providing a plurality of scanning lines, controlling which scanning line is selected, and changing the number of light emitting elements to emit light. It is also possible to express gradation by providing a plurality of lines and controlling what signals are input to which signal lines and changing the number of light emitting elements to emit light. A configuration example in this case is shown in FIG.

First, the configuration of the pixel shown in FIG. 27 will be described. The sub-pixel 1 includes a first selection transistor 2711, a first drive transistor 2713, a first storage capacitor 2712, a first signal line 2715, a first power supply line 2716, a scanning line 2717, and a first light emitting element 2714. And a second power supply line 2718.

The first selection transistor 2711 has a gate electrode connected to the scan line 2717, a first electrode connected to the first signal line 2715, and a second electrode connected to the second storage capacitor 2712. And the gate electrode of the first driving transistor 2713. The first storage capacitor 2712 has a first electrode connected to the first power supply line 2716. The first driving transistor 2713 has a first electrode connected to the first power supply line 2716 and a second electrode connected to the first electrode of the first light-emitting element 2714. The first light emitting element 2714 has a second electrode connected to the second power supply line 2718.

The sub-pixel 2 includes a second selection transistor 2721, a second driving transistor 2723, a second storage capacitor 2722, a second signal line 2725, a first power supply line 2716, a scanning line 2717, and a second light emitting element 2724. And a third power supply line 2728. Since the connection of each element and wiring of the sub-pixel 2 is the same as that of the sub-pixel 1, description thereof is omitted.

Next, the operation of the pixel shown in FIG. 27 will be described. Here, the operation of the sub-pixel 1 will be described. By increasing the potential of the scan line 2717, the scan line 2717 is selected, the first selection transistor 2711 is turned on, and a video signal is input from the first signal line 2715 to the first storage capacitor 2712. Then, the current of the first driving transistor 2713 is controlled in accordance with the video signal, and current flows from the first power supply line 2716 to the first light emitting element 2714. Note that the operation of the sub-pixel 2 is the same as the operation of the sub-pixel 1, and thus the description thereof is omitted.

At this time, the number of light emitting elements that emit light changes depending on signals input to the first and second signal lines. For example, when a low signal is input to the first signal line 2715 and a high signal is input to the second signal line 2725, only the first driving transistor 2713 is turned on, so that the first light-emitting element 2714 Only emits light. That is, only the sub-pixel 1 emits light. On the other hand, when a high signal is input to the first signal line 2715 and a low signal is input to the second signal line 2725, only the second driving transistor 2723 is turned on, so that the second light-emitting element 2724 Only emits light. That is, only the sub-pixel 2 emits light. Further, when a Low signal is input to the first and second signal lines 2715 and 2725, the first and second driving transistors 2713 and 2723 are both turned on, and thus the first and second light emitting elements 2714, 2724 emits light. That is, both the subpixel 1 and the subpixel 2 emit light.

Here, by controlling the voltage of the video signal input to the first and second signal lines 2715 and 2725, the current flowing through the first and second light-emitting elements 2714 and 2724 can be controlled. As a result, the luminance of each sub-pixel can be changed, and gradation can be expressed. For example, when the sub-pixel 1 having the area 1 is lit in the SF 11 having the lighting period 0.5, the emission intensity is 0.5, but the magnitude of the voltage of the video signal input to the first signal line 2715 The luminance of the first light emitting element 2714 can be changed. Accordingly, it is possible to express more gradations than the number of gradations that can be expressed using the area of the subpixel and the length of the lighting period of the subframe. In addition to using the area of the sub-pixel and the length of the lighting period of the sub-frame, the same number of gradations can be expressed by expressing the gradation by the voltage applied to the light emitting element included in each sub-pixel. The number of sub-pixels and the number of sub-frames required for the above can be reduced. Thereby, the aperture ratio of the pixel portion can be increased. In addition, the duty ratio can be improved and the luminance can be increased. In addition, the voltage applied to the light emitting element can be reduced by improving the duty ratio. Therefore, power consumption can be reduced and deterioration of the light emitting element can be reduced.

Note that in the case where one pixel is divided into m sub-pixels (m is an integer of m ≧ 2), in order to realize the pixel configuration illustrated in FIG. The selection transistor included in at least one of the m subpixels may be connected to a signal line different from the selection transistors included in the other subpixels.

In FIGS. 26 and 27, a common power supply line (first power supply lines 2616 and 2716) is connected to each subpixel. However, a plurality of power supply lines are provided, and a power supply voltage applied to the subpixels is changed. Also good. For example, FIG. 28 shows a configuration example in the case of using two power supply lines in FIG.

First, the configuration of the pixel shown in FIG. 28 will be described. The sub-pixel 1 includes a first selection transistor 2811, a first driving transistor 2813, a first storage capacitor 2812, a signal line 2815, a first power supply line 2816, a first scanning line 2817, and a first light emitting element 2814. And a second power supply line 2818.

The first selection transistor 2811 has a gate electrode connected to the first scan line 2817, a first electrode connected to the signal line 2815, and a second electrode connected to the second storage capacitor 2812. And the gate electrode of the first driving transistor 2813. The first storage capacitor 2812 has a first electrode connected to the first power supply line 2816. The first driver transistor 2813 has a first electrode connected to the first power supply line 2816 and a second electrode connected to the first electrode of the first light-emitting element 2814. The first light-emitting element 2814 has a second electrode connected to the second power supply line 2818.

The sub-pixel 2 includes a second selection transistor 2821, a second driving transistor 2823, a second storage capacitor 2822, a signal line 2815, a second scanning line 2827, a second light emitting element 2824, and a third power supply line 2828. And a fourth power supply line 2836. In addition, since the connection of each element and wiring of the subpixel 2 is the same as that of the subpixel 1, description thereof is omitted.

Here, by controlling the voltage applied to the first and fourth power supply lines 2816 and 2836, the current flowing through the first and second light emitting elements 2814 and 2824 can be controlled. As a result, the luminance of each sub-pixel can be changed, and gradation can be expressed. For example, when the sub-pixel 1 having the area 1 is lit in the SF 11 having the lighting period 0.5, the emission intensity is 0.5, but the magnitude of the voltage applied to the first power supply line 2816 is changed. Thus, the luminance of the first light-emitting element 2814 can be changed. Accordingly, it is possible to express more gradations than the number of gradations that can be expressed using the area of the subpixel and the length of the lighting period of the subframe. Further, in addition to the area of the sub-pixel and the length of the lighting period of the sub-frame, the gradation is expressed by the voltage applied to the light emitting element included in each sub-pixel, so that it is necessary to express the same number of gradations. The number of subpixels and the number of subframes can be further reduced. Thereby, the aperture ratio of the pixel portion can be increased. In addition, the duty ratio can be improved and the luminance can be increased. In addition, the voltage applied to the light emitting element can be reduced by improving the duty ratio. Therefore, power consumption can be reduced and deterioration of the light emitting element can be reduced.

Note that when one pixel is divided into m (m is an integer of m ≧ 2) sub-pixels, in order to realize the pixel configuration shown in FIG. The number of power supply lines corresponding to the first power supply line is 2 or more and m or less, and a drive transistor included in at least one subpixel of the m subpixels is different from a drive transistor included in other subpixels. What is necessary is just to connect with the said power supply line.

Next, FIG. 29 shows a timing chart in the case where the period for writing a signal to the pixel and the lighting period are not separated. When a signal writing operation is performed in each row, the lighting period starts immediately.

In a certain row, a signal is written, and after a predetermined lighting period ends, a signal writing operation in the next subframe is started. By repeating signal writing, the length of the lighting period is in the order of 0.5, 2, 8, 0.5, 2, 8.

This makes it possible to arrange many subframes in one frame even if the signal writing operation is slow.

Such a driving method is preferably applied to a plasma display. Note that in the case of using for a plasma display, an initialization operation or the like is necessary, but in FIG. 29, it is omitted for simplicity.

This driving method is also preferably applied to an EL display, a field emission display, a display using a digital micromirror device (DMD), and the like.

Here, FIG. 30 illustrates a pixel configuration for realizing a driving method in which a period for writing a signal to a pixel and a lighting period are not separated. In order to realize such a driving method, it must be possible to select a plurality of rows at the same time.

First, the configuration of the pixel shown in FIG. 30 will be described. The sub-pixel 1 includes a first selection transistor 3011, a second selection transistor 3021, a first driving transistor 3013, a first storage capacitor 3012, a first signal line 3015, a second signal line 3025, a first A power supply line 3016, a first scan line 3017, a second scan line 3027, a first light-emitting element 3014, and a second power supply line 3018 are included.

The first selection transistor 3011 has a gate electrode connected to the first scan line 3017, a first electrode connected to the first signal line 3015, and a second electrode connected to the second selection transistor 3021. Are connected to the second electrode of the first storage capacitor 3012 and the gate electrode of the first driving transistor 3013. The second selection transistor 3021 has a gate electrode connected to the second scan line 3027 and a first electrode connected to the second signal line 3025. The first storage capacitor 3012 has a first electrode connected to the first power supply line 3016. The first driving transistor 3013 has a first electrode connected to the first power supply line 3016 and a second electrode connected to the first electrode of the first light-emitting element 3014. The first light-emitting element 3014 has a second electrode connected to the second power supply line 3018.

The sub-pixel 2 includes a third selection transistor 3031, a fourth selection transistor 3041, a second drive transistor 3023, a second storage capacitor 3022, a first signal line 3015, a second signal line 3025, A power supply line 3016, a third scan line 3037, a fourth scan line 3047, a second light emitting element 3024, and a third power supply line 3028 are included. Since the connection of each element and wiring of the sub-pixel 2 is the same as that of the sub-pixel 1, description thereof is omitted.

Next, the operation of the pixel shown in FIG. 30 will be described. Here, the operation of the sub-pixel 1 will be described. By increasing the potential of the first scanning line 3017, the first scanning line 3017 is selected, the first selection transistor 3011 is turned on, and a signal is transmitted from the first signal line 3015 to the first storage capacitor. Input to 3012. Then, the current of the first driving transistor 3013 is controlled in accordance with the signal, and current flows from the first power supply line 3016 to the first light emitting element 3014. Similarly, by raising the potential of the second scanning line 3027, the second scanning line 3027 is selected, the second selection transistor 3021 is turned on, and a signal is sent from the second signal line 3025 to the first signal line. Is input to the storage capacitor 3012. Then, the current of the first driving transistor 3013 is controlled in accordance with the signal, and current flows from the first power supply line 3016 to the first light emitting element 3014. Note that the operation of the sub-pixel 2 is the same as the operation of the sub-pixel 1, and thus the description thereof is omitted.

The first scanning line 3017 and the second scanning line 3027 can be controlled separately. Similarly, the third scanning line 3037 and the fourth scanning line 3047 can be controlled separately. In addition, the first signal line 3015 and the second signal line 3025 can be controlled separately. Therefore, it is possible to input signals to the pixels for two rows at the same time, so that the driving method as shown in FIG. 29 can be realized.

Note that the driving method shown in FIG. 29 can be realized by using the circuit shown in FIG. At this time, a method of dividing one gate selection period into a plurality of subgate selection periods is used. First, as shown in FIG. 31, one gate selection period is divided into a plurality of (two in FIG. 31) sub-gate selection periods. Then, by raising the potential of each scanning line within each sub-gate selection period, each scanning line is selected, and a corresponding signal is input to the signal line 2615 at that time. For example, in one gate selection period, the first half selects the i-th row and the second half selects the j-th row. Then, it is possible to operate as if two rows are selected at the same time in one gate selection period.

Details of such a driving method are described in, for example, Japanese Patent Application Laid-Open No. 2001-324958, and the contents thereof can be applied in combination with the present application.

Note that although FIG. 30 illustrates an example in which a plurality of scanning lines are provided, a single signal line may be provided and the first electrodes of the first to fourth selection transistors may be connected to the signal line. A plurality of power supply lines corresponding to the first power supply line in FIG. 30 may be provided.

Next, FIG. 32 shows a timing chart in the case of performing an operation of erasing the pixel signal. In each row, a signal writing operation is performed, and the pixel signal is erased before the next signal writing operation is performed. In this way, the length of the lighting period can be easily controlled.

In a certain row, a signal is written, and after a predetermined lighting period ends, a signal writing operation in the next subframe is started. If the lighting period is short, a signal erasing operation is performed to forcibly turn off the light. By repeating this, the lighting periods are arranged in the order of 0.5, 2, 8, 0.5, 2, 8.

In FIG. 32, the signal erasing operation is performed when the lighting periods are 0.5 and 2, but the present invention is not limited to this. The erase operation may be performed in other lighting periods.

This makes it possible to arrange many subframes in one frame even if the signal writing operation is slow. Further, when performing an erasing operation, it is not necessary to acquire erasing data in the same manner as a video signal, so that the driving frequency of the source driver can be reduced.

Such a driving method is preferably applied to a plasma display. In the case of using for a plasma display, an initialization operation or the like is required, but in FIG. 32, it is omitted for simplicity.

This driving method is also preferably applied to an EL display, a field emission display, a display using a digital micromirror device (DMD), and the like.

Here, FIG. 33 shows a pixel configuration in the case of performing an erasing operation. The pixel shown in FIG. 33 is a configuration example in the case where an erasing operation is performed using an erasing transistor.

First, the configuration of the pixel shown in FIG. 33 will be described. The sub-pixel 1 includes a first selection transistor 3311, a first driving transistor 3313, a first erasing transistor 3319, a first storage capacitor 3312, a signal line 3315, a first power supply line 3316, and a first scanning line 3317. , A second scanning line 3327, a first light emitting element 3314, and a second power supply line 3318.

The first selection transistor 3311 has a gate electrode connected to the first scanning line 3317, a first electrode connected to the signal line 3315, and a second electrode connected to the second erase transistor 3319. , The second electrode of the first storage capacitor 3312, and the gate electrode of the first driving transistor 3313. The first erase transistor 3319 has a gate electrode connected to the second scan line 3327 and a first electrode connected to the first power supply line 3316. The first storage capacitor 3312 has a first electrode connected to the first power supply line 3316. The first driving transistor 3313 has a first electrode connected to the first power supply line 3316 and a second electrode connected to the first electrode of the first light-emitting element 3314. The first light-emitting element 3314 has a second electrode connected to the second power supply line 3318.

The sub-pixel 2 includes a second selection transistor 3321, a second driving transistor 3323, a second erasing transistor 3329, a second storage capacitor 3322, a signal line 3315, a first power supply line 3316, and a third scanning line 3337. , A fourth scanning line 3347, a second light emitting element 3324, and a third power supply line 3328. Since the connection of each element and wiring of the sub-pixel 2 is the same as that of the sub-pixel 1, description thereof is omitted.

Next, the operation of the pixel shown in FIG. 33 will be described. Here, the operation of the sub-pixel 1 will be described. By increasing the potential of the first scanning line 3317, the first scanning line 3317 is selected, the first selection transistor 3311 is turned on, and a signal is input from the signal line 3315 to the first storage capacitor 3312. To do. Then, the current of the first driving transistor 3313 is controlled in accordance with the signal, and current flows from the first power supply line 3316 to the first light-emitting element 3314.

When the signal is to be erased, the potential of the second scan line 3327 is increased to select the second scan line 3327, the first erase transistor 3319 is turned on, and the first drive transistor 3313 is turned on. Try to turn it off. Then, no current flows through the first light emitting element 3314. As a result, a non-lighting period can be created and the length of the lighting period can be freely controlled.

Note that the operation of the sub-pixel 2 is the same as the operation of the sub-pixel 1, and thus the description thereof is omitted.

In FIG. 33, the erase transistors 3319 and 3329 are used, but another method can be used. This is because it is only necessary to forcibly create a non-lighting period, and it is sufficient to prevent current from being supplied to the light emitting elements 3314 and 3324. Therefore, a switch is arranged somewhere along a path through which current flows from the first power supply line 3316 to the second and third power supply lines 3318 and 3328 through the light emitting elements 3314 and 3324, and the switch is turned on. -Control off and create a non-lighting period. Alternatively, the gate-source voltage of the driving transistors 3313 and 3323 may be controlled so that the driving transistor is forcibly turned off.

Here, FIG. 34 shows an example of a pixel configuration when the driving transistor is forcibly turned off. The pixel shown in FIG. 34 is a configuration example when the driving transistor is forcibly turned off using an erasing diode.

First, the configuration of the pixel shown in FIG. 34 will be described. The sub-pixel 1 includes a first selection transistor 3411, a first driving transistor 3413, a first storage capacitor 3412, a signal line 3415, a first power supply line 3416, a first scanning line 3417, and a second scanning line 3427. , A first light emitting element 3414, a second power supply line 3418, and a first erasing diode 3419.

The first selection transistor 3411 has a gate electrode connected to the first scanning line 3417, a first electrode connected to the signal line 3415, and a second electrode connected to the second erasing diode 3419. , The second electrode of the first storage capacitor 3412, and the gate electrode of the first driving transistor 3413. The first erasing diode 3419 has a first electrode connected to the second scanning line 3427. The first storage capacitor 3412 has a first electrode connected to the first power supply line 3416. The first driver transistor 3413 has a first electrode connected to the first power supply line 3416 and a second electrode connected to the first electrode of the first light-emitting element 3414. The first light-emitting element 3414 has a second electrode connected to the second power supply line 3418.

The sub-pixel 2 includes a second selection transistor 3421, a second driving transistor 3423, a second storage capacitor 3422, a signal line 3415, a first power supply line 3416, a third scanning line 3437, and a fourth scanning line 3447. , A second light emitting element 3424, a third power supply line 3428, and a second erasing diode 3429. Since the connection of each element and wiring of the sub-pixel 2 is the same as that of the sub-pixel 1, description thereof is omitted.

Next, the operation of the pixel shown in FIG. 34 will be described. Here, the operation of the sub-pixel 1 will be described. By increasing the potential of the first scan line 3417, the first scan line 3417 is selected, the first selection transistor 3411 is turned on, and a signal is input from the signal line 3415 to the first storage capacitor 3412. To do. Then, according to the signal, the current of the first driving transistor 3413 is controlled, and current flows from the first power supply line 3416 to the first light-emitting element 3414.

When the signal is to be erased, the potential of the second scanning line 3427 is increased to select the second scanning line 3427, the first erasing diode 3419 is turned on, and the second scanning line 3427 is turned on. A current is allowed to flow to the gate electrode of one driving transistor 3413. As a result, the first driving transistor 3413 is turned off. Then, current does not flow from the first power supply line 3416 to the first light emitting element 3414. As a result, a non-lighting period can be created and the length of the lighting period can be freely controlled.

When the signal is to be held, the second scanning line 3427 is not selected by lowering the potential of the second scanning line 3427. Then, the first erasing diode 3419 is turned off, so that the gate potential of the first driving transistor 3413 is held.

Note that the operation of the sub-pixel 2 is the same as the operation of the sub-pixel 1, and thus the description thereof is omitted.

Note that the erasing diodes 3419 and 3429 may be anything as long as they are rectifying elements. A PN-type diode, a PIN-type diode, a Schottky diode, or a Zener-type diode may be used.

Alternatively, a transistor may be used in a diode connection (a gate and a drain are connected). A circuit diagram in that case is shown in FIG. As the first and second erasing diodes 3419 and 3429, diode-connected transistors 3519 and 3529 are used. Here, an N-channel type is used, but the present invention is not limited to this. A P-channel type may be used.

As another circuit, the driving method shown in FIG. 32 can be realized by using the circuit shown in FIG. In this case, a method of dividing one gate selection period into a plurality of subgate selection periods is used. First, as shown in FIG. 31, one gate selection period is divided into a plurality of (two in FIG. 31) sub-gate selection periods. Then, by increasing the potential of each scanning line within each sub-gate selection period, each scanning line is selected, and a signal (video signal and signal for erasing) corresponding to that time is input to the signal line 2615. To do. For example, in one gate selection period, the first half selects the i-th row and the second half selects the j-th row. When the i-th row is selected, a video signal to be input to the i-th row pixel is input to the signal line 2615. On the other hand, when the j-th row is selected, a signal that turns off the driving transistor of the pixel in the j-th row is input to the signal line 2615. Then, it is possible to operate as if two rows are selected at the same time in one gate selection period.

Details of such a driving method are described in, for example, Japanese Patent Application Laid-Open No. 2001-324958, and the contents thereof can be applied in combination with the present application.

33, FIG. 34, and FIG. 35 show an example in which a plurality of scanning lines are provided. However, a plurality of signal lines may be provided, or a power supply line corresponding to the first power supply line in FIGS. A plurality of may be provided.

Note that the timing chart, the pixel configuration, and the driving method shown in this embodiment mode are examples, and the present invention is not limited to this. The present invention can be applied to various timing charts, pixel configurations, and driving methods.

Note that although a lighting period, a signal writing period, and a non-lighting period are arranged in one frame in this embodiment mode, the present invention is not limited to this. Other operation periods may be arranged. For example, a period in which the voltage applied to the light-emitting element has a polarity opposite to that of the normal voltage, that is, a so-called reverse bias period may be provided. By providing the reverse bias period, the reliability of the light emitting element may be improved.

Note that in the pixel structure described in this embodiment, the polarity of the transistor is not limited thereto.

Note that in the pixel configuration shown in this embodiment, the storage capacitor can be omitted by substituting the parasitic capacitance of the transistor.

Note that the contents described in this embodiment can be implemented in free combination with the contents described in Embodiments 1 and 2.

(Embodiment 4)
In this embodiment mode, a pixel layout in the display device of the present invention will be described. As an example, FIG. 36 shows a layout diagram of the circuit diagram shown in FIG. Note that the circuit diagram and the layout diagram are not limited to FIGS. 26 and 36.

In FIG. 36, first and second selection transistors 3611 and 3621, first and second driving transistors 3613 and 3623, first and second storage capacitors 3612 and 3622, and electrodes of the first and second light emitting elements. 3614 and 3624, a signal line 3615, a power supply line 3616, and first and second scanning lines 3617 and 3627 are provided. For the subpixel 1 (SP1), the source electrode and the drain electrode of the first selection transistor 3611 are connected to the signal line 3615 and the gate electrode of the first driving transistor 3613, respectively. A gate electrode of the first selection transistor 3611 is connected to the first scanning line 3617. A source electrode and a drain electrode of the first driving transistor 3613 are connected to the power supply line 3616 and the electrode 3614 of the first light-emitting element, respectively. The first storage capacitor 3612 is connected between the gate electrode of the first driving transistor 3613 and the power supply line 3606. A similar connection relationship is established for the sub-pixel 2 (SP2). The area ratio of the electrodes 3614 and 3624 of the first and second light emitting elements is 1: 2.

The signal line 3615 and the power supply line 3616 are formed by the second wiring, and the first and second scanning lines 3607 and 3617 are formed by the first wiring.

FIG. 37 shows an example of the pixel layout when the area ratio of the sub-pixels is 1: 2: 4. In FIG. 37, the first, second, and third selection transistors 3711, 3721, and 3731, the first, second, and third drive transistors 3713, 3723, and 3733, and the first, second, and third storage capacitors 3712 are illustrated. , 3722, 3732, electrodes 3714, 3724, 3734, signal lines 3715, power lines 3716, first, second and third scanning lines 3717, 3727, 3737 of the first, second and third light emitting elements. Has been. The area ratio of the electrodes 3714, 3724, and 3734 of the first, second, and third light emitting elements is 1: 2: 4.

When the transistor has a top gate structure, a film is formed in the order of a substrate, a semiconductor layer, a gate insulating film, a first wiring, an interlayer insulating film, and a second wiring. In the case where the transistor has a bottom gate structure, a film is formed in the order of a substrate, a first wiring, a gate insulating film, a semiconductor layer, an interlayer insulating film, and a second wiring.

In this embodiment, the selection transistor and the driving transistor are described with a single gate structure, but the structure of these transistors can take various forms. For example, a multi-gate structure having two or more gate electrodes may be used. When the multi-gate structure is used, the channel regions are connected in series, so that a plurality of transistors are connected in series. FIG. 38 is a layout diagram in which the driving transistors 3613 and 3623 have a multi-gate structure in FIG. In FIG. 38, the driving transistors 3813 and 3823 have a multi-gate structure. The multi-gate structure reduces the off current, improves the breakdown voltage of the transistor to improve reliability, and even when the drain-source voltage changes when operating in the saturation region. The inter-current does not change so much, and a flat characteristic can be obtained. Alternatively, a structure in which gate electrodes are arranged above and below the channel may be employed. By adopting a structure in which gate electrodes are arranged above and below the channel, the channel region increases, so that the current value can be increased, and a depletion layer can be easily formed to improve the S value. When gate electrodes are provided above and below a channel, a structure in which a plurality of transistors are connected in parallel is obtained. Further, a structure in which a gate electrode is disposed above a channel, a structure in which a gate electrode is disposed below a channel, a normal staggered structure, or an inverted staggered structure may be employed. The channel region may be divided into a plurality of regions, may be connected in parallel, or may be connected in series. In addition, a source electrode or a drain electrode may overlap with the channel (or a part thereof). By using a structure in which a source electrode or a drain electrode overlaps with a channel (or part of it), it is possible to prevent electric charges from being accumulated in part of the channel and unstable operation. There may also be an LDD region. By providing an LDD region, the off-current can be reduced, the breakdown voltage of the transistor can be improved to improve reliability, or the drain-source voltage can be changed even when the drain-source voltage changes when operating in the saturation region. The current does not change so much, and a flat characteristic can be obtained.

The wiring and electrodes are made of aluminum (Al), tantalum (Ta), titanium (Ti), molybdenum (Mo), tungsten (W), neodymium (Nd), chromium (Cr), nickel (Ni), platinum (Pt ), Gold (Au), silver (Ag), copper (Cu), magnesium (Mg), scandium (Sc), cobalt (Co), zinc (Zn), niobium (Nb), silicon (Si), phosphorus (P ), Boron (B), arsenic (As), gallium (Ga), indium (In), tin (Sn), oxygen (O), or one or more elements selected from the group consisting of A compound or alloy material containing one or more elements selected from the group (for example, indium tin oxide (ITO), indium zinc oxide (IZO), indium tin oxide to which silicon oxide is added (ITS) ), Zinc oxide (ZnO), aluminum neodymium (Al-Nd), magnesium silver (Mg-Ag), etc.), or is formed with a like material that combines these compounds. Alternatively, a silicon compound (silicide) (for example, aluminum silicon, molybdenum silicon, nickel silicide, or the like) or a nitrogen compound (for example, titanium nitride, tantalum nitride, molybdenum nitride, or the like) is formed. . Note that silicon (Si) may contain a large amount of N-type impurities (such as phosphorus) and P-type impurities (such as boron). By containing these impurities, the conductivity is improved or the same behavior as that of a normal conductor is obtained, so that it can be easily used as a wiring or an electrode. Silicon may be single crystal, polycrystalline (polysilicon), or amorphous (amorphous silicon). The resistance can be reduced by using single crystal silicon or polycrystalline silicon. By using amorphous silicon, it can be manufactured by a simple manufacturing process. Note that since aluminum and silver have high conductivity, signal delay can be reduced and etching is easy, so that patterning is easy and fine processing can be performed. Note that copper has high conductivity, so that signal delay can be reduced. Molybdenum can be manufactured without causing problems such as defective materials even when it comes into contact with oxide semiconductors such as ITO and IZO, and silicon, and is easy to pattern and etch, and has high heat resistance. Therefore, it is desirable. Titanium is desirable because it can be manufactured without causing problems such as failure of the material even when it comes into contact with an oxide semiconductor such as ITO or IZO or silicon, and has high heat resistance. Tungsten is desirable because of its high heat resistance. Neodymium is desirable because of its high heat resistance. In particular, an alloy of neodymium and aluminum is preferable because the heat resistance is improved and aluminum does not easily cause hillocks. Silicon is preferable because it can be formed at the same time as a semiconductor layer included in the transistor and has high heat resistance. Note that indium tin oxide (ITO), indium zinc oxide (IZO), indium tin oxide added with silicon oxide (ITSO), zinc oxide (ZnO), and silicon (Si) have translucency. Therefore, it is desirable because it can be used for a portion that transmits light. For example, it can be used as a pixel electrode or a common electrode.

In addition, these may form wiring and an electrode with a single layer, and may have a multilayer structure. By forming with a single layer structure, the manufacturing process can be simplified, the number of process days can be reduced, and the cost can be reduced. In addition, by using a multilayer structure, the merit of each material can be utilized, the demerit can be reduced, and high performance wiring and electrodes can be formed. For example, by including a low-resistance material (such as aluminum) in the multilayer structure, the resistance of the wiring can be reduced. In addition, if a material having high heat resistance is included, for example, a wiring or electrode as a whole can be obtained by forming a laminated structure in which a material having low merit is sandwiched between materials having another merit. As a result, the heat resistance can be increased. For example, it is preferable to form a layered structure in which a layer containing aluminum is sandwiched between layers containing molybdenum or titanium. In addition, if there is a portion that is in direct contact with a wiring or electrode of another material, it may adversely affect each other. For example, one material may be contained in the other material, changing its properties and failing to fulfill its original purpose, or producing a problem and making it impossible to manufacture normally. is there. In such a case, the problem can be solved by sandwiching or covering one layer with another layer. For example, when indium tin oxide (ITO) and aluminum are in contact with each other, it is desirable to sandwich titanium or molybdenum between them. In addition, when silicon and aluminum are to be brought into contact with each other, it is desirable to sandwich titanium or molybdenum between them.

Note that, in each of R (red), G (green), and B (blue) pixels, the total light emission area of the pixels may be changed. An embodiment in this case is shown in FIG.

In the example shown in FIG. 39, each pixel is composed of two sub-pixels. In addition, a signal line 3915, a first power supply line 3916, and first and second scanning lines 3917 and 3927 are provided. In FIG. 39, the size of the area of each sub-pixel corresponds to the light-emitting area of each sub-pixel.

In FIG. 39, G, R, and B are in descending order of the total light emission area of the pixel. Thereby, an appropriate color balance of R, G, and B can be realized, and higher-definition color display can be achieved. In addition, power consumption can be reduced and the lifetime of the light-emitting element can be extended.

In the R, G, B, and W (white) configurations, the number of RGB subpixels may be different from the number of W subpixels. An embodiment in this case is shown in FIG.

In the example shown in FIG. 40, the RGB portion is divided into two subpixels, and the W portion is divided into three subpixels. In addition, a signal line 4015, a first power supply line 4016, a first scanning line 4017, a second scanning line 4027, and a third scanning line 4037 are provided.

In FIG. 40, the RGB portion is divided into two subpixels, and the W portion is divided into three subpixels. Thereby, higher-definition white display is possible.

Note that the contents described in this embodiment can be implemented by being freely combined with the contents described in Embodiments 1 to 3.

(Embodiment 5)
In this embodiment, the configuration and operation of a signal line driver circuit, a scan line driver circuit, and the like in a display device will be described. In the present embodiment, a case where one pixel is divided into two sub-pixels (SP1, SP2) will be described as an example.

For example, consider a case where a pixel configuration is used in which a plurality of scanning lines are provided. First, in the case where the period for writing a signal to the pixel and the period for lighting are separated, the display device includes a pixel portion 4101, first and second scan line driver circuits 4102, as shown in FIG. 4103 and a signal line driver circuit 4104. The pixel configuration in this case is as shown in FIG. 26 as an example.

First, the scanning line driving circuit will be described. The first and second scan line driver circuits 4102 and 4103 sequentially output selection signals to the pixel portion 4101. An example of the structure of the first and second scan line driver circuits 4102 and 4103 is illustrated in FIG. The scan line driver circuit includes a shift register 4105, an amplifier circuit 4106, and the like.

Next, operations of the first and second scan line driver circuits 4102 and 4103 illustrated in FIG. 41B will be briefly described. A clock signal (G-CLK), a start pulse (G-SP), and a clock inversion signal (G-CLKB) are input to the shift register 4105, and sampling pulses are sequentially output according to the timing of these signals. The output sampling pulse is amplified by the amplifier circuit 4106 and input to the pixel portion 4101 from each scanning line.

Note that the amplifier circuit 4106 may have a buffer circuit or a level shifter circuit. In addition to the shift register 4105 and the amplifier circuit 4106, a pulse width control circuit or the like may be provided in the scan line driver circuit.

Here, the first scanning line driving circuit 4102 is a driving circuit for sequentially outputting a selection signal to the first scanning line 4111 connected to the sub-pixel 1 (SP1), and the second scanning line driving circuit. Reference numeral 4103 denotes a driving circuit for sequentially outputting a selection signal to the second scanning line 4112 connected to the sub-pixel 2 (SP2). In general, when one pixel is divided into m (m is an integer of m ≧ 2) sub-pixels, m scanning line driver circuits may be provided.

Next, the signal line driver circuit will be described. The signal line driver circuit 4104 sequentially outputs video signals to the pixel portion 4101 through the signal line 4113. The pixel portion 4101 displays an image by controlling the state of light according to the video signal. A video signal input from the signal line driver circuit 4104 to the pixel portion 4101 is often a voltage. That is, the state of the light-emitting elements and the elements that control the light-emitting elements arranged in each pixel changes depending on the video signal (voltage) input from the signal line driver circuit 4104. Examples of the light emitting element arranged in the pixel include an EL element, an element used in an FED (field emission display), a liquid crystal, a DMD (digital micromirror device), and the like.

An example of a structure of the signal line driver circuit 4104 is illustrated in FIG. The signal line driver circuit 4104 includes a shift register 4107, a first latch circuit (LAT1) 4108, a second latch circuit (LAT2) 4109, an amplifier circuit 4110, and the like. Note that the amplifier circuit 4110 may have a buffer circuit, a level shifter circuit, a circuit having a function of converting a digital signal into analog, or gamma correction. You may have a circuit which has a function to perform.

Further, the pixel has a light emitting element such as an EL element. A circuit for outputting a current (video signal) to the light emitting element, that is, a current source circuit may be provided.

Next, the operation of the signal line driver circuit 4104 will be briefly described. The shift register 4107 receives a clock signal (S-CLK), a start pulse (S-SP), and a clock inversion signal (S-CLKB), and sequentially outputs sampling pulses according to the timing of these signals.

The sampling pulse output from the shift register 4107 is input to the first latch circuit (LAT1) 4108. A video signal is input to the first latch circuit (LAT1) 4108 from the video signal line 4121, and the video signal is held in each column in accordance with the timing at which the sampling pulse is input.

When the first latch circuit (LAT1) 4108 completes holding the video signal up to the last column, a latch pulse (Latch Pulse) is input from the latch control line 4122 during the horizontal blanking period, and the first latch circuit (LAT1) The video signals held in 4108 are transferred all at once to the second latch circuit (LAT2) 4109. After that, the video signal held in the second latch circuit (LAT2) 4109 is input to the amplifier circuit 4110 for one row at the same time. A signal output from the amplifier circuit 4110 is input to the pixel portion 4101 from each signal line.

While the video signal held in the second latch circuit (LAT2) 4109 is input to the amplifier circuit 4110 and is input to the pixel portion 4101, the shift register 4107 outputs a sampling pulse again. That is, two operations are performed simultaneously. Thereby, line-sequential driving becomes possible. Thereafter, this operation is repeated.

Note that the signal line driver circuit and a part thereof (such as a current source circuit and an amplifier circuit) do not exist on the same substrate as the pixel portion 4101, and may be configured using, for example, an external IC chip.

By using the scanning line driver circuit and the signal line driver circuit as described above, it is possible to realize driving in a case where a period for writing a signal to a pixel and a lighting period are separated.

Next, in the case of performing an operation of erasing a pixel signal, the display device includes a pixel portion 4201, first, second, third, and fourth scan line driver circuits 4202, 4203, and 4204 as shown in FIG. 4205 and a signal line driver circuit 4206. The pixel configuration in this case is as shown in FIG. 33 as an example. Note that the structures of the scan line driver circuit and the signal line driver circuit are the same as those described with reference to FIG. 41, and thus description thereof is omitted here.

Here, the first and second scanning line driving circuits 4202 and 4203 are circuits for driving the scanning lines connected to the sub-pixel 1. Here, the first scan line driver circuit 4202 sequentially outputs a selection signal to the first scan line 4207 connected to the sub-pixel 1 (a scan line to which a selection transistor is connected). On the other hand, the second scan line driver circuit 4203 sequentially outputs erase signals to the second scan line 4208 connected to the sub-pixel 1 (scan line to which the erase transistor is connected). As a result, the selection signal and the erase signal are written to the sub-pixel 1.

Similarly, the third and fourth scanning line driving circuits 4204 and 4205 are circuits for driving the scanning lines connected to the sub-pixel 2. Here, the third scan line driver circuit 4204 sequentially outputs a selection signal to the third scan line 4209 connected to the sub-pixel 2. On the other hand, the fourth scan line driver circuit 4205 sequentially outputs an erase signal to the fourth scan line 4210 connected to the sub-pixel 2. Thereby, a selection signal and an erasure signal are written in the sub-pixel 2.

In addition, the signal line driver circuit 4206 is a circuit for sequentially outputting video signals to the pixel portion 4201 through the signal line 4211.

By using the scanning line driver circuit and the signal line driver circuit as described above, it is possible to realize driving when performing an operation of erasing a pixel signal.

In the present embodiment, the case where a type in which a plurality of scanning lines are provided is used as the pixel configuration has been described. A driver circuit may be provided.

For example, in the case of performing an operation of erasing a pixel signal, the display device includes a pixel portion 4301, first and second scan line driver circuits 4302 and 4303, and first and second signal lines as illustrated in FIG. Drive circuits 4304 and 4305 are provided. Note that the structures of the scan line driver circuit and the signal line driver circuit are the same as those described with reference to FIG. 41, and thus description thereof is omitted here.

Here, the first scanning line driving circuit 4302 is a driving circuit for sequentially outputting a selection signal to the first scanning line 4306 (a scanning line to which a selection transistor is connected), and the second scanning line driving is performed. A circuit 4303 is a driver circuit for sequentially outputting erase signals to the second scan line 4307 (a scan line to which an erase transistor is connected).

The first signal line driver circuit 4304 is a driver circuit for sequentially outputting video signals to the first signal line 4308 connected to the sub-pixel 1 (SP1), and the second signal line driver circuit 4305 is used. Is a drive circuit for sequentially outputting video signals to the second signal line 4309 connected to the sub-pixel 2 (SP2). In general, when one pixel is divided into m (m is an integer of m ≧ 2) sub-pixels, m signal line driver circuits may be provided.

By using the scanning line driver circuit and the signal line driver circuit as described above, it is possible to realize driving when performing an operation of erasing a pixel signal.

Note that the structures of the signal line driver circuit, the scan line driver circuit, and the like are not limited to those illustrated in FIGS.

Note that the transistor in the present invention may be any type of transistor, and may be formed on any substrate. Therefore, the circuits as shown in FIGS. 41 to 43 may all be formed on a glass substrate, may be formed on a plastic substrate, or may be formed on a single crystal substrate. It may be formed on an SOI substrate or on any substrate. Alternatively, part of the circuits in FIGS. 41 to 43 may be formed on a certain substrate, and another part of the circuits in FIGS. 41 to 43 may be formed on another substrate. That is, all the circuits in FIGS. 41 to 43 may not be formed on the same substrate. For example, in FIGS. 41 to 43, the pixel portion and the scan line driver circuit are formed using a transistor over a glass substrate, and the signal line driver circuit (or part thereof) is formed over a single crystal substrate. The IC chip may be connected to the glass substrate by COG (Chip On Glass). Alternatively, the IC chip may be connected to the glass substrate using TAB (Tape Automated Bonding) or a printed board.

Note that the description in this embodiment can be implemented by being freely combined with the contents described in Embodiments 1 to 4.

(Embodiment 6)
In this embodiment, a display panel used in the display device of the present invention will be described with reference to FIG. 62A is a top view showing the display panel, and FIG. 62B is a cross-sectional view taken along line AA ′ in FIG. 62A. A signal line driver circuit 6201, a pixel portion 6202, a first scan line driver circuit 6203, and a second scan line driver circuit 6206 indicated by dotted lines are included. Further, a sealing substrate 6204 and a sealing material 6205 are provided, and an inner side surrounded by the sealing material 6205 is a space 6207.

Note that the wiring 6208 is a wiring for transmitting a signal input to the first scan line driver circuit 6203, the second scan line driver circuit 6206, and the signal line driver circuit 6201, and is supplied from the FPC 6209 which is an external input terminal to the video. Receive signals, clock signals, start signals, etc. IC chips (semiconductor chips on which a memory circuit, a buffer circuit, and the like are formed) 6218 and 6219 are mounted on a joint portion between the FPC 6209 and the display panel using COG (Chip On Glass) or the like. Although only the FPC is shown here, a printed wiring board (PWB) may be attached to the FPC.

Next, a cross-sectional structure will be described with reference to FIG. A pixel portion 6202 and its peripheral driver circuits (a first scan line driver circuit 6203, a second scan line driver circuit 6206, and a signal line driver circuit 6201) are formed over the substrate 6210. Here, signal lines A driver circuit 6201 and a pixel portion 6202 are shown.

Note that the signal line driver circuit 6201 includes a number of transistors such as a transistor 6220 and a transistor 6221. In this embodiment, a display panel in which peripheral drive circuits are integrally formed on a substrate is shown. However, this is not always necessary, and all or part of the peripheral drive circuits are formed on an IC chip or the like and mounted by COG or the like. May be.

The pixel portion 6202 includes a plurality of circuits included in a pixel including a switching transistor 6211 and a driving transistor 6212. Note that the source electrode of the driving transistor 6212 is connected to the first electrode 6213. In addition, an insulator 6214 is formed so as to cover an end portion of the first electrode 6213. Here, a positive photosensitive acrylic resin film is used.

In order to improve the coverage, a curved surface having a curvature is formed at the upper end portion or the lower end portion of the insulator 6214. For example, in the case where positive photosensitive acrylic is used as a material for the insulator 6214, it is preferable that only the upper end portion of the insulator 6214 have a curved surface with a curvature radius (0.2 μm to 3 μm). As the insulator 6214, either a negative type that becomes insoluble in an etchant by photosensitive light or a positive type that becomes soluble in an etchant by light can be used.

A layer 6216 containing an organic compound and a second electrode 6217 are formed over the first electrode 6213. Here, as a material used for the first electrode 6213 which functions as an anode, a material having a high work function is preferably used. For example, ITO (Indium Tin Oxide) film, Indium Zinc Oxide (IZO) film, Titanium nitride film, Chromium film, Tungsten film, Zn film, Pt film, etc., as well as titanium nitride and aluminum as main components And a three-layer structure of a titanium nitride film, a film containing aluminum as its main component, and a titanium nitride film can be used. Note that with a stacked structure, resistance as a wiring is low, good ohmic contact can be obtained, and a function as an anode can be obtained.

The layer 6216 containing an organic compound is formed by an evaporation method using an evaporation mask or an inkjet method. For the layer 6216 containing an organic compound, a Group 4 metal complex of the periodic table of elements is used as a part thereof, and other materials that can be used in combination include high molecular weight materials even if they are low molecular weight materials. It may be. In addition, as a material used for a layer containing an organic compound, an organic compound is usually used in a single layer or a stacked layer, but in this embodiment, an inorganic compound is also used for a part of a film made of an organic compound. Include. Further, a known triplet material can be used.

Further, as a material used for the second electrode 6217 which is a cathode formed on the layer 6216 containing an organic compound, a material having a low work function (Al, Ag, Li, Ca, or alloys thereof such as MgAg, MgIn, AlLi, CaF ₂ , or calcium nitride) may be used. Note that in the case where light generated in the layer 6216 containing an organic compound passes through the second electrode 6217, a thin metal film and a transparent conductive film (ITO (indium tin oxide) are used as the second electrode 6217. Or the like), a stack of indium oxide-zinc oxide alloy (In ₂ O ₃ —ZnO), zinc oxide (ZnO), or the like) is preferably used.

Further, the sealing substrate 6204 is attached to the substrate 6210 with the sealing material 6205, whereby the light-emitting element 6218 is provided in the space 6207 surrounded by the substrate 6210, the sealing substrate 6204, and the sealing material 6205. . Note that the space 6207 includes a structure filled with a sealant 6205 in addition to a case where the space 6207 is filled with an inert gas (nitrogen, argon, or the like).

Note that an epoxy-based resin is preferably used for the sealant 6205. Moreover, it is desirable that these materials are materials that do not transmit moisture and oxygen as much as possible. In addition to a glass substrate and a quartz substrate, a plastic substrate formed of FRP (Fiberglass-Reinforced Plastics), PVF (polyvinyl fluoride), Mylar, polyester, acrylic, or the like can be used as a material used for the sealing substrate 6204.

As described above, a display panel having the pixel configuration of the present invention can be obtained.

As shown in FIG. 62, the signal line driver circuit 6201, the pixel portion 6202, the first scan line driver circuit 6203, and the second scan line driver circuit 6206 are integrally formed, so that the cost of the display device can be reduced. Note that since the transistors used for the signal line driver circuit 6201, the pixel portion 6202, the first scan line driver circuit 6203, and the second scan line driver circuit 6206 are unipolar, the manufacturing process can be simplified, so that the manufacturing process can be further reduced. Cost can be reduced. Further, by using amorphous silicon for a semiconductor layer of a transistor used in the signal line driver circuit 6201, the pixel portion 6202, the first scan line driver circuit 6203, and the second scan line driver circuit 6206, cost can be further reduced. be able to.

Note that as a structure of the display panel, a signal line driver circuit 6201, a pixel portion 6202, a first scan line driver circuit 6203, and a second scan line driver circuit 6206 are integrally formed as shown in FIG. The configuration is not limited, and a signal line driver circuit corresponding to the signal line driver circuit 6201 may be formed over an IC chip and mounted on a display panel with COG or the like.

That is, only the signal line driver circuit that requires high-speed operation of the driver circuit is formed on the IC chip using a CMOS or the like to reduce power consumption. Further, by using a semiconductor chip such as a silicon wafer as the IC chip, higher speed operation and lower power consumption can be achieved.

The cost can be reduced by forming the scanning line driving circuit integrally with the pixel portion. Note that the scan line driver circuit and the pixel portion are formed of unipolar transistors, thereby further reducing the cost. As the structure of the pixel included in the pixel portion, the structure described in Embodiment Mode 3 can be applied. Further, by using amorphous silicon for the semiconductor layer of the transistor, the manufacturing process can be simplified and further cost reduction can be achieved.

Thus, the cost of a high-definition display device can be reduced. Further, by mounting an IC chip on which a functional circuit (memory or buffer) is formed at a connection portion between the FPC 6209 and the substrate 6210, the substrate area can be effectively used.

In addition, the signal line driver circuit corresponding to the signal line driver circuit 6201, the first scan line driver circuit 6203, and the second scan line driver circuit 6206 in FIG. 62A, the first scan line driver circuit, and the second scan line driver circuit are shown. The scan line driver circuit may be formed over the IC chip and mounted on the display panel with COG or the like. In this case, a high-definition display device can have lower power consumption. Therefore, in order to obtain a display device with lower power consumption, it is preferable to use polysilicon for a semiconductor layer of a transistor used in the pixel portion.

In addition, cost can be reduced by using amorphous silicon for the semiconductor layer of the transistor in the pixel portion 6202. Further, a large display panel can be manufactured.

Note that the scan line driver circuit and the signal line driver circuit are not limited to being provided in the row direction and the column direction of the pixel.

Next, examples of light-emitting elements applicable to the light-emitting element 6218 are illustrated in FIGS.

An anode 7302 over a substrate 7301, a hole injection layer 7303 made of a hole injection material, a hole transport layer 7304 made of a hole transport material, a light emitting layer 7305, an electron transport layer 7306 made of an electron transport material, and an electron This is an element structure in which an electron injection layer 7307 made of an injection material and a cathode 7308 are laminated. Here, the light emitting layer 7305 may be formed of only one type of light emitting material, but may be formed of two or more types of materials. Further, the structure of the element of the present invention is not limited to this structure.

In addition to the laminated structure in which each functional layer shown in FIG. 63 is laminated, variations such as an element using a polymer compound, a high-efficiency element using a triplet light emitting material that emits light from a triplet excited state in the light emitting layer, etc. Wide range. The present invention can also be applied to a white light emitting element obtained by controlling a carrier recombination region by a hole blocking layer and dividing a light emitting region into two regions.

Next, a method for manufacturing the element of the present invention shown in FIG. 63 will be described. First, a hole injecting material, a hole transporting material, and a light emitting material are sequentially deposited on a substrate 7301 having an anode 7302 (ITO (indium tin oxide)). Next, an electron transport material and an electron injection material are vapor-deposited, and finally a cathode 6308 is formed by vapor deposition.

Next, materials suitable for the hole injection material, the hole transport material, the electron transport material, the electron injection material, and the light emitting material are listed below.

As the hole injection material, porphyrin compounds, phthalocyanine (hereinafter referred to as “H ₂ Pc”), copper phthalocyanine (hereinafter referred to as “CuPc”), and the like are effective as long as they are organic compounds. In addition, any material that has a smaller ionization potential than the hole transport material used and has a hole transport function can also be used as the hole injection material. There is also a material obtained by chemically doping a conductive polymer compound, and examples thereof include polyethylenedioxythiophene (hereinafter referred to as “PEDOT”) doped with polystyrene sulfonic acid (hereinafter referred to as “PSS”), polyaniline, and the like. An insulating polymer compound is also effective in terms of planarization of the anode, and polyimide (hereinafter referred to as “PI”) is often used. In addition, inorganic compounds are also used. In addition to metal thin films such as gold and platinum, there are ultra thin films of aluminum oxide (hereinafter referred to as “alumina”).

The most widely used hole transport material is an aromatic amine-based compound (that is, a compound having a benzene ring-nitrogen bond). As widely used materials, 4,4′-bis (diphenylamino) -biphenyl (hereinafter referred to as “TAD”) and its derivative 4,4′-bis [N- (3-methylphenyl) -N-phenyl-amino] -biphenyl (hereinafter referred to as “TPD”), 4,4′-bis [N- (1-naphthyl) -N-phenyl-amino] -biphenyl (hereinafter referred to as “α-NPD”) ). 4,4 ′, 4 ″ -tris (N, N-diphenyl-amino) -triphenylamine (hereinafter referred to as “TDATA”), 4,4 ′, 4 ″ -tris [N- (3-methylphenyl) And starburst aromatic amine compounds such as —N-phenyl-amino] -triphenylamine (hereinafter referred to as “MTDATA”).

As an electron transport material, a metal complex is often used, and tris (8-quinolinolato) aluminum (hereinafter referred to as “Alq ₃ ”), BAlq, tris (4-methyl-8-quinolinolato) aluminum (hereinafter referred to as “Almq”). And a metal complex having a quinoline skeleton or a benzoquinoline skeleton such as bis (10-hydroxybenzo [h] -quinolinato) beryllium (hereinafter referred to as “Bebq”). Further, bis [2- (2-hydroxyphenyl) -benzoxazolate] zinc (hereinafter referred to as “Zn (BOX) ₂ ”), bis [2- (2-hydroxyphenyl) -benzothiazolate] zinc (hereinafter referred to as “Zn (BOX) ₂ ”) There is also a metal complex having an oxazole-based or thiazole-based ligand such as “Zn (BTZ) ₂ ”). In addition to metal complexes, 2- (4-biphenylyl) -5- (4-tert-butylphenyl) -1,3,4-oxadiazole (hereinafter referred to as “PBD”), OXD-7, and the like An oxadiazole derivative of TAZ, 3- (4-tert-butylphenyl) -4- (4-ethylphenyl) -5- (4-biphenylyl) -1,2,4-triazole (hereinafter referred to as “p-EtTAZ”) ) And other phenanthroline derivatives such as bathophenanthroline (hereinafter referred to as “BPhen”) and BCP have electron transport properties.

The electron transport material described above can be used as the electron injection material. In addition, an ultra-thin film of an insulator such as a metal halide such as calcium fluoride, lithium fluoride, or cesium fluoride, or an alkali metal oxide such as lithium oxide is often used. In addition, alkali metal complexes such as lithium acetylacetonate (hereinafter referred to as “Li (acac)”) and 8-quinolinolato-lithium (hereinafter referred to as “Liq”) are also effective.

As the luminescent material, various fluorescent dyes are effective in addition to the metal complexes such as Alq ₃ , Almq, BeBq, BAlq, Zn (BOX) ₂ , Zn (BTZ) _{2 described} above. As fluorescent dyes, blue 4,4′-bis (2,2-diphenyl-vinyl) -biphenyl and red-orange 4- (dicyanomethylene) -2-methyl-6- (p-dimethylaminostyryl)- 4H-pyran. A triplet light emitting material is also possible, and is mainly a complex having platinum or iridium as a central metal. As the triplet light emitting material, tris (2-phenylpyridine) iridium, bis (2- (4′-tolyl) pyridinato-N, C ^{2 ′} ) acetylacetonatoiridium (hereinafter referred to as “acacIr (tpy) ₂ ”), 2,3,7,8,12,13,17,18-octaethyl-21H, 23H porphyrin-platinum and the like are known.

A highly reliable light-emitting element can be manufactured by combining the materials having the functions described above.

Alternatively, a light-emitting element in which layers are formed in the order opposite to that in FIG. 63 may be used. That is, the cathode 7308 over the substrate 7301, the electron injection layer 7307 made of an electron injection material, the electron transport layer 7306 made of an electron transport material thereon, the light emitting layer 7305, the hole transport layer 7304 made of a hole transport material, In this element structure, a hole injection layer 7303 made of a hole injection material and an anode 7302 are laminated.

In addition, in order to extract light emitted from the light emitting element, at least one of the anode and the cathode may be transparent. Then, a transistor and a light emitting element are formed over the substrate, and a top emission that extracts light from a surface opposite to the substrate, a bottom emission that extracts light from a surface on the substrate side, and a surface opposite to the substrate side and the substrate. The pixel structure of the present invention can be applied to a light emitting element having any emission structure.

First, a light-emitting element having a top emission structure will be described with reference to FIG.

A driving transistor 6401 is formed over a substrate 6400, a first electrode 6402 is formed in contact with a source electrode of the driving transistor 6401, and a layer 6403 containing an organic compound and a second electrode 6404 are formed thereover. Yes.

The first electrode 6402 is an anode of the light emitting element. The second electrode 6404 is a cathode of the light emitting element. That is, a region where the layer 6403 containing an organic compound is sandwiched between the first electrode 6402 and the second electrode 6404 is a light-emitting element.

Here, as a material used for the first electrode 6402 functioning as an anode, a material having a high work function is preferably used. For example, in addition to a single layer film such as a titanium nitride film, a chromium film, a tungsten film, a Zn film, or a Pt film, a stack of titanium nitride and a film containing aluminum as a main component, a film containing a titanium nitride film and aluminum as a main component A three-layer structure of titanium nitride film and the like can be used. Note that with a stacked structure, resistance as a wiring is low, good ohmic contact can be obtained, and a function as an anode can be obtained. By using a metal film that reflects light, an anode that does not transmit light can be formed.

The material used for the second electrode 6404 functioning as a cathode is made of a material having a low work function (Al, Ag, Li, Ca, or an alloy thereof such as MgAg, MgIn, AlLi, CaF ₂ , or calcium nitride). A stack of a metal thin film and a transparent conductive film (ITO (indium tin oxide), indium zinc oxide (IZO), zinc oxide (ZnO), or the like) is preferably used. Thus, a cathode capable of transmitting light can be formed by using a thin metal thin film and a transparent conductive film having transparency.

In this manner, light from the light emitting element can be extracted to the upper surface as indicated by an arrow in FIG. That is, when applied to the display panel in FIG. 62, light is emitted to the sealing substrate 6204 side. Therefore, in the case where a light-emitting element having a top emission structure is used for a display device, the sealing substrate 6204 is a light-transmitting substrate.

In the case where an optical film is provided, an optical film may be provided over the sealing substrate 6204.

Note that the first electrode 6402 can also be formed using a metal film formed of a material with a low work function, such as MgAg, MgIn, or AlLi, which functions as a cathode. In this case, a transparent conductive film such as an ITO (indium tin oxide) film or indium zinc oxide (IZO) can be used for the second electrode 6404. Therefore, according to this configuration, it is possible to increase the transmittance of top emission.

Next, a light-emitting element having a bottom emission structure will be described with reference to FIG. Except for the emission structure, the light-emitting element has the same structure as that in FIG.

Here, as a material used for the first electrode 6402 functioning as an anode, a material having a high work function is preferably used. For example, a transparent conductive film such as an ITO (indium tin oxide) film or an indium zinc oxide (IZO) film can be used. By using a transparent conductive film having transparency, an anode capable of transmitting light can be formed.

The material used for the second electrode 6404 functioning as a cathode is made of a material having a low work function (Al, Ag, Li, Ca, or an alloy thereof such as MgAg, MgIn, AlLi, CaF ₂ , or calcium nitride). A metal film can be used. Thus, by using a metal film that reflects light, a cathode that does not transmit light can be formed.

In this manner, light from the light emitting element can be extracted to the lower surface as indicated by an arrow in FIG. That is, when applied to the display panel of FIG. 62, light is emitted to the substrate 6210 side. Therefore, when a light-emitting element having a bottom emission structure is used for a display device, the substrate 6210 is a light-transmitting substrate.

In the case of providing an optical film, the substrate 6210 may be provided with an optical film.

Next, a light-emitting element having a dual emission structure will be described with reference to FIG. Except for the emission structure, the light-emitting element has the same structure as that in FIG.

Here, as a material used for the first electrode 6402 functioning as an anode, a material having a high work function is preferably used. For example, a transparent conductive film such as an ITO (indium tin oxide) film or an indium zinc oxide (IZO) film can be used. By using a transparent conductive film having transparency, an anode capable of transmitting light can be formed.

The material used for the second electrode 6404 functioning as a cathode is made of a material having a low work function (Al, Ag, Li, Ca, or an alloy thereof such as MgAg, MgIn, AlLi, CaF ₂ , or calcium nitride). A stack of a metal thin film and a transparent conductive film (ITO (indium tin oxide), indium zinc oxide alloy (In ₂ O ₃ —ZnO), zinc oxide (ZnO), or the like) is preferably used. Thus, a cathode capable of transmitting light can be formed by using a thin metal thin film and a transparent conductive film having transparency.

In this manner, light from the light emitting element can be extracted on both sides as indicated by arrows in FIG. That is, when applied to the display panel in FIG. 62, light is emitted to the substrate 6210 side and the sealing substrate 6204 side. Therefore, in the case where a light-emitting element having a dual emission structure is used for a display device, the substrate 6210 and the sealing substrate 6204 are both light-transmitting substrates.

In the case where an optical film is provided, the optical film may be provided on both the substrate 6210 and the sealing substrate 6204.

In addition, the present invention can be applied to a display device that realizes full color display using a white light emitting element and a color filter.

As shown in FIG. 65, a base film 6502 is formed over a substrate 6500, a driving transistor 6501 is formed over the base film 6502, and a first electrode 6503 is formed in contact with the source electrode of the driving transistor 6501. A layer 6504 containing an organic compound and a second electrode 6505 are formed thereover.

The first electrode 6503 is an anode of the light emitting element. The second electrode 6505 is a cathode of the light emitting element. That is, a region where the layer 6504 containing an organic compound is sandwiched between the first electrode 6503 and the second electrode 6505 is a light-emitting element. 65 emits white light. A red color filter 6506R, a green color filter 6506G, and a blue color filter 6506B are provided above the light-emitting element, so that full color display can be performed. Further, a black matrix (also referred to as BM) 6507 for separating these color filters is provided.

The above structures of the light-emitting elements can be used in combination and can be used as appropriate for the display device of the present invention. Further, the structure of the display panel and the light-emitting element described above are examples, and the present invention can be applied to a display device having another structure different from the structure described above.

Next, a partial cross-sectional view of a pixel portion of the display panel is shown.

First, the case where a polysilicon (p-Si: H) film is used for a semiconductor layer of a transistor will be described with reference to FIGS.

Here, as the semiconductor layer, for example, an amorphous silicon (a-Si) film is formed on a substrate by a known film formation method. Note that the semiconductor film is not limited to an amorphous silicon film, and any semiconductor film including an amorphous structure (including a microcrystalline semiconductor film) may be used. Further, a compound semiconductor film including an amorphous structure such as an amorphous silicon germanium film may be used.

Then, the amorphous silicon film is crystallized by a laser crystallization method, a thermal crystallization method using an RTA or a furnace annealing furnace, or a thermal crystallization method using a metal element that promotes crystallization. Of course, these may be combined.

By the above crystallization, a partially crystallized region is formed in the amorphous semiconductor film.

Further, a pattern is formed in a desired shape from the crystalline semiconductor film partially improved in crystallinity, and an island-shaped semiconductor film is formed from the crystallized region. This semiconductor film is used for a semiconductor layer of a transistor.

As shown in FIG. 66A, a base film 602 is formed on a substrate 601, and a semiconductor layer is formed thereon. The semiconductor layer includes a channel formation region 603, an LDD region 604, and an impurity region 605 serving as a source region or a drain region of the driving transistor 618, and a channel formation region 606, an LDD region 607, and an impurity region 608 that serve as a lower electrode of the capacitor 619. Have Note that channel doping may be performed on the channel formation region 603 and the channel formation region 606.

As the substrate, a glass substrate, a quartz substrate, a ceramic substrate, or the like can be used. As the base film 602, a single layer such as aluminum nitride (AlN), silicon oxide (SiO ₂ ), or silicon oxynitride (SiO _x N _y ) or a stacked layer thereof can be used.

Over the semiconductor layer, a gate electrode 610 and an upper electrode 611 of the capacitor 619 are formed with a gate insulating film 609 interposed therebetween.

An interlayer insulating film 612 is formed to cover the capacitor 619 and the driving transistor 618, and a wiring 613 is in contact with the impurity region 605 through a contact hole over the interlayer insulating film 612. A pixel electrode 614 is formed in contact with the wiring 613, and an insulator 615 is formed to cover the end of the pixel electrode 614 and the wiring 613. Here, a positive photosensitive acrylic resin film is used. A layer 616 containing an organic compound and a counter electrode 617 are formed over the pixel electrode 614, and a light-emitting element 620 is formed in a region where the layer 616 containing an organic compound is sandwiched between the pixel electrode 614 and the counter electrode 617. Yes.

In addition, as illustrated in FIG. 66B, a region 621 in which an LDD region that forms part of the lower electrode of the capacitor 619 overlaps with the upper electrode 611 of the capacitor 619 may be provided. Note that portions common to FIG. 66A are denoted by common reference numerals, and description thereof is omitted.

As shown in FIG. 67A, the capacitor 623 may include a second upper electrode 622 formed in the same layer as the wiring 613 in contact with the impurity region 605 of the driving transistor 618. Note that portions common to FIG. 66A are denoted by common reference numerals, and description thereof is omitted. Since the second upper electrode 622 is in contact with the impurity region 608, the first capacitor element including the upper electrode 611 and the channel formation region 606 sandwiching the gate insulating film 609, the upper electrode 611, And the second capacitor element formed by sandwiching the interlayer insulating film 612 between the upper electrode 622 and the capacitor element 623 composed of the first capacitor element and the second capacitor element. . Since the capacitance of the capacitor 623 is a combined capacitance obtained by adding the capacitances of the first capacitor and the second capacitor, a capacitor having a large area and a small capacitance can be formed. That is, the aperture ratio can be further improved when used as a capacitor having a pixel structure of the present invention.

Further, a structure of a capacitor as shown in FIG. A base film 702 is formed over a substrate 701, and a semiconductor layer is formed thereover. The semiconductor layer includes a channel formation region 703, an LDD region 704, and an impurity region 705 serving as a source region or a drain region of the driving transistor 718. Note that the channel formation region 703 may be channel-doped.

As the substrate, a glass substrate, a quartz substrate, a ceramic substrate, or the like can be used. As the base film 702, a single layer such as aluminum nitride (AlN), silicon oxide (SiO ₂ ), or silicon oxynitride (SiO _x N _y ) or a stacked layer thereof can be used.

A gate electrode 707 and a first electrode 708 are formed over the semiconductor layer with a gate insulating film 706 interposed therebetween.

A first interlayer insulating film 709 is formed so as to cover the driving transistor 718 and the first electrode 708, and a wiring 710 is in contact with the impurity region 705 through a contact hole on the first interlayer insulating film 709. In addition, a second electrode 711 made of the same material as the wiring 710 is formed in the same layer as the wiring 710.

Further, a second interlayer insulating film 712 is formed so as to cover the wiring 710 and the second electrode 711, and a pixel electrode 713 is formed on the second interlayer insulating film 712 in contact with the wiring 710 through a contact hole. Has been. A third electrode 714 made of the same material as the pixel electrode 713 is formed in the same layer as the pixel electrode 713. Here, a capacitor 719 including the first electrode 708, the second electrode 711, and the third electrode 714 is formed.

A layer 716 containing an organic compound and a counter electrode 717 are formed over the pixel electrode 713, and a light-emitting element 720 is formed in a region where the layer 716 containing an organic compound is sandwiched between the pixel electrode 713 and the counter electrode 717.

As described above, the structure of the transistor in which the crystalline semiconductor film is used for the semiconductor layer includes the structures illustrated in FIGS. Note that the structure of the transistor illustrated in FIGS. 66 and 67 is an example of a top-gate transistor. That is, the LDD region may overlap with the gate electrode, may not overlap with the gate electrode, or a part of the LDD region may overlap. Further, the gate electrode may have a tapered shape, and an LDD region may be provided in a self-aligned manner below the tapered portion of the gate electrode. Further, the number of gate electrodes is not limited to two, but may be three or more multi-gate structures or one gate electrode.

By using a crystalline semiconductor film for a semiconductor layer (a channel formation region, a source region, a drain region, or the like) of a transistor included in a pixel of the present invention, a scan line driver circuit and a signal line driver circuit are formed integrally with a pixel portion. Becomes easier. Alternatively, part of the signal line driver circuit may be formed integrally with the pixel portion, and part of the signal line driver circuit may be formed over an IC chip and mounted by COG or the like as shown in the display panel in FIG. With such a configuration, the manufacturing cost can be reduced.

In addition, as a transistor structure using polysilicon (p-Si) as a semiconductor layer, a structure in which a gate electrode is sandwiched between a substrate and a semiconductor layer, that is, a bottom gate structure in which the gate electrode is located under the semiconductor layer. The transistor may be applied. Here, a partial cross-sectional view of a pixel portion of a display panel to which a bottom-gate transistor is applied is shown in FIG.

As shown in FIG. 68A, a base film 802 is formed on a substrate 801. Further, a gate electrode 803 is formed on the base film 802. A first electrode 804 made of the same material as the gate electrode 803 is formed in the same layer as the gate electrode 803. As a material for the gate electrode 803, polycrystalline silicon to which phosphorus is added can be used. In addition to polycrystalline silicon, silicide which is a compound of metal and silicon may be used.

A gate insulating film 805 is formed so as to cover the gate electrode 803 and the first electrode 804. As the gate insulating film 805, a silicon oxide film, a silicon nitride film, or the like is used.

A semiconductor layer is formed over the gate insulating film 805. The semiconductor layer includes a channel formation region 806, an LDD region 807, and an impurity region 808 serving as a source region or a drain region of the driver transistor 822, and a channel formation region 809, an LDD region 810, and an impurity region serving as a second electrode of the capacitor 823. 811. Note that the channel formation region 806 and the channel formation region 809 may be channel-doped.

As the substrate, a glass substrate, a quartz substrate, a ceramic substrate, or the like can be used. As the base film 802, a single layer such as aluminum nitride (AlN), silicon oxide (SiO ₂ ), or silicon oxynitride (SiO _x N _y ) or a stacked layer thereof can be used.

A first interlayer insulating film 812 is formed to cover the semiconductor layer, and a wiring 813 is in contact with the impurity region 808 over the first interlayer insulating film 812 through a contact hole. A third electrode 814 is formed in the same layer as the wiring 813 with the same material as the wiring 813. The capacitor 823 is formed by the first electrode 804, the second electrode, and the third electrode 814.

An opening 815 is formed in the first interlayer insulating film 812. A second interlayer insulating film 816 is formed so as to cover the driving transistor 822, the capacitor 823, and the opening 815, and a pixel electrode 817 is formed over the second interlayer insulating film 816 through a contact hole. . Further, an insulator 818 is formed so as to cover an end portion of the pixel electrode 817. For example, a positive photosensitive acrylic resin film can be used. A layer 819 containing an organic compound and a counter electrode 820 are formed over the pixel electrode 817, and a light-emitting element 821 is formed in a region where the layer 819 containing an organic compound is sandwiched between the pixel electrode 817 and the counter electrode 820. Yes. An opening 815 is positioned below the light emitting element 821. That is, when light emitted from the light-emitting element 821 is extracted from the substrate side, the opening 815 is provided, so that the transmittance can be increased.

In FIG. 68A, the fourth electrode 824 may be formed using the same material in the same layer as the pixel electrode 817 so that the structure shown in FIG. Then, a capacitor 825 including the first electrode 804, the second electrode, the third electrode 814, and the fourth electrode 824 can be formed.

Next, the case where an amorphous silicon (a-Si) film is used for the semiconductor layer of the transistor will be described with reference to FIGS.

FIG. 44 shows a partial cross-sectional view of a pixel portion of a display panel to which a top-gate transistor using amorphous silicon as a semiconductor layer is applied. As shown in FIG. 44A, a base film 4402 is formed on a substrate 4401. Further, a pixel electrode 4403 is formed over the base film 4402. A first electrode 4404 made of the same material as the pixel electrode 4403 is formed in the same layer as the pixel electrode 4403.

As the substrate, a glass substrate, a quartz substrate, a ceramic substrate, or the like can be used. As the base film 4402, a single layer such as aluminum nitride (AlN), silicon oxide (SiO ₂ ), or silicon oxynitride (SiO _x N _y ) or a stacked layer thereof can be used.

A wiring 4405 and a wiring 4406 are formed over the base film 4402, and an end portion of the pixel electrode 4403 is covered with the wiring 4405. Over the wirings 4405 and 4406, an N-type semiconductor layer 4407 and an N-type semiconductor layer 4408 having an N-type conductivity are formed. A semiconductor layer 4409 is formed between the wiring 4405 and the wiring 4406 and over the base film 4402. A part of the semiconductor layer 4409 extends to the N-type semiconductor layer 4407 and the N-type semiconductor layer 4408. Note that this semiconductor layer 4409 is formed using a non-crystalline semiconductor film such as amorphous silicon (a-Si) or microcrystalline semiconductor (μ-Si).

A gate insulating film 4410 is formed over the semiconductor layer 4409. In addition, an insulating film 4411 made of the same material as the gate insulating film 4410 is formed over the first electrode 4404 in the same layer as the gate insulating film 4410. Note that as the gate insulating film 4410, a silicon oxide film, a silicon nitride film, or the like is used.

A gate electrode 4412 is formed over the gate insulating film 4410. In addition, in the same layer as the gate electrode 4412, a second electrode 4413 made of the same material as the gate electrode 4412 is formed over the first electrode 4404 with an insulating film 4411 interposed therebetween. Accordingly, a capacitor element 4419 having a structure in which the insulating film 4411 is sandwiched between the first electrode 4404 and the second electrode 4413 is formed. Further, an interlayer insulating film 4414 is formed so as to cover an end portion of the pixel electrode 4403, the driving transistor 4418, and the capacitor 4419.

A layer 4415 containing an organic compound and a counter electrode 4416 are formed over the interlayer insulating film 4414 and the pixel electrode 4403 located in the opening, and the layer 4415 containing an organic compound is sandwiched between the pixel electrode 4403 and the counter electrode 4416. A light emitting element 4417 is formed in the region.

In addition, the first electrode 4404 illustrated in FIG. 44A may be formed using the first electrode 4420 as illustrated in FIG. Note that the first electrode 4420 illustrated in FIG. 44B is formed in the same layer as the wirings 4405 and 4406 with the same material as the wirings 4405 and 4406.

Next, FIGS. 45 and 46 are partial cross-sectional views of a pixel portion of a display panel to which a bottom-gate transistor using amorphous silicon as a semiconductor layer is applied.

As shown in FIG. 45A, a base film 4502 is formed on a substrate 4501. Further, a gate electrode 4503 is formed over the base film 4502. A first electrode 4504 made of the same material as the gate electrode 4503 is formed in the same layer as the gate electrode 4503. As a material for the gate electrode 4503, polycrystalline silicon to which phosphorus is added can be used. In addition to polycrystalline silicon, silicide which is a compound of metal and silicon may be used.

A gate insulating film 4505 is formed so as to cover the gate electrode 4503 and the first electrode 4504. As the gate insulating film 4505, a silicon oxide film, a silicon nitride film, or the like is used.

A semiconductor layer 4506 is formed over the gate insulating film 4505. A semiconductor layer 4507 made of the same material as the semiconductor layer 4506 is formed in the same layer as the semiconductor layer 4506.

As the substrate, a glass substrate, a quartz substrate, a ceramic substrate, or the like can be used. As the base film 4502, a single layer such as aluminum nitride (AlN), silicon oxide (SiO ₂ ), or silicon oxynitride (SiO _x N _y ), or a stacked layer thereof can be used.

N-type semiconductor layers 4508 and 4509 having N-type conductivity are formed over the semiconductor layer 4506, and an N-type semiconductor layer 4510 is formed over the semiconductor layer 4507.

Wirings 4511 and 4512 are formed over the N-type semiconductor layers 4508 and 4509, respectively. A conductive layer 4513 made of the same material as the wirings 4511 and 4512 is formed over the N-type semiconductor layer 4510 in the same layer as the wirings 4511 and 4512.

Thus, a second electrode including the semiconductor layer 4507, the N-type semiconductor layer 4510, and the conductive layer 4513 is formed. Note that a capacitor 4520 having a structure in which the gate insulating film 4505 is sandwiched between the second electrode and the first electrode 4504 is formed.

In addition, one end of the wiring 4511 extends, and a pixel electrode 4514 is formed in contact with the upper portion of the extended wiring 4511.

In addition, an insulator 4515 is formed so as to cover an end portion of the pixel electrode 4514, the driving transistor 4519, and the capacitor 4520.

A layer 4516 containing an organic compound and a counter electrode 4517 are formed over the pixel electrode 4514 and the insulator 4515, and a light-emitting element 4518 is formed in a region where the layer 4516 containing an organic compound is interposed between the pixel electrode 4514 and the counter electrode 4517. Is formed.

Note that the semiconductor layer 4507 and the N-type semiconductor layer 4510 which are part of the second electrode of the capacitor 4520 are not necessarily provided. That is, the second electrode of the capacitor 4520 may be the conductive layer 4513, and the capacitor 4520 may have a structure in which the gate insulating film is sandwiched between the first electrode 4504 and the conductive layer 4513.

In FIG. 45A, by forming the pixel electrode 4514 before forming the wiring 4511, the same material as the pixel electrode 4514 is formed in the same layer as the pixel electrode 4514 as shown in FIG. A second electrode 4521 can be formed. Accordingly, the capacitor 4522 having a structure in which the gate insulating film 4505 is sandwiched between the second electrode 4521 and the first electrode 4504 can be formed.

Note that although an example in which an inverted staggered channel etch transistor is used is shown in FIG. 45, a channel protection transistor may be applied as a matter of course. The case where a transistor having a channel protective structure is applied will be described with reference to FIGS.

The transistor having the channel protection structure illustrated in FIG. 46A serves as an etching mask over the region where the channel of the semiconductor layer 4506 of the driving transistor 4519 having the channel etch structure illustrated in FIG. The difference is that an insulator 4601 is provided, and other common parts use common reference numerals.

Similarly, in the channel protection type transistor illustrated in FIG. 46B, the channel of the semiconductor layer 4506 of the driving transistor 4519 having the channel etch structure illustrated in FIG. The difference is that an insulator 4601 serving as an etching mask is provided, and common portions are denoted by common reference numerals.

By using an amorphous semiconductor film for a semiconductor layer (a channel formation region, a source region, a drain region, or the like) of a transistor included in the pixel of the present invention, manufacturing cost can be reduced.

Note that the structure of the transistor and the structure of the capacitor that can be applied to the pixel portion of the display device of the present invention are not limited to the above structures, and the structure of the transistor and the structure of the capacitor can be used in various structures. it can.

Note that the content described in this embodiment mode can be freely combined with the content described in Embodiment Modes 1 to 5.

(Embodiment 7)
In this embodiment mode, a method for manufacturing a semiconductor device using plasma treatment will be described as a method for manufacturing a semiconductor device including a transistor.

FIG. 47 is a diagram illustrating a structure example of a semiconductor device including a transistor. 47B, FIG. 47B corresponds to a cross-sectional view taken along line ab in FIG. 47A, and FIG. 47C corresponds to a cross-sectional view taken along line cd in FIG. 47A. To do.

The semiconductor device illustrated in FIG. 47 includes semiconductor films 4703a and 4703b provided over a substrate 4701 with an insulating film 4702 interposed therebetween, and a gate electrode 4705 provided over the semiconductor films 4703a and 4703b with a gate insulating film 4704 interposed therebetween. And insulating films 4706 and 4707 provided so as to cover the gate electrode, and conductive films 4708 electrically connected to the source region or the drain region of the semiconductor films 4703a and 4703b and provided over the insulating film 4707. Yes. Note that FIG. 47 shows the case where an N-channel transistor 4710a using part of the semiconductor film 4703a as a channel region and a P-channel transistor 4710b using part of the semiconductor film 4703b as a channel region are shown. However, it is not limited to this configuration. For example, in FIG. 47, an LDD region is not provided in the N-channel transistor 4710a and an LDD region is not provided in the P-channel transistor 4710b. However, the structure may be provided in both or may not be provided in both. Is possible.

Note that in this embodiment, at least one of the substrate 4701, the insulating film 4702, the semiconductor films 4703a and 4703b, the gate insulating film 4704, the insulating film 4706, and the insulating film 4707 is oxidized or nitrided using plasma treatment. The semiconductor device shown in FIG. 47 is manufactured by oxidizing or nitriding the semiconductor film or the insulating film. In this manner, the surface of the semiconductor film or the insulating film is modified by oxidizing or nitriding the semiconductor film or the insulating film using plasma treatment, and compared with an insulating film formed by a CVD method or a sputtering method. Since a dense insulating film can be formed, defects such as pinholes can be suppressed and characteristics and the like of the semiconductor device can be improved.

Note that in this embodiment, the semiconductor films 4703a and 4703b or the gate insulating film 4704 in FIG. 47 are subjected to plasma treatment, and the semiconductor films 4703a and 4703b or the gate insulating film 4704 are oxidized or nitrided to manufacture a semiconductor device. The method will be described with reference to the drawings.

First, the case where an island-shaped semiconductor film provided over a substrate is provided with an end portion of the island-shaped semiconductor film having a shape close to a right angle is described.

First, island-shaped semiconductor films 4703a and 4703b are formed over the substrate 4701 (FIGS. 48A-1 and 48A-2). The island-shaped semiconductor films 4703a and 4703b are formed using a material containing silicon (Si) as a main component (for example, Si _x ) by using a sputtering method, an LPCVD method, a plasma CVD method, or the like over an insulating film 4702 formed in advance on a substrate 4701. An amorphous semiconductor film can be formed using Ge _1-x, etc., the amorphous semiconductor film can be crystallized, and the semiconductor film can be selectively etched. The crystallization of the amorphous semiconductor film may be performed by laser crystallization, thermal crystallization using an RTA or furnace annealing furnace, thermal crystallization using a metal element that promotes crystallization, or a combination of these methods. The crystallization method can be used. In FIG. 48, the end portions of the island-shaped semiconductor films 4703a and 4703b are provided in a shape close to a right angle (θ = 85 to 100 °).

Next, plasma treatment is performed to oxidize or nitride the semiconductor films 4703a and 4703b, so that oxide or nitride films 4721a and 4721b (hereinafter also referred to as insulating films 4721a and 4721b) are formed on the surfaces of the semiconductor films 4703a and 4703b, respectively. (FIGS. 48B-1 and 48B-2). For example, when Si is used for the semiconductor films 4703a and 4703b, silicon oxide or silicon nitride is formed as the insulating films 4721a and 4721b. Alternatively, the semiconductor films 4703a and 4703b may be oxidized by plasma treatment and then nitrided by performing plasma treatment again. In this case, silicon oxide is formed in contact with the semiconductor films 4703a and 4703b, and silicon nitride oxide (SiN _x O _y ) (x> y) is formed on the surface of the silicon oxide. Note that in the case where the semiconductor film is oxidized by plasma treatment, an oxygen atmosphere (eg, oxygen (O ₂ ) and a rare gas (including at least one of He, Ne, Ar, Kr, and Xe) atmosphere or oxygen is used. Plasma treatment is performed under an atmosphere of hydrogen (H ₂ ) and a rare gas or dinitrogen monoxide and a rare gas. On the other hand, in the case of nitriding a semiconductor film by plasma treatment, in a nitrogen atmosphere (for example, nitrogen (N ₂ ) and a rare gas (including at least one of He, Ne, Ar, Kr, and Xe) atmosphere or nitrogen Plasma treatment is performed under a hydrogen and rare gas atmosphere or a NH ₃ and rare gas atmosphere. As the rare gas, for example, Ar can be used. A gas in which Ar and Kr are mixed may be used. Therefore, the insulating films 4721a and 4721b include a rare gas (including at least one of He, Ne, Ar, Kr, and Xe) used for plasma treatment. When Ar is used, the insulating films 4721a and 4721b are used. Contains Ar.

In addition, the plasma treatment is performed in the above gas atmosphere at an electron density of 1 × 10 ¹¹ cm ⁻³ or more and 1 × 10 ¹³ cm ⁻³ or less and an electron temperature of plasma of 0.5 eV or more and 1.5 eV or less. . Since the electron density of plasma is high and the electron temperature in the vicinity of the object to be processed (here, the semiconductor films 4703a and 4703b) formed over the substrate 4701 is low, damage to the object to be processed is prevented. Can do. In addition, since the electron density of plasma is as high as 1 × 10 ¹¹ cm ⁻³ or more, an oxide or a nitride film formed by oxidizing or nitriding an irradiation object using plasma treatment is a CVD method. Compared with a film formed by sputtering or the like, a film having excellent uniformity in film thickness and the like and a dense film can be formed. In addition, since the electron temperature of plasma is as low as 1 eV or less, oxidation or nitridation can be performed at a lower temperature than conventional plasma treatment or thermal oxidation. For example, even if the plasma treatment is performed at a temperature that is 100 degrees or more lower than the strain point temperature of the glass substrate, the oxidation or nitriding treatment can be sufficiently performed. Note that a high frequency such as a microwave (2.45 GHz) can be used as a frequency for forming plasma. Note that the plasma treatment is performed using the above conditions unless otherwise specified.

Next, a gate insulating film 4704 is formed so as to cover the insulating films 4721a and 4721b (FIGS. 48C-1 and 48C-2). The gate insulating film 4704 is formed using silicon oxide, silicon nitride, silicon oxynitride (SiO _x N _y ) (x> y), silicon nitride oxide (SiN _x O _y ) by sputtering, LPCVD, plasma CVD, or the like. A single-layer structure of an insulating film containing oxygen or nitrogen such as (x> y) or a stacked structure thereof can be used. For example, in the case where Si is used as the semiconductor films 4703a and 4703b and silicon oxide is formed as the insulating films 4721a and 4721b on the surfaces of the semiconductor films 4703a and 4703b by oxidizing the Si by plasma treatment, over the insulating films 4721a and 4721b Then, silicon oxide (SiOx) is formed as a gate insulating film. 48B-1 and 48B-2, the insulating films 4721a and 4721b formed by oxidizing or nitriding the semiconductor films 4703a and 4703b by plasma treatment are sufficient. The insulating films 4721a and 4721b can also be used as gate insulating films.

Next, a gate electrode 4705 and the like are formed over the gate insulating film 4704, so that a semiconductor device including an N-channel transistor 4710a and a P-channel transistor 4710b using the island-shaped semiconductor films 4703a and 4703b as channel regions is manufactured. (FIG. 48 (D-1), (D-2)).

In this manner, before the gate insulating film 4704 is provided over the semiconductor films 4703a and 4703b, the surface of the semiconductor films 4703a and 4703b is oxidized or nitrided by plasma treatment, so that the gate insulation in the end portions 4551a and 4751b of the channel region is obtained. A short-circuit between the gate electrode and the semiconductor film due to the coating failure of the film 4704 can be prevented. That is, when the end portion of the island-shaped semiconductor film has a shape close to a right angle (θ = 85 to 100 °), the gate insulating film is formed so as to cover the semiconductor film by a CVD method, a sputtering method, or the like. However, there is a possibility that a coating defect may occur due to disconnection of the gate insulating film at the edge of the semiconductor film. However, by oxidizing or nitriding the surface of the semiconductor film in advance using plasma treatment, the edge of the semiconductor film It is possible to prevent a defective coating of the gate insulating film at the portion.

In FIG. 48, the gate insulating film 4704 may be oxidized or nitrided by performing plasma treatment after the gate insulating film 4704 is formed. In this case, plasma treatment is performed on the gate insulating film 4704 (FIGS. 49A-1 and 49A-2) formed so as to cover the semiconductor films 4703a and 4703b, and the gate insulating film 4704 is oxidized or nitrided. Thus, an oxide film or a nitride film 4805 (hereinafter also referred to as an insulating film 4805) is formed on the surface of the gate insulating film 4704 (FIGS. 49B-1 and 49B-2). The conditions for the plasma treatment can be the same as in FIGS. 48B-1 and 48B-2. The insulating film 4805 contains a rare gas used for plasma treatment. For example, when Ar is used, the insulating film 4805 contains Ar.

Further, in FIGS. 49B-1 and 49-2, the gate insulating film 4704 is once oxidized by performing plasma treatment in an oxygen atmosphere, and then nitrided by performing plasma treatment again in a nitrogen atmosphere. You may let them. In this case, silicon oxide or silicon oxynitride (SiO _x N _y ) (x> y) is formed in the semiconductor films 4703a and 4703b, and silicon nitride oxide (SiN _x O _y ) (x> y is in contact with the gate electrode 4705. ) Is formed. After that, by forming the gate electrode 4705 and the like over the insulating film 4805, a semiconductor device including the N-channel transistor 4710a and the P-channel transistor 4710b using the island-shaped semiconductor films 4703a and 4703b as channel regions is manufactured. (FIGS. 49 (C-1) and (C-2)). In this manner, by performing plasma treatment on the gate insulating film, the surface of the gate insulating film is oxidized or nitrided, whereby the surface of the gate insulating film can be modified and a dense film can be formed. An insulating film obtained by plasma treatment is denser and has fewer defects such as pinholes than an insulating film formed by a CVD method or a sputtering method, so that the characteristics of the transistor can be improved.

Note that FIG. 49 illustrates the case where the semiconductor films 4703a and 4703b are previously subjected to plasma treatment to oxidize or nitride the surfaces of the semiconductor films 4703a and 4703b, but the semiconductor films 4703a and 4703b are subjected to plasma treatment. Alternatively, a method in which plasma treatment is performed after the gate insulating film 4704 is formed may be used. As described above, by performing the plasma treatment before forming the gate electrode, even if a coating failure occurs due to a step breakage of the gate insulating film at the end of the semiconductor film, the semiconductor film exposed due to the coating failure Therefore, short-circuit between the gate electrode and the semiconductor film due to poor coverage of the gate insulating film at the end of the semiconductor film can be prevented.

In this manner, even when the end portion of the island-shaped semiconductor film is provided in a shape that is nearly perpendicular, plasma treatment is performed on the semiconductor film or the gate insulating film to oxidize or nitride the semiconductor film or the gate insulating film. As a result, a short circuit between the gate electrode and the semiconductor film due to poor coverage of the gate insulating film at the end of the semiconductor film can be prevented.

Next, in the island-shaped semiconductor film provided over the substrate, the case where the end portion of the island-shaped semiconductor film is provided in a tapered shape (θ = 30 to 85 °) is described.

First, island-shaped semiconductor films 4703a and 4703b are formed over the substrate 4701 (FIGS. 50A-1 and 50A-2). The island-shaped semiconductor films 4703a and 4703b are formed using a material containing silicon (Si) as a main component (for example, Si _x ) by using a sputtering method, an LPCVD method, a plasma CVD method, or the like over an insulating film 4702 formed in advance on a substrate 4701. Ge _1-x etc.) is used to form an amorphous semiconductor film, and the amorphous semiconductor film is subjected to laser crystallization, thermal crystallization using an RTA or furnace annealing furnace, metal element for promoting crystallization The semiconductor film can be formed by crystallization by a crystallization method such as a thermal crystallization method using, and selectively removing the semiconductor film by etching. Note that in FIG. 50, an end portion of the island-shaped semiconductor film is provided in a tapered shape (θ = 30 to 85 °).

Next, a gate insulating film 4704 is formed so as to cover the semiconductor films 4703a and 4703b (FIGS. 50B-1 and 50B-2). The gate insulating film 4704 is formed using silicon oxide, silicon nitride, silicon oxynitride (SiO _x N _y ) (x> y), silicon nitride oxide (SiN _x O _y ) by sputtering, LPCVD, plasma CVD, or the like. A single-layer structure of an insulating film containing oxygen or nitrogen such as (x> y) or a stacked structure thereof can be used.

Next, plasma treatment is performed to oxidize or nitride the gate insulating film 4704, thereby forming an oxide film or a nitride film 4724 (hereinafter also referred to as an insulating film 4724) on the surface of the gate insulating film 4704 (FIG. C-1), (C-2)). The plasma treatment conditions can be the same as described above. For example, when silicon oxide or silicon oxynitride (SiO _x N _y ) (x> y) is used as the gate insulating film 4704, the gate insulating film 4704 is oxidized by performing plasma treatment in an oxygen atmosphere, whereby the gate insulating film A dense film with few defects such as pinholes can be formed on the surface of this film as compared with a gate insulating film formed by CVD or sputtering. On the other hand, by performing plasma treatment in a nitrogen atmosphere to nitride the gate insulating film 4704, silicon nitride oxide (SiN _x O _y ) (x> y) can be provided as the insulating film 4724 on the surface of the gate insulating film 4704. . Alternatively, the gate insulating film 4704 may be oxidized by once performing plasma treatment in an oxygen atmosphere and then nitrided by performing plasma treatment again in a nitrogen atmosphere. The insulating film 4724 contains a rare gas used for plasma treatment. For example, when Ar is used, the insulating film 4724 contains Ar.

Next, a gate electrode 4705 and the like are formed over the gate insulating film 4704, so that a semiconductor device including an N-channel transistor 4710a and a P-channel transistor 4710b using the island-shaped semiconductor films 4703a and 4703b as channel regions is manufactured. (FIG. 50 (D-1), (D-2)).

Thus, by performing plasma treatment on the gate insulating film, an insulating film made of an oxide film or a nitride film can be provided on the surface of the gate insulating film, and the surface of the gate insulating film can be modified. An insulating film oxidized or nitrided by plasma treatment is denser and has fewer defects such as pinholes than a gate insulating film formed by a CVD method or a sputtering method, so that transistor characteristics can be improved. it can. In addition, by forming the end portion of the semiconductor film in a tapered shape, a short circuit between the gate electrode and the semiconductor film due to poor coverage of the gate insulating film at the end portion of the semiconductor film can be suppressed. By performing plasma treatment after the formation, a short circuit between the gate electrode and the semiconductor film can be further prevented.

Next, a method for manufacturing a semiconductor device different from that in FIGS. Specifically, a case where plasma treatment is selectively performed on an end portion of a semiconductor film having a tapered shape is described.

First, island-shaped semiconductor films 4703a and 4703b are formed over the substrate 4701 (FIGS. 51A-1 and 51A-2). Island-shaped semiconductor films 4703a, 4703b is sputtering over the insulating film 4702 which is previously formed on the substrate 4701, LPCVD method, a material mainly composed of silicon (Si) by a plasma CVD method or the like (e.g., Si _x An amorphous semiconductor film is formed using Ge _1-x or the like, the amorphous semiconductor film is crystallized, and the semiconductor film is selectively etched using the resists 4725a and 4725b as masks. it can. The crystallization of the amorphous semiconductor film may be performed by laser crystallization, thermal crystallization using an RTA or furnace annealing furnace, thermal crystallization using a metal element that promotes crystallization, or a combination of these methods. The crystallization method can be used.

Next, before removing the resists 4725a and 4725b used for etching the semiconductor film, plasma treatment is performed to selectively oxidize or nitride the end portions of the island-shaped semiconductor films 4703a and 4703b. An oxide film or a nitride film 4726 (hereinafter also referred to as an insulating film 4726) is formed on end portions of the films 4703a and 4703b, respectively (FIGS. 51B-1 and 51B-2). The plasma treatment is performed under the conditions described above. The insulating film 4726 contains a rare gas used for plasma treatment.

Next, a gate insulating film 4704 is formed so as to cover the semiconductor films 4703a and 4703b (FIGS. 51C-1 and 51C-2). The gate insulating film 4704 can be provided in a manner similar to the above.

Next, a gate electrode 4705 and the like are formed over the gate insulating film 4704, so that a semiconductor device including an N-channel transistor 4710a and a P-channel transistor 4710b using the island-shaped semiconductor films 4703a and 4703b as channel regions is manufactured. (FIG. 51 (D-1), (D-2)).

In the case where the end portions of the semiconductor films 4703a and 4703b are provided in a tapered shape, the end portions 4752a and 4752b of the channel regions formed in part of the semiconductor films 4703a and 4703b are also tapered and the thickness of the semiconductor film or the gate insulating film Since the film thickness changes as compared with the central portion, the characteristics of the transistor may be affected. Therefore, here, by selectively oxidizing or nitriding an end portion of the channel region by plasma treatment and forming an insulating film in the semiconductor film which is the end portion of the channel region, a transistor caused by the end portion of the channel region The influence on can be reduced.

Note that although FIG. 51 shows an example in which oxidation or nitridation is performed by plasma treatment only on the end portions of the semiconductor films 4703a and 4703b, it goes without saying that the gate insulating film 4704 is also subjected to plasma treatment as shown in FIG. It is also possible to perform oxidation or nitridation (FIGS. 53A-1 and 53A-2).

Next, a method for manufacturing a semiconductor device different from the above is described with reference to drawings. Specifically, a case where plasma treatment is performed on a semiconductor film having a tapered shape is described.

First, island-shaped semiconductor films 4703a and 4703b are formed over the substrate 4701 in the same manner as described above (FIGS. 52A-1 and 52A-2).

Next, plasma treatment is performed to oxidize or nitride the semiconductor films 4703a and 4703b, whereby oxide or nitride films 4727a and 4727b (hereinafter also referred to as insulating films 4727a and 4727b) are formed on the surfaces of the semiconductor films 4703a and 4703b, respectively. (FIGS. 52B-1 and 52B-2). The plasma treatment can be similarly performed under the above-described conditions. For example, when Si is used for the semiconductor films 4703a and 4703b, silicon oxide (SiOx) or silicon nitride (SiNx) is formed as the insulating films 4727a and 4727b. Alternatively, the semiconductor films 4703a and 4703b may be oxidized by plasma treatment and then nitrided by performing plasma treatment again. In this case, silicon oxide or silicon oxynitride (SiO _x N _y ) (x> y) is formed in contact with the semiconductor films 4703a and 4703b, and silicon nitride oxide (SiN _x O _y ) (x> is formed on the surface of the silicon oxide. y) is formed. Therefore, the insulating films 4727a and 4727b contain a rare gas used for plasma treatment. Note that the end portions of the semiconductor films 4703a and 4703b are also oxidized or nitrided at the same time by performing plasma treatment.

Next, a gate insulating film 4704 is formed so as to cover the insulating films 4727a and 4727b (FIGS. 52C-1 and 52C-2). The gate insulating film 4704 is formed using silicon oxide, silicon nitride, silicon oxynitride (SiO _x N _y ) (x> y), silicon nitride oxide (SiN _x O _y ) by sputtering, LPCVD, plasma CVD, or the like. A single-layer structure of an insulating film containing oxygen or nitrogen such as (x> y) or a stacked structure thereof can be used. For example, when silicon oxide is formed as the insulating films 4727a and 4727b on the surfaces of the semiconductor films 4703a and 4703b by oxidizing Si as the semiconductor films 4703a and 4703b by plasma treatment, a gate is formed over the insulating films 4727a and 4727b. Silicon oxide is formed as an insulating film.

Next, a gate electrode 4705 and the like are formed over the gate insulating film 4704, so that a semiconductor device including an N-channel transistor 4710a and a P-channel transistor 4710b using the island-shaped semiconductor films 4703a and 4703b as channel regions is manufactured. (FIG. 52 (D-1), (D-2)).

When the end portion of the semiconductor film is provided in a tapered shape, the end portions 4753a and 4753b of the channel region formed in part of the semiconductor film are also tapered, which may affect the characteristics of the semiconductor element. Therefore, by oxidizing or nitriding the semiconductor film by plasma treatment, as a result, the end portion of the channel region is also oxidized or nitrided, so that the influence on the semiconductor element can be reduced.

Note that although FIG. 52 illustrates an example in which oxidation or nitridation is performed by plasma treatment only on the semiconductor films 4703a and 4703b, of course, as shown in FIG. 50, the gate insulating film 4704 is oxidized or oxidized by plasma treatment. Nitridation is also possible (FIGS. 53 (B-1) and (B-2)). In this case, after the gate insulating film 4704 is oxidized by performing plasma treatment once in an oxygen atmosphere, it may be nitrided by performing plasma treatment again in a nitrogen atmosphere. In this case, silicon oxide or silicon oxynitride (SiO _x N _y ) (x> y) is formed in the semiconductor films 4703a and 4703b, and silicon nitride oxide (SiN _x O _y ) (x> y is in contact with the gate electrode 4705. ) Is formed.

In this manner, by performing plasma treatment to oxidize or nitride the semiconductor film or the gate insulating film to modify the surface, a dense insulating film with good film quality can be formed. As a result, even when the insulating film is formed thin, defects such as pinholes can be prevented, and miniaturization and high performance of semiconductor elements such as transistors can be achieved.

Note that in this embodiment, the semiconductor films 4703a and 4703b or the gate insulating film 4704 in FIG. 47 are subjected to plasma treatment, and the semiconductor films 4703a and 4703b or the gate insulating film 4704 are oxidized or nitrided. The layer used for oxidation or nitridation is not limited to this. For example, plasma treatment may be performed on the substrate 4701 or the insulating film 4702, or plasma treatment may be performed on the insulating film 4706 or the insulating film 4707.

Note that the description in this embodiment can be implemented in free combination with the contents described in Embodiments 1 to 6.

(Embodiment 8)
In the present embodiment, hardware for controlling the driving method described in the first to fifth embodiments will be described.

A rough block diagram is shown in FIG. Over the substrate 6251, a pixel portion 6254, a signal line driver circuit 6256, and a scan line driver circuit 6255 are provided. In addition, a power supply circuit, a precharge circuit, a timing generation circuit, and the like may be arranged. Note that the signal line driver circuit 6256 and the scan line driver circuit 6255 are not necessarily provided. In that case, what is not arranged on the substrate 6251 may be formed in the IC. The IC may be disposed on the substrate 6251 by COG (Chip On Glass). Alternatively, an IC may be arranged on a connection board 6257 that connects the peripheral circuit board 6252 and the board 6251.

A signal 6253 is input to the peripheral circuit board 6252. Then, the controller 6258 controls to store the signals in the memories 6259 and 6250 and the like. In the case where the signal 6253 is an analog signal, it is often stored in the memories 6259 and 6250 after analog-digital conversion. Then, the controller 6258 outputs a signal to the substrate 6251 using the signal stored in the memories 6259 and 6250 and the like.

In order to realize the driving method described in Embodiments 1 to 5, the controller 6258 controls the appearance order of subframes and outputs a signal to the substrate 6251.

Note that the contents described in this embodiment mode can be implemented by being freely combined with the contents described in Embodiment Modes 1 to 7.

(Embodiment 9)
In this embodiment, a configuration example of an EL module and an EL television receiver using the display device of the present invention will be described.

FIG. 55 shows an EL module in which a display panel 6301 and a circuit board 6302 are combined. The display panel 6301 includes a pixel portion 6303, a scan line driver circuit 6304, and a signal line driver circuit 6305. On the circuit board 6302, for example, a control circuit 6306, a signal dividing circuit 6307, and the like are formed. The display panel 6301 and the circuit board 6302 are connected by a connection wiring 6308. An FPC or the like can be used for the connection wiring.

The control circuit 6306 corresponds to the controller 6208, the memories 6209, 6210, and the like in the eighth embodiment. Mainly, the control circuit 6306 controls the appearance order of subframes.

In the display panel 6301, a pixel portion and some peripheral driver circuits (a driver circuit having a low operating frequency among a plurality of driver circuits) are formed over a substrate using transistors, and some peripheral driver circuits (a plurality of driver circuits) are formed. A driver circuit having a high operating frequency among the circuits) is formed over the IC chip, and the IC chip is preferably mounted on the display panel 6301 by COG (Chip On Glass) or the like. Alternatively, the IC chip may be mounted on the display panel 6301 using TAB (Tape Automated Bonding) or a printed board.

In addition, by performing impedance conversion of a signal set to the scanning line or the signal line using a buffer, the pixel writing time for each row can be shortened. Therefore, a high-definition display device can be provided.

In order to further reduce power consumption, a pixel portion is formed using a transistor on a glass substrate, all signal line driver circuits are formed on an IC chip, and the IC chip is displayed on a COG (Chip On Glass) display. It may be mounted on a panel.

For example, the entire screen of the display panel is divided into several areas, and an IC chip in which a part or all of peripheral drive circuits (signal line drive circuit, scan line drive circuit, etc.) are formed is arranged in each area. (Chip On Glass) or the like may be mounted on the display panel. The structure of the display panel in this case is shown in FIG.

FIG. 56 shows an example in which the entire screen is divided into four areas and driven using eight IC chips. The structure of the display panel includes a substrate 6410, a pixel portion 6411, FPCs 6412a to 6412h, and IC chips 6413a to 6413h. Of the eight IC chips, signal line driver circuits are formed in 6413a to 6413d, and scanning line driver circuits are formed in 6413e to 6413h. Then, by driving an arbitrary IC chip, it is possible to drive only an arbitrary screen area among the four screen areas. For example, when only the IC chips 6413a and 6413e are driven, only the upper left area of the four screen areas can be driven. By doing so, it is possible to reduce power consumption.

An example of a display panel having another structure is shown in FIG. The display panel in FIG. 57 includes a pixel portion 6521 in which a plurality of pixels 6538 including sub-pixels 6530a and 6530b are arranged over a substrate 6520, a scanning line driver circuit 6522 for controlling signals of the scanning lines 6533a and 6533b, and a signal line 6531. A signal line driver circuit 6523 for controlling the above signals. In addition, a monitor circuit 6524 for correcting a luminance change of the light emitting elements 6537a and 6537b included in each of the sub pixels 6530a and 6530b may be provided. The light emitting elements 6537a and 6537b and the light emitting elements included in the monitor circuit 6524 have the same structure. The structures of the light-emitting elements 6537a and 6537b have a shape in which a layer containing a material that exhibits electroluminescence is sandwiched between a pair of electrodes.

In the periphery of the substrate 6520, an input terminal 6525 for inputting a signal from an external circuit to the scan line driver circuit 6522, an input terminal 6526 for inputting a signal from the external circuit to the signal line driver circuit 6523, and a signal to the monitor circuit 6524 are input. An input terminal 6529 is provided.

Each of the sub-pixels 6530a and 6530b includes transistors 6534a and 6534b connected to the signal line 6531, and transistors 6535a and 6535b connected in series between the power supply line 6532 and the light emitting elements 6537a and 6537b. The gates of the transistors 6534a and 6534b are connected to the scanning lines 6533a and 6533b, respectively, and when selected by the scanning signal, the signal of the signal line 6531 is input to the sub-pixels 6530a and 6530b. The input signal is supplied to the gates of the transistors 6535a and 6535b, and the storage capacitor portions 6536a and 6536b are charged. In response to this signal, the power supply line 6532 and the light emitting elements 6537a and 6537b are turned on, and the light emitting elements 6537a and 6537b emit light.

In order to cause the light emitting elements 6537a and 6537b provided in the sub-pixels 6530a and 6530b to emit light, it is necessary to supply power from an external circuit. A power supply line 6532 provided in the pixel portion 6521 is connected to an external circuit at an input terminal 6527. Since the power supply line 6532 has a resistance loss due to the length of the wiring to be routed, it is preferable to provide a plurality of input terminals 6527 in the periphery of the substrate 6520. The input terminals 6527 are provided at both ends of the substrate 6520 and are arranged so that luminance unevenness is not conspicuous in the plane of the pixel portion 6521. That is, it prevents the one side from being bright and the other side from being dark in the screen. In addition, the electrode on the side opposite to the electrode connected to the power supply line 6532 of the light-emitting elements 6537a and 6537b including a pair of electrodes is formed as a common electrode shared by the plurality of pixels 6538. In order to reduce the height, a plurality of terminals 6528 are provided.

Such a display panel is effective particularly when the screen size is increased because the power supply line is formed of a low resistance material such as Cu. For example, when the screen size is the 13-inch class, the length of the diagonal line is 340 mm, but when the screen size is the 60-inch class, the length is 1500 mm or more. In such a case, since the wiring resistance cannot be ignored, it is preferable to use a low resistance material such as Cu as the wiring. In consideration of wiring delay, signal lines and scanning lines may be formed in the same manner.

An EL television receiver can be completed with the EL module having the panel configuration as described above. FIG. 58 is a block diagram illustrating a main configuration of an EL television receiver. A tuner 6601 receives video signals and audio signals. The video signal includes a video signal amplifying circuit 6602, a video signal processing circuit 6603 that converts a signal output from the video signal into a color signal corresponding to each color of red, green, and blue, and uses the video signal as input specifications of the drive circuit. Processed by a control circuit 6306 for conversion. The control circuit 6306 outputs a signal to each of the scan line side and the signal line side. In the case of digital driving, a signal dividing circuit 6307 may be provided on the signal line side so that an input digital signal is divided into M pieces and supplied.

Of the signals received by the tuner 6601, the audio signal is sent to the audio signal amplifier circuit 6604, and the output is supplied to the speaker 6606 via the audio signal processing circuit 6605. The control circuit 6607 receives the receiving station (reception frequency) and volume control information from the input unit 6608 and sends a signal to the tuner 6601 and the audio signal processing circuit 6605.

A television receiver can be completed by incorporating an EL module into a housing. A display portion is formed by the EL module. In addition, speakers, video input terminals, and the like are provided as appropriate.

Of course, the present invention is not limited to a television receiver, and is applied to various uses as a display medium of a particularly large area such as a monitor of a personal computer, an information display board in a railway station or airport, an advertisement display board in a street, etc. can do.

As described above, by using the display device of the present invention and its driving method, a beautiful image with reduced pseudo contour can be viewed. Therefore, even an image whose gradation changes slightly like human skin can be displayed neatly.

Note that the content described in this embodiment mode can be freely combined with the content described in Embodiment Modes 1 to 8.

(Embodiment 10)
As an electronic device using the display device of the present invention, a video camera, a digital camera, a goggle type display (head mounted display), a navigation system, a sound reproduction device (car audio, audio component, etc.), a notebook personal computer, a game device, A portable information terminal (mobile computer, mobile phone, portable game machine, electronic book, etc.), an image playback device (specifically, Digital Versatile Disc (DVD)) provided with a storage medium is played back, and the image is displayed. A device provided with a display capable of displaying). Specific examples of these electronic devices are shown in FIGS.

FIG. 59A illustrates a light-emitting device, which includes a housing 6701, a supporting base 6702, a display portion 6703, a speaker portion 6704, a video input terminal 6705, and the like. The present invention can be used for a display device included in the display portion 6703. According to the present invention, a beautiful image with reduced pseudo contour can be viewed. Since the light-emitting device is a self-luminous type, a backlight is not necessary and a display portion thinner than a liquid crystal display can be obtained. The light emitting device includes all display devices for displaying information such as for personal computers, for receiving TV broadcasts, and for displaying advertisements.

FIG. 59B shows a digital still camera, which includes a main body 6706, a display portion 6707, an image receiving portion 6708, operation keys 6709, an external connection port 6710, a shutter 6711, and the like. The present invention can be used for a display device included in the display portion 6707, and according to the present invention, a clear image with reduced pseudo contour can be viewed.

FIG. 59C illustrates a laptop personal computer, which includes a main body 6712, a housing 6713, a display portion 6714, a keyboard 6715, an external connection port 6716, a pointing mouse 6717, and the like. The present invention can be used for a display device included in the display portion 6714, and according to the present invention, a beautiful image with reduced pseudo contour can be viewed.

FIG. 59D illustrates a mobile computer, which includes a main body 6718, a display portion 6719, a switch 6720, operation keys 6721, an infrared port 6722, and the like. The present invention can be used for a display device included in the display portion 6719, and according to the present invention, a clear image with reduced pseudo contour can be viewed.

FIG. 59E shows a portable image reproducing device (specifically, a DVD reproducing device) provided with a recording medium, which includes a main body 6723, a housing 6724, a display portion A 6725, a display portion B 6726, and a storage medium (such as a DVD). A reading unit 6727, operation keys 6728, a speaker unit 6729, and the like are included. The display unit A6725 mainly displays image information, and the display unit B mainly displays character information. The present invention can be used for a display device that constitutes the display portions A, B6725, and 6726, and according to the present invention, a beautiful image with reduced pseudo contour can be viewed. Note that an image reproducing device provided with a recording medium includes a home game machine and the like.

FIG. 59F shows a goggle type display (head mounted display), which includes a main body 6730, a display portion 6731, an arm portion 6732, and the like. The present invention can be used for a display device included in the display portion 6731. According to the present invention, a beautiful image with reduced pseudo contour can be viewed.

FIG. 59G shows a video camera, which includes a main body 6733, a display portion 6734, a housing 6735, an external connection port 6736, a remote control reception portion 6737, an image receiving portion 6738, a battery 6739, an audio input portion 6740, operation keys 6741, and the like. . The present invention can be used for a display device included in the display portion 6734, and according to the present invention, a beautiful image with reduced pseudo contour can be viewed.

FIG. 59H shows a cellular phone, which includes a main body 6742, a housing 6743, a display portion 6744, an audio input portion 6745, an audio output portion 6746, operation keys 6747, an external connection port 6748, an antenna 6749, and the like. The present invention can be used for a display device included in the display portion 6744. Note that the display portion 6744 can suppress current consumption of the mobile phone by displaying white characters on a black background. In addition, according to the present invention, it is possible to view a beautiful image with a reduced pseudo contour.

Note that if a light emitting material having high light emission luminance is used, light including output image information can be enlarged and projected by a lens or the like and used for a front type or rear type projector.

In addition, the electronic devices often display information distributed through electronic communication lines such as the Internet and CATV (cable television), and in particular, opportunities to display moving image information are increasing. Since the response speed of the light emitting material is very high, the light emitting device is preferable for displaying moving images.

In addition, since the light emitting device consumes power in the light emitting portion, it is desirable to display information so that the light emitting portion is minimized. Therefore, when a light emitting device is used for a display unit mainly including character information, such as a portable information terminal, particularly a mobile phone or a sound reproduction device, it is driven so that character information is formed by the light emitting part with the non-light emitting part as the background It is desirable to do.

As described above, the applicable range of the present invention is so wide that it can be used for electronic devices in various fields. In addition, the electronic device of this embodiment may use any display device having any structure shown in Embodiments 1 to 9.

FIG. 6 is a diagram illustrating an example of a subframe and subpixel selection method according to the driving method of the present invention. The figure which shows the effect that a pseudo contour reduces in the drive system of this invention. FIG. 6 is a diagram illustrating an example of a subframe and subpixel selection method according to the driving method of the present invention. The figure which shows the effect that a pseudo contour reduces in the drive system of this invention. FIG. 6 is a diagram illustrating an example of a subframe and subpixel selection method according to the driving method of the present invention. The figure which shows the effect that a pseudo contour reduces in the drive system of this invention. FIG. 6 is a diagram illustrating an example of a subframe and subpixel selection method according to the driving method of the present invention. The figure which shows the effect that a pseudo contour reduces in the drive system of this invention. FIG. 6 is a diagram illustrating an example of a subframe and subpixel selection method according to the driving method of the present invention. The figure which shows the effect that a pseudo contour reduces in the drive system of this invention. FIG. 6 is a diagram illustrating an example of a subframe and subpixel selection method according to the driving method of the present invention. The figure which shows the effect that a pseudo contour reduces in the drive system of this invention. FIG. 6 is a diagram illustrating an example of a subframe and subpixel selection method according to the driving method of the present invention. The figure which shows the effect that a pseudo contour reduces in the drive system of this invention. FIG. 6 is a diagram illustrating an example of a subframe and subpixel selection method according to the driving method of the present invention. The figure which shows the effect that a pseudo contour reduces in the drive system of this invention. FIG. 6 is a diagram illustrating an example of a subframe and subpixel selection method according to the driving method of the present invention. FIG. 6 is a diagram illustrating an example of a subframe and subpixel selection method according to the driving method of the present invention. FIG. 6 is a diagram illustrating an example of a subframe and subpixel selection method according to the driving method of the present invention. FIG. 6 is a diagram illustrating an example of a subframe and subpixel selection method according to the driving method of the present invention. The figure which shows an example of the selection method of a sub-frame and a sub-pixel at the time of performing a gamma correction with the drive system of this invention. The figure which shows the relationship between the gradation at the time of performing a gamma correction with the drive system of this invention, and a brightness | luminance. The figure which shows an example of the selection method of a sub-frame and a sub-pixel at the time of performing a gamma correction with the drive system of this invention. The figure which shows the relationship between the gradation at the time of performing a gamma correction with the drive system of this invention, and a brightness | luminance. The figure which shows an example of the timing chart in case the period which writes in the signal of a pixel, and the lighting period are isolate | separated. The figure which shows an example of a pixel structure in case the period which writes the signal of a pixel, and the lighting period are isolate | separated. The figure which shows an example of a pixel structure in case the period which writes the signal of a pixel, and the lighting period are isolate | separated. The figure which shows an example of a pixel structure in case the period which writes the signal of a pixel, and the lighting period are isolate | separated. The figure which shows an example of the timing chart in case the period which writes the signal of a pixel, and the lighting period are not isolate | separated. The figure which shows an example of a pixel structure in case the period which writes the signal of a pixel, and the lighting period are not isolate | separated. The figure which shows an example of the timing chart for selecting 2 rows during 1 gate selection period. FIG. 10 is a diagram illustrating an example of a timing chart in the case of performing an operation of erasing a pixel signal. FIG. 6 is a diagram illustrating an example of a pixel configuration in the case of performing an operation of erasing a pixel signal. FIG. 6 is a diagram illustrating an example of a pixel configuration in the case of performing an operation of erasing a pixel signal. FIG. 6 is a diagram illustrating an example of a pixel configuration in the case of performing an operation of erasing a pixel signal. FIG. 6 is a diagram showing an example of a pixel portion layout of a display device using the driving method of the present invention. FIG. 6 is a diagram showing an example of a pixel portion layout of a display device using the driving method of the present invention. FIG. 6 is a diagram showing an example of a pixel portion layout of a display device using the driving method of the present invention. FIG. 6 is a diagram showing an example of a pixel portion layout of a display device using the driving method of the present invention. FIG. 6 is a diagram showing an example of a pixel portion layout of a display device using the driving method of the present invention. FIG. 6 illustrates an example of a display device using a driving method according to the present invention. FIG. 6 illustrates an example of a display device using a driving method according to the present invention. FIG. 6 illustrates an example of a display device using a driving method according to the present invention. FIG. 14 illustrates an example of a structure of a display device of the present invention. FIG. 14 illustrates an example of a structure of a display device of the present invention. FIG. 14 illustrates an example of a structure of a display device of the present invention. 3A and 3B each illustrate a structure of a transistor used for a display device of the present invention. 4A and 4B illustrate a method for manufacturing a transistor used in a display device of the present invention. 4A and 4B illustrate a method for manufacturing a transistor used in a display device of the present invention. 4A and 4B illustrate a method for manufacturing a transistor used in a display device of the present invention. 4A and 4B illustrate a method for manufacturing a transistor used in a display device of the present invention. 4A and 4B illustrate a method for manufacturing a transistor used in a display device of the present invention. 4A and 4B illustrate a method for manufacturing a transistor used in a display device of the present invention. The figure which shows an example of the hardware which controls the drive system of this invention. The figure which shows an example of the EL module using the drive system of this invention. FIG. 11 illustrates a configuration example of a display panel using the driving method of the present invention. FIG. 11 illustrates a configuration example of a display panel using the driving method of the present invention. FIG. 6 is a diagram showing an example of an EL television receiver using the driving method of the present invention. FIG. 11 is a diagram showing an example of an electronic device to which the driving method of the present invention is applied. The figure which shows the state in which the pseudo contour generate | occur | produces in the conventional drive system. The figure which shows the state in which the pseudo contour generate | occur | produces in the conventional drive system. FIG. 14 illustrates an example of a structure of a display panel used in a display device of the present invention. FIG. 14 illustrates an example of a structure of a light-emitting element used for a display device of the present invention. FIG. 14 illustrates an example of a structure of a display device of the present invention. FIG. 14 illustrates an example of a structure of a display device of the present invention. FIG. 14 illustrates an example of a structure of a display device of the present invention. FIG. 14 illustrates an example of a structure of a display device of the present invention. FIG. 14 illustrates an example of a structure of a display device of the present invention.

Explanation of symbols

2611 Selection transistor 2612 Holding capacitor 2613 Driving transistor 2614 Light emitting element 2615 Signal line 2616 Power line 2617 Scanning line 2618 Power supply line 2621 Selection transistor 2622 Holding capacitor 2623 Driving transistor 2624 Light emitting element 2627 Scanning line 2628 Power line 2711 Selection transistor 2712 Holding capacitor 2713 Driving Transistor 2714 Light-emitting element 2715 Signal line 2716 Power line 2717 Scan line 2718 Power line 2721 Selection transistor 2722 Holding capacitor 2723 Driving transistor 2724 Light-emitting element 2725 Signal line 2728 Power line 2811 Selection transistor 2812 Holding capacitor 2813 Driving transistor 2814 Light-emitting element 2815 Signal line 2816 Power line 2817 Scan line 2818 Power line 2821 Jistor 2822 Retention capacitor 2823 Drive transistor 2824 Light emitting element 2827 Scanning line 2828 Power supply line 2836 Power supply line 3011 Selection transistor 3012 Retention capacitor 3013 Drive transistor 3014 Light emitting element 3015 Signal line 3016 Power supply line 3017 Scanning line 3018 Power supply line 3021 Selection transistor 3022 Retention capacitor 3023 Drive transistor 3024 Light emitting element 3025 Signal line 3027 Scan line 3028 Power line 3031 Select transistor 3037 Scan line 3041 Select transistor 3047 Scan line 3311 Select transistor 3312 Holding capacitor 3313 Drive transistor 3314 Light emitting element 3315 Signal line 3316 Power line 3317 Scan line 3318 Power line 3319 Erase transistor 3321 Select transistor 3322 Retention capacitance 33 3 driving transistor 3324 light emitting element 3327 scanning line 3328 power line 3329 erasing transistor 3337 scanning line 3347 scanning line 3411 selection transistor 3412 holding capacitor 3413 driving transistor 3414 light emitting element 3415 signal line 3416 power line 3417 scanning line 3418 power line 3419 erasing diode 3421 selection Transistor 3422 Storage capacitor 3423 Drive transistor 3424 Light emitting element 3427 Scan line 3428 Power line 3429 Erase diode 3437 Scan line 3447 Scan line 3519 Transistor 3605 Signal line 3606 Power line 3607 Scan line 3611 Select transistor 3612 Storage capacitor 3613 Drive transistor 3614 Electrode 3615 Signal line 3616 Power line 3617 Scan line 3711 Select transistor 371 Storage capacitor 3713 Drive transistor 3714 Electrode 3715 Signal line 3716 Power line 3717 Scan line 3813 Drive transistor 3915 Signal line 3916 Power line 3917 Scan line 4015 Signal line 4016 Power line 4017 Scan line 4027 Scan line 4037 Scan line 4101 Pixel portion 4102 Scan line drive Circuit 4103 Scanning line driving circuit 4104 Signal line driving circuit 4105 Shift register 4106 Amplifying circuit 4107 Shift register 4110 Amplifying circuit 4111 Scanning line 4121 Video signal line 4112 Scanning line 4122 Latch control line 4113 Signal line 4201 Pixel portion 4202 Scanning line driving circuit 4203 Scanning Line drive circuit 4204 Scan line drive circuit 4205 Scan line drive circuit 4206 Signal line drive circuit 4207 Scan line 4208 Scan line 4209 Scan line 4210 Scan line 4211 Signal line 4301 Pixel portion 4302 Scan line driver circuit 4303 Scan line driver circuit 4304 Signal line driver circuit 4305 Signal line driver circuit 4306 Scan line 4307 Scan line 4308 Signal line 4309 Signal line 601 Substrate 602 Base film 603 Channel formation region 604 LDD region 605 Impurity region 606 Channel formation region 607 LDD region 608 Impurity region 609 Gate insulating film 610 Gate electrode 611 Upper electrode 612 Interlayer insulating film 613 Wiring 614 Pixel electrode 615 Insulator 616 Layer 617 Counter electrode 618 Driving transistor 619 Capacitance element 620 Light emitting element 621 Region 622 Upper electrode 623 Capacitor element 701 Substrate 702 Base film 703 Channel formation region 704 LDD region 705 Impurity region 707 Gate electrode 708 Electrode 709 Interlayer insulating film 710 Line 711 Electrode 712 Interlayer insulating film 713 Pixel electrode 714 Electrode 716 Layer 717 Counter electrode 718 Drive transistor 719 Capacitor element 720 Light emitting element 801 Substrate 802 Base film 803 Gate electrode 804 Electrode 805 Gate insulating film 806 Channel formation region 807 LDD region 808 Impurity Region 809 Channel formation region 810 LDD region 811 Impurity region 812 Interlayer insulating film 813 Wiring 814 Electrode 815 Opening 816 Interlayer insulating film 817 Pixel electrode 818 Insulator 819 Layer 820 Counter electrode 821 Light emitting element 822 Driving transistor 823 Capacitance element 824 Electrode 825 Capacitor 4401 Substrate 4402 Base film 4403 Pixel electrode 4404 Electrode 4405 Wiring 4406 Wiring 4407 N-type semiconductor layer 4408 N-type semiconductor layer 4409 Semiconductor layer 4410 Gate Insulating film 4411 Insulating film 4412 Gate electrode 4413 Electrode 4414 Interlayer insulating film 4415 Layer 4416 Counter electrode 4417 Light emitting element 4418 Driving transistor 4419 Capacitor element 4420 Electrode 4501 Substrate 4502 Base film 4503 Gate electrode 4504 Electrode 4505 Gate insulating film 4506 Semiconductor layer 4507 Semiconductor Layer 4508 N-type semiconductor layer 4510 N-type semiconductor layer 4511 wiring 4513 conductive layer 4514 pixel electrode 4515 insulator 4516 layer 4517 counter electrode 4518 light-emitting element 4519 driving transistor 4520 capacitor element 4521 electrode 4522 capacitor element 4601 insulator 4701 substrate 4701 substrate 4702 Insulating film 4704 Gate insulating film 4705 Gate electrode 4706 Insulating film 4707 Insulating film 4708 Conductive film 4724 Nitride film 4724 Film 4726 Nitride film 4726 Insulating film 4805 Nitride film 4805 Insulating film 6208 Controller 6209 Memory 6251 Board 6252 Peripheral circuit board 6253 Signal 6254 Pixel 6255 Scan line driver circuit 6256 Signal line driver circuit 6257 Connection board 6258 Controller 6259 Memory 6301 Display panel 6302 Circuit Substrate 6303 Pixel portion 6304 Scan line driver circuit 6305 Signal line driver circuit 6306 Control circuit 6307 Signal dividing circuit 6308 Connection wiring 6410 Substrate 6411 Pixel portion 6520 Substrate 6521 Pixel portion 6522 Scan line driver circuit 6523 Signal line driver circuit 6524 Monitor circuit 6525 Input terminal 6526 Input terminal 6527 Input terminal 6528 Terminal 6529 Input terminal 6531 Signal line 6532 Power line 6538 Pixel 6601 Chu N 6602 Video signal amplification circuit 6603 Video signal processing circuit 6604 Audio signal amplification circuit 6605 Audio signal processing circuit 6606 Speaker 6607 Control circuit 6608 Input unit 6701 Case 6702 Base film 6702 Support base 6703 Display unit 6704 Speaker unit 6705 Video input terminal 6706 Gate Insulating film 6707 Display unit 6708 Image receiving unit 6709 Operation key 6710 External connection port 6711 Shutter 6712 Body 6713 Housing 6714 Display unit 6715 Keyboard 6716 External connection port 6717 Pointing mouse 6718 Body 6719 Display unit 6720 Switch 6721 Operation key 6722 Infrared port 6723 Body 6724 Housing 6725 Display unit A
6726 Display B
6727 section 6728 operation key 6729 speaker section 6730 main body 6730 display section 6732 arm section 6733 main body 6734 display section 6735 housing 6636 external connection port 6737 remote control receiving section 6638 image receiving section 6737 battery 6740 audio input section 6741 operation key 6742 body 6743 housing 6744 Display portion 6745 Audio input portion 6746 Audio output portion 6747 Operation key 6748 External connection port 6749 Antenna 4703a Semiconductor film 4703b Semiconductor film 4710a N-channel transistor 4710b P-channel transistor 4721a Nitride film 4721a Insulation film 4721b Insulation film 4725a Resist 4727a Nitride film 4727a Insulating film 4727b Insulating film 4751a End portion 4752a End portion 4753a End portion 6412a FPC
6413a IC chip 6530a Sub-pixel 6533a Scan line 6534a Transistor 6535a Transistor 6536a Storage capacitor portion 6537a Light emitting element 7301 Substrate 7302 Anode 7303 Hole injection layer 7304 Hole transport layer 7305 Light emission layer 7306 Electron transport layer 7307 Electron injection layer 7308 Cathode

Claims (17)

A driving method of a display device including a plurality of pixels including m sub-pixels (m is an integer of m ≧ 2) provided with light emitting elements,
The area ratio of the m sub-pixels is 2 ⁰ : 2 ¹ : 2 ² :...: 2 ^m−3 : 2 ^m−2 : 2 ^m−1
In the lighting period of the m subpixels, k subframe groups (k is an integer of k ≧ 2) including a plurality of subframes are provided in one frame,
In each of the k subframe groups, the lighting period length ratio is 2 ⁰ : 2 ^m : 2 ^2m :...: 2 ^{(n-3) m} : 2 ^{(n-2) m} : 2 ^(N−1) n (n is an integer of n ≧ 2) subframes that become ^m are provided,
In each of the k subframe groups, the appearance order of subframes having the same lighting period length is approximately the same,
A method for driving a display device, characterized in that, in the subframe, the gradation of the pixel is expressed by selecting a lighting state or a non-lighting state of the m subpixels. A driving method of a display device including a plurality of pixels including m sub-pixels (m is an integer of m ≧ 2) provided with light emitting elements,
The area ratio of the m sub-pixels is 2 ⁰ : 2 ¹ : 2 ² :...: 2 ^m−3 : 2 ^m−2 : 2 ^m−1
In the lighting period of the m subpixels, k subframe groups (k is an integer of k ≧ 2) including a plurality of subframes are provided in one frame,
The ratio of the length of the lighting period of the one frame is 2 ⁰ : 2 ^m : 2 ^2m :...: 2 ^{(n−3) m} : 2 ^{(n−2) m} : 2 ^{(n−1) m} Divided into n (n is an integer of n ≧ 2) first subframes,
Dividing each of the n first subframes into k second subframes having a lighting period of approximately 1 / k in length of the first subframe;
In each of the n first subframes, the second subframes divided into the k subframes have the same appearance order of the second subframes having the same lighting period length. One in each of the k subframe groups,
A driving method of a display device, characterized in that, in each of the second sub-frames, the gradation of the pixel is expressed by selecting a lighting state or a non-lighting state of the m sub-pixels. A driving method of a display device including a plurality of pixels including m sub-pixels (m is an integer of m ≧ 2) provided with light emitting elements,
The area ratio of the m sub-pixels is 2 ⁰ : 2 ¹ : 2 ² :...: 2 ^m−3 : 2 ^m−2 : 2 ^m−1
In the lighting period of the m subpixels, k subframe groups (k is an integer of k ≧ 2) including a plurality of subframes are provided in one frame,
The ratio of the length of the lighting period of the one frame is 2 ⁰ : 2 ^m : 2 ^2m :...: 2 ^{(n−3) m} : 2 ^{(n−2) m} : 2 ^{(n−1) m} Divided into n (n is an integer of n ≧ 2) first subframes,
Of the n first subframes, at least one first subframe is approximately 1 / (a × k) (a is an integer of a ≧ 2) in length. Divided into (a × k) second subframes having a lighting period,
In the n first subframes, each of the second subframes divided into (a × k) is arranged in a in each of the k subframe groups,
Each of the remaining first subframes of the n first subframes is divided into k second subframes having a lighting period of approximately 1 / k of the first subframe. And
In each of the remaining first subframes, each of the second subframes divided into k pieces is arranged in each of the k subframe groups, and
The divided second subframes are arranged so that the appearance order of the second subframes having the same lighting period length is approximately the same in each of the k subframe groups.
A driving method of a display device, characterized in that, in each of the second sub-frames, the gradation of the pixel is expressed by selecting a lighting state or a non-lighting state of the m sub-pixels. In claim 3,
Driving the display device, wherein the second subframe that divides the lighting period into (a × k) is a subframe having the longest lighting period among the n first subframes. Method. In any one of Claims 1 thru | or 4,
In the k subframe groups, the second subframes constituting the subframe groups are arranged in ascending order of lighting periods. In any one of Claims 1 thru | or 4,
In the k subframe groups, the second subframes constituting the subframe groups are arranged in descending order of lighting periods. In claim 5 or claim 6,
In each of the k subframe groups, at least one subframe of the second subframes having the longest lighting period among the second subframes constituting each of the subframe groups and the next And a second sub-frame having a long lighting period in reverse order. In any one of Claims 1 thru | or 7,
A display device driving method comprising: a gradation region in which the luminance of the pixel and the gradation are in a proportional relationship; and a gradation region in which the relationship between the luminance of the pixel and the gradation is nonlinear. Pixels including m sub-pixels (m is an integer of m ≧ 2) having an area ratio of 2 ⁰ : 2 ¹ : 2 ² :...: 2 ^m−3 : 2 ^m−2 : 2 ^m−1 A plurality of
Each of the m subpixels includes a light emitting element, a signal line, a scanning line, a first power supply line, a second power supply line, a selection transistor, and a drive transistor.
One of the source and drain electrodes of the selection transistor is electrically connected to the signal line, and the other is electrically connected to the gate electrode of the driving transistor,
One of the source and drain electrodes of the driving transistor is electrically connected to the first power supply line,
The light-emitting element includes a first electrode and a second electrode, and the first electrode is electrically connected to the other of the source and drain electrodes of the driving transistor, and the second electrode is the second electrode. Connected to the power line
In the lighting period of the m subpixels, k subframe groups (k is an integer of k ≧ 2) including a plurality of subframes are provided in one frame,
The ratio of the length of the lighting period of the one frame is 2 ⁰ : 2 ^m : 2 ^2m :...: 2 ^{(n−3) m} : 2 ^{(n−2) m} : 2 ^{(n−1) m} Divided into n (n is an integer of n ≧ 2) first subframes,
Dividing each of the n first subframes into k second subframes having a lighting period of approximately 1 / k in length of the first subframe;
In each of the n first subframes, the second subframes divided into the k subframes have the same appearance order of the second subframes having the same lighting period length. One in each of the k subframe groups,
In each of the second sub-frames, a gradation of the pixel is expressed by selecting a lighting state or a non-lighting state of the m sub-pixels. Pixels including m sub-pixels (m is an integer of m ≧ 2) having an area ratio of 2 ⁰ : 2 ¹ : 2 ² :...: 2 ^m−3 : 2 ^m−2 : 2 ^m−1 A plurality of
Each of the m subpixels includes a light emitting element, a signal line, a scanning line, a first power supply line, a second power supply line, a selection transistor, and a drive transistor.
One of the source and drain electrodes of the selection transistor is electrically connected to the signal line, and the other is electrically connected to the gate electrode of the driving transistor,
One of the source and drain electrodes of the driving transistor is electrically connected to the first power supply line,
The light-emitting element includes a first electrode and a second electrode, and the first electrode is electrically connected to the other of the source and drain electrodes of the driving transistor, and the second electrode is the second electrode. Connected to the power line
In the lighting period of the m subpixels, k subframe groups (k is an integer of k ≧ 2) including a plurality of subframes are provided in one frame,
The ratio of the length of the lighting period of the one frame is 2 ⁰ : 2 ^m : 2 ^2m :...: 2 ^{(n−3) m} : 2 ^{(n−2) m} : 2 ^{(n−1) m} Divided into n (n is an integer of n ≧ 2) first subframes,
Of the n first subframes, at least one first subframe is approximately 1 / (a × k) (a is an integer of a ≧ 2) in length. Divided into (a × k) second subframes having a lighting period,
In the n first subframes, each of the second subframes divided into (a × k) is arranged in a in each of the k subframe groups,
Each of the remaining first subframes of the n first subframes is divided into k second subframes having a lighting period of approximately 1 / k of the first subframe. And
In each of the remaining first subframes, each of the second subframes divided into k pieces is arranged in each of the k subframe groups, and
The divided second subframes are arranged so that the appearance order of the second subframes having the same lighting period length is approximately the same in each of the k subframe groups.
In each of the second sub-frames, a gradation of the pixel is expressed by selecting a lighting state or a non-lighting state of the m sub-pixels. In claim 9 or claim 10,
The display device, wherein the m sub-pixels share the signal line. In any one of Claim 9 thru | or Claim 11,
The display device, wherein the m sub-pixels share the scanning line. In any one of Claim 9 or Claim 12,
The display device, wherein the m sub-pixels share at least one of the first power supply line or the second power supply line. In claim 9 or claim 10,
The number of the signal lines of the pixel is 2 or more and m or less;
The display device, wherein the selection transistor included in any one of the m sub-pixels is electrically connected to the signal line different from the selection transistor included in another sub-pixel. In any one of Claim 9, Claim 10, and Claim 14,
The number of the scanning lines of the pixel is 2 or more;
The display device, wherein the selection transistor included in any one of the m sub-pixels is electrically connected to the scanning line different from the selection transistor included in another sub-pixel. In any one of Claim 9, Claim 10, Claim 14, and Claim 15,
The number of the first power supply lines of the pixel is 2 or more and m or less,
The drive transistor included in any one of the m sub-pixels is electrically connected to the first power supply line different from the drive transistors included in the other sub-pixels. Display device. An electronic apparatus comprising the display device according to any one of claims 9 to 16.

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