JP2007082355A - Control unit for inverter - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a control unit for an inverter, capable of a reliable and stable drive without restriction of a voltage zero vector in generating PWM (Pulse Width Modulation) signal on the basis of direct current flowing through a bus bar of an inverter main circuit, and also without a restriction of detecting momentary current information in a first half period of one carrier period of the PWM signal and detecting the remaining momentary current information in a second half period of the one carrier period. <P>SOLUTION: An inverter control portion 7A includes: a device 14 for determining to or not to provide the PWM signal to the inverter main circuit 2 after shifting the PWM signal from a PWM signal generator 13A every carrier period, a device 15 for shifting the PWM signal, which was determined to be shifted, so as to increase a number of phase current information obtained from direct current which is detected by a direct current detector Q in one carrier period, and a device 16 for creating a timing to detect the phase current information from the direct current based on the PWM signal which is eventually transmitted to the inverter main circuit 2. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an inverter control device that converts a DC power into a three-phase AC power using a plurality of semiconductor switching elements, and more particularly, a three-phase PWM (pulse width modulation) that defines a switching state of the plurality of semiconductor switching elements. The present invention relates to an inverter control device that generates a signal by detecting a direct current flowing in a bus of an inverter main circuit.

  In general, an inverter control device arranges three sets of two semiconductor switching elements connected in series between a bus connected to a positive electrode end and a bus connected to a negative electrode end of a DC power supply in parallel. An inverter main circuit that outputs a drive signal from the connection end to the three-phase motor, and a current value for three phases that the inverter main circuit supplies to the three-phase motor, and two voltage zero vectors having no vector length based thereon And an inverter controller that generates a three-phase PWM signal composed of a combination of six voltage vectors having a vector length in each carrier cycle and drives the plurality of semiconductor switching elements on and off. The present invention relates to an improvement of an inverter control unit.

  By the way, in order to simplify the configuration of the current detection means for obtaining the current values for the three phases generated by the inverter main circuit, the inverter main circuit is not detected but the actual drive current to the three-phase motor is detected. When detecting a direct current flowing in the bus on the positive or negative side of the circuit, phase current information for two phases cannot be detected from the direct current during one carrier cycle.

  Therefore, for example, in Patent Document 1, it is connected between the DC power supply and the inverter main circuit, one instantaneous current information is detected in the first half of one carrier cycle of the PWM signal, and the remaining instantaneous current information is detected by one carrier. One current detection means for detecting in the second half of the cycle and one of two voltage zero vectors in one carrier cycle of the PWM signal are generated in the first half of one carrier cycle, and the remaining voltage zero vector is set to 1 Voltage vector generating means for generating in the second half of the carrier cycle, and generating the voltage zero vector after the instantaneous current detection or generating the voltage zero vector before the instantaneous current detection. An inverter control device is disclosed in which no voltage zero vector is generated.

Japanese Patent No. 3610897

  However, the above conventional inverter control device generates one of two voltage zero vectors in one carrier cycle in the first half of one carrier cycle, and generates the remaining voltage zero vector in the second half of one carrier cycle. Therefore, when the voltage zero vector occupies a large ratio as in the low-rotation region, there is a problem that the control as expected cannot be performed when one voltage zero vector is in a state over a half carrier period or more.

  Also, since one instantaneous current information is detected in the first half cycle of one carrier cycle of the PWM signal and the remaining instantaneous current information is detected in the second half cycle of one carrier cycle, the time difference between the two instantaneous current detection timings There is a possibility that the controllability is deteriorated due to the influence of the difference in detection timing, particularly in the high rotation region.

  In addition, since two voltage zero vectors are always required to generate a PWM signal, there is also a problem that it is not possible to cope with a two-phase modulation method including only one voltage zero vector.

  In short, in the conventional inverter control device, when generating a PWM signal based on the direct current flowing through the bus of the inverter main circuit, there is a restriction of the voltage zero vector, and one instantaneous current information is converted into one carrier cycle of the PWM signal. There is a problem that reliable and stable operation cannot be performed because the detection is performed in the first half cycle and the remaining instantaneous current information is detected in the second half cycle of one carrier cycle.

  The present invention has been made in view of the above. When a PWM signal is generated based on a direct current flowing through a bus of an inverter main circuit, one instantaneous current can be obtained without being restricted by a voltage zero vector. Inverter control device capable of realizing reliable and stable operation without being restricted by detecting information in the first half of one carrier cycle of the PWM signal and detecting remaining instantaneous current information in the second half of one carrier cycle The purpose is to obtain.

  In order to achieve the above-described object, the present invention provides DC power supplied by the DC power supply using a plurality of semiconductor switching elements disposed between DC buses connected to the positive electrode end and the negative electrode end of the DC power supply, respectively. An inverter control device comprising an inverter main circuit for converting into three-phase AC power and an inverter control unit for controlling the inverter main circuit, wherein the inverter control unit detects a DC current flowing in one of the DC buses. Means, timer value calculation means for calculating a timer value of each phase based on phase current information obtained from the DC current detected by the DC current detection means, and each phase obtained by the timer value calculation means PMW signal generating means for generating a PWM signal for on / off control of the plurality of semiconductor switching elements based on the timer value of PWM signal shift determining means for determining whether or not to supply the inverter main circuit after shifting the PWM signal for each carrier period, and determining that the PWM signal shift determining means shifts and outputs the PWM signal Based on the PWM signal shifting means for shifting the PWM signal so that the number of phase current information obtained from the DC current increases within one carrier period, and finally the PWM signal supplied to the inverter main circuit And a detection timing generation means for generating a timing for detecting the phase current information from the direct current.

  According to the present invention, it is possible to obtain an inverter control device that is not restricted by the voltage zero vector, and the ratio of the voltage zero vector is large as in the low rotation region, and one voltage zero vector exceeds a half carrier period. Control is possible even in the case of In addition, it is possible to eliminate the control restriction that one instantaneous current information is detected in the first half period of one carrier period of the PWM signal and the remaining instantaneous current information is detected in the second half period of one carrier period. The deterioration of controllability due to the timing difference can be suppressed as much as possible. And it can respond also to the two phase modulation system which can reduce the switching loss in an inverter main circuit.

  According to the present invention, even when a PWM signal is generated based on a direct current flowing through the bus of the inverter main circuit, there is an effect that an inverter control device that can realize reliable and stable operation is obtained.

  Exemplary embodiments of an inverter control device according to the present invention will be described below in detail with reference to the drawings.

Embodiment 1 FIG.
1 is a block diagram showing a configuration of an inverter control apparatus according to Embodiment 1 of the present invention. The inverter control device shown in FIG. 1 includes an inverter main circuit 2 in which a DC power source 1 is connected to an input terminal and a three-phase motor 3 is connected to an output terminal, and the inverter main circuit 2 based on the operating state of the inverter main circuit 2. And an inverter control unit 7A for driving the three-phase motor 3 to a desired operation state.

  The inverter main circuit 2 includes three sets of two semiconductor switching elements “SW1, SW4” and “DC” connected in series between a DC bus P connected to the positive terminal of the DC power source 1 and a DC bus N connected to the negative terminal. A switching circuit provided with SW2, SW5 and SW3, SW6 in parallel, and a PWM signal “UP, UN, VP, VN, WP, which is a drive signal from the inverter control unit 7A, although not shown, each semiconductor switching element. , WN "to drive on / off. Flywheel diodes D1 to D6 are connected in antiparallel to each semiconductor switching element.

  The series connection ends of the three sets of semiconductor switching elements “SW1, SW4”, “SW2, SW5”, “SW3, SW6” convert the DC power of the DC power supply 1 into AC power of a three-phase pseudo sine wave and output it. The three-phase motor 3 is connected. In the example shown in FIG. 1, each semiconductor switching element is configured by a power switching element IGBT having an insulated gate. Moreover, the inverter main circuit 2 is comprised by IPM (Intelligent Power Module), for example.

  The three-phase motor 3 includes a three-phase Y-connected stator 3a composed of a U phase, a V phase, and a W phase, and a permanent magnet rotor 3b.

  As a means for taking in the operation state of the inverter main circuit 2 into the inverter control unit 7A, in FIG. 1, a detection element (in the illustrated example) for detecting a DC current flowing toward the DC power source 1 in the DC bus N on the negative electrode side. A DC current amplifier circuit 5 (see FIG. 2) to which a voltage drop at the resistor 4 is input, and a DC voltage (bus voltage) of the DC power supply 1 is detected. A voltage detection circuit 6 (see FIG. 3) is provided.

  FIG. 2 is a circuit diagram illustrating a configuration example of the DC current amplifier circuit 5. For example, as shown in FIG. 2, the DC current amplifier circuit 5 is composed of a non-inverting amplifier circuit composed of an OP amplifier 5a and resistance elements 5b and 5c, and DC current information (bus line) obtained by amplifying the voltage drop at the resistor 4 (Current) idc is applied to the A / D conversion circuit 8 in the inverter control section 7A. The resistor 4 and the DC current amplifier circuit 5 constitute a DC current detecting means Q as a whole.

  FIG. 3 is a circuit diagram showing a configuration example of the DC voltage detection circuit 6. For example, as shown in FIG. 3, the DC voltage detection circuit 6 divides the DC voltage (bus voltage) of the DC power supply 1 by resistance elements 6a and 6b connected in series, and smoothes the divided voltage by a capacitor 6c. The DC voltage information vdc thus obtained is supplied to the A / D conversion circuit 9 in the inverter control unit 7A.

  The inverter control unit 7A is based on the frequency command f * input from the outside, the DC current information idc detected by the DC current detection means Q, and the DC voltage information vdc detected by the DC voltage detection circuit 6. Thus, PWM signals “UP, UN, VP, VN, WP, WN” for driving on / off the semiconductor switching elements SW1 to SW6 of the inverter main circuit 2 are generated. The PWM signals “UP, VP, WP” are signals for driving the upper arm side semiconductor switching elements SW1, SW2, SW3 connected to the DC bus P of the inverter main circuit 2, and the PWM signals “UN, VN”. , WN ”is a signal for driving the semiconductor switching elements SW4, SW5, SW6 on the lower arm side connected to the DC bus N of the inverter main circuit 2.

  The inverter control unit 7A includes the A / D conversion circuits 8 and 9, the direct current / phase current conversion means 10, the voltage command value / phase command value calculation means 11A, the timer value calculation means 12, the PWM signal generation means 13A, PWM A signal shift determination unit 14, a PWM signal shift unit 15, a detection timing generation unit 16, and a voltage vector information holding unit 17 are provided. Each of these means can be realized by a microprocessor, for example.

  The detection timing generation means 16 is based on the PWM signal “UP, UN, VP, VN, WP, WN” that is finally supplied to the inverter main circuit 2, and the A / D conversion trigger timing of the A / D conversion circuit 8. Are generated in one carrier cycle (Trg1, Trg2).

  The A / D conversion circuit 8 digitally converts the DC current information idc detected by the DC current detection means Q at the trigger timings Trg1 and Trg2 generated by the detection timing generation means 16, and the DC current information Idc1 at the trigger timing Trg1 And DC current information Idc2 at the trigger timing Trg2 are supplied to the DC current / phase current conversion means 10. In this way, two DC current information Idc1 and Idc2 are obtained in one carrier cycle from one DC current information idc detected by the DC current detecting means Q.

  On the other hand, the A / D conversion circuit 9 digitally converts the DC voltage information vdc detected by the DC voltage detection circuit 6 at every certain time interval (for example, 10 μs) regardless of the operation of the A / D conversion circuit 8. The converted DC voltage information Vdc is supplied to the voltage command value / phase command value calculation means 11A.

  The voltage vector information holding means 17 is based on the PWM signal “UP, UN, VP, VN, WP, WN” that is finally supplied to the inverter main circuit 2, and the voltage vector information Va at the two rig timings Trg1, Trg2. , Vb.

  The DC current / phase current conversion means 10 is the voltage vector at the trigger timings Trg1 and Trg2 held by the voltage vector information holding means 17 with the DC current information Idc1 and Idc2 A / D converted at the trigger timings Trg1 and Trg2. The information Va, Vb is converted into phase current information for two phases every carrier period. The phase current information for the remaining one phase is calculated from the detected phase current information for the two phases. Here, even a high-speed A / D conversion has a processing time of about several μs, and this is one factor of restrictions when converting DC current information to phase current information. Therefore, in this embodiment, an A / D conversion circuit 8 used exclusively for DC current and an A / D conversion circuit 9 used exclusively for DC voltage are provided.

  The voltage command value / phase command value calculating means 11A is configured, for example, as shown in FIG. 4, and the phase current information Iu, Iv, Iw for three phases converted by the DC current / phase current converting means 10 and A The voltage command value V * and the phase command value θ * are calculated from the DC voltage information Vdc converted by the / D conversion circuit 9 and the frequency command f * input from the outside. give.

  FIG. 4 is a block diagram showing a configuration example of the voltage command value / phase command value calculating means 11A. For example, as shown in FIG. 4, the voltage command value / phase command value calculation means 11A includes a three-phase / two-phase coordinate conversion means 11a, a frequency / phase estimation means 11b, a frequency comparison means 11c, a d-axis current command value. Calculation means 11d, d-axis current comparison means 11e, q-axis current command value calculation means 11f, q-axis current comparison means 11g, dq-axis voltage command value calculation means 11h, voltage command value calculation means 11i, phase A command value calculation unit 11j, a dq conversion phase calculation unit 11k, and a dq conversion phase holding unit 11L are provided.

  In FIG. 4, the three-phase / two-phase coordinate conversion means 11a holds the phase current information Iu, Iv, Iw for three phases converted by the direct current / phase current conversion means 10 in the dq conversion phase holding means 11L. Conversion to d-axis current Id and q-axis current Iq is performed based on dq conversion phase θdq. The converted d-axis current Id and q-axis current Iq are input to the frequency / phase estimation means 11b. Also, the converted d-axis current Id is input to the d-axis current comparison unit 11e. On the other hand, the converted q-axis current Iq is input to the d-axis current command value calculation means 11d and the q-axis current comparison means 11g.

  The frequency / phase estimation unit 11b estimates the execution frequency f and the phase θ of the magnetic pole position of the permanent magnet rotor 3b from the d-axis current Id and the q-axis current Iq. The estimated execution frequency f is input to the frequency comparison unit 11c, the phase command value calculation unit 11j, and the dq conversion phase calculation unit 11k. The estimated phase θ is input to the phase command value calculation means 11j and the dq conversion phase calculation means 11k.

  The dq conversion phase calculation means 11k obtains the dq conversion phase θdq from the execution frequency f and the phase θ, and gives and holds it to the dq conversion phase holding means 11L.

  The frequency comparison unit 11c obtains a frequency error ferr between the frequency command f * supplied from the outside and the estimated execution frequency f, and supplies it to the q-axis current command value calculation unit 11f. The q-axis current command value calculation means 11f obtains the q-axis current command value Iq * from the frequency error ferr and gives it to the q-axis current comparison means 11g. The q-axis current comparison unit 11g obtains a q-axis current error Iqerr between the q-axis current command value Iq * and the q-axis current Iq, and gives it to the dq-axis voltage command value calculation unit 11h.

  Further, the d-axis current command value calculation means 11d obtains a d-axis current command value Id * from the q-axis current Iq and gives it to the d-axis current comparison means 11e. The d-axis current comparison unit 11e obtains a d-axis current error Iderr between the d-axis current command value Id * and the d-axis current Id, and supplies it to the dq-axis voltage command value calculation unit 11h.

The dq-axis voltage command value calculation means 11h obtains a d-axis voltage command value Vd * and a q-axis voltage command value Vq * from the d-axis current error Iderr and the q-axis current error Iqerr, and gives them to the voltage command value calculation means 11i. The voltage command value calculation means 11i applies the d-axis voltage command value Vd *, the q-axis voltage command value Vq *, and the DC voltage information Vdc input from the A / D conversion circuit 9 to the following equation (1). A voltage command value V * consisting of a normalized value is obtained and given to the timer value calculation means 12.
Voltage command value V * = √2 × √ (Vd * ² + Vq * ² ) / Vdc (1)

  Further, the phase command value calculation means 11 j obtains a phase command value θ * that gives the phase of the timing at which the actual PWM signal is output from the execution frequency f and the phase θ, and gives it to the timer value calculation means 12.

  Next, in FIG. 1, the timer value calculation means 12 defines the pulse width of the PWM signal from the voltage command value V * and the phase command value θ * calculated by the voltage command value / phase command value calculation means 11A. The timer values (Tu, Tv, Tw) of each phase to be calculated are calculated and output to the PWM signal generating means 13A. Note that Tu is a U-phase timer value, Tv is a V-phase timer value, and Tw is a W-phase timer value. Here, the timer value is a section where the total phase is 30 ° before and after the maximum phase of the phase voltage fundamental wave in each phase is 60 °, and a section where the total phase is 30 ° before and after the minimum phase of the phase voltage fundamental wave is 60 °. Are calculated on the basis of a two-phase modulation method for controlling so as not to switch.

  The PWM signal generation unit 13A drives the semiconductor switching elements SW1 to SW6 of the inverter main circuit 2 on and off based on the timer values (Tu, Tv, Tw) of each phase calculated by the timer value calculation unit 12. PWM signal “UP, UN, VP, VN, WP, WN” is generated and applied to the PWM signal shift determination means 14.

  The PWM signal shift determination means 14 is the target of determination among the three-phase PWM signals “UP, UN, VP, VN, WP, WN” generated by the PWM signal generation means 13 for each carrier period. It is determined whether or not to shift the PWM signal based on the pulse width and pulse width difference of the PWM signal for the phase, and the determination result is sent to the PWM signal shift means 15, the detection timing generation means 16, and the voltage vector information holding means 17. The following operation is performed according to the determination result.

  That is, when the PWM signal shift determination means 14 does not determine that the shift is to occur, the PWM signal “UP, UN, VP, VN, WP, WN” generated by the PWM signal generation means 13A is directly compared with the voltage detected by the detection timing generation means 16. This is supplied to the vector information holding means 17 and directly to the inverter main circuit 2.

  On the other hand, when the PWM signal shift determination means 14 determines to shift, the PWM signal “UP, UN, VP, VN, WP, WN” generated by the PWM signal generation means 13 A is output to the PWM signal shift means 15. . The PWM signal shift means 15 increases the number of phase current information obtained from the direct current within one carrier period for the PWM signal “UP, UN, VP, VN, WP, WN” input from the PWM signal shift determination means 14. The shifted PWM signal “UP, UN, VP, VN, WP, WN” is output to the detection timing generation means 16 and the voltage vector information holding means 17 and supplied to the inverter main circuit 2.

  That is, the PWM signal “UP, UN, VP, VN, WP, WN” finally supplied to the inverter main circuit 2 is input to the detection timing generation unit 16 and the voltage vector information holding unit 17.

  Next, the operation of the inverter control unit 7A will be described. In the semiconductor switching elements SW1 to SW6 of the inverter main circuit 2, either the upper arm side semiconductor switching elements SW1, SW2, SW3 are turned on or the lower arm side semiconductor switching elements SW4, SW5, SW6 are turned on. Since there are three phases, there are eight types of switching states in total. This is the output state to the three-phase motor 3.

  FIG. 5 is a vector diagram for explaining the relationship between the basic voltage vector and the voltage command value V * and the phase command value θ * generated by the voltage command value / phase command value calculation means 11A. In FIG. 5, V0 to V7 are basic voltage vectors that define the above-described eight switching states of the semiconductor switching elements SW1 to SW6 of the inverter main circuit 2. Among them, basic voltage vectors V1 to V6 arranged at intervals of 60 ° are voltage vectors having a vector length, and basic voltage vectors V0 and V7 indicated at the origin position are voltage zero vectors having no vector length. . In FIG. 5, when the direction of the voltage vector V4 is a reference phase, and the rotation direction of the phase is a clockwise direction (V4 → V6 → V2 → V3 → V1 → V5 → V4), the voltage vector V4 to the voltage vector The state where the voltage command value V * is obtained at the position rotated by the phase command value θ * in the direction of V6 is shown. When the magnitude of the voltage vector V4 is 1, the magnitude of the voltage command value V * is 0.5.

  FIG. 6 is a diagram collectively showing the relationship between the eight types of basic voltage vectors and the switching states of the semiconductor switching elements SW1 to SW6. As shown in FIG. 6, when the voltage zero vector V0, the upper arm side semiconductor switching elements SW1, SW2, SW3 are all in the OFF state, and the lower arm side semiconductor switching elements SW4, SW5, SW6 are both in the ON state. Become. On the contrary, when the voltage is zero vector V7, the upper arm side semiconductor switching elements SW1, SW2, and SW3 are both turned on, and the lower arm side semiconductor switching elements SW4, SW5, and SW6 are both turned off. When the voltage vectors are V1 to V6, at least one of the upper arm side semiconductor switching elements SW1, SW2, and SW3 and at least one of the lower arm side semiconductor switching elements SW4, SW5, and SW6 are in the ON state. For example, when the voltage vector is V4, the semiconductor switching elements SW1, SW5, and SW6 are turned on, and the semiconductor switching elements SW2, SW3, and SW4 are turned off.

  The timer value calculation means 12 sets timer values (Tu, Tv, Tw) as shown in FIG. FIG. 7 is a time chart for explaining the operation of the timer value calculation means 12. In FIG. 7, when the magnitude of the voltage command value V * input from the voltage command value / phase command value calculating means 11A is 0.5 as shown in FIG. 5, (a) the phase command value θ * and The relationship between (b) nodes and (c) each phase timer value (Tu, Tv, Tw) is shown.

  In FIG. 7, (a) the phase command value θ * is a reference phase (0 ° in the illustrated example) when the voltage command value V * is at the position of the voltage vector V4 as described in FIG. And repeat rotating clockwise. (B) The node is composed of 12 nodes “node 1” to “node 12” in which an angle range of 360 ° in which the phase command value θ * rotates once from the reference phase 0 ° is divided every 30 °. The (C) Each phase timer value (Tu, Tv, Tw) is set as follows using these 12 nodes. Tmax is the maximum value of the timer value, and the minimum value is 0 (zero).

  That is, when the phase command value θ * is the reference phase 0 ° (position of the voltage vector V4), the voltage fundamental wave of the U-phase voltage becomes the maximum value, and therefore, the interval of 30 ° before and after the reference phase 0 ° is defined. The U-phase timer value Tu = Tmax is fixed at the nodes 1 and 12, and the U-phase timer value Tu is set at the nodes 6 and 7 that define the interval of 30 ° before and after 180 ° (position of the voltage vector V3) of the opposite phase. = 0 is fixed. Further, when the phase command value θ * is the phase 120 ° (position of the voltage vector V2), the voltage fundamental wave of the V-phase voltage becomes the maximum value, so that the node 4 that defines the section of 30 ° before and after the phase 120 ° 4 5, the V-phase timer value Tv is fixed at Tmax, and the V-phase timer value Tv is set to 0 when the nodes 10 and 11 define an interval of 30 ° before and after 300 ° of the opposite phase (the position of the voltage vector V5). In addition, when the phase command value θ * is the phase 240 ° (position of the voltage vector V1), the voltage fundamental wave of the W-phase voltage becomes the maximum value, so the interval of 30 ° before and after the phase 240 ° is specified. W-phase timer value Tw = Tmax is fixed at nodes 8 and 9, and W-phase timer value is set at nodes 2 and 3 that define a section of 30 ° before and after 60 ° (position of voltage vector V6) of opposite phase. Tw is fixed to 0. The rest at each node Timer value, the voltage between the lines on the basis of the two-phase modulation scheme is to be set by calculating as a sine wave.

  Here, FIG. 8 is a diagram for explaining the relationship between the node and the carrier determined as shown in FIG. As shown in FIG. 8, (b) the carrier is switched (a) every node "12,1" "2,3" "4,5" "6,7" "8,9" "10,11" Is done. The processing in the inverter control unit 7A other than the A / D conversion circuits 8 and 9 is performed when the node is “1, 4, 5, 8, 9, 12” and the carrier valley timing is used as the calculation start timing. Is "2, 3, 6, 7, 10, 11", the carrier peak timing is used as the calculation start timing.

  Next, the operation of the PWM signal generation unit 13A will be described with reference to FIGS. FIG. 9 shows the operation and voltage vector state in the PWM signal generation means 13A in one carrier cycle when the node = 1. FIG. 10 shows the operation and voltage vector state in the PWM signal generating means 13A in one carrier cycle when the node = 2.

  In FIG. 9, the relationship between the carrier and each phase timer value shown in (a) is as follows. In the case of one carrier cycle, when node = 1, as described above, the rising interval from the minimum value of the first half to the maximum value and the falling value from the maximum value to the minimum value of the second half are based on the peak timing of the carrier 20 It consists of a section. In this case, since the U-phase timer value Tu is fixed at Tmax, it is at the position of the maximum value of the carrier 20. On the other hand, the W-phase timer value Tw is at, for example, the center position between the minimum value and the maximum value of the carrier 20, and the V-phase timer value Tv is closer to the maximum value side of the carrier 20 than the W-phase timer value Tw. It is required in relation to the raised position.

  The PWM signals “UP, UN, VP, VN, WP, WN” shown in FIG. 9B are generated as follows. The PWM signal UP is generated to maintain the “1” level for one carrier cycle, and the PWM signal UN is generated to maintain the “0” level for one carrier cycle. This means that the upper arm side semiconductor switching element SW1 is turned on and the lower arm side semiconductor switching element SW4 is turned off.

  The PWM signal VP is “1” level until the timer 20 reaches the timer value Tv in the process where the carrier 20 rises toward the maximum value, and becomes “0” level when reaching the timer value Tv, and then the carrier 20 falls toward the minimum value. The “0” level is maintained until the timer value Tv is reached, and the carrier 20 is generated so as to change to the “1” level when the carrier 20 falls below the timer value Tv. This means that the upper arm side semiconductor switching element SW2 changes from ON state → OFF state → ON state. Since the PWM signal VN is generated in the reverse relationship to the PWM signal VP, the lower arm side semiconductor switching element SW5 changes from OFF state → ON state → OFF state.

  The PWM signal WP becomes “1” level until the carrier 20 reaches the timer value Tw in the process of rising toward the maximum value, and becomes “0” level when reaching the timer value Tw. The “0” level is maintained until the value Tw is reached, and the carrier 20 is generated so as to change to the “1” level when the carrier 20 falls below the timer value Tw. This means that the upper arm side semiconductor switching element SW3 changes from ON state → OFF state → ON state. Since the PWM signal WN is generated in a reverse relationship with the PWM signal WP, the lower arm side semiconductor switching element SW6 changes from OFF state → ON state → OFF state.

  It should be noted that during the period ton_a in which the PWM signal VN is at “1” level and the period ton_b in which the PWM signal WN is at “1” level, the PWM signal shift determination means 14 needs to shift the PWM signal when “node = 1”. This is the pulse width used for determination (see FIG. 12). As described above, this pulse width has a relationship of ton_a <ton_b.

  As shown in FIG. 9D, the voltage vector state is the state of the zero voltage vector V7 until the carrier 20 rises from the minimum value and reaches the timer value Tw, and then the carrier 20 changes from the timer value Tw to the timer value Tv. Until it rises, it is in the state of the voltage vector V6, after that, until the carrier 20 falls from the maximum value and reaches the timer value Tv, it is in the state of the voltage vector V4, and then until the carrier 20 falls from the timer value Tv to the timer value Tw. The state of the voltage vector V6 and then the state of the zero voltage vector V7 until the carrier 20 falls to the minimum value.

  In FIG. 10, (a) the relationship between the carrier and each phase timer value is as follows. In the case of one carrier cycle, when node = 2, as described above, the descending section from the maximum value to the minimum value in the first half and the increase from the minimum value to the maximum value in the second half with reference to the valley timing of the carrier 21 It consists of a section. In this case, since the W-phase timer value Tw is fixed to zero, it is at the position of the minimum value of the carrier 21. On the other hand, the U-phase timer value Tu is at, for example, the center position between the maximum value and the minimum value of the carrier 21, and the V-phase timer value Tv is lower than the U-phase timer value Tu to the minimum value side of the carrier 21. It is required in relation to the position.

  The PWM signal “UP, UN, VP, VN, WP, WN” shown in FIG. 10B is generated as follows. The PWM signal UP becomes “0” level until the timer 21 reaches the timer value Tu in the process of the carrier 21 descending toward the minimum value, becomes “1” when it reaches the timer value Tu, and then the timer value in the process of the carrier 21 increasing toward the maximum value. It is generated so as to maintain the “1” level until reaching Tu, and to change to the “0” level when the carrier 21 exceeds the timer value Tu. This means that the upper arm side semiconductor switching element SW1 changes from OFF state → ON state → OFF state. Since the PWM signal UN is generated in the reverse relationship with the PWM signal UP, the lower arm side semiconductor switching element SW4 changes from the ON state to the OFF state to the ON state.

  The PWM signal VP becomes “0” level until the timer 21 reaches the timer value Tv while the carrier 21 is decreasing toward the minimum value, becomes “1” when the carrier 21 reaches the timer value Tv, and then reaches the timer value when the carrier 21 increases toward the maximum value. The “1” level is maintained until Tv is reached, and the carrier 21 is generated to change to the “0” level when the timer value Tv is exceeded. This means that the upper arm side semiconductor switching element SW2 changes from OFF state → ON state → OFF state. Since the PWM signal VN is generated in a reverse relationship with the PWM signal VP, the lower arm side semiconductor switching element SW5 changes from the ON state to the OFF state to the ON state.

  The PWM signal WP is generated so as to maintain a “0” level during one carrier cycle, and the PWM signal WN is generated so as to maintain a “1” level during one carrier cycle. This means that the upper arm side semiconductor switching element SW3 is turned off and the lower arm side semiconductor switching element SW6 is turned on.

  It should be noted that during the period ton_b in which the PWM signal UP is at “1” level and the period ton_a in which the PWM signal VP is at “1” level, whether or not the PWM signal shift determination unit 14 needs to shift the PWM signal at “node = 2” This is the pulse width used for determination (see FIG. 12). As described above, the relationship is ton_a <ton_b.

  As shown in FIG. 10D, the voltage vector state is the state of the zero voltage vector V0 until the carrier 21 falls from the maximum value and reaches the timer value Tu, and then the carrier 21 changes from the timer value Tu to the timer value Tv. The voltage vector is in the state of the voltage vector V4 until it falls, the carrier 21 then rises from the minimum value until it reaches the timer value Tv, the state of the voltage vector V6, and then the carrier 21 rises from the timer value Tv to the timer value Tu. The state of the voltage vector V4, and then the state of the zero voltage vector V0 until the carrier 21 rises to the maximum value.

  Accordingly, the DC current information idc shown in FIGS. 9C and 10C is obtained as follows. When the voltage vector state is V6, in the upper arm side semiconductor switching element, the U-phase and V-phase upper arm side semiconductor switching elements SW1 and SW2 are in the ON state, and in the lower arm side semiconductor switching element, the W-phase lower arm side semiconductor The switching element SW6 is turned on. As a result, the U-phase winding and the V-phase winding of the three-phase motor 3 flow from the positive electrode side of the DC power source 1 via the semiconductor switching elements SW1 and SW2, pass through the W-phase winding and pass through the semiconductor switching element SW6. Thus, a current path that flows through the resistor 4 and returns to the negative electrode side of the DC power source 1 is formed. Therefore, when the direction of the current flowing into the three-phase motor 3 is positive, the DC current information idc detected by the DC current detecting means Q when the voltage vector state is V6 is -Iw (-W phase current). Here, the description is made on the power running operation, but it goes without saying that the phase current information can be obtained from the DC current information in the regenerative operation as well.

  When the voltage vector state is V4, the U-phase upper arm side semiconductor switching element SW1 is turned ON in the upper arm side semiconductor switching element, and the V arm and the W phase lower arm side semiconductor are turned on in the lower arm side semiconductor switching element. The switching elements SW5 and SW6 are turned on. As a result, the U-phase winding of the three-phase motor 3 flows from the positive electrode side of the DC power source 1 through the semiconductor switching element SW1, passes through the V-phase and W-phase windings, and is resistance through the semiconductor switching elements SW5 and SW6. A current path that flows through the device 4 and returns to the negative electrode side of the DC power supply 1 is formed. Therefore, when the direction of current flowing into the three-phase motor 3 is positive, the DC current information idc detected when the voltage vector state is V4 is + Iu (+ U phase current). Here, the description is made on the power running operation, but it goes without saying that the phase current information can be obtained from the DC current information in the regenerative operation as well.

  On the other hand, when the voltage vector state is V7, only the upper arm side semiconductor switching elements SW1, SW2, and SW3 are turned on. When the voltage vector state is V0, only the lower arm side semiconductor switching elements SW4, SW5, SW6 are turned on. In these states, since the current path as described above is not formed, the phase current information obtained from the detected direct current information idc is indefinite.

  FIG. 11 is a diagram collectively showing the relationship between the voltage vector state, the generated PWM signal, and the phase current information obtained from the detected DC current information. In FIG. 11, “OFF” in the PWM signal “UP, UN, VP, VN, WP, WN” means “0” level, and “ON” means “1” level. The phase current information in the zero voltage vectors V0 and V7 is indefinite. Further, it is shown that the phase current information in the voltage vectors V1, V2, V3, V4, V5, and V6 is + Iw, + Iv, −Iu, + Iu, −Iv, and −Iw in this order.

  Next, the operation of the PWM signal shift determination unit 14 will be described with reference to FIGS. FIG. 12 is a flowchart for explaining the operation of the PWM signal shift determination means 14. FIG. 13 is a diagram collectively showing the relationship between the node shown in FIG. 7 and two PWM signals that are targets of two pulse widths used when the PWM signal shift determination means determines whether or not the shift is necessary at the node. is there. FIG. 14 is a diagram for explaining the DC current → phase current conversion necessary time used in the determination operation by the PWM signal shift determination unit and the operation of the detection timing generation unit shown in FIG. 1 (when node = 1). FIG. 15 is a time chart for explaining an example of a PWM signal determined to be shifted by the shift method 1 in FIG. FIG. 16 is a time chart illustrating an example of a PWM signal that is determined to be shifted by the shift method 2 in FIG.

  In the determination of necessity of shift in the PWM signal shift determination means 14, as shown in FIG. 12, in addition to the two pulse widths ton_a and ton_b having the relationship of “ton_a <ton_b” described in FIG. 9 and FIG. Since the DC current → phase current conversion necessary time Tneed (see FIG. 14) is used as the determination time width, these will be described first.

  As can be understood from the description in FIG. 9 and FIG. 10, in each of the 12 nodes (see FIG. 7), of the three-phase PWM signals “UP, UN, VP, VN, WP, WN” The PWM signal changes between the “1” level and the “0” level without maintaining the “1” level and the “0” level within one carrier cycle, and the semiconductor switching element performs the ON / OFF switching operation. Let it be done. The two pulse widths ton_a and ton_b used for determining whether or not the shift is necessary in the PWM signal shift determining unit 14 are time widths for causing the semiconductor switching element to perform the ON operation. “Level PWM signal is targeted.

  Therefore, FIG. 13 summarizes the relationship between the two PWM signals that are the targets of the two pulse widths ton_a and ton_b used when the PWM signal shift determination unit 14 determines whether or not the shift is necessary at each of the 12 nodes. It becomes like this. In the case of “node 1” in FIG. 13, as described in FIG. 9, the pulse width ton_a is the pulse width of the PWM signal VN, and the pulse width ton_b is the pulse width of the PWM signal WN. In the case of “node 2”, as described in FIG. 10, the pulse width ton_a is the pulse width of the PWM signal VP, and the pulse width ton_b is the pulse width of the PWM signal UP. Hereinafter, two PWM signals to be subjected to two pulse widths ton_a and ton_b up to the node 12 are shown.

  Next, the DC current → phase current conversion necessary time Tneed will be described with reference to FIG. 14 mainly describes the operation of the detection timing generation means 16, and will be described later. Here, the contents related to the DC current → phase current conversion necessary time Tneed will be described. In FIG. 14, (a) phase current information from DC current information when phase current information for two phases is obtained from DC current information at the timing when the voltage vector state changes from V4 to V6 (see FIG. 9) at node 1. (B) PWM signals VN and WN, and (c) DC current information idc detected by the DC current detection means Q are shown.

  In FIG. 14, the first trigger timing Trg1 input to the A / D conversion circuit 8 is A / D conversion from the time when the PWM signal VN changes from “1” level (ON) to “0” level (OFF). DC current information Idc1 which is generated at a timing advanced by time 24 and detected by the DC current detecting means Q is digitally converted by the A / D conversion circuit 8 to obtain U-phase phase current information. It becomes. The second trigger timing Trg2 input to the A / D conversion circuit 8 is that the semiconductor switching element SW5 is actually started from the time when the PWM signal VN changes from “1” level (ON) to “0” level (OFF). The timing when “switching delay time + detection delay time” 25, which is a combination of the switching delay time and the detection time delay in the DC current detecting means Q, and the ringing time 26 generated in the DC current before the change from ON to OFF is reached. The DC current information idc generated by the DC current detection means Q is digitally converted by the A / D conversion circuit 8 and becomes DC current information Idc2 for obtaining W-phase phase current information.

  The DC current → phase current conversion required time Tneed22 is a determination time width used for determining whether or not phase current information for two phases can be obtained from the DC current detected in this way. In the example of FIG. 14, the A / D conversion time 24 in which the DC current information Idc1 is obtained is such that the PWM signal VN changes from “1” level (ON) to “0” level (OFF) from the first trigger timing Trg1. This is the period up to the point of change. The A / D conversion time 27 for obtaining the DC current information Idc2 is within a certain period before the PWM signal WN changes from the “1” level (ON) to the “0” level (OFF) from the second trigger timing Trg2. It is a predetermined period. Between the A / D conversion time 24 and the A / D conversion time 27, the switching delay time until the semiconductor switching element SW5 actually changes from ON to OFF and the detection delay time in the DC current detection means Q “Switching delay time + detection delay time” 25 and a ringing time 26 generated in the direct current.

  Therefore, the DC current → phase current conversion required time Tneed22 is the “switching delay time + detection delay time” 25 and the ringing time from when the PWM signal VN changes from “1” level (ON) to “0” level (OFF). 26 and A / D conversion time 27 is set as a predetermined time in consideration of the time, and when the A / D conversion times 24 and 27 cannot be secured, the phase current information Idc cannot be obtained from the DC current information idc. Determined. Hereinafter, the DC current → phase current conversion necessary time Tneed22 is abbreviated as a determination time width Tneed.

  That is, in FIG. 12, the PWM signal shift determination means 14 first determines whether or not the shorter pulse width ton_a is less than the determination time width Tneed (ST1). As a result, when ton_a <Tneed (ST1: Yes), even if the PWM signal is shifted, phase current information for two phases cannot be obtained from the DC current information, so it is determined that the PMW signal is not shifted ( ST2). The PWM signal state in this case is assumed to be a PWM pattern 1. In this case, the PWM signal shift determination unit 14 directly supplies the output of the PWM signal generation unit 13A to the inverter main circuit 2, the detection timing generation unit 16, and the voltage vector holding unit 17. The PWM signal shift determination unit 14 simultaneously notifies the detection timing generation unit 16 and the voltage vector holding unit 17 of the determination result “PWM pattern 1”.

  Further, when the determination result in ST1 is ton_a ≧ Tneed (ST1: No), the PWM signal shift determination unit 14 next determines whether or not 1/2 of (ton_b−ton_a) is equal to or greater than Tneed ( ST3). As a result, when (ton_b−ton_a) / 2 ≧ Tneed (ST3: Yes), phase current information for two phases can be obtained from DC current information without shifting the PWM signal, so the PMW signal is shifted. It is determined not to be performed (ST4). The PWM signal state in this case is assumed to be a PWM pattern 2. In this case, the PWM signal shift determination unit 14 directly supplies the output of the PWM signal generation unit 13A to the inverter main circuit 2, the detection timing generation unit 16, and the voltage vector holding unit 17. The PWM signal shift determination unit 14 simultaneously notifies the detection timing generation unit 16 and the voltage vector holding unit 17 of the determination result “PWM pattern 2”.

  In addition, when the determination result in ST3 is (ton_b-ton_a) / 2 <Tneed (ST3: No), the PWM signal shift determination unit 14 next sets the longer pulse width ton_b from (2 × Tneed). It is also determined whether it is smaller (ST5). For example, when the PWM signal is as shown in FIG. 15, since ton_b <(2 × Tneed) is satisfied (ST5: Yes), it is determined that the PWM signal is shifted by the shift method 1 (ST6). In this case, the PWM signal state after the PWM signal shift is defined as a PWM pattern 3. In this case, the PWM signal shift determination unit 14 supplies the output of the PWM signal generation unit 13A to the PWM signal shift unit 15 and simultaneously notifies the PWM signal shift unit 15 of the determination result “shift method 1”. Further, the PWM signal shift determination means 14 notifies the detection timing generation means 16 and the voltage vector holding means 17 of the determination result “PWM pattern 3”. The inverter main circuit 2, the detection timing generation unit 16, and the voltage vector holding unit 17 are supplied with a PWM signal of the PWM pattern 3 shifted by applying the shift method 1 from the PWM signal shift unit 15.

  In the determination in ST5, when the PWM signal is as shown in FIG. 16, for example, ton_b ≧ (2 × Tneed) (ST5: No), it is determined that the PWM signal is shifted by the shift method 2. In this case, the PWM signal state after the PWM signal shift is defined as a PWM pattern 4. In this case, the PWM signal shift determination unit 14 supplies the output of the PWM signal generation unit 13A to the PWM signal shift unit 15 and simultaneously notifies the PWM signal shift unit 15 of the determination result “shift method 2”. Further, the PWM signal shift determination unit 14 notifies the determination result “PWM pattern 4” to the detection timing generation unit 16 and the voltage vector holding unit 17. The inverter main circuit 2, the detection timing generation unit 16, and the voltage vector holding unit 17 are supplied with a PWM signal of the PWM pattern 4 shifted by applying the shift method 2 from the PWM signal shift unit 15.

  Next, in FIGS. 15 and 16, in the case of node = 1, (a) the relationship between the carrier and each phase timer value, and (b) the PWM signal “UP, UN, VP, VN, WP, WN” (C) DC current information idc detected by the DC current detecting means Q, (d) a voltage vector state, and a Tneed time width used in the determination are shown.

  In ST5, the PWM signal determined as ton_b <(2 × Tneed) is generated, for example, as shown in FIG. In the example shown in FIG. 15A, the W-phase timer value Tw is at a position that is considerably closer to the maximum value side of the carrier 20, and the V-phase timer value Tv is the maximum value of the carrier 20 than the W-phase timer value Tw. The position is closer to the side. In this case, as shown in FIG. 15B, the time width ton_b where the PWM signal WN is at the “1” level is slightly larger than the time width of Tneed, so that ton_b <(2 × Tneed ) Is determined as the PWM signal. As shown in FIG. 15 (d), the voltage vector state changes from V7 → V6 → V4 → V6 → V7 as in FIG. 9, but the time width is short in the voltage vector V6, so the phase current information is the voltage vector. Only available at V4. In this case, by shifting the PWM signal by the shift method 1, phase current information for two phases can be detected from DC current information in one carrier cycle (see FIG. 17).

  In ST5, the PWM signal determined as ton_b ≧ (2 × Tneed) is generated, for example, as shown in FIG. In the example shown in FIG. 16A, the W-phase timer value Tw is at a position slightly raised from the central position between the minimum value and the maximum value of the carrier 20 to the maximum value side, and the V-phase timer value Tv is The relationship is a position that is higher than the W-phase timer value Tw toward the maximum value of the carrier 20. In this case, as shown in FIG. 16B, the time width ton_b in which the PWM signal WN is at the “1” level is considerably larger than the time width of Tneed, so that ton_b ≧ (2 × Tneed). It is determined that the signal is a PWM signal. As shown in FIG. 16D, the voltage vector state changes from V7 → V6 → V4 → V6 → V7 as in FIG. 9, but since the time width is short in the voltage vector V6, the phase current information is the voltage vector. Only available at V4. In this case, phase current information for two phases can be detected from DC current information in one carrier period by shifting the PWM signal by the shift method 2 (see FIG. 18).

  Thus, except for the case of PWM pattern 1, phase current information for two phases can be detected from DC current information. Therefore, in the case of the PWM pattern 1 in which the phase current information for two phases cannot be detected from the DC current information, until the determination in ST1 is negative (No) in the period of one electrical angle, that is, ton_a ≧ Until the condition of Tneed is satisfied, the three-phase motor 3 is accelerated and driven in an open loop, and after satisfying the condition of ton_a ≧ Tneed, a limiter is provided for the pulse width. The phase current information for two phases can be detected from the DC current information.

  As a result, the PWM signal shift determination unit 14 determines whether or not the shift is necessary based on the pulse width of the PWM signal generated by the PWM signal generation unit 13A and the difference between the pulse widths, so that the two-phase is not required. It is only necessary to determine a PWM signal that can detect minute phase current information and a PWM signal that can detect phase current information for two phases if shifted.

  Note that the PWM signal shift determination unit 14 has been described with reference to the case where the shift value is determined based on the pulse width of the PWM signal generated by the PWM signal generation unit 13A and the difference between the pulse widths. The timer values (Tu, Tv, Tw) calculated at 12 may be used. In this way as well, it is possible to reliably determine whether or not shifting is necessary.

  Next, referring to FIGS. 17 and 18, the shift method 1 and the shift method 2 performed by the PWM signal shift means 15 will be described. FIG. 17 is a time chart for explaining the operation (when node = 1) in which the PWM signal shift means 14 performs the shift method 1 to obtain the PWM signal of the PWM pattern 3. FIG. 17 shows a case where the shift method 1 is applied to the PWM signal shown in FIG. FIG. 18 is a time chart for explaining the operation (when node = 1) in which the PWM signal shift means 15 performs the shift method 2 to obtain the PWM signal of the PWM pattern 4. FIG. 18 shows a case where the shift method 2 is applied to the PWM signal shown in FIG.

  In the shift method 1, the center of the carrier in the first half of one carrier period (in the case of the nodes 1, 4, 5, 8, 9, 12, the carrier peak timing, the nodes 2, 3, 6, 7, 10, 11 In this case, the PWM signal that is the target of the shorter pulse width ton_a becomes “1” level by the pulse width ton_a with reference to the position advanced by the determination time width Tneed from the carrier valley timing in the case of the carrier valley timing). The corresponding timer value is changed for each half carrier so that the PWM signal that is the target of the longer pulse width ton_b with respect to the center becomes the “1” level by the pulse width ton_b. According to this shift method 1, it is possible to obtain phase current information for two phases from a direct current in one carrier cycle.

  In the example illustrated in FIG. 15, the PWM signal that is the target of ton_a is VN, and the PWM signal that is the target of ton_b is WN. Therefore, as illustrated in FIG. 17A, the timer value corresponding to the PWM signal VN The timer value Tw corresponding to Tv and the PWM signal WN is changed for each half carrier so as to change in a crank shape between the first half cycle and the second half cycle with reference to the center (crest timing) of the carrier 20, and FIG. As shown in FIG. 4, the PWM signal WN is generated. By shifting the PWM signal in this way, in one carrier cycle, the voltage vector state changes from V7 → V5 → V4 → V6 → V7 as shown in FIG. , A time equal to or greater than the determination time width Tneed can be secured at V6, and phase current information can be obtained.

  In the shift method 2, the PWM signal that is the target of ton_b is output as it is, so the corresponding timer value is not changed, the PWM signal that is the target of ton_a is the “1” level of the PWM signal that is the target of ton_b. The corresponding timer value is set to the half carrier so that the pulse width ton_a is set to “1” level across the carrier center with reference to the position advanced by the determination time width Tneed toward the carrier center from the time when the level changes from “0” to “0” level. Change every time. According to this shift method 2, similarly to the shift method 1, it is possible to obtain phase current information for two phases from DC current information detected in one carrier cycle.

  In the example shown in FIG. 16, the PWM signal that is the target of ton_a is VN, and the PWM signal that is the target of ton_b is WN. Therefore, as shown in FIG. 18A, the timer value corresponding to the PWM signal WN Although Tw is not changed, the timer value Tv corresponding to the PWM signal VN is changed for each half carrier so as to change in a crank shape between the first half cycle and the second half cycle with reference to the center (crest timing) of the carrier 20. As shown in FIG. 18B, the pulse width ton_a straddling the carrier center with reference to the position advanced by the determination time width Tneed toward the carrier center from the time when the PWM signal WN changes from the “1” level to the “0” level. Only the PWM signal VN having the “1” level is generated. By shifting the PWM signal in this way, in one carrier cycle, the voltage vector state changes from V7 → V5 → V4 → V6 → V7 as shown in FIG. 18 (d), so that the voltage vector state is V4. , A time equal to or greater than the determination time width Tneed can be secured at V6, and phase current information can be obtained.

  In this way, the PWM signal shift means 15 uses the determination time width Tneed as a shift amount. Therefore, by shifting the PWM signal with the minimum shift amount, the phase current information obtained from the DC current within one carrier cycle can be obtained. You can increase the number. As a result, it is possible to suppress an influence such as a decrease in efficiency due to the generation of the regenerative current as much as possible.

  Further, in the shift method 2, since the PWM signal is shifted so that the phase current information for two phases can be obtained in the latter half of one carrier cycle, the inverter controller 7A has a phase current for two phases at a timing close to the calculation timing. Information can be detected, and more stable control is possible.

  Next, the operation of the detection timing generation unit 16 will be described. The detection timing generation unit 16 operates as follows according to “PWM pattern 1”, “PWM pattern 2”, “PWM pattern 3”, and “PWM pattern 4” notified from the PWM signal shift determination unit 14.

  First, a detection timing generation method when the PWM pattern 2 and the PWM pattern 4 are notified will be described with reference to FIG. In FIG. 14, the first trigger timing Trg1 of the A / D conversion circuit 8 is A from the time when the PWM signal VN targeted for ton_a changes from “1” level (ON) to “0” level (OFF). / D conversion time is generated at a timing advanced by 24. The second trigger timing Trg2 of the A / D conversion circuit 8 starts from the point in time when the PWM signal VN targeted for ton_a changes from “1” level (ON) to “0” level (OFF). “Switching delay time + detection delay time” 25, which is a combination of the switching delay time until the actual change from ON to OFF and the detection delay time in the DC current detection means Q, and the ringing time 26 generated in the DC current Generated at the elapsed timing.

  When the PWM pattern 3 is notified, the first trigger timing Trg1 of the A / D conversion circuit 8 is generated at a timing advanced from the center of the carrier to the first half cycle side by the A / D conversion time 24. . The second trigger timing Trg2 of the A / D conversion circuit 8 is generated by the same method as that for the PWM pattern 2 and the PWM pattern 4 described above. When the PWM pattern 1 is notified, the trigger current is not generated because phase current information for two phases cannot be obtained from the direct current.

  Next, voltage vector information (Va, Vb) held by the voltage vector information holding unit 17 will be described. Here, Va is voltage vector information at the first trigger timing Trg1 to the A / D conversion circuit 8. Vb is voltage vector information at the second trigger timing Trg2 to the A / D conversion circuit 8. The voltage vector information holding means 17 holds the voltage vector information (Va, Vb) as shown in FIGS.

  FIG. 19 is a table that collectively stores the relationship between voltage vector information (Va, Vb) held by the voltage vector information holding unit 17 for the PWM patterns 2 and 4 and the nodes. In the table shown in FIG. 19, as the voltage vector information (Va, Vb), for example, (V4, V6) is held in the node 1 and (V6, V4) is held in the node 2.

  FIG. 20 is a table that collectively stores the relationship between the voltage vector information (Va, Vb) held by the voltage vector information holding unit 17 for the PWM pattern 3 and the nodes. In the table shown in FIG. 20, as voltage vector information (Va, Vb), for example, (V5, V6) is held in node 1 and (V2, V4) is held in node 2.

  The voltage vector information holding means 17 receives the notification of the “PWM pattern 2, 4” from the PWM signal shift determination means 14 and the PWM signal “UP, UN, VP, VN, WP, WN” inputted at that time. Based on the logical state (node), the corresponding voltage vector information is held by the table shown in FIG. Further, the voltage vector information holding unit 17 receives the notification of the “PWM pattern 3” from the PWM signal shift determination unit 14 and the PWM signal “UP, UN, VP, VN, WP, WN” input at that time. Based on the logical state (node), the corresponding voltage vector information is held by the table shown in FIG.

  In the DC current / phase current conversion means 10, the DC current information Idc 1 and Idc 2 for two phases A / D converted by the A / D conversion circuit 8 based on the trigger timings Trg 1 and Trg 2 are converted into voltage vector information holding means. 17 is converted into two-phase phase current information based on the voltage vector information (Va, Vb) at the trigger timings Trg1 and Trg2 held in FIG. The remaining phase current information is obtained by applying the converted two-phase phase current information to the relationship of “Iu + Iv + Iw = 0”. For example, in the case of the PWM pattern 2, at node 1, Va = V4, and + Iu = Idc1 from FIG. Further, Vb = V6, and −Iw = Idc2 from FIG. The remaining phase current information is Iv, and is obtained as Iv = − (Iu + Iw). Thus, since the remaining phase current information is obtained by estimation from the converted phase current information, the interval between the two trigger timings Trg1, Trg2 to the A / D detection circuit 8 needs to be as narrow as possible. There is.

  Next, the operation of the voltage command value / phase command value calculating means 11A will be described with reference to FIG. First, in the three-phase / two-phase conversion unit 11a, the phase current information Iu, Iv, Iw converted by the direct current / phase current conversion unit 10 is held in the dq conversion phase holding unit 11L as will be described later. It converts into d-axis current Id and q-axis current Iq using dq conversion phase θdq. The frequency / phase estimation means 11b estimates the execution frequency f and the phase θ of the magnetic pole position of the permanent magnet rotor 3b from the d-axis current Id and the q-axis current Iq. The d-axis current command value calculating means 11d obtains the d-axis current command value Id * from the q-axis current Iq-d-axis current command value Id * table that is held in advance based on the q-axis current Iq. Further, the q-axis current command value calculation means 11f obtains the q-axis current command value Iq * by performing proportional integral control of the frequency error ferr between the frequency command f * obtained by the frequency comparison means 11c and the execution frequency f.

  The dq-axis voltage command value calculation means 11h performs a d-axis voltage command by proportionally integrating the d-axis current error Iderr between the d-axis current command value Id * and the d-axis current value Id obtained by the d-axis current comparison means 11e. The value Vd * is determined. Further, the dq-axis voltage command value calculation means 11h performs q-axis current error Iqerr between the q-axis current command value Iq * and the q-axis current value Iq obtained by the q-axis current comparison means 11g by proportional integration. A voltage command value Vq * is obtained.

  The voltage command value calculation means 11i applies the d-axis voltage command value Vd *, the q-axis voltage command value Vq *, and the DC voltage information Vdc input from the A / D conversion circuit 9 to the above equation (1). The voltage command value V * is calculated. The phase command value calculating means 11j obtains a phase command value θ * at which a PWM signal is actually output from the execution frequency f and the magnetic pole position phase θ. Further, the dq conversion phase calculation means 11k obtains the phase θdq at the trigger timing of the A / D conversion circuit 8 from the execution frequency f and the magnetic pole position phase θ, and updates the held data of the dq conversion phase holding means 11L. .

  FIG. 21 is a diagram for explaining the timing relationship of each phase in the voltage command value / phase command value calculating means 11A. In FIG. 21, the timing relationship of each phase (θdq, θ, θ *) when the calculation start timing 29 of the voltage command value / phase command value calculation means 11A is the valley timing of the carrier 20 is shown. Nodes based on the carrier valley timing are nodes 1, 4, 5, 8, 9, and 12 as described with reference to FIG. As described above, the calculation start timing 29 is a calculation start timing in the inverter control unit 7A.

  In FIG. 21, the phase θdq (1) shown in the first half of one carrier period including the calculation start timing 29 is a dq conversion phase held in the dq conversion phase holding means 11L. In the frequency / phase estimation unit 11b, the d-axis current value Id and the q-axis converted by the three-phase / two-phase conversion unit 11a based on the dq conversion phase θdq (1) held in the dq conversion phase holding unit 11L. From the current value Iq, the execution frequency f and the magnetic pole position phase θ at the calculation start timing 29 are estimated.

The phase command value θ * shown 1.5 × Tc after the calculation start timing 29 is obtained by applying the execution frequency f and the magnetic pole position phase θ to the equation (2) in the phase command value calculation unit 11j. Tc is a carrier cycle.
Phase command value θ * = θ + 2πf × (1.5 × Tc) (2)

The phase θdq (2) is a dq conversion phase of the three-phase / two-phase conversion unit 11a used at the next calculation start timing. This is the first trigger timing Trg1 to the A / D conversion circuit 8 that occurs after the period t1 has elapsed from the calculation start timing 29, and the A / D that occurs after the period t2 (t2> t1) has elapsed from the calculation start timing 29. This is the phase of the timing that bisects the second trigger timing Trg2 to the conversion circuit 8, and the execution frequency f and the magnetic pole position phase θ in the dq conversion phase calculation means 11k are expressed by the equation (3). Required by application. The data held in the dq conversion phase holding means 11L is updated as θdq (1) → θdq (2).
dq conversion phase θdq (2) = θ + 2πf × {(t1 + t2) / 2} (3)

  That is, in the three-phase / two-phase coordinate conversion unit 11a, the three-phase / two-phase coordinate conversion process is performed based on the phase in the middle of the timing of detecting the phase current information for two phases from the direct current. As a result, the influence that phase current information for two phases cannot be detected at the same time can be suppressed, and the processing load can be reduced.

  The respective phases (θdq, θ, θ *) described above are obtained in the same manner when the calculation start timing of the inverter control unit 7A is the carrier peak timing (nodes 2, 3, 6, 7, 10, 11). .

  Thus, based on the voltage command value V * and the phase command value θ * obtained by the voltage command value / phase command value calculation means 11A, the timer value calculation means 12, the PWM signal generation means 13A, the PWM signal described above. The shift determination means 14 and the PWM signal shift means 15 generate PWM signals “UP, UN, VP, VN, WP, WN” for controlling the inverter main circuit 2, and the three-phase motor 3 is in a desired operation state. Is driven to rotate.

  In the above description, the description of the upper and lower short-circuit prevention time for preventing the upper and lower arm semiconductor switching elements of the inverter main circuit 2 from simultaneously turning ON and short-circuiting is omitted. It is necessary to set a time around 3 μs as the prevention time. In that case, the detection timing (Trg1, Trg2) of the A / D conversion circuit 8 is set in consideration of the upper and lower short-circuit prevention time.

  Further, in the section of one electrical angle cycle, the three-phase motor 3 is accelerated and driven in an open loop until the condition of ton_a ≧ Tneed is satisfied, and after the condition of ton_a ≧ Tneed is satisfied, a limiter is applied to the pulse width. Although it has been explained that the phase current information for two phases can be detected from the direct current within one carrier period at all times during normal operation, the phase current waveform is distorted by performing the pulse width limiter. There is a case.

  In that case, noise, vibration, etc. may occur. If the phase current information for two phases cannot be obtained from the direct current within one carrier period without performing the pulse width limiter, the three phases The two-phase coordinate conversion unit 11a may perform control based on the d-axis current value and the q-axis current value calculated last time. As a result, stable operation can be realized.

  As described above, according to the first embodiment, the inverter control unit determines whether or not to output the PWM signal generated by the PMW signal generation means to the semiconductor switching element of the inverter main circuit for each carrier period. The PWM signal is shifted so that the number of phase current information obtained from the DC current detected by the DC current detecting means within one carrier period increases when the PWM signal is output after being shifted. The timing for detecting the phase current information from the DC current is generated based on the PWM signal finally supplied to the inverter main circuit.

  Accordingly, an inverter control device that is not restricted by the voltage zero vector can be obtained, and the proportion of the voltage zero vector is large as in the low rotation region, and when one voltage zero vector exceeds the half carrier period, Can also be controlled.

  In addition, the control restriction of detecting one instantaneous current information in the first half period of one carrier period of the PWM signal and detecting the remaining instantaneous current information in the second half period of one carrier period can be eliminated. Deterioration of controllability due to a time difference in detection timing can be suppressed as much as possible. And it can respond also to the two phase modulation system which can reduce the switching loss in an inverter main circuit.

  In addition, in the means for calculating a timer value that complies with the generation of the PWM signal, in each phase, a section of 30 ° before and after the maximum value phase of the phase voltage fundamental wave is 60 ° in total, and the phase voltage fundamental wave Since each phase timer value is generated on the basis of a two-phase modulation method for controlling so as not to switch between 30 ° before and after the minimum value phase and 60 °, a shift determination target in a three-phase PWM signal It becomes easy to secure the pulse width of the PWM signal for two phases to be equal to or greater than the determination time width. As a result, the range in which phase current information for two phases can be obtained from the direct current can be expanded, and a reliable inverter control device that can be stably controlled can be obtained.

  In addition, since the shift determination of the PWM signal is performed based on the pulse width of the generated PWM signal and the difference between the pulse widths, or based on the timer value of each phase and the difference between the timer values, the PWM signal is reliably transmitted. Signal shift determination can be performed.

  In addition, in the shift operation of the PWM signal that increases the number of phase current information obtained from the direct current within one carrier cycle, the shift amount of the PWM signal is minimized, so that the PWM signal is shifted. It is possible to suppress the influence such as the efficiency decrease due to the generation of the regenerative current due to.

  In addition, in the shift operation of the PWM signal, when the pulse width of the generated PWM signal of each phase is greater than a certain value, phase current information for two phases obtained from the detected DC current is obtained in the second half cycle of the carrier. Since the PWM signal is shifted as described above, phase current information for two phases can be detected at a timing close to the calculation timing of the inverter control device, and more stable control is possible.

  Further, in the inverter control unit, when phase current information for two phases cannot be obtained from the DC current within one carrier cycle, the inverter main circuit is opened in an open loop until the phase current information for two phases is obtained. After that, since a limiter is provided for the pulse width of the generated PWM signal, phase current information for two phases can always be detected from the direct current within one carrier cycle, and the reliability can be controlled stably. A characteristic inverter control device can be obtained.

  In addition, with the above-described configuration, the inverter control unit, based on the phase current information actually detected without using the estimated current, the output error corresponding to the vertical short circuit time that occurs when the vertical short circuit prevention time is provided. Therefore, more stable control is possible.

  Further, in the inverter control unit, when the phase current information for two phases cannot be detected from the direct current within one carrier cycle, the d-axis current value and the q-axis current value previously calculated by the three-phase / 2-phase coordinate conversion means If the control is performed based on the above, an inverter control device that can be stably controlled with a small processing load can be obtained.

  In addition, in the three-phase / two-phase coordinate conversion means, the conversion process is performed based on the phase in the middle of the timing for detecting the phase current information for two phases from the direct current. It is possible to obtain an inverter control device capable of performing stable control with a small arithmetic processing load while suppressing the influence that current information cannot be detected at the same time.

Embodiment 2. FIG.
FIG. 22 is a block diagram showing a configuration of an inverter control apparatus according to Embodiment 2 of the present invention. In FIG. 22, the same reference numerals are given to components that are the same as or equivalent to the components shown in FIG. 1 (Embodiment 1). Here, the description will be focused on the portion related to the second embodiment.

  As shown in FIG. 22, in inverter control unit 7B in the inverter control apparatus according to the second embodiment, voltage command value / phase command value calculating means 11A in inverter control unit 7A shown in FIG. A voltage command value / phase command value calculating means 11B instead of the PWM signal generating means 13B and a PWM signal generating means 13B instead of the PWM signal generating means 13A are provided.

  FIG. 23 is a block diagram showing a configuration example of the voltage command value / phase command value calculation means 11B. As shown in FIG. 23, in the voltage command value / phase command value calculating means 11B, a carrier frequency changing means 11m is added to the voltage command value / phase command value calculating means 11A shown in FIG. A phase command value calculation means 11n is provided instead of 11j.

  The voltage command value / phase command value calculating means 11B has the configuration shown in FIG. 23, the phase current information (Iu, Iv, Iw) for three phases converted by the DC current / phase current converting means 10, and A / In addition to the voltage command value V * and the phase command value θ *, the carrier frequency is designated from the DC voltage information Vdc A / D converted by the D conversion circuit 9 and the frequency command f * input from the outside. The carrier frequency command value fc * is calculated.

  In FIG. 22, the carrier generating means is not clearly shown, but the carrier frequency is configured to be generated by switching the carrier frequency. When the voltage command value / phase command value calculating means 11B outputs the carrier frequency command value fc *, the carrier frequency is changed. The calculation is changed from the calculation start timing of the next inverter control unit 7B to the carrier frequency by the carrier frequency command value fc *.

  The PWM signal generation means 13B drives the semiconductor switching elements SW1 to SW6 of the inverter main circuit 2 on and off based on the timer values (Tu, Tv, Tw) of the respective phases calculated by the timer value calculation means 12. PWM signal “UP, UN, VP, VN, WP, WN” is generated. In the second embodiment, the carrier frequency command value fc * input from the voltage command value / phase command value calculation means 11B is designated. A PWM signal is generated according to the carrier frequency.

  Next, the configuration and operation of the voltage command value / phase command value calculating means 11B according to the second embodiment will be described with reference to FIGS. FIG. 24 is a flowchart for explaining the operation of the carrier frequency changing means 11m. FIG. 25 and FIG. 26 are diagrams for explaining the operation performed by the phase command value calculating unit 11n based on the carrier frequency command value fc * from the carrier frequency changing unit 11m.

  In FIG. 23, the carrier frequency changing unit 11m determines whether or not the carrier frequency needs to be changed based on the execution frequency f obtained by the frequency / phase estimating unit 11b (see FIG. 24), and specifies the carrier frequency to be changed. The frequency command fc * is output to the phase command value calculation unit 11n and the PWM signal generation unit 13B.

  The phase command value calculation means 11n outputs an actual PWM signal based on the execution frequency f and phase θ obtained by the frequency / phase estimation means 11b and the carrier frequency command fc * input from the carrier frequency change means 11m. A phase command value θ * indicating the phase of the timing is obtained (see FIGS. 25 and 26).

  In FIG. 24, the carrier frequency changing unit 11m determines whether or not the execution frequency f estimated by the frequency / phase estimating unit 11b is less than the determination reference frequency A [Hz] (ST8). As a result, when f <A [Hz] (ST8: Yes), the carrier frequency command value fc * is set to the carrier frequency fc1 (ST9), and when f ≧ A [Hz] (ST8: No), the execution frequency It is determined whether or not f exceeds another determination reference frequency B [Hz] where A [Hz] <B [Hz] (ST10).

  When the determination result in ST10 is f> B [Hz] (ST10: Yes), the carrier frequency command value fc * is set to the carrier frequency fc2 where fc1 <fc2 (ST11), and A ≦ f ≦ B [Hz] In the case (ST10: No), the carrier frequency command value fc * is not changed (ST12).

  Here, with respect to the frequencies A [Hz] and B [Hz] that give judgment criteria, appropriate hysteresis is provided. For example, B = A + 10 [Hz]. As a result, frequent switching of the carrier frequency can be prevented, and generation of noise due to switching of the carrier frequency can be prevented.

  25 and 26 show the operations at nodes 1, 4, 5, 8, 9, and 12 where the carrier valley timing is the calculation start timing of the inverter control unit 7B. The phase command value calculation means 11n When the carrier frequency command value fc * is switched from the carrier frequency fc1 to the carrier frequency fc2, the phase command value θ * is calculated according to the procedure shown in FIG. 25, and the carrier frequency command value fc * is changed from the carrier frequency fc2 to the carrier frequency fc1. In the case of switching, the phase command value θ * is calculated according to the procedure shown in FIG. The same applies to nodes 2, 3, 6, 7, 10, and 11 in which the carrier peak timing is the calculation start timing of the inverter control unit 7B.

  In FIG. 25, the carrier 31 has a frequency fc1 and a period Tc1 of 1 / fc1. The carrier 32 has a frequency of fc2 and a period Tc2 of 1 / fc2. When the carrier frequency command value fc * is switched from the carrier frequency fc1 to the carrier frequency fc2, as shown in FIG. 25, the valley after the carrier 31 at the carrier frequency fc1 (calculation start timing 30) is one valley after the carrier period Tc1 Although the timing is the calculation start timing of the next inverter control unit 7B, the carrier 31 is switched to the carrier 32 so that this timing becomes the valley timing of the carrier 32 of the carrier frequency fc2.

  Therefore, the phase command value calculating means 11n is estimated at the calculation start timing 30 when the carrier frequency command value fc * is changed from fc1 to fc2 by the carrier frequency changing means 11m calculated at the calculation start timing 30. Based on the obtained phase θ, the phase command value θ * to be applied at the peak time of the carrier 32 existing at the position after “Tc1 + Tc2 / 2” from the calculation start timing 30 is obtained.

  In FIG. 26, the carrier 34 has a frequency fc2 and a period Tc2 of 1 / fc2. The carrier 35 has a frequency fc1 and a period Tc1 of 1 / fc1. When the carrier frequency command value fc * is switched from the carrier frequency fc2 to the carrier frequency fc1, as shown in FIG. 26, the valley after one carrier cycle Tc2 from the trough timing of the carrier 34 at the carrier frequency fc2 (calculation start timing 33). Although the timing is the calculation start timing of the next inverter control unit 7B, the carrier 34 is switched to the carrier 35 so that this timing becomes the valley timing of the carrier 35 of the carrier frequency fc1.

  Therefore, the phase command value calculating means 11n is estimated at the calculation start timing 33 when the carrier frequency command value fc * is changed from fc2 to fc1 by the carrier frequency changing means 11m calculated at the calculation start timing 33. Based on the obtained phase θ, the phase command value θ * to be applied at the peak timing of the carrier 35 existing at the position after “Tc2 + Tc1 / 2” from the calculation start timing 33 is obtained.

  As described above, according to the second embodiment, when the execution frequency is low, the carrier frequency is also lowered, so that it is easy to secure the pulse width of the PWM signal to be subjected to shift determination to be greater than the determination time width. . Therefore, since the range in which the phase current information for two phases can be obtained from the direct current can be expanded, a reliable inverter control device that can be stably controlled can be obtained. Further, since the ratio of the PWM pattern 2 from which phase current information for two phases can be obtained without shifting is increased, it is possible to suppress the influence of efficiency reduction due to generation of regenerative current due to shifting of the PWM signal as much as possible. .

  In the second embodiment, there are two carrier frequencies to be switched, fc1 and fc2, but the carrier frequency may be switched more finely. Further, although the execution frequency f is used as the carrier frequency switching condition, other parameters (for example, the voltage command value V *) that can obtain the same effect may be used as the switching condition.

Embodiment 3 FIG.
FIG. 27 is a block diagram showing a configuration of an inverter control apparatus according to Embodiment 3 of the present invention. In FIG. 27, constituent elements that are the same as or equivalent to those shown in FIG. 1 (Embodiment 1) are given the same reference numerals. Here, the description will be focused on the portion related to the third embodiment.

  As shown in FIG. 27, in the inverter control device according to the third embodiment, a converter circuit 39 is provided instead of DC power supply 1 in the inverter control device shown in FIG. 1 (first embodiment), and inverter control unit 7A Instead of this, an inverter control unit 7C is provided. In inverter control unit 7C, in place of voltage command value / phase command value calculating means 11A in inverter control unit 7A shown in FIG. 1 (Embodiment 1), for example, a voltage command value configured as shown in FIG. / Phase command value calculation means 11C is provided.

  The converter circuit 39 is a circuit that converts a commercial power supply 40 of AC 100 V into a DC power supply, and includes a reactor 41, a rectifying circuit 42, a switch 43, capacitors 44 and 45 for voltage doubler rectification, and a smoothing capacitor 46.

  The rectifier circuit 42 is configured by a diode bridge including two sets of diodes “D7, D8” and “D9, D10” connected in series between the DC bus P and the DC bus N. The series connection end of one set of diodes D9 and D10 is directly connected to one electrode end of the commercial power supply 40, and the series connection end of the other set of diodes D7 and D8 is connected to the other end of the commercial power supply 40 via the reactor 19. It is connected to the electrode end. The reactor 19 is provided to suppress the peak current of the commercial power supply 40 and improve the power factor. Further, the voltage rectifying capacitors 44 and 45 are arranged in series between the DC bus P and the DC bus N, and the smoothing capacitor 46 is also arranged between the DC bus P and the DC bus N. Yes. The switch 43 controlled by the voltage command value / phase command value calculating means 11C is disposed between the series connection end of the capacitors 44 and 45 and the series connection end of the diodes D9 and D10.

  FIG. 28 is a block diagram showing a configuration example of the voltage command value / phase command value calculating means 11C. As shown in FIG. 28, in the voltage command value / phase command value calculating means 11C, a switch switching means 11p is added to the voltage command value / phase command value calculating means 11A shown in FIG. The switch switching unit 11p includes a binary level signal that causes the switch 43 to perform a closing operation (ON operation) and an opening operation (OFF operation) based on the execution frequency f obtained by the frequency / phase estimation unit 11b. Outputs a switch switching signal.

  Next, the operation of the configuration according to the third embodiment will be described with reference to FIG. FIG. 29 is a flowchart for explaining the operation of the switch switching means 11p. In FIG. 29, the switch switching unit 11p determines whether or not the execution frequency f estimated by the frequency / phase estimation unit 11b is less than the determination reference frequency C [Hz] (ST13). As a result, when f <C [Hz] (ST13: Yes), a switch switching signal for causing the switch 43 to perform an opening operation (off operation) is output (ST14). As a result, the converter circuit 39 performs a full-wave rectification operation, so that the DC buses P and N are connected to a DC power source by the full-wave rectification operation.

  On the other hand, in ST13, when f ≧ C [Hz] (ST13: No), it is determined whether or not the execution frequency f exceeds another determination reference frequency D [Hz] where C [Hz] <D [Hz]. If it is determined (ST15) and f> D [Hz] (ST15: Yes), a switch switching signal for causing the switch 43 to perform a closing operation (ON operation) is output (ST16). As a result, the voltage doubler rectification operation is performed in the converter circuit 39, so that a higher DC power source is connected to the DC buses P and N than in the full-wave rectification operation.

  In ST15, when C ≦ f ≦ D [Hz] (ST15: No), the operation state of the switch 43 is not changed. That is, when the switch 43 performs, for example, a closing operation (ON operation), the switch switching unit 11p outputs a switch switching signal for maintaining it.

  Here, with respect to the frequencies C [Hz] and D [Hz] that give judgment criteria, appropriate hysteresis is provided. For example, D = C + 10 [Hz]. Accordingly, it is possible to prevent the switch 43 from being frequently switched, and it is possible to prevent noise from being generated in the switch 43.

  As described above, according to the third embodiment, a converter circuit that is a variable DC power supply is provided instead of a fixed DC power supply, and the power supply voltage is lowered when the execution frequency is low. It becomes easy to ensure the pulse width of the target PWM signal to be equal to or greater than the determination time width. Therefore, since the range in which the phase current information for two phases can be obtained from the direct current can be expanded, a reliable inverter control device that can be stably controlled can be obtained. Further, since the ratio of the PWM pattern 2 from which phase current information for two phases can be obtained without shifting is increased, it is possible to suppress the influence of efficiency reduction due to generation of regenerative current due to shifting of the PWM signal as much as possible. .

  In the third embodiment, there are two types of variable DC power supplies, one based on full-wave rectification and the other based on voltage doubler rectification. However, a means that can vary the DC voltage more finely is used. Good. Moreover, although the execution frequency f was used as the condition for switching the DC voltage, other parameters (for example, the voltage command value V *) that can obtain the same effect may be used as the switching condition.

  In the third embodiment, the application example to the first embodiment has been described. However, the third embodiment can be similarly applied to the second embodiment. According to this, it is possible to obtain an effect that finer control can be realized by using the carrier frequency changing means and the means for changing the DC voltage in combination.

  As described above, the inverter control device according to the present invention generates one instantaneous current without being restricted by the zero voltage vector when generating a PWM signal based on a direct current flowing in the bus of the inverter main circuit. Useful for realizing reliable and stable operation without the restriction that information is detected in the first half of one carrier cycle of PWM signal and the remaining instantaneous current information is detected in the second half of one carrier cycle. It is.

It is a block diagram which shows the structure of the inverter control apparatus by Embodiment 1 of this invention. It is a circuit diagram which shows the structural example of the direct current amplifier circuit shown in FIG. FIG. 2 is a circuit diagram illustrating a configuration example of a DC voltage detection circuit illustrated in FIG. 1. It is a block diagram which shows the structural example of the voltage command value / phase command value calculating means shown in FIG. FIG. 2 is a vector diagram for explaining a relationship between a basic voltage vector that defines a switching state of a semiconductor switching element of the inverter main circuit shown in FIG. 1, and a voltage command value and a phase command value generated by a voltage command value / phase command value calculation means. . It is the figure which showed collectively the relationship between eight types of basic voltage vectors shown in FIG. 5, and the switching state of a semiconductor switching element. It is a time chart explaining operation | movement of the timer value calculating means shown in FIG. It is a figure explaining the relationship between the node shown in FIG. 7, and a carrier. It is a figure explaining the operation | movement (in the case of node = 1) of the PWM signal generation means shown in FIG. It is a figure explaining the operation | movement (when node = 2) of the PWM signal generation means shown in FIG. It is the figure which showed collectively the relationship between the voltage vector state, the generated PWM signal, and the phase current information obtained from the detected DC current information. 3 is a flowchart for explaining the operation of a PWM signal shift determination unit shown in FIG. It is the figure which showed collectively the relationship between the node shown in FIG. 7, and two PWM signals used as the object of two pulse widths used when a PWM signal shift determination means performs the necessity determination of a shift in the node. It is a figure explaining the direct current-> phase current conversion required time which PWM signal shift determination means uses by determination operation | movement, and operation | movement (when node = 1) of the detection timing generation means shown in FIG. 13 is a time chart for explaining an example of a PWM signal determined to be shifted by the shift method 1 in FIG. 12 (when node = 1). 13 is a time chart for explaining an example of a PWM signal determined to be shifted by the shift method 2 in FIG. 12 (when node = 1). 2 is a time chart for explaining an operation (when node = 1) in which the PWM signal shift means shown in FIG. 1 performs a shift method 1 to obtain a PWM signal of a PWM pattern 3; 3 is a time chart for explaining an operation (when node = 1) in which the PWM signal shift means shown in FIG. 1 performs a shift method 2 to obtain a PWM signal of a PWM pattern 4; 3 is a table collectively showing the relationship between voltage vector information held by the voltage vector information holding means shown in FIG. 1 for PWM patterns 2 and 4 and nodes. 3 is a table collectively showing the relationship between voltage vector information held by the voltage vector information holding means shown in FIG. 1 for a PWM pattern 3 and nodes. FIG. 5 is a diagram for explaining the timing relationship of each phase in the voltage command value / phase command value calculating means shown in FIG. 4. It is a block diagram which shows the structure of the inverter control apparatus by Embodiment 2 of this invention. It is a block diagram which shows the structural example of the voltage command value / phase command value calculating means shown in FIG. It is a flowchart explaining operation | movement of the carrier frequency change means shown in FIG. It is a figure explaining the operation | movement (the 1) which a phase command value calculating means shown in FIG. 23 performs based on the carrier frequency command value from a carrier frequency change means. It is a figure explaining the operation | movement (the 2) which a phase command value calculating means shown in FIG. 23 performs based on the carrier frequency command value from a carrier frequency change means. It is a block diagram which shows the structure of the inverter control apparatus by Embodiment 3 of this invention. It is a block diagram which shows the structural example of the voltage command value / phase command value calculating means shown in FIG. It is a flowchart explaining operation | movement of the switch switching means shown in FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 DC power supply 2 Inverter main circuit 3 Three-phase motor 4 Resistor 5 DC current amplification circuit 6 DC voltage detection circuit 7A, 7B, 7C Inverter control part 8, 9 A / D converter 10 DC current / phase current conversion means 11A, 11B, 11C Voltage command value / phase command value calculation means 11a 3 phase / 2 phase coordinate conversion means 11b Frequency / phase estimation means 11c Frequency comparison means 11d d axis current command value calculation means 11e d axis current comparison means 11f q axis current command Value calculation means 11g q-axis current comparison means 11h dq-axis voltage command value calculation means 11i voltage command value calculation means 11j, 11n phase command value calculation means 11k dq conversion phase calculation means 11L dq conversion phase holding means 11m carrier frequency change means 11p switch switching means 12 timer value calculating means 13A, 13B PWM signal generating means 14 PWM signal shift determining means 15 PWM signal shifting means 16 Detection timing generating means 17 Voltage vector information holding means 39 Converter circuit 40 Commercial power supply 41 Reactor 42 Rectifier circuit 43 Switch 44, 45 Double voltage rectifier capacitor 46 Smoothing capacitor P DC bus on the positive side N DC bus on the negative side Q DC current detection means

Claims (10)

An inverter main circuit for converting DC power supplied by the DC power source into three-phase AC power using a plurality of semiconductor switching elements disposed between DC buses respectively connected to the positive electrode end and the negative electrode end of the DC power source; In an inverter control device comprising an inverter control unit for controlling an inverter main circuit,
The inverter control unit
DC current detection means for detecting a DC current flowing in one of the DC buses;
Timer value calculating means for calculating a timer value for each phase based on phase current information obtained from the DC current detected by the DC current detecting means;
PMW signal generation means for generating a PWM signal for on / off control of the plurality of semiconductor switching elements based on the timer value of each phase obtained by the timer value calculation means;
PWM signal shift determination means for determining whether or not to supply the inverter main circuit after shifting the PWM signal for each carrier period;
PWM signal shift for shifting the PWM signal so that the number of phase current information obtained from the DC current increases within one carrier period when the PWM signal shift determining means determines that the PWM signal is output after being shifted. Means,
An inverter control device comprising: detection timing generation means for generating timing for detecting the phase current information from the DC current based on the PWM signal that is finally supplied to the inverter main circuit.   In each phase, the timer value calculation means has a total of 60 °, 30 ° before and after the maximum phase of the phase voltage fundamental wave, and a total of 60 ° 30 ° before and after the minimum phase of the phase voltage fundamental wave. 2. The inverter control device according to claim 1, wherein each phase timer value is generated based on a two-phase modulation method for controlling so as not to switch between sections.   The PWM signal shift determining means is based on the difference between the pulse width and the pulse width of the PWM signal generated by the PWM signal generating means, or the difference between the timer value and the timer value obtained by the timer value calculating means. The inverter control device according to claim 1, wherein the necessity of the shift is determined based on the determination.   The PWM signal shift means performs a shift operation to increase the number of phase current information obtained from the DC current within one carrier period so that the shift amount of the PWM signal is minimized. The inverter control device according to claim 1.   When the pulse width of the PWM signal generated by the PWM signal generation means is greater than a certain value, the PWM signal shift means has the phase current information for two phases obtained from the DC current in the latter half of one carrier period. The inverter control device according to claim 1, wherein the PWM signal is shifted so as to be obtained.   If the phase control information for two phases cannot be obtained from the DC current within one carrier cycle, the inverter control unit controls the inverter main circuit in an open loop until the phase current information for the two phases is obtained. Thereafter, the inverter control apparatus according to claim 1, further comprising means for providing a limiter to a pulse width of the PWM signal output from the PWM signal generating means.   The inverter control unit performs a three-phase / two-phase coordinate conversion process on phase current information of each phase obtained from the direct current to generate a d-axis current and a q-axis current, and generates a d-axis current and a q-axis current. And when phase current information for two phases cannot be obtained from the DC current within one carrier cycle, it is based on the d-axis current value and q-axis current value previously calculated by the three-phase / 2-phase coordinate conversion means. The inverter control device according to claim 1, further comprising a means for controlling the inverter main circuit.   The three-phase / two-phase coordinate conversion means performs a three-phase / two-phase coordinate conversion process at a phase intermediate between detection timings of phase current information for two phases obtained from the DC current. Item 8. The inverter control device according to Item 7.   2. The inverter according to claim 1, wherein the inverter control unit includes means for switching the carrier frequency so as to lower the carrier frequency when the execution frequency is low or when the voltage command value is small. Control device. The DC power supply is a variable DC power supply capable of switching and outputting two or more DC voltages,
The said inverter control part is provided with the means to switch the said variable DC power supply so that a low DC voltage may be output when an execution frequency is low or a voltage command value is small. Inverter control device.

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