JP2007081533A - Power-on reset circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a power-on reset circuit capable of generating a reset signal when a power supply voltage rises up to a desired voltage at application of power and thereafter automatically reducing a consumed current. <P>SOLUTION: At application of power, a control circuit section 3 supplies a current to resistors R1 to R3 and a diode D1, when a voltage determined from a power supply through the resistors R1, R3 exceeds the forward voltage of the diode D1, a comparator 11 outputs a reset signal RES, and a sleep signal SLEEP and the reset signal RES for automatically shutting off the current supplied to the resistors R1 to R3 and the diode D1 are respectively applied to a clock input terminal CK of a D flip-flop DFF1 for controlling operations of a PMOS transistor TR1 and the comparator 11. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a power-on reset circuit of a semiconductor integrated circuit used for a device requiring low power consumption such as a portable device.

FIG. 4 is a diagram showing a circuit example of a conventional power-on reset circuit.
In FIG. 4, after the power is turned on, the voltage V101 at the inverting input terminal of the comparator 101 becomes the forward voltage VD101 of the diode D101, and the voltage V102 at the non-inverting input terminal of the comparator 101 is V102 = VCC with respect to the power supply voltage VCC. Xr103 / (r101 + r103). Note that r101 indicates the resistance value of the resistor R101, and r103 indicates the resistance value of the resistor R103. When the power supply voltage VCC rises and V102> VD101, the reset signal RESET, which is the output signal of the comparator 101, changes from the low level to the high level. To change. From such an operation, the power-on reset is performed by setting the resistance values of the resistors R101 and R103 so that the high-level reset signal RESET is output from the comparator 101 when the power supply voltage VCC becomes a desired voltage after power-on. A circuit can be realized.

Further, as shown in FIG. 5, there is a circuit in which a circuit is further added to the circuit of FIG. 4 (see, for example, Patent Document 1).
In FIG. 5, when the power is turned on, the charging time of the capacitor C111 is set by the resistor R111, and the Q output of the flip-flop 114 is set to a low level to turn on the P-channel MOS transistor 115 and supply a current to the reset pulse generating circuit 116. The reset pulse is generated from the reset pulse generation circuit 116. Further, the current to the reset pulse generating circuit 116 can be cut off by turning off the P-channel MOS transistor 115 by the sleep signal SLEEP.

FIG. 6 is a diagram showing another example of a conventional power-on reset circuit (see, for example, Patent Document 2).
In FIG. 6, when the power supply voltage VDD rises, a current flows through the transistors M121, M122, and M123, and when the drain voltage Pr0 of the transistor M122 exceeds the threshold voltage of the inverter composed of the transistors Mp and Mn, The output signal Pr changes from high level to low level. A feature of the circuit of FIG. 6 is that the chip area can be reduced because the circuit can be configured with only transistors without using resistors and capacitors.
JP 2004-48429 A JP 2003-283317 A

  However, the circuit of FIG. 4 has a problem that the current consumption of the power-on reset circuit cannot be cut off. Further, in the circuit of FIG. 5, in the state immediately after the reset is applied when the power is turned on, a current flows in the circuit, and the current is cut off unless the sleep signal SLEEP is set to the high level after the reset pulse is generated. I couldn't. Further, in the circuit using the threshold value of the inverter as shown in FIG. 6, the temperature characteristic of the threshold voltage for outputting the reset signal is compared with the circuit constituted by the diode and the comparator as shown in FIG. There was a problem that was large.

  The present invention has been made to solve the above-described problems, and generates a reset signal when the power supply voltage rises to a desired voltage when power is turned on, and then automatically reduces current consumption. It is an object to obtain a power-on reset circuit capable of

The power-on reset circuit according to the present invention is a power-on reset circuit that generates and outputs a predetermined reset signal when the power is turned on.
A forward voltage generation circuit unit that generates and outputs a forward voltage of a diode generated by the power supply current when power is supplied;
A voltage dividing circuit section that divides the power supply voltage at a predetermined voltage dividing ratio so as to be larger than the forward voltage when power is supplied;
A voltage comparison between the divided voltage from the voltage dividing circuit unit and the forward voltage from the forward voltage generation circuit unit is performed, and the reset signal including a binary signal indicating the comparison result is generated. A voltage comparison circuit to output;
A switch circuit unit that supplies power to the voltage dividing circuit unit and the forward voltage generation circuit unit in accordance with an input control signal;
A control circuit unit that controls the operation of the switch circuit unit according to a reset signal output from the voltage comparison circuit unit;
With
The voltage dividing circuit unit generates the divided voltage so that a forward voltage from the forward voltage generation circuit unit increases when the power supply voltage rises after power is turned on, and the voltage comparison circuit unit When the divided voltage is smaller than the forward voltage, the reset signal is asserted, and when the divided voltage becomes larger than the forward voltage and the reset signal is negated, the control circuit unit The switch circuit unit cuts off the power supply to the voltage dividing circuit unit and the forward voltage generation circuit unit.

  In addition, the voltage comparison circuit unit performs a sleep operation to stop operation and reduce power consumption when a predetermined control signal is input, and the control circuit unit receives the voltage when the reset signal is negated. The comparison circuit unit is caused to perform the sleep operation.

  The control circuit unit includes a flip-flop to which the reset signal is input at a clock input terminal, and the operation of the switch circuit unit and the voltage comparison circuit unit is controlled by an output signal of the flip-flop.

  According to the power-on reset circuit of the present invention, the voltage dividing circuit unit is configured such that the forward voltage from the forward voltage generation circuit unit increases when the power supply voltage rises after power-on. The voltage comparison circuit unit asserts the reset signal when the divided voltage is smaller than the forward voltage, and the control circuit unit determines that the divided voltage is larger than the forward voltage. When the reset signal is negated, the power supply to the voltage dividing circuit unit and the forward voltage generation circuit unit is cut off from the switch circuit unit. It is possible to automatically cut off the current supply to the forward voltage generation circuit unit and the voltage dividing circuit unit to reduce power consumption.

  In addition, when the reset signal is negated, the voltage comparison circuit unit is caused to perform the sleep operation. Therefore, after the power-on reset, the voltage comparison circuit unit is automatically set to the sleep operation state. Therefore, power consumption can be further reduced.

Next, the present invention will be described in detail based on the embodiments shown in the drawings.
First embodiment.
FIG. 1 is a diagram showing a circuit example of a power-on reset circuit according to the first embodiment of the present invention.
In FIG. 1, a power-on reset circuit 1 includes a reset signal generation circuit 2 that generates and outputs a predetermined reset signal RES at power-on, and a PMOS transistor that supplies a power supply voltage VCC to the reset signal generation circuit 2 TR1 and a control circuit unit 3 that controls the operation of the PMOS transistor TR1.

  The reset signal generation circuit unit 2 includes a comparator 11, a diode D1, and resistors R1 to R3. The control circuit unit 3 includes a D flip-flop DFF1, AND circuits AN1 and AN2, NAND circuit NA1, an OR circuit OR1, an inverter INV1, The first delay circuit 15, the second delay circuit 16, and the third delay circuit 17 are configured. The first delay circuit 15 is configured by an inverter, and the second delay circuit 16 and the third delay circuit 17 are each configured by a buffer. The resistors R1 and R3 form a voltage dividing circuit, the resistor R2 and the diode D1 form a forward voltage generation circuit, the comparator 11 forms a voltage comparison circuit, and the PMOS transistor TR1 forms a switch circuit.

  The source of the PMOS transistor TR1 is connected to the power supply voltage VCC, and resistors R1 and R3 are connected in series between the drain of the PMOS transistor TR1 and the ground voltage. The connection portion between the resistors R1 and R3 is connected to the non-inverting input terminal of the comparator 11, and the reset signal RES is output from the output terminal of the comparator 11. A resistor R2 is connected between the drain of the PMOS transistor TR1 and the inverting input terminal of the comparator 11, and a diode D1 is connected between the inverting input terminal of the comparator 11 and the ground voltage.

  The sleep signal SLEEP is input from the outside to one input terminal of the AND circuit AN1, and the sleep signal SLEEP is input to one input terminal of the OR circuit OR1 via the inverter INV1. The output terminal of the inverter INV1 is input to the other input terminal of the OR circuit OR1 through the first delay circuit 15. The output terminal of the OR circuit OR1 is connected to one input terminal of the AND circuit AN2 via the second delay circuit 16 and to one input terminal of the NAND circuit NA1. The reset signal RES is input to the other input terminal of the NAND circuit NA1, and the reset signal RES is input to the other input terminal of the AND circuit AN2 via the third delay circuit 17.

  The output terminal of the AND circuit AN2 is connected to the clock input terminal CK of the D flip-flop DFF1, and the output terminal of the NAND circuit NA1 is connected to the input terminal R of the D flip-flop DFF1. The power supply voltage VCC is input to the input terminal D of the D flip-flop DFF1, and the output terminal Q of the D flip-flop DFF1 is connected to the other input terminal of the AND circuit AN1. The output terminal of the AND circuit AN1 is connected to the gate of the PMOS transistor TR1 and to the sleep signal input terminal SLP of the comparator 11.

In such a configuration, FIG. 2 is a timing chart showing a waveform example of each part in the power-on reset circuit 1 in FIG. 1, and the operation of the power-on reset circuit 1 in FIG. 1 will be described with reference to FIG. .
In FIG. 2, “INV1-out” is the output signal of the inverter INV1, “Delay1-out” is the output signal of the first delay circuit 15, “OR1-out” is the output signal of the OR circuit OR1, and “Delay2- “out” indicates an output signal of the second delay circuit 16.

  “AN2-out” indicates the output signal of the AND circuit AN2, “NA1-out” indicates the output signal of the NAND circuit NA1, “DFF1-R” indicates the waveform of the input terminal R of the D flip-flop DFF1, “DFF1-Q” indicates the waveform of the output terminal Q of the D flip-flop DFF1, and “AN1-out” indicates the output signal of the AND circuit AN1. “COMP1-SLP” is the waveform of the sleep signal input terminal SLP of the comparator 11, “COMP1-in +” is the waveform of the non-inverting input terminal of the comparator 11, and “COMP1-in−” is the inverting input terminal of the comparator 11. “COMP1-out” indicates the output signal of the comparator 11, and “Delay3-out” indicates the output signal of the third delay circuit 17.

FIG. 2 shows the operation in each of the operation blocks B1 to B4. The operation block B1 is when the power is turned on, and the operation block B2 is a current cut-off state (hereinafter referred to as current) to the reset signal generation circuit unit 2 after the power is turned on. The operation block B3 indicates a current interruption release state when the sleep signal SLEEP becomes low level, and the operation block B4 causes the sleep signal SLEEP to become high level. Each current interruption state is shown.
In the operation block B1, it is assumed that the sleep signal SLEEP is set to a high level (state a). That is, the sleep signal SLEEP also rises simultaneously with the rise of the power supply voltage VCC, and the output signal of the inverter INV1 is a signal obtained by inverting the signal level of the sleep signal SLEEP, so that it is stable at a low level.

The output signal of the first delay circuit 15 is a signal obtained by delaying the sleep signal SLEEP, and the output signal of the OR circuit OR1 indicates the logical sum of the output signal of the inverter INV1 and the output signal of the first delay circuit 15. And rises with the output signal of the first delay circuit 15.
Here, it is considered separately when the reset signal RES is at a low level and at a high level.
When the reset signal RES is at a low level, the output signal of the NAND circuit NA1 is at a high level, the D flip-flop DFF1 is reset, and the output terminal Q of the D flip-flop DFF1 is at a low level. That is, the output signal of the AND circuit AN1 becomes a low level, and the PMOS transistor TR1 is turned on to make it conductive and the comparator 11 is operated.

When a current flows through the resistors R1 and R2, the inverting input terminal of the comparator 11 becomes the same as the forward voltage of the diode D1, and becomes about 0.7V. On the other hand, when the resistance values of the resistors R1 and R3 are r1 and r3, the voltage at the non-inverting input terminal of the comparator 11 is VCC × r3 / (r1 + r3). When the power supply voltage VCC rises, when the voltage at the non-inverting input terminal of the comparator 11 rises to the forward voltage of the diode D1, the reset signal RES that is the output signal of the comparator 11 rises from a low level to a high level (state) b).
Even when the reset signal RES is at a high level in the initial state, the output signal of the OR circuit OR1 maintains the delay time and the low level of the first delay circuit 15, so that the output signal of the NAND circuit NA1 is also changed from the high level. Since the D flip-flop DFF1 has been reset, the PMOS transistor TR1 is turned on and the comparator 11 is activated as described above.

  When the reset signal RES changes from low level to high level (state b), the output signal of the NAND circuit NA1 becomes low level, and the reset state of the D flip-flop DFF1 is released. Further, after the delay time by the third delay circuit 17, since the output signal of the third delay circuit 17 becomes high level, the D flip-flop DFF1 rises the clock and reads the power supply voltage VCC as input data. The end Q becomes a high level. Since the sleep signal SLEEP is at a high level, the output signal of the AND circuit AN1 is at a high level, the PMOS transistor TR1 is turned off, and the comparator 11 stops operating. At this time, the comparator 11 is a circuit as shown in FIG. 3, and when the output end of the comparator 11 becomes high level in the sleep state, the reset signal RES is held in the high level state, and the D flip-flop The input signal of DFF1 does not change any further. This is the state of the operation block B2 in FIG.

  Next, the operation when the sleep signal SLEEP is set to the low level (state d), the PMOS transistor TR1 is turned on and the comparator 11 is operated is the operation block B3. In the operation block B3, the output signal of the inverter INV1 becomes a high level, the high level signal is delayed by the first delay circuit 15, and then output from the first delay circuit 15 as a low level signal. However, since a high level signal is input from the inverter INV1, the OR circuit OR1 outputs a high level signal regardless of the signal level of the signal input from the first delay circuit 15. Since there is no change in the signal level of each input terminal of the D flip-flop DFF1, the output terminal Q remains at the high level and the sleep signal SLEEP is at the low level, so that the output signal of the AND circuit AN1 is at the low level. Thus, the PMOS transistor TR1 is turned on and the comparator 11 is operated. Unlike when the power is turned on, the input voltage of the comparator 11 instantaneously becomes (the voltage at the non-inverting input terminal)> (the voltage at the inverting input terminal), so the reset signal RES remains at the low level.

  The operation when the sleep signal SLEEP is set to the high level again (state e) is the operation block B4. In the operation block B4, the output signal of the inverter INV1 becomes low level, and the low level signal is delayed by the first delay circuit 15 and then output from the first delay circuit 15 as a high level signal. For this reason, the output signal of the OR circuit OR1 becomes low level for the delay time of the first delay circuit 15, and then returns to high level. Since the reset signal RES is at a high level, the NAND circuit NA1 outputs a low level reset pulse to the D flip-flop DFF1, so that the output terminal Q of the D flip-flop DFF1 is at a low level.

  At this time, the output signal of the AND circuit AN1 is at a low level, the PMOS transistor TR1 is turned on and the comparator 11 is operated. However, after the delay time by the second delay circuit 16, the clock input terminal CK of the D flip-flop DFF1 changes from low level to high level, so that the output terminal Q returns to high level and the output signal of the AND circuit AN1 becomes high level. . For this reason, the PMOS transistor TR1 is turned off and the comparator 11 stops operating. In this way, it is possible to realize an operation in which the current is automatically interrupted by being reset when the power is turned on without causing any trouble in the control by the sleep signal SLEEP.

  As described above, the power-on reset circuit according to the first embodiment inputs the sleep signal SLEEP and the reset signal RES to the clock input terminal CK of the D flip-flop DFF1 that controls the operation of the PMOS transistor TR1 and the comparator 11. Therefore, after power-on reset, current supply to a part of the circuits in the reset signal generation circuit unit 2 can be automatically cut off to reduce power consumption.

It is the figure which showed the circuit example of the power-on reset circuit in the 1st Embodiment of this invention. 2 is a timing chart showing an example of waveforms at various parts in the power-on reset circuit 1 of FIG. 1. It is the figure which showed the example of the internal circuit of the comparator 11 of FIG. It is the figure which showed the circuit example of the conventional power-on reset circuit. It is the figure which showed the other circuit example of the conventional power-on reset circuit. It is the figure which showed the other circuit example of the conventional power-on reset circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Power-on reset circuit 2 Reset signal generation circuit part 3 Control circuit part 11 Comparator 15 1st delay circuit 16 2nd delay circuit 17 3rd delay circuit D1 Diode R1-R3 Resistance TR1 PMOS transistor DFF1 D flip-flop AN1, AN2 AND circuit NA1 NAND circuit OR1 OR circuit INV1 Inverter

Claims (3)

In a power-on reset circuit that generates and outputs a predetermined reset signal when the power is turned on,
A forward voltage generation circuit unit that generates and outputs a forward voltage of a diode generated by the power supply current when power is supplied;
A voltage dividing circuit section that divides the power supply voltage at a predetermined voltage dividing ratio so as to be larger than the forward voltage when power is supplied;
A voltage comparison between the divided voltage from the voltage dividing circuit unit and the forward voltage from the forward voltage generation circuit unit is performed, and the reset signal including a binary signal indicating the comparison result is generated. A voltage comparison circuit to output;
A switch circuit unit that supplies power to the voltage dividing circuit unit and the forward voltage generation circuit unit in accordance with an input control signal;
A control circuit unit that controls the operation of the switch circuit unit according to a reset signal output from the voltage comparison circuit unit;
With
The voltage dividing circuit unit generates the divided voltage so that a forward voltage from the forward voltage generation circuit unit increases when the power supply voltage rises after power is turned on, and the voltage comparison circuit unit When the divided voltage is smaller than the forward voltage, the reset signal is asserted, and when the divided voltage becomes larger than the forward voltage and the reset signal is negated, the control circuit unit A power-on reset circuit characterized in that the switch circuit unit cuts off power supply to the voltage dividing circuit unit and the forward voltage generation circuit unit.   The voltage comparison circuit unit performs a sleep operation to stop operation and reduce power consumption when a predetermined control signal is input, and when the reset signal is negated, the voltage comparison circuit unit The power-on reset circuit according to claim 1, wherein the sleep operation is performed by a unit. The control circuit unit includes a flip-flop to which the reset signal is input at a clock input terminal, and controls the operation of the switch circuit unit and the voltage comparison circuit unit according to an output signal of the flip-flop. 3. A power-on reset circuit according to 2.

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