JP2007081040A - Manufacturing method of semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce man-hours in manufacturing an integrated MOS capacitor. <P>SOLUTION: A manufacturing method of a semiconductor device having a MOS transistor and a MOS capacitor integrated includes a step (A) of doping a channel with impurities with a first conductivity type in a transistor formation region 100P and at the same time forming a first impurity layer 38 with a first conductivity type in a capacitor formation region 200C, a step (B) of forming a gate insulation layer 70 on the transistor formation region 100P and forming a dielectric layer 30 above the first impurity layer 38 in the region 200C, a step (C) of forming a gate electrode 72 above the gate insulation layer 70, a step (D) of forming a conductive layer 32 above the dielectric layer 30, a step (E) of forming a source 74 and a drain 76 with a second conductivity type in the transistor formation region 100P, and a step (F) of forming a second impurity layer 34 and a third impurity layer 36 with a first conductivity type in a semiconductor layer 10 on the side of the conductive layer 32 in the capacitor formation region 200C. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device.

In recent years, portable electronic devices have been reduced in weight and size, and research and development for reducing the size of semiconductor devices mounted on the electronic devices has been performed. As such a technique, there is a method in which a transistor and a MOS capacitor are mixedly mounted on the same substrate (same chip), and the entire semiconductor device mounted on an electronic device is reduced (see, for example, Japanese Patent Laid-Open No. 5-82730). ).
JP-A-5-82730

  An object of the present invention is to provide a semiconductor device manufacturing method capable of improving productivity and reducing production costs.

A method for manufacturing a semiconductor device according to the present invention includes:
(A) forming an element isolation region in the semiconductor layer;
(B) forming a first well of the first conductivity type in the semiconductor layer in the transistor formation region;
(C) forming a second well of the second conductivity type in the semiconductor layer in the capacitor formation region;
(D) Channel doping is performed by implanting a first conductivity type impurity into the semiconductor layer in the transistor formation region, and simultaneously, a first conductivity type first impurity layer is formed in the semiconductor layer in the capacitor formation region. Forming, and
(E) forming a gate insulating layer in the transistor formation region, and forming a dielectric layer above the first impurity layer in the capacitor formation region;
(F) forming a gate electrode above the gate insulating layer;
(G) forming a conductive layer above the dielectric layer;
(H) forming a second conductivity type source region and drain region in the transistor formation region;
(I) forming a second impurity layer of a first conductivity type and a third impurity layer in the semiconductor layer on the side of the conductive layer in the capacitor formation region.

  In this method of manufacturing a semiconductor device, the first conductivity type impurity is implanted into the semiconductor layer in the transistor formation region to perform channel doping, and at the same time, the first conductivity type is introduced into the semiconductor layer in the capacitor formation region. Forming the first impurity layer. Thus, for example, the transistor formation region is channel-doped while the capacitor formation region is covered with a resist layer, and the capacitor formation is performed as a separate step with the first transistor formation region covered with a resist layer. The manufacturing process can be simplified as compared with the case where the first impurity layer is formed in the region. As a result, productivity can be improved and production cost can be reduced.

  In the description of the present invention, the word “upper” is, for example, “forms another specific thing (hereinafter referred to as“ B ”)“ above ”a specific thing (hereinafter referred to as“ A ”)”. Etc. In the description according to the present invention, in the case of this example, the case where B is directly formed on A and the case where B is formed on A via another are included. The word “upward” is used.

  Preferred embodiments of the present invention will be described below with reference to the drawings.

  1. First, the semiconductor device according to the present embodiment will be described. FIG. 1 is a cross-sectional view schematically showing the semiconductor device according to the present embodiment.

  The semiconductor device according to this embodiment includes a semiconductor layer 10. The semiconductor layer 10 can be made of, for example, a p-type silicon substrate. The semiconductor device is provided with a first transistor formation region 100P, a second transistor formation region 100N, and a capacitor formation region 200C. A p-type first transistor 100p is formed in the first transistor formation region 100P. An n-type second transistor 100n is formed in the second transistor formation region 100N. A capacitor 200 is formed in the capacitor formation region 200C.

  That is, the p-type first transistor 100p, the n-type second transistor 100n, and the capacitor 200 are mounted together on the same substrate (same chip). Although FIG. 1 shows only two transistors and one capacitor, this is for convenience and the number of each transistor and capacitor is not particularly limited.

  Hereinafter, the first transistor formation region 100P, the second transistor formation region 100N, and the capacitor formation region 200C will be specifically described.

  1.1. First, the first transistor formation region 100P will be described.

  A p-type first transistor 100p is provided in the first transistor formation region 100P. The first transistor formation region 100P is surrounded by the element isolation region 20. The first transistor formation region 100P is adjacent to the second transistor formation region 100N, and the element isolation region 20 is formed at the boundary.

  The p-type first transistor 100p includes a first gate insulating layer 70, a first gate electrode 72, a p-type first source region 74, a p-type first drain region 76, a first channel region 78, n-type first well 80.

  The first gate insulating layer 70 is provided on the first channel region 78 in the first well 80. The first gate electrode 72 is formed on the first gate insulating layer 70. The first source region 74 and the first drain region 76 are formed in the upper portion of the first well 80 and between the first channel region 78 under the first gate insulating layer 70 and the element isolation region 20. . The first well 80 is formed in the upper part in the semiconductor layer 10. The first well 80 includes a first source region 74, a first drain region 76, and a first channel region 78.

  1.2. Next, the second transistor formation region 100N will be described.

  An n-type second transistor 100n is provided in the second transistor formation region 100N. The second transistor formation region 100N is surrounded by the element isolation region 20.

  The n-type second transistor 100n includes a second gate insulating layer 50, a second gate electrode 52, an n-type second source region 54, an n-type second drain region 56, a second channel region 58, p-type second well 40.

  The second gate insulating layer 50 is provided on the second channel region 58 in the second well 40. The second gate electrode 52 is formed on the second gate insulating layer 50. The second source region 54 and the second drain region 56 are formed in the upper portion of the second well 40 and between the second channel region 58 and the element isolation region 20 below the second gate insulating layer 50. . The second well 40 is formed in the upper part in the semiconductor layer 10. The second well 40 includes a second source region 54, a second drain region 56, and a second channel region 58. The second well 40 is continuously formed in the second transistor formation region 100N and the capacitor formation region 200C.

  1.3. Next, the capacitor formation region 200C will be described.

  The capacitor 200 is provided in the capacitor formation region 200C. The capacitor formation region 200 </ b> C is surrounded by the element isolation region 20. The capacitor formation region 200C is adjacent to the second transistor formation region 100N, and the element isolation region 20 is formed at the boundary.

  The capacitor 200 includes a dielectric layer 30, a conductive layer 32, an n-type first impurity layer 38, an n-type second impurity layer 34, an n-type third impurity layer 36, and a p-type second impurity layer. Well 40.

  The dielectric layer 30 is provided on the first impurity layer 38 in the second well 40. The conductive layer 32 is formed on the dielectric layer 30. The second impurity layer 34 and the third impurity layer 36 are formed in the upper portion of the second well 40 and between the first impurity layer 38 below the dielectric layer 30 and the element isolation region 20. The second well 40 is formed in the upper part in the semiconductor layer 10. The second well 40 includes first to third impurity layers 38, 34 and 36.

  2. Next, a method for manufacturing the semiconductor device according to the present embodiment will be described. 2 to 4 are sectional views schematically showing one manufacturing process of the semiconductor device according to the present embodiment. 2 to 4 correspond to the cross-sectional view shown in FIG.

  (1) First, an n-type first well 80 is formed in the semiconductor layer 10 of the first transistor formation region 100P by a known method, as shown in FIG. Similarly, the p-type second well 40 is formed in the semiconductor layer 10 in the second transistor formation region 100N and the capacitor formation region 200C. The order in which the first well 80 and the second well 40 are formed is not particularly limited. Next, as shown in FIG. 2, the element isolation region 20 is formed by, for example, the STI method.

  (2) Next, as shown in FIG. 3, a resist layer R <b> 1 having a predetermined pattern is formed on the semiconductor layer 10. Next, using the resist layer R1 as a mask, p-type impurities 90 are implanted into the semiconductor layer 10 to perform channel doping. Thereby, the second channel region 58 of the second transistor formation region 100N is formed. Thereafter, the resist layer R1 is removed.

(3) Next, as shown in FIG. 4, a resist layer R <b> 2 having a predetermined pattern is formed on the semiconductor layer 10. Next, channel doping is performed by implanting an n-type impurity 92 into the semiconductor layer 10 of the first transistor formation region 100P using the resist layer R2 as a mask. At the same time, an n-type impurity 92 is implanted into the semiconductor layer 10 in the capacitor formation region 200C. As a result, the first channel region 78 of the first transistor formation region 100P is formed, and the first impurity layer 38 of the capacitor formation region 200C is formed. As the n-type impurity 92, for example, arsenic (As), phosphorus (P), or the like can be used. As the implantation conditions of the impurity 92 in this step, for example, the implantation energy can be set to 30 keV to 100 keV, and the dose amount can be set to 1.0 × 10 ¹³ / cm ^{2 to} 3.0 × 10 ¹³ / cm ² . Thereafter, the resist layer R2 is removed.

  (4) Next, as shown in FIG. 1, the first gate insulating layer 70 in the first transistor formation region 100P, the second gate insulating layer 50 in the second transistor formation region 100N, and capacitor formation are performed by thermal oxidation. The dielectric layer 30 in the region 200C is formed. The first gate insulating layer 70, the second gate insulating layer 50, and the dielectric layer 30 can be patterned by a known method.

  Next, the first gate electrode 72 is formed on the first gate insulating layer 70, the second gate electrode 52 is formed on the second gate insulating layer 50, and the conductive layer 32 is formed on the dielectric layer 30. Form. The first gate electrode 72, the second gate electrode 52, and the conductive layer 32 are formed by, for example, a CVD method. As the first gate electrode 72, for example, p-type polysilicon can be used. As the second gate electrode 52 and the conductive layer 32, for example, n-type polysilicon can be used. The first gate electrode 72, the second gate electrode 52, and the conductive layer 32 are patterned using a known lithography technique and etching technique.

  Next, a resist layer (not shown) having a predetermined pattern is formed, and using this resist layer as a mask, n-type impurity ions are applied to the predetermined regions of the semiconductor layer 10 in the second transistor formation region 100N and the capacitor formation region 200C. Inject into the area. Thereby, as shown in FIG. 1, the second source region 54 and the second drain region 56 of the second transistor formation region 100N, and the second impurity layer 34 and the third impurity layer 36 of the capacitor formation region 200C are formed. The Thereafter, the resist layer is removed. Similarly, a first source region 74 and a first drain region 76 are formed in a predetermined region of the semiconductor layer 10 in the first transistor formation region 100P.

  The semiconductor device according to this embodiment can be manufactured through the above steps.

  3. In the method for manufacturing a semiconductor device according to the present embodiment, n-type impurities 92 are implanted into the semiconductor layer 10 in the first transistor formation region 100P to perform channel doping, and at the same time, in the semiconductor layer 10 in the capacitor formation region 200C. An n-type first impurity layer 38 is formed (see FIG. 4). Thereby, for example, channel doping is performed on the first transistor formation region 100P in a state where the capacitor formation region 200C is covered with the resist layer, and as a separate process, the capacitor formation region 200P is covered with the resist layer. The manufacturing process can be simplified as compared with the case where the first impurity layer 38 is formed in the formation region 200C. As a result, productivity can be improved and production cost can be reduced.

  4). As described above, the embodiments of the present invention have been described in detail. However, those skilled in the art can easily understand that many modifications can be made without departing from the novel matters and effects of the present invention. . Accordingly, all such modifications are included in the scope of the present invention.

  For example, the semiconductor device can be formed by exchanging all the p-type and n-type layers in the above-described embodiments.

FIG. 3 is a cross-sectional view schematically showing the semiconductor device according to the embodiment. Sectional drawing which shows typically one manufacturing process of the semiconductor device which concerns on this embodiment. Sectional drawing which shows typically one manufacturing process of the semiconductor device which concerns on this embodiment. Sectional drawing which shows typically one manufacturing process of the semiconductor device which concerns on this embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Semiconductor layer, 20 Element isolation region, 30 Dielectric layer, 32 Conductive layer, 34 2nd impurity layer, 36 3rd impurity layer, 38 1st impurity layer, 40 2nd well, 50 2nd gate insulating layer, 52 1st 2 gate electrode, 54 second source region, 56 second drain region, 58 second channel region, 70 first gate insulating layer, 72 first gate electrode, 74 first source region, 76 first drain region, 78 first Channel region, 80 first well, 90 impurity, 92 impurity, 100p first transistor, 100P first transistor formation region, 100n second transistor, 100N second transistor formation region, 200 capacitor, 200C capacitor formation region

Claims (1)

(A) forming an element isolation region in the semiconductor layer;
(B) forming a first well of the first conductivity type in the semiconductor layer in the transistor formation region;
(C) forming a second well of the second conductivity type in the semiconductor layer in the capacitor formation region;
(D) Channel doping is performed by implanting a first conductivity type impurity into the semiconductor layer in the transistor formation region, and simultaneously, a first conductivity type first impurity layer is formed in the semiconductor layer in the capacitor formation region. Forming, and
(E) forming a gate insulating layer in the transistor formation region, and forming a dielectric layer above the first impurity layer in the capacitor formation region;
(F) forming a gate electrode above the gate insulating layer;
(G) forming a conductive layer above the dielectric layer;
(H) forming a second conductivity type source region and drain region in the transistor formation region;
(I) forming a first impurity type second impurity layer and a third impurity layer in the semiconductor layer on the side of the conductive layer in the capacitor formation region, Method.

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