JP2007078643A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To eliminate the effect due to signal delay or waveform distortion caused by connecting a measurement system, such as an LSI tester in an AC test, without enlarging the circuit scale so much, in a semiconductor integrated circuit having a built-in interface circuit for transferring serial data. <P>SOLUTION: The semiconductor integrated circuit comprises a first storage region 13a for storing parallel data supplied from the outside, a transmission circuit 11 for converting parallel data stored in the first storage region into serial data and transmitting it, a reception circuit 12 for converting the serial data received from the outside into parallel data, a second storage region 13b for storing the parallel data converted by the receiving circuit, and a matching detection circuit 14 for detecting the matching of the parallel data stored in the first storage region, with the parallel data stored in the second storage region, and outputting the detection result to the outside. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit incorporating an interface circuit, and more particularly to a semiconductor integrated circuit incorporating an interface circuit that transfers high-speed serial data.

  For example, in a personal computer, an LVDS interface circuit using a low voltage differential signal (LVDS), which is a low voltage differential signal, is used to transfer image data as serial data at high speed between a main body and a display unit. It has been. In order to perform an AC test of such a high-speed interface circuit, an LSI tester capable of high-speed operation is usually used. However, a high-speed LSI tester is expensive and skew is generated due to a difference in delay amount between measurement channels, and the measurement result is easily affected by the skew. Various techniques have been developed to solve such problems and facilitate AC testing of high-speed interface circuits.

  As a related technique, the following Patent Document 1 discloses a semiconductor integrated circuit for inspecting a semiconductor device that operates at high speed by using an inspection apparatus having an operation speed slower than that of the semiconductor device, and an inspection method thereof. According to this inspection method, in the device under test, the first logic circuit converts the signal pattern of the normal signal transfer rate stored in the register into a high-speed signal pattern of a high signal transfer rate, and the high-speed signal is transmitted to the transmission circuit. Send. At the time of this inspection, the switch circuit is closed, and the transmitted high-speed signal is received by the receiving circuit. This received high-speed signal is output to the second logic circuit, converted to a low-speed signal at a normal rate by this logic circuit, and output to the inspection apparatus.

  Patent Document 2 below discloses a transmission device, a reception device, a test circuit, and a test method that operate the circuit at high speed while performing input / output to / from the tester at a low speed. This test circuit divides a test clock input from a tester to generate a PLL clock, stores input data input from the tester as a test clock, and outputs a FIFO output by the PLL clock, and input data. Bit-distributed encoder, driver that transmits encoder output signal to the outside, PLL that divides the test clock to generate PLL clock, decoder that bit-aligns the signal received by the receiver, and PLL clock And a FIFO for outputting the output signal of the decoder to the tester in synchronization with the test clock.

  According to Patent Document 1 or 2, it is possible to reduce the bit rate of data transmitted between the semiconductor integrated circuit and the LSI tester, but it is unavoidable that the transmission data is affected by signal delay or waveform distortion. Absent.

  Further, Patent Document 3 below discloses a test method for performing a high-speed I / O test exceeding 1 GHz quickly with a simple board configuration without changing the test system for each of a plurality of I / O specifications. Yes. In this test method, a semiconductor integrated circuit device is mounted on a load board provided with a loopback path for connecting an external output terminal and an external input terminal of a semiconductor integrated circuit device having a high-speed input / output device with a transmission line. The operation of the high-speed input / output device is tested inside the semiconductor integrated circuit device by using the test means and the loopback path provided inside the semiconductor integrated circuit device.

According to Patent Document 3, there is no need to transmit data between a semiconductor integrated circuit and an LSI tester, but there is a problem that the circuit scale becomes large because a boundary scan register is used.
JP 2000-171524 A (first page, FIG. 1) JP 2003-337161 A (first page, FIG. 1) Japanese Patent Laying-Open No. 2003-167034 (first page, FIG. 1)

  Therefore, in view of the above points, the present invention provides a semiconductor integrated circuit incorporating an interface circuit for transferring serial data by connecting a measurement system such as an LSI tester in an AC test without enlarging the circuit scale. The object is to eliminate the influence of signal delay and waveform distortion.

  In order to solve the above problem, a semiconductor integrated circuit according to one aspect of the present invention has a higher frequency than a first clock signal in synchronization with a first clock signal supplied from the outside in a test mode. A PLL circuit for generating a clock signal of 2, a first storage area for storing parallel data supplied from the outside in the test mode, and converting parallel data stored in the first storage area into serial data A transmission circuit for transmitting the serial data to the outside in synchronization with the second clock signal, and a reception circuit for receiving the serial data from the outside in synchronization with the second clock signal and converting the serial data to parallel data And in the test mode, the second storage area for storing the parallel data converted by the receiving circuit and the first storage area It performs coincidence detection between the parallel data stored in the parallel data and a second storage area being comprises a coincidence detection circuit for outputting a detection result to the outside.

  Here, the semiconductor integrated circuit includes a third storage area for storing data for setting a delay amount of the second clock signal supplied to the transmission circuit, and data stored in the third storage area. Based on this, a delay circuit for adjusting the delay amount of the second clock signal supplied to the transmission circuit in the test mode may be further provided.

  In addition, the semiconductor integrated circuit has a first switch circuit that selectively supplies parallel data read from the first storage area to the transmission circuit in the test mode, and a parallel converted by the reception circuit in the test mode. A second switch circuit that selectively supplies data to the second storage area; and a test control circuit that controls the first and second switch circuits in accordance with a test control signal supplied from the outside. May be.

  In this case, the semiconductor integrated circuit has a first terminal for transmitting serial data from the transmission circuit to the outside, a second terminal for receiving serial data from the outside to the reception circuit, and a first storage area. A third terminal for inputting parallel data stored in the memory, a fourth terminal for inputting data stored in the third storage area, and a test control signal supplied to the test control circuit are input. And a sixth terminal for inputting the first clock signal supplied to the PLL circuit, and a seventh terminal for outputting the detection result of the coincidence detection circuit. You may make it do. In the test mode, an AC test can be performed by externally shorting the first terminal and the second terminal.

  According to the present invention, the parallel data for transmission is stored in the first storage area, converted into serial data and transmitted, and the serial data obtained by receiving the parallel data is converted into parallel data to be converted into the second data. By storing these in the storage area, detecting the coincidence and outputting the detection results to the outside, the signal delay and waveform by connecting a measurement system such as an LSI tester in the AC test without significantly increasing the circuit scale The influence of distortion can be eliminated.

The best mode for carrying out the present invention will be described below in detail with reference to the drawings.
FIG. 1 is a diagram showing the configuration of a semiconductor integrated circuit and a measurement system for performing an AC test according to an embodiment of the present invention. When performing an AC test of the semiconductor integrated circuit 1, signals are transmitted between the semiconductor integrated circuit 1 and the LSI tester 3 using a probe card 2 having a plurality of probes. The probe card 2 is provided with a high-frequency relay 21 for forming a loopback path. Note that it is not necessary to use an LSI tester 3 having a high-speed specification in particular, so that the test cost can be reduced.

  As shown in FIG. 1, the semiconductor integrated circuit 1 is a high-speed interface circuit that generates a high-speed clock signal CKH having a frequency higher than that of the low-speed clock signal CKL in synchronization with the supplied low-speed clock signal CKL. The parallel circuit converts serial data into serial data, and transmits the serial data to the outside in synchronization with the high-speed clock signal CKH. The serial data is received from the outside in synchronization with the high-speed clock signal CKH. And a receiving circuit 12 for converting data into parallel data.

  The PLL circuit 10 is supplied with the low-speed clock signal CKL from the internal circuit in the normal operation mode, and the probe card 2 is connected from the LSI tester 3 in the test mode of the high-speed interface circuit (also simply referred to as “test mode” in the present application). Through this, the low-speed clock signal CKL is supplied.

  Further, the semiconductor integrated circuit 1 detects a match between the RAM (Random Access Memory) 13 and the data for transmission stored in the RAM 13 and the received data, and outputs a detection result to the outside. A delay circuit 15 that adjusts a delay amount of the high-speed clock signal CKH supplied to the transmission circuit 11 based on the delay control data stored in the circuit 14 and the RAM 13, switch circuits 16 to 18, and switch circuits 16 to And a test control circuit 19 for controlling 18.

  The RAM 13 is provided for use in general signal processing in the normal operation mode. In the test mode, the RAM 13 is used for temporarily storing data for transmission, received data, and the like. In the test mode, the RAM 13 stores a transmission data storage area 13a for storing parallel data supplied from the LSI tester 3 via the probe card 2, and a reception data storage for storing parallel data converted from serial data by the receiving circuit 12. An area 13b and a delay control data storage area 13c for storing delay control data for setting a delay amount in the delay circuit 15 are provided.

  The coincidence detection circuit 14 performs coincidence detection between the parallel data stored in the transmission data storage area 13a and the parallel data stored in the reception data storage area 13b. The delay circuit 15 adjusts the delay amount of the high-speed clock signal CKH generated by the PLL circuit 10 based on the delay control data stored in the delay control data storage area 13c. Thereby, the transition timing of data output from the transmission circuit 11 in synchronization with the high-speed clock signal CKH is adjusted, and the AC characteristics can be tested between the transmission circuit 11 and the reception circuit 12.

  The switch circuit 16 supplies the high-speed clock signal CKH generated by the PLL circuit 10 to the transmission circuit 11 in the normal operation mode, and transmits the high-speed clock signal CKH whose delay amount is adjusted by the delay circuit 15 in the test mode. 11 is supplied.

  The switch circuit 17 supplies the parallel data generated in the internal circuit to the transmission circuit 11 in the normal operation mode, and supplies the parallel data read from the transmission data storage area 13a of the RAM 13 to the transmission circuit 11 in the test mode. To do. The switch circuit 18 supplies the parallel data converted from the serial data by the receiving circuit 12 to the internal circuit in the normal operation mode, and the parallel data converted from the serial data by the receiving circuit 12 in the test mode in the RAM 13. The data is supplied to the reception data storage area 13b.

  The semiconductor integrated circuit 1 includes a terminal P1 for transmitting serial data from the transmission circuit 11 to the outside as a terminal (pad) used in both the normal operation mode and the test mode, and serial data to the reception circuit 12 from the outside. And a terminal P2 for receiving.

  Furthermore, parallel data stored in the transmission data storage area 13a of the RAM 13 is input to the semiconductor integrated circuit 1 as terminals (pads) used for inputting / outputting signals to / from the LSI tester 3 in the test mode. A terminal P3 for inputting data, a terminal P4 for inputting data stored in the delay control data storage area 13c of the RAM 13, a terminal P5 for inputting a test control signal supplied to the test control circuit 19, and a PLL A terminal P6 for inputting the low-speed clock signal CKL supplied to the circuit 10 and a terminal P7 for outputting the detection result of the coincidence detection circuit 14 are provided.

  In the test mode, under the control of the LSI tester 3, the high frequency relay 21 provided in the probe card 2 shorts the terminals P1 and P2. As a result, a loopback of high-speed serial data is formed in the vicinity of the semiconductor integrated circuit 1, and it is not necessary to transmit high-speed serial data between the semiconductor integrated circuit 1 and the LSI tester 3, so that the semiconductor integrated circuit 1 and the LSI tester 3 can avoid the influence of the wiring for connecting 3 to the high-speed serial data.

  The LSI tester 3 supplies the low-speed clock signal CKL to the PLL circuit 10 of the semiconductor integrated circuit 1 through the probe card 2 and supplies parallel data to the transmission data storage area 13 a of the RAM 13, thereby delay control data of the RAM 13. Delay control data is supplied to the storage area 13c.

  Further, the LSI tester 3 supplies a test control signal to the test control circuit 19 of the semiconductor integrated circuit 1 via the probe card 2, whereby the test control circuit 19 controls the switch circuits 16 to 18. As a result, the switch circuits 16 to 18 are connected as shown by a solid line in FIG. Thereby, the parallel data read from the transmission data storage area 13a of the RAM 13 is supplied to the transmission circuit 11, the delay amount of the serial data output from the transmission circuit 11 is adjusted by the delay circuit 15, and the reception circuit 12 The parallel data converted from the serial data is written in the reception data storage area 13b of the RAM 13.

  The coincidence detection circuit 14 compares the parallel data stored in the transmission data storage area 13a with the parallel data stored in the reception data storage area 13b, and performs coincidence detection. 2 to output to the LSI tester 3. Thus, using the RAM 13 built in the semiconductor integrated circuit 1, the parallel data for transmission and the parallel data converted from the received serial data are temporarily stored in the memory and then compared. Thus, coincidence detection can be simultaneously performed on a plurality of bits included in the parallel data, and the detection result can be output. Unlike the case where the transmission data is output and the coincidence detection is performed by the LSI tester 3, the AC of the transmission system and the reception system is not affected by signal delay or waveform distortion in the wiring between the semiconductor integrated circuit 1 and the LSI tester 3. Tests can be performed simultaneously.

The figure which shows the structure of the measurement system for performing the semiconductor integrated circuit and AC test concerning one Embodiment of this invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 Semiconductor integrated circuit, 2 Probe card, 3 LSI tester, 10 PLL circuit, 11 Transmission circuit, 12 Reception circuit, 13 RAM, 13a Transmission data storage area, 13b Reception data storage area, 13c Delay control data storage area, 14 Match detection Circuit, 15 delay circuit, 16-18 switch circuit, 19 test control circuit, 21 relay

Claims (5)

A PLL circuit that generates a second clock signal having a frequency higher than that of the first clock signal in synchronization with the first clock signal supplied from the outside in the test mode;
A first storage area for storing parallel data supplied from outside in the test mode;
A transmission circuit for converting parallel data stored in the first storage area into serial data and transmitting the serial data to the outside in synchronization with a second clock signal;
A receiving circuit for receiving serial data from the outside in synchronization with the second clock signal and converting the serial data into parallel data;
A second storage area for storing parallel data converted by the receiving circuit in the test mode;
A coincidence detection circuit for performing coincidence detection between the parallel data stored in the first storage area and the parallel data stored in the second storage area, and outputting a detection result to the outside;
A semiconductor integrated circuit comprising: A third storage area for storing data for setting a delay amount of the second clock signal supplied to the transmission circuit;
A delay circuit that adjusts a delay amount of the second clock signal supplied to the transmission circuit in a test mode based on data stored in the third storage area;
The semiconductor integrated circuit according to claim 1, further comprising: In a test mode, a first switch circuit that selectively supplies parallel data read from the first storage area to the transmission circuit;
A second switch circuit for selectively supplying the parallel data converted by the receiving circuit to the second storage area in a test mode;
A test control circuit for controlling the first and second switch circuits in accordance with a test control signal supplied from the outside;
The semiconductor integrated circuit according to claim 2, further comprising: A first terminal for transmitting serial data from the transmission circuit to the outside;
A second terminal for receiving serial data from the outside to the receiving circuit;
A third terminal for inputting parallel data stored in the first storage area;
A fourth terminal for inputting data stored in the third storage area;
A fifth terminal for inputting a test control signal supplied to the test control circuit;
A sixth terminal for inputting a first clock signal supplied to the PLL circuit;
A seventh terminal for outputting a detection result of the coincidence detection circuit;
The semiconductor integrated circuit according to claim 3, further comprising:   The semiconductor integrated circuit according to claim 4, wherein in the test mode, the first terminal and the second terminal are short-circuited externally.

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