JP2007074271A - Impedance adjusting circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an impedance adjusting circuit to be built in LSI capable of adjusting an input/output impedance to an appropriate value. <P>SOLUTION: A plurality of adjusting circuits 20 of the same configuration, capable of selectively connecting by a control signal CON, is provided between an input terminal 11 and an input node NI of a cascode amplifier 30, parallel to a fixed type capacitor 12. In the adjusting circuit 20, a capacitor 21, NMOS22, and capacitor 23 are connected in series, and the gate of NMOS22 is applied with a control signal CON. Since the capacitors 21 and 23 are connected together in series when the control signal CON becomes "H", by properly selecting the control signal CON, an input impedance Zin can be close to an appropriate value. By inserting an adjusting circuit between an output node NO of the cascode amplifier 30 and an output terminal, an output impedance can be adjusted. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an impedance adjustment circuit for adjusting the input / output impedance of a cascode amplifier.

Japanese Patent Laid-Open No. 9-307459

  FIG. 2 is a configuration diagram of a conventional impedance matching circuit described in Patent Document 1. In FIG. This impedance matching circuit is used for a medium power class transmitter in a short wave band, and impedance matching elements 1a, 1b,..., 1n corresponding to different transmission frequency bands, switching circuits 2 and 3, and a control circuit. It is composed of a device 4.

  Each impedance matching element 1a to 1n includes fixed coils L1 and L2, variable capacitors C1 and C2, and motors M1 and M2. The variable capacitors C1 and C2 exhibit a capacitance according to the facing area between the electrode plate attached to the rotating shaft and the fixed electrode plate, and by rotating the rotating shaft by the motors M1 and M2, The capacitance can be adjusted.

  Each of the switching circuits 2 and 3 is configured by a relay, and any one of impedance matching elements 1a to 1n is provided between an input terminal RFIN to which an output circuit of the transmitter is connected and an output terminal RFOUT to which an antenna is connected. Are selectively connected.

  The controller 4 switches the switching circuits 2 and 3 so as to select the impedance matching element 1i having the corresponding frequency as a band according to the given frequency data FDATA, and further the variable capacitors C1 and C2 of the selected impedance matching element 1i. The motors M1 and M2 are rotated so that the electrostatic capacity of the motor corresponds to the target frequency.

  In this impedance matching circuit, when the frequency data FDATA is given to the controller 4, the corresponding impedance matching element 1i is selected according to the information stored in advance in the controller 4, and this impedance matching element 1i is output from the input terminal RFIN. The switching circuits 2 and 3 are controlled so as to be connected between the terminals RFOUT. Further, the rotation angle of the variable capacitors C1 and C2 with respect to the designated frequency is determined based on information stored in advance in the controller 4, and the motors M1 and M2 are controlled. Thereby, the impedance matching element 1i is accurately impedance-matched according to the frequency data FDATA.

  However, since the impedance matching circuit uses a variable capacitor having a rotary electrode plate, it is not suitable for a small wireless device. On the other hand, with the advance of ICs (integrated circuits) of inductors and capacitors, it has become possible to incorporate impedance matching circuits into LSIs (Large Scale Integration). However, inductors and capacitors have a problem that it is difficult to obtain a desired impedance because of a large variation in capacitance due to variations in manufacturing processes.

  The present invention provides an impedance adjustment circuit for incorporation into an LSI that can be adjusted to an appropriate impedance even if there are variations in the manufacturing process.

  The impedance adjustment circuit of the present invention adjusts the input impedance or the output impedance by being provided between the input terminal and the input node of the cascode amplifier or between the output terminal and the output node of the cascode amplifier. A first capacitor connected between the first node and the first node; a transistor provided between the first node and the second node and controlled to be turned on / off by a control signal; a second node; And a second capacitor connected between an input node or an output node of the cascode amplifier.

  In the present invention, for example, first and second capacitors are connected in series via a switching transistor between an input terminal and an input node of a cascode amplifier, and the transistor is controlled to be turned on / off by a control signal. It is composed. Therefore, when the transistor is turned on by the control signal, the first and second capacitors are inserted on the input side of the cascode amplifier. Therefore, if a plurality of capacitors are arranged and selectively connected, the input impedance can be brought close to a desired value.

The impedance adjustment circuit is configured by a plurality of first to nth adjustment units connected in parallel, and each of these adjustment units is connected to a first node connected between an input (or output) terminal and the first node. 1 capacitor, a transistor provided between the first node and the second node and controlled to be turned on / off by a corresponding control signal, an input (or output) node of the second node and the cascode amplifier And a second capacitor connected between them. Furthermore, the first and second capacitors of each adjustment unit have the same capacitance, and the capacitor of the ^i- th adjustment unit has a capacitance 2 ^i-1 times that of the capacitor of the first adjustment unit. Set as follows.

  The above and other objects and novel features of the present invention will become more fully apparent when the following description of the preferred embodiment is read in conjunction with the accompanying drawings. However, the drawings are for explanation only, and do not limit the scope of the present invention.

FIG. 1 is a circuit diagram of an impedance adjustment circuit showing Embodiment 1 of the present invention.
This impedance adjustment circuit is inserted, for example, between the input terminal 11 to which the receiving antenna is connected and the cascode amplifier 30, and adjusts the input impedance Zin when the cascode amplifier 30 side is viewed from the input terminal 11. The impedance adjustment circuit is formed by connecting adjustment circuits 20 a and 20 b in parallel with a fixed capacitor 12 connected between the input terminal 11 and the input node NI of the cascode amplifier 30.

  The adjustment circuit 20 a includes a capacitor 21 having one end connected to the input terminal 11, a switching N-channel MOS transistor (hereinafter referred to as “NMOS”) 22 having a source connected to the other end of the capacitor 21, and one end A capacitor 23 is connected to the drain of the NMOS 22 and connected to the input node NI of the cascode amplifier 30 at the other end. The source and drain of the NMOS 22 are connected to the ground potential GND through high resistances 24 and 25, respectively. Further, a control signal CONa is supplied to the gate of the NMOS 22 through the resistor 26. The high resistances 24 and 25 are provided to ensure that the NMOS 22 is turned on when the control signal CONa is set to the level “H” by applying the ground potential GND to the source and drain of the NMOS 22. .

  The adjustment circuit 20b has a circuit configuration similar to that of the adjustment circuit 20a. However, the control signal CONb is supplied to the gate of the NMOS 22 of the adjustment circuit 20b via the resistor 26.

  The cascode amplifier 30 includes a grounded-gate amplifier connected to a subsequent stage of a common-source amplifier, and has a feature that isolation between input and output is sufficiently large. The cascode amplifier 30 includes an inductor 31, NMOSs 32 and 33, and an inductor 34 connected in series between the ground potential GND and the power supply potential VDD. The gate of the NMOS 32 is connected to an input node NI through an inductor 35, and a bias voltage VB1 is applied to the input node NI through a high resistance 36.

  The gate of the NMOS 33 is connected to the ground potential GND through a capacitor 37 in an AC manner, and is supplied with a bias voltage VB2 through a resistor 38. Then, an amplified signal OUT is output from the drain of the NMOS 33 which is the output node NO.

Next, the operation will be described.
In FIG. 1, the input impedance Z30i seen from the input node NI of the cascode amplifier 30 is as follows. The inductances of the inductors 31 and 35 are L31 and L35, respectively. It is expressed as:
Z30i = (L31 / Cgs) × gm + jω (L35 + L31) (1)

Therefore, the input impedance Zin viewed from the input terminal 11 is expressed by the following equation, where Cx is the capacitance of the capacitor connected in series between the input terminal 11 and the input node NI of the cascode amplifier 30. .
Zin = (L31 / Cgs) × gm + jω (L35 + L31) −j (1 / ωCx) (2)

  That is, in FIG. 1, the input impedance Zin can be adjusted to a desired value by adjusting the value of Cx.

  For example, when the control signals CONa and CONb are set to “L”, the NMOS 22 of the adjustment circuits 20a and 20b is turned off, and the capacitance Cx becomes the capacitance C12 of the capacitor 12.

  Further, when the control signals CONa and CONb are set to “H”, the NMOS 22 of the adjustment circuits 20a and 20b is turned on. Therefore, if the capacitances of the capacitors 21 and 23 of the adjustment circuits 20a and 20b are all C20, the capacitance Cx is C12 + C20. Further, when the control signals CONa and CONb are set to “H” and “L”, respectively, the capacitance Cx becomes C12 + C20 / 2.

  As described above, the impedance adjustment circuit according to the first embodiment includes the adjustment circuits 20a and 20b that can be connected and controlled by the control signals CONa and CONb between the input terminal 11 and the input node NI of the cascode amplifier 30. . Thereby, the input impedance Zin can be adjusted, and there is an advantage that the input impedance Zin can be brought close to a desired value.

In addition, this invention is not limited to the said Example 1, A various deformation | transformation is possible. Examples of this modification include the following.
(1) What is connected to the input terminal 11 is not limited to a receiving antenna.
(2) The number of adjustment circuits 20a and 20b is not limited to two.
(3) The capacitances of the capacitors 21 and 23 of the adjustment circuits 20a and 20b need not all be the same.
(4) The circuit configurations of the adjustment circuits 20a and 20b are not limited to those illustrated in FIG. Any circuit configuration may be used as long as the connection control of the capacitor can be performed in accordance with the control signal CON.

  FIG. 3 is a circuit diagram of an impedance adjustment circuit showing a second embodiment of the present invention. Elements common to those in FIG. 1 are denoted by common reference numerals.

  This impedance adjustment circuit is inserted, for example, between the output terminal 51 to which the transmission antenna is connected and the output node NO of the cascode amplifier 30, and adjusts the output impedance Zout when the cascode amplifier 30 side is viewed from the output terminal 51. It is. The impedance adjustment circuit is obtained by connecting adjustment circuits 40 a and 40 b in parallel with a fixed capacitor 52 connected between the output terminal 51 and the output node NO of the cascode amplifier 30.

  The adjustment circuits 40 a and 40 b have the same configuration as the adjustment circuits 20 a and 20 b in FIG. 1, and a capacitor 41 having one end connected to the output node NO of the cascode amplifier 30 and a source connected to the other end of the capacitor 41. The switching NMOS 42 and a capacitor 43 having one end connected to the drain of the NMOS 42 and the other end connected to the output terminal 51 are provided. The source and drain of the NMOS 42 are connected to the ground potential GND through high resistances 44 and 45, respectively. Further, the control signal CONa is supplied to the gate of the NMOS 42 of the adjustment circuit 40a through the resistor 46, and the control signal CONb is supplied to the gate of the NMOS 42 of the adjustment circuit 40b through the resistor 46. .

In this circuit, if the constants of the inductor 34 and the NMOS 33 of the cascode amplifier 30 are appropriately selected, the output impedance Z30o viewed from the output node NO of the cascode amplifier 30 is expressed by the following equation.
Z30o = R + jX (3)

The output impedance Zout viewed from the output terminal 51 is expressed by the following equation, where Cx is the capacitance of a capacitor connected in series between the output terminal 51 and the output node NO of the cascode amplifier 30.
Zout = R + jX−j (1 / ωCx) (4)

  Therefore, the value of the capacitance Cx can be adjusted by turning on and off the NMOS 42 of the adjustment circuits 40a and 40b by the control signals CONa and CONb, and the output impedance Zout can be adjusted to a desired value.

  As described above, in the impedance adjustment circuit according to the second embodiment, the adjustment circuits 40 a and 40 b that can be connected and controlled by the control signals CONa and CONb are provided between the output terminal 51 and the output node NO of the cascode amplifier 30. . As a result, the output impedance Zout can be adjusted, and this output impedance Zout can be brought close to a desired value.

In addition, this invention is not limited to the said Example 2, A various deformation | transformation is possible. Examples of this modification include the following.
(1) What is connected to the output terminal 51 is not limited to the transmission antenna.
(2) The number of adjustment circuits 40a and 40b is not limited to two.
(3) The capacitances of the capacitors 41 and 43 of the adjustment circuits 40a and 40b need not all be the same.
(4) The circuit configurations of the adjustment circuits 40a and 40b are not limited to those illustrated in FIG. Any circuit configuration may be used as long as the connection control of the capacitor can be performed in accordance with the control signal CON.

  FIG. 4 is a circuit diagram of an adjustment circuit showing a third embodiment of the present invention. This adjustment circuit is provided in place of the adjustment circuits 20a and 20b in FIG. 1 or the adjustment circuits 40a and 40b in FIG.

In this adjustment circuit, a plurality of adjustment units 60 _i (where i = 1 to 4) are connected in parallel between nodes NA and NB. These adjustment unit 60 _i is the same circuit configuration, for example, adjusting unit 60 ₁ has one end the capacitor 61 ₁ connected to the node NA, a switch whose source is connected to the other end of the capacitor 61 ₁ The NMOS 62 ₁ has a capacitor 63 ₁ having _one end connected to the drain of the NMOS 62 ₁ and the other end connected to the node NB. The source and drain of the NMOS 62 ₁ are respectively connected to the ground potential GND through a high resistance ₆₄ 1, 65 _1, further, the gate of NMOS 62 _1, the control signal CON1 so that is applied through a resistor 66 ₁ It has become. The high resistance ₆₄ 1, ₆₅ 1, by applying the ground potential GND to the source and the drain of the NMOS 62 _1, when the "H" control signal CON1, for causing the NMOS 62 ₁ and reliably turned on Is.

The capacitors 61 _i and 63 _i of each adjustment unit 60 _i have the same capacitance, and the capacitances of these capacitors 61 _i and 63 _i are the capacitances of the capacitors 61 ₁ and 63 ₁ of the adjustment unit 60 _1. Is set to 2 ^i-1 times. The control signal CONi is supplied to the gate of the NMOS 62 _i of the adjustment unit 60 _i through the resistor 66 _i .

This adjustment circuit, by the "H" control signal CONi, NMOS 62 _i of the adjusting unit 60 _i is turned on and node NA, the capacitor ₆₁ i, 63 _i between NB are connected in series. Therefore, if the capacitances of the capacitors 61 ₁ and 63 ₁ are 2Ca, the capacitances Ca, 2Ca, 4Ca, and 8Ca are respectively set by setting the control signals CON1, CON2, CON3, and CON4 to “H”. The nodes NA and NB are connected. That is, in this adjustment circuit, the capacitance between the nodes NA and NB can be adjusted from 0 to 15Ca in units of Ca by the combination of the control signals CONi.

  As described above, the adjustment circuit according to the third embodiment includes a plurality of adjustment units having capacitors set so that the capacitance value has a power-of-two relationship. There is an advantage that the capacitance can be adjusted in a wide range by the combination.

In addition, this invention is not limited to the said Example 3, A various deformation | transformation is possible. Examples of this modification include the following.
(1) The number of adjustment units is not limited to four.
(2) The gate width of the NMOS 62 _i of the i-th adjustment unit 60 _i is set to 2 ^i-1 times the gate width of the NMOS 62 ₁ of the _first adjustment unit 60 ₁ . As a result, when the capacitances of the capacitors 61 and 63 are large (that is, the impedance is low), the ON resistance is lowered by increasing the gate width of the NMOS 62 for switching, and the influence of the series resistance is reduced. Can do. Note that when the capacitances of the capacitors 61 and 63 are small, the impedance is high. Therefore, even if the gate width of the NMOS 62 is small, the influence is small.

It is a circuit diagram of an impedance adjustment circuit showing Example 1 of the present invention. It is a block diagram of the conventional impedance matching circuit. It is a circuit diagram of the impedance adjustment circuit which shows Example 2 of this invention. It is a circuit diagram of the adjustment circuit which shows Example 3 of this invention.

Explanation of symbols

11 Input terminal 12, 21, 23, 37, 41, 43, 52, 61, 63 Capacitor 20, 40 Adjustment circuit 22, 32, 33, 42, 62 NMOS
24 to 26, 36, 38, 44 to 46, 64 to 66 Resistor 30 Cascode amplifier 31, 34, 35 Inductor 51 Output terminal

Claims (6)

An impedance adjustment circuit for adjusting an input impedance by providing between an input terminal and an input node of a cascode amplifier,
A first capacitor connected between the input terminal and a first node;
A transistor provided between the first node and the second node and controlled to be turned on / off by a control signal;
A second capacitor connected between the second node and an input node of the cascode amplifier;
An impedance adjustment circuit comprising: An impedance adjustment circuit for adjusting an output impedance by providing between an output terminal and an output node of a cascode amplifier,
A first capacitor connected between the output terminal and a first node;
A transistor provided between the first node and the second node and controlled to be turned on / off by a control signal;
A second capacitor connected between the second node and an output node of the cascode amplifier;
An impedance adjustment circuit comprising: An impedance adjustment circuit for adjusting an input impedance by providing between an input terminal and an input node of a cascode amplifier,
The impedance adjustment circuit includes a plurality of adjustment units from the first to n (where n is an integer of 2 or more) connected in parallel.
Each adjustment unit is
A first capacitor connected between the input terminal and a first node;
A transistor provided between the first node and the second node and controlled to be turned on / off by a corresponding control signal;
A second capacitor connected between the second node and an input node of the cascode amplifier;
An impedance adjustment circuit comprising: An impedance adjustment circuit for adjusting an output impedance by providing between an output terminal and an output node of a cascode amplifier,
The impedance adjustment circuit includes a plurality of adjustment units from the first to n (where n is an integer of 2 or more) connected in parallel.
Each adjustment unit is
A first capacitor connected between the output terminal and a first node;
A transistor provided between the first node and the second node and controlled to be turned on / off by a corresponding control signal;
A second capacitor connected between the second node and an output node of the cascode amplifier;
An impedance adjustment circuit comprising: The first and second capacitors of each adjustment unit have the same capacitance, and the first and second capacitors of the i-th adjustment unit (where i is an integer from 2 to n) are: 5. The impedance adjustment circuit according to claim 3, wherein the impedance adjustment circuit has a capacitance 2 ⁱ⁻¹ times that of the first and second capacitors of the first adjustment unit. 6. The impedance adjustment circuit according to claim 5, wherein the gate width of the transistor of the i-th adjustment unit is 2 ^i-1 times the gate width of the transistor of the first adjustment unit.

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