JP2007067336A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor device capable of surely preventing short-circuit defects without generating deposited foreign matters when removing a side wall formed when using fluorine-based gas for dry-etching a metal film containing titanium, and the semiconductor device. <P>SOLUTION: An etching mask 23 is formed on the metal film 17 containing the titanium and formed on a semiconductor substrate, and the metal film 17 is dry-etched through the etching mask 23. After the dry etching, the etching mask 23 is removed and a waterproof film 32 which obstructs the permeation of water molecules is formed on the surface of the metal film 17. Then, the projected part projected upwards from the upper surface of the metal film 17 of the side wall 31 composed of a reaction product and formed on the inner side face of an etching part 18 in the process of the dry etching is removed by plasma treatment using gas containing fluorine elements. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device including a step of dry etching a metal film containing titanium.

  In recent years, with the miniaturization of semiconductor integrated circuit devices (hereinafter referred to as semiconductor devices), high-concentration thin-layer impurity diffusion in which high-concentration impurities are introduced shallowly into the surface of a semiconductor layer into semiconductor elements constituting the semiconductor device The area is adopted. In the impurity diffusion region of the high concentration thin layer, when the semiconductor substrate is heated and thermal diffusion occurs in the impurity, the characteristics of the semiconductor element greatly change. For this reason, the heat treatment performed after the formation of the impurity diffusion region in the manufacturing process of this type of semiconductor device is required to have a low calorific value (low temperature process or short time high temperature process).

In addition, in a semiconductor device equipped with a capacitive element such as a DRAM (Dynamic Random Access Memory), in addition to the above-described requirement for the low heat amount heat treatment, a high capacity is required in order to reduce the area occupied by the capacitive element. Yes. For this reason, in recent capacitive elements, a tantalum oxide film (hereinafter referred to as Ta ₂ O ₅ film) capable of forming a high-capacity thin film at a relatively low process temperature is adopted as a capacitive insulating film, and a relatively low process. A tantalum nitride film (hereinafter referred to as a TiN film) that can be formed at a temperature is employed as the electrode film. Furthermore, since the TiN film is difficult to cause diffusion of metal atoms (Ti) and functions as a barrier layer for preventing the diffusion of other metal atoms, a highly reliable small-sized capacitor element can be realized by this configuration. (For example, refer to Patent Document 1).

  FIG. 8 is a cross-sectional view showing a cross-sectional structure of a DRAM memory cell of the semiconductor device described above. In FIG. 8, the interlayer insulating films 10, 12, 13, and 19 are shown as blanks.

  As shown in FIG. 8, the memory cell includes a selection transistor 3 formed on the semiconductor substrate 1 and a capacitive element 20 connected to the selection transistor 3. In the example of FIG. 8, two select transistors 3 having a common drain region 7 are formed in a region on the semiconductor substrate 1 divided into element isolation insulating films 2. The drain region 7 of the selection transistor 3 is electrically connected to the upper layer wiring 9 (bit line) through the contact plug 8 formed in the interlayer insulating film 10 and the contact plug 42 formed in the interlayer insulating films 12, 13, 19. It is connected. Further, the source region 5 formed at a position facing the drain region 7 across the gate electrode 4 (word line) of the selection transistor 3 passes through the contact plug 6 formed in the interlayer insulating film 10 and is located below the capacitor element. It is electrically connected to the electrode 15a.

  The capacitive element 20 has a structure in which a lower electrode 15a, a capacitive insulating film 16a, and an upper electrode 17a are sequentially stacked in a trench formed in the interlayer insulating films 12 and 13. In this example, a ground potential is applied to the upper electrode 18a.

  9 to 11 are process cross-sectional views showing a manufacturing process of a semiconductor device on which a conventional DRAM is mounted. 9 to 11 show a process of forming a layer above the interlayer insulating film 12 in FIG. The structure below the interlayer insulating film 12 is formed by a well-known process. Here, illustration and description of the lower layer structure 11 are omitted.

  As shown in FIG. 9A, an interlayer insulating film 12 made of a silicon nitride film or the like and an interlayer insulating film 13 made of a silicon oxide film or the like are sequentially formed on the lower structure 11. Next, as shown in FIG. 9B, the interlayer insulating film 13 and the interlayer insulating film 12 are etched by the photolithography technique and the etching technique, and the concave capacitor forming region 14 is formed.

  As shown in FIG. 9C, a polysilicon film 15 doped with an n-type impurity such as phosphorus (P) is formed on the interlayer insulating film 13 in which the capacitor formation region 14 is formed. Next, a resist film 21 is formed on the polysilicon film 15, and the polysilicon film 15 in a region other than the capacitor formation region 14 is removed together with the resist film 21 by CMP (Chemical Mechanical Polishing) or etching back. As shown in FIG. 9D, the lower electrode 15a is formed. Thereafter, the resist film 21 remaining in the capacitor formation region 14 is removed by ashing or organic cleaning.

On the semiconductor substrate on which the lower electrode 15a is formed, as shown in FIG. 9E, a Ta ₂ O ₅ film 16 having a thickness of about 10 nm is formed as a capacitive insulating film. On the Ta ₂ O ₅ film 16, a TiN film 17 having a thickness of about 50 nm is formed as an upper electrode. The TiN film 17 is formed at a film forming temperature of 580 ° C., for example, by LP-CVD (Low Pressure-Chemical Vapor Deposition) using titanium chloride (TiCl ₄ ) and ammonia (NH ₃ ) as source gases.

Subsequently, the contact hole 18 (see FIG. 8) in which the TiN film 17 and the Ta ₂ O ₅ film 16 are filled with the contact plug 42 for connecting the upper wiring 9 (see FIG. 8) and the contact plug 8 (see FIG. 8). 10 (b)) is formed. In this step, after the capacitor forming region 14 is filled with the filling material 22, a resist film is formed on the TiN film 17, and a resist pattern 23 having an opening at the position where the contact hole 18 is formed is formed by photolithography. .

Next, the TiN film 17 and the Ta ₂ O ₅ film 16 are etched using the resist pattern 23 as an etching mask. The etching is performed, for example, by introducing Cl ₂ gas as an etching gas into an ICP (Inductive Coupling Plasma) etching method dry etching apparatus at a flow rate of 50 ml / min (1 ° C., 1 atm) and an internal pressure of 5 mTorr. It can implement by applying 300W high frequency electric power in the state maintained. In the following, the gas flow rate is a flow rate when the temperature is 1 ° C. and 1 atm.

As shown in FIG. 10B, the inner surface of the contact hole 18 formed in the TiN film 17 and the Ta ₂ O ₅ film 16 by the etching has a side wall (fence) made of a reaction product containing Ti and Ta. 31 is formed. By forming the contact hole 18, the TiN film 17 becomes the upper electrode 17a, and the Ta ₂ O ₅ film 16 becomes the capacitive insulating film 16a. Thereafter, as shown in FIG. 10C, the resist pattern 23 and the filling material 22 are removed by an ashing process or the like. Thus, by removing the register pattern 23, the upper end of the side wall 31 protrudes above the upper surface of the TiN film 17. Such a side wall 31 having a protruding portion is easily peeled off in the subsequent processes to become particles, which causes a reduction in the manufacturing yield of the semiconductor device. For this reason, as shown in FIG. 10D, the side wall 31 formed on the inner surface of the contact hole 18 is removed in the next step.

Etching for removing the side wall 31 is performed, for example, by introducing CHF ₃ as an etching gas at a flow rate of 10 ml / min and O ₂ gas at a flow rate of 800 ml / min into an ECR (Electron Cyclotron Resonance) etching type dry etching apparatus. Is carried out in a state where the pressure is maintained at 100 Pa.

As described above, the side wall 31 is formed by depositing reaction products formed in the etching process of the TiN film 17 and the Ta ₂ O ₅ film 16, and the main components thereof are Ti, Ta, and the resist pattern 23. It is an element such as C that was present inside. Therefore, the side wall 31 is removed as TiF ₄ , TaF ₅ , and CO ₂ by reacting with CHF ₃ and O ₂ that are etching gases.

  Thereafter, cleaning for removing the organic residue in the contact hole 18 is performed using, for example, an amine chemical solution. The reason why the cleaning liquid is an amine chemical solution is that the TiN film 17 is dissolved when cleaning is performed using SPM (Sulfuric acid-hydrogen Peroxide Mixture), APM (Ammonium hydroxide-hydrogen Peroxide Mixture), or the like. The cleaning with the amine chemical is performed at a temperature of 70 ° C. for about 5 minutes.

Next, an interlayer insulating film 19 made of NSG (Non-Doped Silicate Glass) or the like is deposited, and the interlayer insulating film 19 is planarized by CMP (FIG. 11A). Then, a resist pattern 24 having an opening at a position corresponding to the contact hole 18 is formed on the interlayer insulating film 19 by photolithography. Then, using the resist pattern 24 as an etching mask, the interlayer insulating film 19, the interlayer insulating film 13, and the interlayer insulating film 12 are etched to form a contact hole 41 as shown in FIG. The etching is performed, for example, by an ECR etching type dry etching apparatus, in which C ₄ F ₈ gas is introduced as an etching gas at a flow rate of 26 ml / min and O ₂ gas is flowed at a flow rate of 22 ml / min, and the internal pressure is maintained at 100 Pa. Done in Thereafter, the resist pattern 24 is removed by ashing or the like.

Then, a tungsten film is formed on the interlayer insulating film 19 in which the contact hole 41 is formed, an unnecessary tungsten film formed in a region other than the contact hole 41 is removed by a CMP method, and a contact plug 42 is formed. The
JP-A-6-151383

As described above, the etching of the refractory metal-containing films such as the TiN film 17 and the Ta ₂ O ₅ film 16 uses a halogen-based gas for forming the contact holes 18 and uses a fluorine-based gas for removing the side walls 31. The However, when a gas containing a fluorine element is used when removing the side wall 31, as shown in FIG. 12A, the residual fluorine contained in the etching gas and titanium contained in the side wall 31 and the TiN film 17. React with each other to produce titanium fluoride TiF _x (1 ≦ X ≦ 3) 52.

Although the titanium fluoride 52 is solid, the ionic solution reaction between titanium and fluorine is Ti + 6F ⁻ Ｔｉ TiF ₆ ² + + 4e ⁻ , and the titanium fluoride 52 reacts with water to form a hydrate and precipitate as foreign matter. . Since the water 53 is contained in the TiN film 17 (upper electrode 17a), the water 53 reacts with the titanium fluoride 52, and as shown in FIG.

  As shown in FIG. 10D, when the above-described deposited foreign matter 51 remains in the contact hole 18 in the step of removing the side wall 31, the contact plug 42 is formed in the contact hole 68 as shown in FIG. At this time, the upper electrode 17 a and the contact plug 42 may be connected by the deposited foreign matter 51. Since the deposited foreign matter 51 is electrically conductive, a short circuit occurs between the upper electrode 17a and the contact plug 42, and the semiconductor device becomes defective.

TiF _x (1 ≦ X ≦ 3) contained in the precipitated foreign matter 51 is dissolved by the reaction between the precipitated foreign matter and fluorine ions (F ⁻ ). For this reason, in the state of FIG. 10 (d), it is possible to remove the deposited foreign matter 51 by cleaning with a chemical solution containing fluorine ions (for example, ammonium fluoride) that does not corrode other films. Conceivable. However, since ammonium fluoride has a low degree of dissociation, the reaction between the fluorine ions and the precipitated foreign matter 51 hardly occurs, and the precipitated foreign matter 51 cannot be sufficiently removed. Furthermore, in reality, there is no cleaning chemical effective for cleaning and removing the deposited foreign matter 51.

  The present invention has been proposed in view of the above-described conventional circumstances, and provides a method of manufacturing a semiconductor device that can prevent the occurrence of a short-circuit failure without generating precipitated foreign matter. It is an object.

  In order to achieve the above object, in a method for manufacturing a semiconductor device according to the present invention, an etching mask is formed on a metal film containing titanium formed on a semiconductor substrate, and the dry etching through the etching mask is performed. A through hole is formed in the metal film. After the dry etching, the etching mask is removed, and a waterproof film that inhibits permeation of water molecules is formed on the surface of the metal film. Then, a front end portion of the side wall made of a reaction product formed on the side surface of the through hole in the dry etching process and extending above the upper surface of the metal film is removed by plasma treatment using a gas containing fluorine element. It is a configuration.

  The waterproof film can be formed by surface oxidation of a metal film. The surface oxidation can be performed using oxygen plasma treatment or a gas containing oxygen.

  Furthermore, in the plasma treatment using the gas containing fluorine element, it is preferable that only the tip of the side wall is completely removed, and the side wall remains on the inner side surface of the through hole. It is more preferable to have waterproofness.

  Note that as the gas containing a fluorine element, a fluorocarbon gas or a mixed gas of a fluorocarbon gas and an oxygen gas can be used.

  On the other hand, in another aspect, the present invention can provide a semiconductor device formed by the above manufacturing method. That is, the semiconductor device according to the present invention includes a through-hole provided in the metal film and a waterproof film that inhibits permeation of water molecules provided on the upper surface of the metal film in a semiconductor device having a metal film containing titanium. And a side wall containing titanium provided on the inner side surface of the through hole.

  According to the present invention, it is possible to suppress the reaction between the titanium fluoride generated when the side wall formed on the inner side surface of the contact hole is removed and the moisture contained in the TiN film. For this reason, when a contact plug is formed in the contact hole, it is possible to reliably prevent a short circuit from occurring between the TiN film and the contact plug.

  Hereinafter, based on an example in which the present invention is applied to a semiconductor device mounted with a DRAM, it will be described in detail with reference to the drawings. 1 to 3 are process cross-sectional views illustrating the manufacturing process of the semiconductor device of this embodiment. The semiconductor device of this embodiment has a structure that is substantially the same as that of the semiconductor device shown in FIG. For this reason, in FIGS. 1-3, the code | symbol same as the code | symbol attached | subjected to FIGS. 8-11 is attached | subjected to the site | part which has the same structure as the past. 1 to 3 show a process of forming a layer above the interlayer insulating film 12 as in FIGS. The structure below the interlayer insulating film 12 is formed by a known process.

  As shown in FIG. 1A, an interlayer insulating film 12 made of a silicon nitride film or the like and an interlayer insulating film 13 made of a silicon oxide film or the like are sequentially formed on the lower structure 11. Next, as shown in FIG. 1B, the interlayer insulating film 13 and the interlayer insulating film 12 are etched by the photolithography technique and the etching technique, and the concave capacitor forming region 14 is formed.

  As shown in FIG. 1C, a polysilicon film 15 doped with an n-type impurity such as phosphorus (P) is formed on the capacitor formation region 14 on the interlayer insulating film 13. A resist film 21 is formed on the polysilicon film 15, and the polysilicon film 15 in a region other than the capacitor formation region 14 is removed together with the resist film 21 by CMP or etch back, as shown in FIG. The lower electrode 15a is formed. Thereafter, the resist film 21 remaining in the capacitor formation region 14 is removed by ashing or organic cleaning.

As shown in FIG. 1E, a Ta ₂ O ₅ film 16 having a thickness of about 10 nm is formed as a capacitive insulating film on the semiconductor substrate on which the lower electrode 15a is formed. The Ta ₂ O ₅ film 16 is formed by, for example, an LP-CVD method using a gas containing pentaethoxytantalum (PET: Ta (OC ₂ H ₅ ) ₅ ) and O ₂ as a source gas. At this time, the substrate temperature is 470 ° C. Thereafter, the Ta ₂ O ₅ film 16 is annealed at a temperature of 800 ° C. for 60 seconds in an oxygen atmosphere, for example, to be polycrystallized.

Next, a TiN film 17 having a thickness of about 50 nm is formed on the Ta ₂ O ₅ film 16 as an upper electrode. The TiN film 17 can be formed by, for example, an LP-CVD method using titanium chloride and ammonia as source gases. In this embodiment, unlike the prior art, the film forming temperature is set to 630 ° C. As described above, by forming the TiN film 17 at a higher film formation temperature than in the prior art, the amount of water contained in the TiN film 17 can be reduced. FIG. 4 is a diagram showing the film formation temperature dependence of the amount of water contained in the formed TiN film. As shown in FIG. 4, the water content in the TiN film 17 decreases as the film formation temperature increases. On the other hand, the step coverage of the TiN film 17 decreases as the film forming temperature increases. For this reason, conventionally, a film forming temperature of about 580 ° C. has been used from the viewpoint of enhancing the step coverage, but in this embodiment, there is a trade-off between the step coverage and the amount of moisture contained in the TiN film 17. From the viewpoint, the film forming temperature is set to 630 ° C. If the film formation temperature is in the range of 600 ° C. to 630 ° C., the effect of reducing the amount of moisture contained in the film can be obtained without greatly reducing the step coverage of the TiN film 17.

Subsequently, a contact hole 18 (FIG. 2) for forming a contact plug 42 for connecting the upper wiring 9 (see FIG. 8) and the contact plug 8 (see FIG. 8) is formed in the TiN film 17 and the Ta ₂ O ₅ film 16. (B) is formed. In this step, after the capacitor forming region 14 is filled with the filling material 22, a resist film is formed on the TiN film 17, and a resist pattern 22 having an opening at the position where the contact hole 18 is formed is formed by photolithography. .

Next, the TiN film 17 and the Ta ₂ O ₅ film 16 are etched using the resist pattern 22 as an etching mask. In this etching, for example, a high frequency power of 300 W is applied to an ICP type dry etching apparatus while introducing Cl ₂ gas as an etching gas at a flow rate of 50 ml / min and maintaining the internal pressure at 5 mTorr. Can be implemented. By forming the contact hole 18, the TiN film 17 becomes the upper electrode 17a, and the Ta ₂ O ₅ film 16 becomes the capacitive insulating film 16a.

As shown in FIG. 2B, a sidewall 31 made of a reaction product containing Ti and Ta is formed on the inner surface of the contact hole 18 formed in the TiN film 17 and the Ta ₂ O ₅ film 16 by the etching. Is done. Thereafter, as shown in FIG. 2C, the resist pattern 23 and the filling material 22 are removed by an ashing process or the like. At this time, the upper end portion of the side wall 31 formed on the inner surface of the contact hole 18 protrudes upward from the upper surface of the TiN film 17.

Under this circumstance, next, for example, ashing (oxygen plasma treatment) is performed under the conditions of an internal pressure of 100 Pa and a treatment time of 30 seconds by MWS (Microwave stripper) in which only O ₂ gas is introduced at a flow rate of 800 ml / min. The surface of the TiN film 17 is oxidized. As a result, an oxide film 32 (waterproof film) is formed on the surface of the TiN film 17 as shown in FIG. By forming the oxide film 32, moisture contained in the TiN film 17 is prevented from escaping from the surface of the TiN film 17 to the outside. The formation of the surface oxide film is not limited to the plasma treatment, and the surface oxidation may be performed by another method.

In the present embodiment, next, as shown in FIG. 2E, the portion protruding upward at the upper end of the side wall 31 is removed. This protrusion is removed by using, for example, an ECR etching apparatus, CHF ₃ gas having a flow rate of 5 ml / min and O ₂ gas having a flow rate of 800 ml / min as etching gas, and a processing time of 30 seconds with an internal pressure of 100 Pa. This can be performed by dry etching. FIG. 5 is a diagram showing the dependence of the height of the remaining side wall 31 on the CHF ₃ gas flow rate under the etching conditions. From FIG. 5, it can be understood that the side wall height (the length from the lower end to the upper end of the side wall 31) can be accurately controlled by controlling the CHF ₃ gas flow rate. According to FIG. 5, it can be understood that, according to the above etching conditions, the height of the side wall 31 is 60 nm, which matches the total film thickness of the TiN film 17 and the Ta ₂ O ₅ film 16 in this embodiment. Therefore, according to the above etching conditions, only the protruding portion of the side wall 31 protruding above the upper surface of the TiN film 17 can be removed, and the side surface of the laminated film of the TiN film 17 and the Ta ₂ O ₅ film 16 is covered. The side wall 31 can remain. Since the oxide film 32 is very thin, its film thickness can be ignored. In addition, by removing the protruding portion of the side wall 31 in this way, it is possible to prevent the side wall 31 from peeling off and generating particles in the subsequent steps.

In the present embodiment, as shown in FIG. 6, after removing the protruding portion of the side wall 31, fluorine remaining in the contact hole 18 reacts with Ti contained in the side wall 31, and TiF _X (1 ≦ X ≦ 3) 52 is formed. However, the moisture in the TiN film 17 is almost completely confined in the TiN film 17 by the oxide film 32 and the side walls 31 on the surface of the TiN film 17. For this reason, the TiF _x (1 ≦ X ≦ 3) 52 and the moisture in the TiN film 17 do not react. Therefore, the deposited foreign matter 51 does not occur.

  FIG. 7 is a diagram showing the amount of precipitated foreign matter 51 generated in the manufacturing process of the present embodiment and the amount of precipitated foreign matter 51 generated in the conventional manufacturing process. Note that the amount of the deposited foreign matter 51 is obtained by counting the number of the deposited foreign matter 51 present in the dense portion of the contact hole 18 with an electron microscope. As can be understood from FIG. 7, according to the present invention, it can be understood that the deposited foreign matter 51 is reduced to 1/80 compared to the conventional case.

Thereafter, cleaning for removing organic residues in the contact hole 18 is performed using, for example, an amine-based chemical solution, and then an interlayer insulating film 19 made of NSG or the like is deposited on the entire surface. The insulating film 19 is planarized (FIG. 3A). Then, a resist pattern 24 having an opening at a position corresponding to the contact hole 18 is formed on the interlayer insulating film 19 by photolithography. Then, using the resist pattern 24 as an etching mask, the interlayer insulating film 19, the interlayer insulating film 13, and the interlayer insulating film 12 are etched to form a contact hole 41 as shown in FIG. State the etching, for example, the dry etching apparatus of ECR etching method, as an etching gas, C ₄ F ₈ gas and 26 ml / min, and O ₂ gas was introduced at a flow rate of 22 ml / min, it was maintained at the internal pressure 100Pa Done in Thereafter, the resist pattern 24 is removed by ashing or the like.

  Then, a tungsten film is formed on the interlayer insulating film 19 in which the contact hole 41 is formed, an unnecessary tungsten film formed in a region other than the contact hole 41 is removed by a CMP method, and a contact plug 42 is formed. The Thereafter, the upper wiring 9 (see FIG. 8) is formed on the contact plug by a known fine processing technique.

  As described above, it is possible to suppress the reaction between the titanium fluoride generated when the side wall formed on the inner side surface of the contact hole is removed and the moisture contained in the TiN film. Therefore, it is possible to reliably prevent a short circuit from occurring between the TiN film 17 and the contact plug 42 when a contact plug is formed in the contact hole.

The present invention is not limited to the embodiments described above, and various modifications and applications are possible within the scope of the effects of the present invention. For example, in the above, a waterproof film is formed by forming an oxide film by surface oxidation of a metal film containing titanium. However, the waterproof film is resistant to etching of the side wall 31 and is a film that inhibits permeation of water molecules. Any film can be used. Therefore, other deposited films may be used. Although CHF ₃ is used for etching the side wall 31, any other fluorocarbon gas can be used.

  In addition, the processes employed in the above steps can be replaced with other equivalent processes without departing from the technical idea of the present invention.

  The present invention is useful for manufacturing a semiconductor device including a step of dry etching a metal film containing titanium, such as a step of forming a capacitor of a DRAM.

Process sectional drawing which shows one Embodiment of this invention Process sectional drawing which shows one Embodiment of this invention Process sectional drawing which shows one Embodiment of this invention The figure which shows the film-forming temperature dependence of the moisture content in a TiN film | membrane It shows a CHF ₃ flow rate dependency of the side wall height Schematic diagram explaining the suppression of the occurrence of precipitated foreign matter A comparison of the amount of foreign matter deposited between the present invention and the conventional method Sectional view showing a conventional semiconductor device Cross-sectional process diagram showing the manufacturing process of a conventional semiconductor device Cross-sectional process diagram showing the manufacturing process of a conventional semiconductor device Cross-sectional process diagram showing the manufacturing process of a conventional semiconductor device Schematic diagram explaining the occurrence of precipitated foreign matter

Explanation of symbols

1 Semiconductor substrate 11 Lower structure 12 Interlayer insulating film (silicon nitride film)
13 Interlayer insulation film (silicon oxide film)
14 Capacitor formation region 15 Polysilicon film 15a Lower electrode 16 Tantalum oxide film 16a Capacitance insulating film 17 Titanium nitride film 17a Upper electrode 18 Contact hole 19 Interlayer insulating film (NSG film)
20 Capacitance element 31 Side wall 32 Oxide film (waterproof film)
42 Contact plug

Claims (8)

Forming a metal film containing titanium on a semiconductor substrate;
Forming an etching mask on the metal film;
Forming a through-hole in the metal film by dry etching through the etching mask;
Removing the etching mask after the dry etching;
Forming a waterproof film that inhibits permeation of water molecules on the surface of the metal film;
The tip portion of the side wall made of the reaction product formed on the inner side surface of the through hole in the dry etching process is removed by plasma treatment using a gas containing fluorine element. Process,
A method for manufacturing a semiconductor device, comprising:   The method for manufacturing a semiconductor device according to claim 1, wherein the waterproof film is formed by surface oxidation of the metal film.   The method of manufacturing a semiconductor device according to claim 2, wherein the surface oxidation of the metal film is performed by oxygen plasma treatment.   The method for manufacturing a semiconductor device according to claim 2, wherein the surface oxidation of the metal film is performed using a gas containing oxygen.   2. The method of manufacturing a semiconductor device according to claim 1, wherein the tip of the side wall is completely removed by plasma treatment of the gas containing fluorine element, and the side wall covering the inner side surface of the through hole remains.   The method for manufacturing a semiconductor device according to claim 1, wherein the side wall is waterproof.   The method for manufacturing a semiconductor device according to claim 1, wherein the gas containing elemental fluorine is a fluorocarbon gas or a mixed gas of a fluorocarbon gas and an oxygen gas. In a semiconductor device having a metal film containing titanium,
A through hole provided in the metal film;
A waterproof membrane that inhibits permeation of water molecules provided on the upper surface of the metal membrane;
A side wall including titanium provided on an inner surface of the through hole;
A semiconductor device comprising:

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