JP2007067256A - Semiconductor inspection pattern and semiconductor inspection method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To eliminate defective products by improving reliability in bump formation. <P>SOLUTION: A semiconductor wafer 1 is prepared wherein a metal pad, a scale 3 formed of the same material as the metal pad, a passivation film covering an outer circumference of the metal pad, and a first mark 4b formed adjacent to the scale 3 by an opening of the passivation film are formed. Thereafter, a gold bump 5 is formed on the metal pad, and a second mark 5a formed of the same gold as the gold bump 5 is formed adjacent to the scale 3. Each position of the first mark 4b and the second mark 5a can be thereby measured by the scale 3. Consequently, it is possible to inspect a displacement amount among the metal pad, the opening 4a of the passivation film, and the gold bump 5; and to manage the displacement amount among the three layers of the metal pad-the opening 4a of the passivation film-the gold bump 5. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor inspection pattern and a semiconductor inspection method, and more particularly to a technique effective when applied to alignment during bump formation.

  The semiconductor integrated circuit device includes a Si substrate, a multilayer wiring layer formed on the Si substrate, and an insulating layer formed on the multilayer wiring layer. The uppermost wiring layer includes a connection wiring. There is a technique in which normal wiring, fuse wiring, stepper alignment marks, and target marks are formed from the same copper film (see, for example, Patent Document 1).

Also, in the wafer batch type measurement inspection alignment method, an alignment mark is previously added to the thin film with bumps based on the arrangement of the bumps of the thin film with bumps, and the bumps are applied to the electrodes of the wafer to be measured and inspected. There is a technique for aligning a wafer and a probe card with reference to an alignment mark before making contact with a thin film bump (see, for example, Patent Document 2).
Japanese Patent Laying-Open No. 2003-163268 (FIG. 1) JP-A-11-154694 (FIG. 4)

  With the high integration of LSI (Large Scale Integration), the increase in the number of pins in IC (Integrated Circuit) chips is expected to progress further in the future. Further, in the field where LSI is actually used, the miniaturization is progressed, the mounting area is required to be highly efficient, and the bumps which are the mounting wiring are also expected to be miniaturized and the pitch is narrowed.

  By downsizing the bumps, the margin of alignment between the three layers of the underlying metal pad (surface electrode) -passivation film (protective film) -bump is reduced, and management of misalignment between the three layers is indispensable. ing.

  Further, when the margin for alignment between the three layers is reduced, a gap is likely to be formed between the bump and the opening of the passivation film, and moisture enters from this gap and corrodes (erodes) the underlying metal pad. The problem is that reliability failure occurs.

  Patent Document 1 (Japanese Patent Laid-Open No. 2003-163268) discloses that an alignment mark for fuse wiring is formed on a chip and used for alignment during fuse processing. However, there is no description that a scale portion is formed of the same material as that of the metal pad, and the scale portion is used to inspect the shift amount between the opening of the metal pad-passivation film and the bump.

  Patent Document 2 (Japanese Patent Application Laid-Open No. 11-154694) discloses that an alignment mark is formed at the time of bump formation and the bump alignment mark is used at the time of probe card alignment. However, as in Patent Document 1, there is no description that a scale portion is formed of the same material as that of the metal pad and the scale portion is used to inspect the shift amount between the opening of the metal pad-passivation film-bump.

  An object of the present invention is to provide a technique capable of improving the reliability by improving the alignment accuracy between a passivation film and a bump in bump formation and preventing the occurrence of defective products due to misalignment.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in this application, the outline of typical ones will be briefly described as follows.

  That is, the present invention provides a plurality of surface electrodes formed on a semiconductor wafer, a scale portion formed of the same material as the surface electrode around the surface electrode, and a surface electrode so that an opening is disposed on the surface electrode. Formed of the same material as that of the bump, the first mark formed adjacent to the scale portion, the bump connected to the surface electrode, and the bump. And the second mark arranged.

  Furthermore, the present invention provides a step of preparing a semiconductor wafer formed with a scale portion made of the same material as the surface electrode, a protective film covering the outer peripheral portion of the surface electrode, and a first mark adjacent to the scale portion; Forming bumps on the surface electrodes, and forming a second mark made of the same material as the bumps and adjacent to the scale part, and measuring the positions of the first and second marks by the scale part. Thus, the amount of deviation between the opening of the surface electrode and the protective film and the bump is inspected.

  Of the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  A semiconductor wafer having a scale portion made of the same material as the surface electrode, a protective film covering the outer periphery of the surface electrode, and a first mark formed adjacent to the scale portion by an opening of the protective film is prepared. In addition to forming a bump on the surface electrode and forming a second mark made of the same material as the bump adjacent to the scale portion, each position of the first and second marks is measured by the scale portion. Can do. Thereby, the deviation | shift amount of a surface electrode and the opening part of a protective film, and a bump can be test | inspected, and the deviation | shift amount between three layers of the opening part of a surface electrode-protective film-bump can be managed. As a result, the reliability in bump formation can be improved, and the production of defective products can be prevented.

  In the following embodiments, the description of the same or similar parts will not be repeated in principle unless particularly necessary.

  Further, in the following embodiment, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments, but they are not irrelevant to each other unless otherwise specified. The other part or all of the modifications, details, supplementary explanations, and the like are related.

  Also, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), particularly when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and it may be more or less than the specific number.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted.

(Embodiment 1)
FIG. 1 is a plan view showing an example of a structure at the time of forming a metal pad in the semiconductor inspection pattern according to the first embodiment of the present invention. FIG. 2 is an example of a cross-sectional structure taken along the line AA shown in FIG. FIG. 3 is a plan view showing an example of a structure when forming a passivation film in the semiconductor inspection pattern of the first embodiment of the present invention, and FIG. 4 is a cross section taken along the line AA shown in FIG. It is a fragmentary sectional view showing an example of the structure. 5 is a plan view showing an example of the structure when gold bumps are formed in the semiconductor inspection pattern according to the first embodiment of the present invention, and FIG. 6 is a cross-sectional structure cut along the line AA shown in FIG. It is a fragmentary sectional view showing an example.

  In the first embodiment, when a bump is formed on a plurality of surface electrodes on a semiconductor wafer, a deviation amount between the position of the surface electrode, the opening of the protective film, and the bump is measured (inspected). By managing the above, it will be possible to cope with the narrowing of the pad pitch and the miniaturization of the bumps, and a technique for improving the reliability of bump formation will be described.

  The semiconductor inspection pattern of the first embodiment will be described. As shown in FIGS. 5 and 6, a plurality of metal pads (surface electrodes) 2 formed on the main surface 1 a of the semiconductor wafer 1 and the periphery of the metal pads 2. A scale portion 3 that is integral with the metal pad 2 and made of the same material, and a passivation film (protective film) 4 that covers the outer periphery of the metal pad 2 so that the opening 4 a is disposed on the metal pad 2. have. Furthermore, the first mark 4b formed by the opening of the passivation film 4 and disposed outside the scale part 3 and adjacent to the scale part 3 is electrically connected to the metal pad 2 and on the metal pad 2 A gold bump 5 formed in the opening 4a of the passivation film 4 and a second mark 5a formed of the same material as the gold bump 5 and disposed outside the scale part 3 and adjacent to the scale part 3; have.

  The metal pad 2 is a plurality of surface electrodes formed in each of a plurality of chip regions on the main surface 1a of the semiconductor wafer 1, and is made of, for example, an aluminum alloy. The passivation film 4 is an insulating protective film. Furthermore, although the gold bump 5 is a bump electrode formed by plating and growing gold, for example, a silver bump or a nickel bump may be used.

  Here, the scale part 3 formed integrally with the metal pad 2 around the metal pad 2 measures the shift amounts of the metal pad 2 and the opening 4a of the passivation film 4 and the metal pad 2 and the gold bump 5. Vernier to (inspect). When the metal pad 2 is formed, the metal pad 2 is formed in the same process as the metal pad 2 using the same photolithography technique as the method of forming the metal pad 2.

  Further, the first mark 4b formed by the opening of the passivation film 4 can be formed by removing the passivation film 4 by etching or the like in the process of forming the passivation film 4. Further, the first mark 4 b is, for example, a triangular shape in plan view, and is formed adjacent to the scale portion 3 so that one corner of the triangle faces the scale portion 3.

  Thereby, the shift amount of the position of the opening 4a of the metal pad 2 and the passivation film 4 can be measured.

  Further, the second mark 5a formed of the same material as that of the gold bump 5, that is, gold, can be formed by a processing method (for example, plating growth method) similar to that of the gold bump 5 in the step of forming the gold bump 5. is there. Similarly to the first mark 4b, the second mark 5a has a triangular planar shape, and is formed adjacent to the scale part 3 so that one corner of the triangle faces the scale part 3. .

  Thereby, the shift amount of the position of the metal pad 2 and the gold bump 5 can be measured.

  As a result, it is possible to measure (inspect) the shift amount between the positions of the metal pad 2, the opening 4a of the passivation film 4 and the gold bump 5, and manage the shift amount.

  The scale portion 3 is not formed around all the metal pads 2 on the semiconductor wafer 1, but as an example, the scale portion 3 may be formed on the metal pads 2 at four corners in one chip region. That's fine. Alternatively, as described later, a misalignment inspection pattern may be formed in the dummy inspection pattern region of the scribe region.

  Next, the semiconductor inspection method according to the first embodiment will be described.

  First, a plurality of metal pads 2, a scale portion 3 that is disposed around the metal pad 2 and made of the same material as the metal pad 2, and an opening 4 a is disposed on the metal pad 2. A semiconductor wafer 1 is prepared in which a passivation film 4 that covers the outer periphery and a first mark 4b that is formed by the opening of the passivation film 4 and that is adjacent to the outside of the scale portion 3 are formed on the main surface 1a. To do.

  Here, a method of forming the first mark 4b including the scale portion 3 around the metal pad 2 and the opening of the passivation film 4 will be described.

  As shown in FIGS. 1 and 2, the scale portion 3 is formed integrally with the metal pad 2 around the metal pad 2. That is, when the metal pad 2 is formed of an aluminum alloy or the like, the metal pad 2 is formed in the same process as the process of forming the metal pad 2 using the same photolithography technique as the method of forming the metal pad 2. Therefore, as shown in FIG. 2, the scale portion 3 can be formed at the same height as the metal pad 2. At this time, the plurality of scales of the scale part 3 are formed with a pitch of one scale of about 0.1 μm, for example.

  Thereby, a scale portion 3 (vernier) composed of a plurality of scales capable of measuring the amount of deviation from the metal pad 2 is formed around the metal pad 2.

  Further, as shown in FIGS. 3 and 4, the first mark 4 b formed of the opening of the passivation film 4 is formed when the opening 4 a is formed on the metal pad 2 in the step of forming the passivation film 4. Similarly, the portion where the 1 mark 4b is formed is formed by removing the passivation film 4 by etching or the like. At this time, as shown in FIG. 3, the first mark 4 b has, for example, a triangular shape in plan view, and is adjacent to the scale portion 3 so that one corner of the triangle faces the scale portion 3. Form. Further, the first mark 4b is formed in alignment with the vertical and horizontal centers of the opening 4a of the passivation film 4 (L = L, M = M). At this time, the triangular pattern is preferably formed in a portion where there is no lower wiring layer.

  Thereby, the shift amount of the position of the opening 4a of the metal pad 2 and the passivation film 4 can be measured.

  Thereafter, as shown in FIGS. 5 and 6, gold bumps 5 are formed by plating growth so as to be electrically connected to the metal pads 2 in the openings 4 a of the passivation film 4 on the metal pads 2. At this time, a second mark 5 a made of the same material as that of the gold bump 5 and adjacent to the outer side of the scale portion 3 is formed by the same plating growth method.

  As shown in FIG. 5, the second mark 5 a has a triangular shape, for example, like the first mark 4 b, and has a scale so that one corner of the triangle faces the scale part 3. It is formed adjacent to the part 3. At that time, the second mark 5a is formed in alignment with the center of each of the vertical and horizontal sides of the gold bump 5 (P = P, Q = Q).

  Thereby, the shift amount of the position of the metal pad 2 and the gold bump 5 can be measured.

  According to the semiconductor inspection pattern and the inspection method of the first embodiment, the semiconductor wafer 1 on which the scale portion 3 arranged around the metal pad 2 and the first mark 4b adjacent to the scale portion 3 are formed. The gold bump 5 is formed on the metal pad 2 and the second mark 5a made of gold is formed adjacent to the scale portion 3, so that the first mark 4b and the second mark are formed by the scale portion 3. The position of each mark 5a can be inspected (measured).

  Thereby, the shift amount between the metal pad 2 and the opening 4 a of the passivation film 4 and the gold bump 5 can be inspected, and the shift amount between the three layers of the metal pad 2-the opening 4 a of the passivation film 4 and the gold bump 5 is determined. Can be managed.

  As a result, the reliability in bump formation can be improved and the production of defective products can be prevented.

(Embodiment 2)
7 is a partial plan view showing an example of the structure of the semiconductor inspection pattern according to the second embodiment of the present invention, FIG. 8 is an enlarged partial plan view showing an example of the structure of the portion B shown in FIG. 7, and FIG. It is a fragmentary sectional view which shows an example of the structure of the cross section cut | disconnected along the AA line shown.

  In the second embodiment, as in the first embodiment, when the bumps are formed on the plurality of surface electrodes on the semiconductor wafer, the amount of displacement between the surface electrodes, the openings of the protective film, and the positions of the bumps is measured. (Inspection), and by managing this deviation amount, it will be possible to cope with the narrowing of the pad pitch and the miniaturization of the bump, and the technology for improving the reliability of bump formation will be described. . However, the difference from the first embodiment is that the scale portion 3, the first mark 4 b and the second mark 5 a are formed in an ineffective area excluding an effective area (chip formation area) of the main surface 1 a of the semiconductor wafer 1. To do.

  In the second embodiment, as an example of the ineffective area, a case where the scale portion 3, the first mark 4b, and the second mark 5a are formed on the dicing line 1b as illustrated in FIGS. 7 and 8 will be described. . However, the area where the scale portion 3, the first mark 4b, and the second mark 5a are formed is not limited to the dicing line 1b, and may be another ineffective area.

  First, a semiconductor wafer 1 is prepared in which a scale portion 3 made of gold and a first mark 4b adjacent to the scale portion 3 are formed on a dicing line 1b on the main surface 1a. The scale portion 3 shown in FIG. 9 is formed in the same process as the metal pad 2 shown in FIG. 6, and the first mark 4 b is the same process as the passivation film 4 and the passivation film 4. Formed by the opening.

  Thereafter, a gold bump 5 is formed by plating growth so as to be electrically connected to the metal pad 2 in the opening 4a of the passivation film 4 on the metal pad 2, and is made of the same gold as the gold bump 5 and is a dicing line. A second mark 5a is formed of gold on the opposite side of the first mark 4b on the opposite side of the first mark 4b with the scale part 3 sandwiched between the scale part 3 on 1b.

  Thereby, the scale part 3, the 1st mark 4b, and the 2nd mark 5a are formed on the dicing line 1b.

  Therefore, also in the second embodiment, the position of each of the first mark 4b and the second mark 5a is measured by the scale portion 3, and the shift amount between the metal pad 2 and the opening 4a of the passivation film 4 and the gold bump 5 is measured. Can be inspected.

  As a result, it is possible to manage the amount of deviation between the three layers of the opening 4a of the metal pad 2-passivation film 4 and the gold bump 5, and as a result, it is possible to improve the reliability of bump formation and Manufacturing can be prevented.

  After the inspection, the scale part 3, the first mark 4b, and the second mark 5a can be removed by cutting the semiconductor wafer 1 into pieces by dicing with the dicing line 1b.

  Thereby, the scale part 3, the 1st mark 4b, and the 2nd mark 5a can be made not to remain on a product.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiments of the invention. However, the present invention is not limited to the embodiments of the invention, and various modifications can be made without departing from the scope of the invention. It goes without saying that it is possible.

  For example, in the first and second embodiments, the case where the first mark 4b and the second mark 5a are triangular has been described as an example. However, the first mark 4b and the second mark 5a are other examples. A rectangle, an arrow, or the like may be used, and any shape may be used as long as the scale of the scale portion 3 is pointed out.

  The present invention is suitable for an alignment technique during bump formation.

It is a top view which shows an example of the structure at the time of metal pad formation in the semiconductor test pattern of Embodiment 1 of this invention. It is a fragmentary sectional view which shows an example of the structure of the cross section cut | disconnected along the AA line shown in FIG. It is a top view which shows an example of the structure at the time of passivation film formation in the semiconductor test pattern of Embodiment 1 of this invention. It is a fragmentary sectional view which shows an example of the structure of the cross section cut | disconnected along the AA line shown in FIG. It is a top view which shows an example of the structure at the time of gold bump formation in the semiconductor test pattern of Embodiment 1 of this invention. It is a fragmentary sectional view which shows an example of the structure of the cross section cut | disconnected along the AA line shown in FIG. It is a fragmentary top view which shows an example of the structure of the semiconductor test pattern of Embodiment 2 of this invention. FIG. 8 is an enlarged partial plan view showing an example of a structure of a B part shown in FIG. 7. It is a fragmentary sectional view which shows an example of the structure of the cross section cut | disconnected along the AA line shown in FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor wafer 1a Main surface 1b Dicing line (ineffective area)
2 Metal pad (surface electrode)
3 Scale part 4 Passivation film (protective film)
4a Opening 4b 1st mark 5 Gold bump 5a 2nd mark

Claims (5)

A semiconductor inspection pattern for inspecting a deviation amount between a front surface electrode and a protective film opening formed on a semiconductor wafer and a bump,
A plurality of surface electrodes formed on the main surface of the semiconductor wafer;
A scale formed of the same material as the surface electrode around the surface electrode;
The protective film covering the outer periphery of the surface electrode so that the opening is disposed on the surface electrode;
A first mark formed by an opening of the protective film and disposed adjacent to the scale portion outside the scale portion;
Electrically connected to the surface electrode, the bump formed in the opening of the protective film on the surface electrode;
A semiconductor inspection pattern comprising a second mark formed of the same material as the bump and disposed adjacent to the scale portion outside the scale portion. A semiconductor inspection pattern for inspecting a deviation amount between a front surface electrode and a protective film opening formed on a semiconductor wafer and a bump,
A plurality of surface electrodes formed on the main surface of the semiconductor wafer;
A scale formed of the same material as the surface electrode on a dicing line on the main surface of the semiconductor wafer;
The protective film covering the outer periphery of the surface electrode so that the opening is disposed on the surface electrode;
A first mark formed by the opening of the protective film and disposed adjacent to the scale on the dicing line;
Electrically connected to the surface electrode, the bump formed in the opening of the protective film on the surface electrode;
The second mark is formed of the same material as the bump, and is disposed adjacent to the scale portion on the dicing line, with the second portion disposed on the side opposite to the first mark. A semiconductor inspection pattern. A semiconductor inspection method for inspecting a deviation amount between a surface electrode and a protective film opening formed on a semiconductor wafer and a bump,
A plurality of surface electrodes, a scale portion disposed around the surface electrode and made of the same material as the surface electrode, and an outer peripheral portion of the surface electrode so as to be disposed on the surface electrode A step of preparing a semiconductor wafer in which the protective film and the first mark formed by the opening of the protective film and adjacent to the outside of the scale portion are respectively formed on the main surface;
The bump is formed in the opening of the protective film on the surface electrode so as to be electrically connected to the surface electrode, and is made of the same material as the bump and adjacent to the outside of the scale portion. Forming a mark of 2, and
A semiconductor inspection method comprising: measuring the positions of the first and second marks by the scale portion and inspecting the displacement amount of the surface electrode, the opening of the protective film, and the bump. A semiconductor inspection method for inspecting a deviation amount between a surface electrode and a protective film opening formed on a semiconductor wafer and a bump,
The surface electrode, a plurality of surface electrodes, a scale portion that is disposed in an ineffective region of the main surface of the semiconductor wafer and made of the same material as the surface electrode, and the opening portion is disposed on the surface electrode And a first mark that is formed by an opening of the protective film and is disposed adjacent to the scale portion in the ineffective region, respectively, on a main surface. Preparing a wafer;
The bump is formed in the opening of the protective film on the surface electrode so as to be electrically connected to the surface electrode, is made of the same material as the bump, and is adjacent to the scale portion in the ineffective area. And forming a second mark disposed on the opposite side of the first mark across the scale portion,
A semiconductor inspection method comprising: measuring the positions of the first and second marks by the scale portion and inspecting the displacement amount of the surface electrode, the opening of the protective film, and the bump. A semiconductor inspection method for inspecting a deviation amount between a surface electrode and a protective film opening formed on a semiconductor wafer and a bump,
The surface electrode, a plurality of surface electrodes, a scale portion disposed on a dicing line on the main surface of the semiconductor wafer and made of the same material as the surface electrode, and the opening portion disposed on the surface electrode A semiconductor in which the protective film covering the outer peripheral portion of the substrate and the first mark formed by the opening of the protective film and disposed adjacent to the scale portion on the dicing line are respectively formed on the main surface Preparing a wafer;
The bump is formed in the opening portion of the protective film on the surface electrode so as to be electrically connected to the surface electrode, is made of the same material as the bump, and is adjacent to the scale portion on the dicing line. Forming a second mark disposed on the opposite side of the first mark across the scale portion;
Cutting the semiconductor wafer at the dicing line,
The scale portion measures the position of each of the first and second marks to inspect the displacement amount of the surface electrode, the opening of the protective film, and the bump, and after the inspection, the scale portion is cut by dicing. A semiconductor inspection method, wherein the first and second marks are removed.

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