JP2007066301A - Semiconductor device, inspection method of semiconductor device and inspection method of wireless chip - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an inspection method for a semiconductor device wirelessly receiving a test program. <P>SOLUTION: As the inspection method of the semiconductor device, a test program is transmitted as a communication signal for every test. By transmitting a test program as a communication signal wirelessly at an operation test, test contents are changed as required. As a result, a test program can be easily changed and an inspection circuit or the like is not required. In this manner, manufacturing cost of a wireless chip can be reduced. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

The present invention relates to an inspection method and a configuration of a semiconductor device for simply inspecting a semiconductor device.

In recent years, there is a need for a card equipped with an RFID (Radio Frequency Identification) chip that can send and receive data in a contactless manner and for any field that requires automatic recognition such as inventory management of securities and products, and the need for an RFID tag The nature is increasing. A card equipped with an RFID chip has a larger recording capacity and higher security than a magnetic card that records data by a magnetic recording method, and recently, a form that can be used in various fields has been proposed. A card equipped with such an RFID chip reads / writes data without contact with an external device via an antenna having a shape adapted to a frequency band used when data is exchanged.

Generally, semiconductor devices such as RFID tags are mass-produced and shipped after an inspection process. As one of inspection methods, there is a method of performing inspection without supplying driving power to a circuit or a substrate (see Patent Document 1). In Patent Document 1, a test circuit is incorporated in an integrated circuit in advance, a unique code is assigned to the test circuit, an electromagnetic wave from the outside is received, an operation power supply is generated, and detection is performed according to a procedure based on the generated test signal. A method for transmitting a detection result to the outside is disclosed.

As another inspection method, there is a method for inspecting the entire substrate including the wiring pattern in a non-contact manner (see Patent Document 2). According to Patent Document 2, a test circuit is incorporated in an integrated circuit in advance, a unique code is assigned to the test circuit, an electromagnetic wave is received by a receiving unit of the test circuit, driving power for the test circuit is generated, and a test control procedure is performed from the test device. Is also disclosed in a non-contact manner and a result is transmitted to the inspection apparatus.
JP 2003-57300 A Japanese Patent Laid-Open No. 2003-60047

Conventional semiconductor devices generally have an inspection method in which an inspection circuit is mounted on a semiconductor device and the semiconductor device is inspected using the inspection circuit. However, in this case, there is an inconvenience that the inspection circuit must be changed in order to cope with the change or update of the test program required for the inspection, and the change or update is extremely difficult.

In view of the above problems, in the present invention, a test program transmitted by wireless communication is recorded in a data storage unit mounted on a semiconductor device, and the test is performed by using the test program. When the content of the test program is changed due to the required inspection, it can be rewritten by erasing and writing by wireless communication. As the semiconductor device, a chip capable of wireless communication (hereinafter referred to as a wireless chip) can be given.

The specific configuration of the present invention is shown below.

One embodiment of the present invention includes a data storage unit and an antenna, and the data storage unit includes a thin film transistor. The data storage unit includes a test program received via an antenna by wireless communication at least during a test process. Is a semiconductor device in which is recorded.

Another embodiment of the present invention includes a data storage unit, a reception circuit, a state control register, and an RF circuit, and the data storage unit, the reception circuit, the state control register, and the RF circuit each include a thin film transistor, and the data At least during the test process, the storage unit stores a test program received by the radio circuit via the RF circuit and then processed by the receiving circuit, and the state control register is in a test program execution state. A semiconductor device characterized by the above.

The state control register may have means for rewriting the test program execution state flag to the test program execution state.

The data storage unit includes a read-only memory and a random access memory.

The test program data includes a test routine for performing an operation test on the read-only memory and the random access memory.

In the above embodiment, an arithmetic circuit and a transmission circuit are provided, and the arithmetic circuit starts the test program when the state control register changes to a test program execution state, and the state control register when the test program ends. Is changed to the transmission processing state, and the transmission circuit processes the transmission data so that it conforms to the format of the communication signal and outputs it to the modulation circuit. Upon completion of transmission, the state control register changes to the reception processing state. It may have a function to make it.

Another embodiment of the present invention is a method for inspecting a semiconductor device having an arithmetic circuit, a data storage unit, a receiving circuit, a state control register, and an RF circuit, wherein the arithmetic circuit starts operation according to the state of the state control register, The arithmetic circuit reads a test program recorded in the data storage unit and executes a test routine in the test program. The arithmetic circuit determines an execution result of the test routine, and the execution result is used as the data. A test method for a semiconductor device, wherein the test program is written into a storage unit and received by the receiving circuit as a communication signal via the RF circuit.

Another embodiment of the present invention is a method for inspecting a semiconductor device having an arithmetic circuit, a data storage unit, a receiving circuit, a state control register, an RF circuit, and a transmitting circuit, and when the state control register changes to a test program execution state. The test program is started, the arithmetic circuit reads the test program recorded in the data storage unit and executes a test routine in the test program, and the arithmetic circuit determines an execution result of the test routine. The execution result is written to the data storage unit, the state control register is changed to the transmission processing state when the test program is finished, and the transmission data is processed by the transmission circuit so as to conform to the format of the communication signal. Output to the modulation circuit, and when the transmission is completed, change the state control register to the reception processing state. Has a capacity, the test program is an inspection method of a semiconductor device characterized in that it is processed by the receiving circuit after being received via the RF circuit as a communication signal.

In the above inspection method, the state control register may be changed to the transmission processing state by means for rewriting the reception state flag to the execution state.

Another embodiment of the present invention is a wireless chip inspection method including an arithmetic circuit, a state control register, a data storage unit, an RF circuit, and a reception circuit. The wireless chip has a liquid crystal element on the wireless chip, and the test program is a communication program. A wireless chip inspection method for displaying whether or not an inspection result is acceptable by the liquid crystal element, which is received as a signal through the RF circuit, processed by the reception circuit, recorded in the data storage unit, and performed by the test program It is.

Another embodiment of the present invention is a wireless chip inspection method including an arithmetic circuit, a state control register, a data storage unit, an RF circuit, and a reception circuit. The wireless chip includes a liquid crystal element and receives light from a laser light source. The wireless chip is arranged between the devices, and the test program is received as a communication signal via the RF circuit and then processed by the reception circuit and recorded in the data storage unit, and is performed by the test program. An inspection method for a wireless chip, wherein whether or not an inspection result is acceptable is determined based on whether or not light from the laser light source is input to the light receiver.

In the above-described wireless chip inspection method, the liquid crystal element may include liquid crystal molecules sandwiched between substrates provided with polarizing plates.

According to the present invention, in a wireless chip that supplies power supply voltage by induced electromotive force from a communication signal and transmits / receives communication data, a test program is transmitted as a communication signal for each test during an operation test of the chip component. The test contents can be changed flexibly as needed. In this way, the manufacturing cost at the time of wireless chip production can be reduced.

The wireless chip of the present invention is composed of a thin film transistor using a semiconductor thin film formed on a substrate having an insulating surface such as a glass substrate, a quartz substrate, a plastic substrate, or the like as an active layer, thereby achieving high performance and low power consumption. A wireless chip can be provided.

Embodiments of the present invention will be described below with reference to the drawings. However, the present invention can be implemented in many different modes, and those skilled in the art can easily understand that the modes and details can be variously changed without departing from the spirit and scope of the present invention. Is done. Therefore, the present invention is not construed as being limited to the description of this embodiment mode. Note that in all the drawings for describing the embodiments, the same portions or portions having similar functions are denoted by the same reference numerals, and repetitive description thereof is omitted.

(Embodiment 1)
In this embodiment mode, a block diagram of a wireless chip to be inspected in the present invention, a device configuration for realizing a wireless chip inspection method, and a flowchart will be described.

FIG. 1 is a block diagram of a wireless chip that is an inspection object in the present invention.

In FIG. 1, a wireless chip 201 includes a data storage unit 221, an arithmetic circuit 202, a state control register 203, a reception circuit 204, a transmission circuit 205, an antenna 206, a resonance circuit 207, a power supply circuit 208, a reset circuit 209, a clock circuit 210, A demodulation circuit 211 and a modulation circuit 212 are included. The wireless chip 201 can transmit and receive the reception signal 213 and the transmission signal 214 by an RF circuit including the antenna 206, the resonance circuit 207, the power supply circuit 208, the reset circuit 209, the clock circuit 210, the demodulation circuit 211, and the modulation circuit 212. . In FIG. 1, for the sake of simplicity of explanation, the reception signal 213 and the transmission signal 214 are shown as separate signals. However, in actuality, they are overlapped between the wireless chip 201 and the reader / writer. They are sent and received at the same time.

In FIG. 1, when the wireless chip 201 is placed in a magnetic field formed by a communication signal, an induced electromotive force is generated by the antenna 206 and the resonance circuit 207. With this induced electromotive force, the power supply voltage of the wireless chip 201 can be supplied. The induced electromotive force is held by the electric capacity of the power supply circuit 208, and the electric potential can be stabilized by the electric capacity. The reset circuit 209 generates a system reset signal 215 that initializes the entire wireless chip 201. The system reset signal 215 has a clock waveform. For example, the system reset signal 215 can be a signal that rises after a certain time delay with respect to the rise of the power supply voltage. The clock circuit 210 generates a clock signal from the communication signal. For example, a communication signal is rectified by a half-wave rectifier circuit and then passed through an inverter circuit, thereby generating a clock signal having the same cycle as the communication signal. This clock signal may be the system clock signal 216 in the wireless chip 201, or may be further divided into the system clock signal 216. The demodulation circuit 211 detects the fluctuation of the amplitude of the reception signal 213 as a “0” or “1” signal. For example, a low-pass filter is used as the demodulation circuit 211. The modulation circuit 212 transmits the transmission data by changing the amplitude of the transmission signal 214. For example, when the transmission data is “0”, the resonance point of the resonance circuit 207 is changed, and the amplitude of the communication signal is changed. The state control register 203 indicates which state is a reception processing state, a data execution state, or a transmission processing state. By changing the state control register 203, it is possible to transition between the states. Specifically, specific bits in the state control register 203 are a reception processing state flag bit, a test program execution state flag bit, and a transmission processing state flag bit. For example, when each status flag bit is “1”, it is assumed that each status is set, and each flag bit is changed. That is, in this case, when the reception processing state flag bit is “1”, the wireless chip 201 is in the reception processing state.

The data storage unit 221 includes a memory element that stores test program data and test results included in the received data received from the reader / writer. As memory elements, there are a read only memory (ROM) and a random access memory (including RAM: Random Access Memory). ROM includes mask ROM (Read Only Memory) and the like, and RAM includes SRAM (Static Random Access Memory) and the like. Specifically, the test program data includes a test routine for inspecting the operation of the ROM and RAM, and the inspection result includes defective addresses and defective contents of the ROM and RAM.

In the reception processing state, the reception circuit 204 operates and the arithmetic circuit 202 and the transmission circuit 205 are stopped. In the arithmetic processing state, the arithmetic circuit 202 operates and the receiving circuit 204 and the transmitting circuit 205 are stopped. Further, in the transmission processing state, the transmission circuit 205 operates and the reception circuit 204 and the arithmetic circuit 202 are stopped.

In the state control described above, in order to stop the supply of the clock signal, for example, when the reception processing state flag bit is “1”, the clock signal enable signal 217 supplied to the reception circuit 204 is set to “1”, and the arithmetic processing is performed. When the status flag bit is “1”, the reset signal of the arithmetic circuit 202 is “0”, the enable signal 218 of the clock signal supplied to the arithmetic circuit 202 is “1”, and the transmission processing status flag bit is “1” This can be realized by setting the enable signal 219 of the clock signal supplied to the transmission circuit 205 to “1”.

More specifically, a clock signal for supplying the logical product of the system reset signal 215 and the enable signal 217 to the receiving circuit 204 and a logical product of the system reset signal 215 and the enable signal 218 to the arithmetic circuit 202 are used. And the logical product of the system reset signal 215 and the enable signal 219 can be realized as a clock signal supplied to the transmission circuit 205.

By supplying only a circuit that requires a clock signal as described above, the power consumption of the entire wireless chip can be reduced.

Hereinafter, the operation of the entire wireless chip will be described with reference to the flowchart of FIG.

The reception circuit 204 identifies and extracts SOF (Start Of Frame), reception data, and EOF (End Of Frame) from the signal demodulated by the demodulation circuit 211 (communication signal reception 271). When the EOF is extracted, the received data is recorded in the data storage unit 221 and the state control register 203 is changed to the test program execution state (state control register setting 272). In order to change the state control register 203 to the test program execution state, it is only necessary to have means for rewriting the test program execution state flag to “1”. Specifically, the receiving circuit 204 only needs to have a means for changing the test program execution state flag to “1” when the receiving circuit 204 extracts the EOF.

The arithmetic circuit 202 includes a dedicated circuit that executes a test program in transmitting / receiving test program data, for example. When the test program execution state flag is “1”, the test program is started (test program execution 273). When the test program is completed, the state control register is changed to the transmission processing state (state control register setting 274). In order to change the state control register 203 to the transmission processing state, it is only necessary to have means for rewriting the transmission state flag to “1”. Specifically, the arithmetic circuit 202 only needs to have means for changing the transmission state flag to “1” when the arithmetic circuit 202 finishes executing the test program.

The transmission circuit 205 processes the transmission data in accordance with the format of the communication signal and outputs it to the modulation circuit 212 (communication signal transmission 275). Upon completion of transmission, the state control register is changed to the reception processing state (state control register setting 276). In order to change the state control register to the reception processing state, it is only necessary to have means for rewriting the reception state flag to “1”. Specifically, it is sufficient that the transmission circuit 205 has a means for changing the reception state flag to “1” when the transmission circuit 205 finishes transmission of transmission data.

Next, the operation of the test program will be described with reference to the flowchart of FIG.

The arithmetic circuit 202 starts the operation in response to the state of the state control register 203 (start 307). The arithmetic circuit 202 reads a test program from the data storage unit 221 (test program read 308) and executes a test routine in the test program (test routine execution 309). The arithmetic circuit 202 discriminates the execution result of the test routine (test result discrimination 310) and writes the result into the data storage unit 221 (test result write 311). Finally, the arithmetic circuit 202 ends the operation (end 312).

By executing the test program in this manner, the test program can be freely changed as necessary by transmitting the test program as a communication signal for each test.

Next, a wireless chip inspection apparatus having the configuration of FIG. 1 and operating in accordance with the procedures of FIGS. 2 and 3 will be described with reference to FIGS.

A substrate 404 illustrated in FIG. 4 is a large glass substrate, and a large number of wireless chips are formed over the substrate. The structure of the wireless chip is as shown in FIG. Specifically, when a fourth generation glass substrate of 600 mm × 720 mm is used, about 4000 1 cm square wireless chips can be formed on one substrate. FIG. 7 shows a top view of the substrate 404. Each wireless chip has an antenna 406. Wireless communication and wireless inspection can be performed with the antenna.

A prober control device 401 shown in FIG. 4 is connected to a wireless prober 403 via a cable 402 and controls the operation of the wireless prober 403. The wireless prober 403 may have a mechanism that operates in the X direction, the Y direction, and the Z direction with respect to the substrate 404 placed on the stage 405.

As shown in FIG. 22, the prober control device 401 includes a host computer 600, a data transmission unit 601, a data reception unit 602, and a stage control unit 603 connected to the computer. The prober control device 401 can transmit test program data to the wireless prober 403 by the data transmission unit 601. The prober control device 401 can receive test program data from the wireless prober 403 by the data receiving unit 602. The prober control device 401 can relatively move the stage and the prober by the stage control unit 603.

Further, the wireless prober 403 can transmit test program data to an antenna 406 of an arbitrary wireless chip on the substrate 404 by using a built-in wireless antenna. At this time, the prober control device 401 and the stage 405 are relatively moved in the X direction, the Y direction, and the Z direction so that the antenna 406 of the wireless chip enters the magnetic field of the wireless antenna formed by the communication signal. Specifically, in the case of a wireless chip operating at 13.56 MHz, it may be at a distance of about 2 to 3 cm from the wireless prober.

When inspecting all of the wireless chips on the substrate 404, for example, if the stage 405 is fixed and the wireless prober 403 is operated in the direction indicated by the arrow on the substrate 404, the moving distance of the wireless prober 403 is short, so the inspection process Throughput can be increased. Alternatively, the wireless prober 403 may be fixed and the stage 405 may be moved in the direction indicated by the arrow.

The wireless prober 403 can transmit test program data to the antenna 406 of an arbitrary wireless chip, and can transmit the inspection result received after the inspection is completed to the prober control device 401 via the cable 402.

As shown in FIG. 5, the inspection result can be determined at a glance by indicating that the non-defective product on the substrate is indicated by “◯” and the defective product by “X”. The display of the inspection result may indicate the location of a non-defective product with coordinates (x, y) or the number of non-defective products.

FIG. 23 shows a flowchart of the inspection method. When the host computer 600 starts the inspection (start 630), the host computer 600 moves the stage 405 to the inspection location (631 that moves the stage to the inspection location). Thereafter, the host computer 600 transmits the test program data to the data transmission unit 601 of the prober control device 401 (transmits the test data to the data transmission unit 632). Specifically, the data transmission unit 601 transmits test program data to an arbitrary wireless chip by the wireless prober 403. Next, the data receiving unit 602 receives data received from an arbitrary wireless chip via a wireless prober, and the host computer 600 receives data collected from the data receiving unit 602 (receives data collected from the data receiving unit). 633). Thereafter, the host computer 600 determines a test result for determining whether the data matches or does not match (test result determination 634). If the inspection result is good (YES), the stage coordinate data of the inspection location and the “OK” flag are recorded in the host computer 600 (stage coordinate data and “OK” are recorded 636). Then, the inspection is finished (end 638). On the other hand, if the inspection result is defective (NO), a retest may be performed to determine (retest determination 635). If the test result is defective (NO) even after the retest, the stage coordinate data of the target location and the “NG” flag are recorded in the host computer 600 (the stage coordinate data and “NG” are recorded). 637). Then, the inspection is finished (end 638). The number of retests is not limited as long as it is two or more times including the first test. By performing the inspection a plurality of times, the accuracy of the test can be increased. Therefore, even if the inspection result is good (YES), a retest may be performed.

Next, different types of inspection apparatuses will be described. FIG. 6 shows a configuration of an inspection apparatus capable of performing an operation inspection of a wireless chip by transmitting and receiving communication signals by a prober in addition to the inspection apparatus shown in FIG.

The prober control device 411 shown in FIG. 6 is connected to the wireless prober 413 via the cable 412 and controls the operation of the wireless prober 413, and the wireless prober 413 has a prober 416. The wireless prober 413 may include a mechanism that operates in the X direction, the Y direction, and the Z direction with respect to the substrate 414 placed on the stage 415. That is, as in FIG. 4, it is only necessary that the prober control device 411 and the stage 415 can be relatively moved in the X direction, the Y direction, and the Z direction.

An electrode pad 417 is provided on the substrate 414. FIG. 8 shows a top view of a substrate to be inspected using the inspection apparatus. A large amount of wireless chips are formed over the substrate 420, electrode pads 417 are provided on part of the substrate 420, and the wireless chip includes an antenna 419. By using such an inspection apparatus, the prober 416 and the electrode pad 417 are directly connected to each other and electrically connected to each other, so that a communication signal including test data can be transmitted to the wireless chip.

With such an inspection apparatus, even when the antenna 419 on the substrate 420 is defective and cannot be used, the wireless chip can be inspected.

By adopting the above form, in a wireless chip that supplies power supply voltage by induced electromotive force from a communication signal and transmits / receives communication data, a test program is transmitted as a communication signal for each inspection at the time of operation inspection of wireless chip components By doing so, the inspection content can be flexibly changed as necessary. As in the prior art, in a wireless chip incorporating an inspection circuit, it is necessary to change the mask and reproduce it every time the inspection content is changed. By using the present invention, it is possible to flexibly cope with changes in inspection contents without performing mask changes and mask reproduction. Thereby, the manufacturing cost at the time of wireless chip production can be reduced.

In addition, the wireless chip in this embodiment mode includes a thin film transistor that uses a semiconductor thin film formed over an insulating substrate such as a glass substrate, a quartz substrate, or a plastic substrate as an active layer, thereby achieving high performance and low power consumption. A wireless chip can be provided.

(Embodiment 2)
In this embodiment mode, a device configuration and a flowchart for realizing a wireless chip inspection method of the present invention, a block diagram of a wireless chip to be inspected, and an element structure will be described with reference to FIGS.

FIG. 9 is a block diagram of a wireless chip that is an inspection target of the wireless chip inspection method according to the present invention. FIG. 9 is a block diagram of the wireless chip according to the first embodiment, with a liquid crystal driving unit 222 added. Similar to FIG. 1, a data storage unit 221, an arithmetic circuit 202, a state control register 203, a receiving circuit 204, and a transmitting circuit. 205, an antenna 206, a resonance circuit 207, a power supply circuit 208, a reset circuit 209, a clock circuit 210, a demodulation circuit 211, and a modulation circuit 212. The liquid crystal driver 222 may include a switching element and a liquid crystal element, and may have means for controlling light transmission from the upper surface to the lower surface of the substrate. The switching element can be formed using a thin film transistor (hereinafter also referred to as TFT). When the arithmetic circuit 202 executes a test program, the specific liquid crystal driving unit 222 applies a voltage to the switching element according to the test result and controls liquid crystal molecules, thereby determining light transmission or non-transmission. be able to.

10 and 11 schematically show the operation of the liquid crystal molecules constituting the liquid crystal driving unit 222. FIG. This schematic diagram shows a display principle of a liquid crystal generally called a TN (twisted nematic) type.

In FIG. 10, a liquid crystal element having liquid crystal molecules 1002 is provided between a first polarizing plate 1001 provided on the first substrate 1004 and a second polarizing plate 1003 provided on the second substrate 1005. Show. When no voltage is applied to the liquid crystal element, light incident from the first substrate 1004 is transmitted to the second substrate 1005. Specifically, light incident from the first substrate 1004 passes through only a component in a single direction by the first polarizing plate 1001 and is second twisted as light that is twisted by 90 ° in the spiral direction by the liquid crystal molecules 1002. By passing through 1003, light is transmitted from the first substrate 1004 to the second substrate 1005.

In FIG. 11, a liquid crystal element having liquid crystal molecules 1012 is provided between a first polarizing plate 1011 provided on the first substrate 1014 and a second polarizing plate 1013 provided on the second substrate 1015. Show. When voltage is applied to the liquid crystal element, light incident from the first substrate 1014 is not transmitted to the second substrate 1015. Specifically, light incident from the first substrate 1014 is allowed to pass through only a component in a single direction by the first polarizing plate 1011, but is blocked by the liquid crystal molecules 1012, so that the light is incident on the second substrate 1015. Does not reach.

FIG. 12 shows a cross-sectional view of the liquid crystal driving unit 222. A TFT 303 is provided on the insulating substrate 301 as a switching element via a base layer. A pixel electrode 304 is connected to a source electrode or a drain electrode of the TFT 303, and a control signal from the TFT 303 is input to the pixel electrode 304. An alignment film 305 is provided so as to cover the pixel electrode 304 and the TFT 303. The alignment film 305 can control the tilt of liquid crystal molecules.

A counter substrate 314 is disposed so as to face the insulating substrate 301. The counter substrate 314 is provided with a counter electrode 318 and an alignment film 315 in this order. Liquid crystal molecules 317 are provided between the insulating substrate 301 and the counter substrate 314. A distance between the insulating substrate 301 and the counter substrate 314 is kept constant by a spacer 319. After the liquid crystal molecules 317 are provided, the insulating substrate 301 and the counter substrate 314 are fixed by the sealant 320.

In such a liquid crystal driving unit 222, voltage application to the liquid crystal molecules 317 is switched by the TFT 303, and the transmitted light 330 reaches the insulating substrate 301 when the TFT 303 is off.

Next, the operation of the test program in the wireless chip having such a liquid crystal driving unit 222 will be described with reference to FIG.

First, the arithmetic circuit 202 included in the wireless chip starts operating in response to the state of the state control register 203 (start 307). The arithmetic circuit 202 reads a test program from the data storage unit 221 (test program read 308) and executes a test routine in the test program (test routine execution 309). The arithmetic circuit 202 discriminates the execution result of the test routine (test result discrimination 310), and applies a voltage to the liquid crystal driving unit 222 when an abnormality is detected (liquid crystal driving unit voltage application 313). Finally, the arithmetic circuit 202 ends the operation (end 312).

By executing the test program in this way and applying a voltage to the liquid crystal driving unit 222 according to the test result, transmission and non-transmission of light can be controlled.

Next, a wireless chip inspection apparatus and inspection method having the configuration of FIG. 9 and capable of performing a test program operation according to the procedure of FIG. 13 will be described with reference to FIG. The present inspection apparatus is used in combination with the apparatus of the first embodiment, and the configuration using the induced electromotive force from the communication signal as the operation power supply of the wireless chip is the same as that of the first embodiment, and the description is omitted.

The laser light source 50 shown in FIG. 14A is emitted from a vertical direction with respect to an arbitrary wireless chip 54 formed on the insulating substrate 53, passes through the chip, and reaches the light receiver 51. Therefore, it is necessary that the optical axis of the laser light source 50 and the center axis of the light receiver 51 coincide.

The insulating substrate 53 and the laser light source 50 move relative to each other so that the laser light source is incident on the wireless chip 54 to be inspected. For example, the stage holding the insulating substrate 53 may have a means for moving in the X direction and the Y direction.

The liquid crystal 56 is sealed inside the spacer 57 of the wireless chip 54, and the liquid crystal 56 is controlled to be transmitted or not transmitted by the liquid crystal driving unit 222. The insulating substrate 53 is divided at the cut region 58 after inspection by the inspection apparatus.

When light is emitted from the laser light source 50 to an arbitrary wireless chip 54, if the execution result of the test program is normal, the liquid crystal is driven, and the light emitted from the laser light source 50 can reach the light receiver 51. Can not. If the execution result of the inspection program is abnormal, the liquid crystal is not driven, and the light emitted from the laser light source 50 reaches the light receiver 51. The light receiver 51 records transmission and non-transmission for each chip and accumulates them as defect information of the chip.

At this time, since the interval between the wireless chips 54 is narrow, anti-collision processing is used. By performing the anti-collision process, it is possible to inspect only a specific wireless chip. The anti-collision process may be set in the inspection apparatus. The anti-collision process is a process that prevents interference from occurring.

As described above, it is possible to detect a non-defective product and a defective product of the wireless chip by transmission and non-transmission of light emitted from the laser light source 50.

By adopting the above form, in the wireless chip that supplies power supply voltage by the induced electromotive force from the communication signal and transmits / receives communication data, the operation inspection is performed according to the driving state of the liquid crystal when the operation of the wireless chip component is inspected. Can do. For this reason, since the result is detected by transmission and non-transmission of light without transmitting the result by communication, it is not affected by the electric noise emitted from the apparatus during the inspection process.

Further, when the wireless chip incorporating the liquid crystal display element is manufactured, when the inspection method described in this embodiment is used, the operation inspection of the display element and the operation inspection of the wireless chip can be performed at the same time. Therefore, the inspection process can be reduced, leading to a reduction in manufacturing cost.

In addition, the wireless chip in this embodiment includes a thin film transistor that uses a semiconductor thin film formed over a substrate having an insulating surface such as a glass substrate, a quartz substrate, or a plastic substrate as an active layer. A wireless chip with low power consumption can be provided.

FIG. 14B shows an enlarged view of the wireless chip and a cutting process. On the wireless chip 54 provided on the insulating substrate 53, a liquid crystal 56 sandwiched between the substrates is disposed. The boundary between adjacent wireless chips is separated by a spacer 57. Therefore, the liquid crystal 56 is not provided over a plurality of wireless chips. In order to achieve such a configuration, a spacer 57 is provided on a substrate holding the liquid crystal 56, the liquid crystal is dropped, and the counter substrate is sealed. By dropping liquid crystal in this manner, liquid crystal elements can be provided in a plurality of regions separated by the spacer 57.

Thereafter, the wireless chip 54 and the liquid crystal element are cut together. A region to be cut is between the spacers 57. Examples of means for cutting include a laser cut method and a scribe method.

Thus, by using the present invention, a wireless chip that can be easily inspected can be provided.

(Embodiment 3)
In the present embodiment, a test routine in a test program for realizing the wireless chip inspection method according to the present invention will be described with reference to FIGS. The test routine in the present embodiment can be incorporated in the test program used in the first and second embodiments.

The operation of the test routine will be described with reference to the flowchart shown in FIG.

The arithmetic circuit 202 reads a test program from the data storage unit 221 and starts a test routine (start 501). The arithmetic circuit 202 determines the command code of the data storage unit (command code determination 502), and processes the data copy routine (data copy routine 504), ROM test routine (ROM test routine 505), RAM test according to the type of command code. It is possible to branch to a routine (RAM test routine 506) and execute any routine. Of course, a plurality of routines may be executed. Finally, the arithmetic circuit 202 ends the test routine (end 503).

FIG. 20 shows the address space of the data storage unit 221. The data storage unit 221 includes a ROM 250, a RAM 251, a control register 252, a reception data register 253, and a transmission data register 254. The control register 252 has a function indicating which state is a reception processing state, a data execution state, or a transmission processing state. The reception data register 253 has a function of storing data received by the wireless chip. The transmission data register 254 has a function of storing data transmitted by the wireless chip. Further, the same contents as in FIG. 20 are also recorded in the reader / writer device that exchanges information and power with the wireless chip.

Next, the details of the process for each command code included in FIG. 16 will be described with reference to the flowcharts of FIGS.

FIG. 17 shows a flowchart of the data copy routine. Depending on the type of command, a data copy routine is started (start 605). Thereafter, the reception data register is copied to the transmission data register (copy the reception data register to the transmission data register 606). By copying the reception data register to the transmission data register, data can be wirelessly communicated, and the data can be transmitted to the reader / writer device. Thereafter, it is determined whether or not the data matches with the data recorded in the reader / writer device. Then, the data copy routine ends (end 607).

Such a data copy routine can determine whether the copy destination data and the copy source data match or not, and can easily perform inspection. Furthermore, it is possible to identify the wiring in which a defect has occurred from the data of the mismatched portion, and it is possible to selectively repair it.

FIG. 18 shows a flowchart of the ROM test routine. Depending on the type of command, the ROM test routine is started (start 611). Then, the data at the selected address is copied to the transmission data register (the data at the selected address is copied to the transmission data register 612). By copying the data at the selected address to the transmission data register, the data becomes wirelessly communicable and can be transmitted to the reader / writer device. Thereafter, it is determined whether or not the data matches by comparing with the address data recorded in the reader / writer device. In this way, the ROM test routine ends (end 613).

Such a ROM test routine can determine whether the copy destination data and the copy source data match or not, and can easily perform inspection. A test is performed on an arbitrary address, but it is not necessary to perform a test on all addresses. The inspection is performed by specifying the address in consideration of the probability of occurrence of the defect. Of course, all addresses may be inspected. In that case, it is possible to identify a wiring in which a defect has occurred and to selectively repair the wiring.

FIG. 19 shows a flowchart of the RAM test routine. Depending on the type of command, a RAM test routine is started (start 621). Then, the data in the reception data register is copied to an arbitrary address in the RAM (the data in the reception data register is copied to an arbitrary address in the RAM 622), and the data is read from the RAM (the data is read from the RAM 623). Next, it is determined whether the copied write data and read data match or do not match (write data and read data match determination 624). If they match (YES), the "OK" flag is written to the transmission data register ("OK" flag is written to the transmission data register 625) to indicate that the test result was good, and the RAM test routine ends ( End 627). On the other hand, if they do not match (NO), the “NG” flag is written to the transmission data register (“NG” flag is written to the transmission data register 626) to indicate that the inspection result is defective, and the process ends ( End 627).

The RAM test routine is a particularly important test because the RAM has a function of temporarily storing the calculation result of the CPU. Further, since the RAM has a smaller capacity than the ROM, the inspection is completed in a short time.

In order to perform such an inspection, data sent from the reader / writer device (R / W) to the wireless chip includes SOF 260, flag 261, command 262, data 263, CRC 264 (Cyclic Redundancy Check), and EOF 265 (FIG. 21 ( A)). The command 262 can determine which test program is executed.

In addition, data transmitted from the wireless chip to the reader / writer device (R / W) includes SOF268, data 269, and EOF270 (see FIG. 21B). The data 269 is data for determining whether the data copied to the transmission data register, that is, the data recorded in the reader / writer device matches or does not match.

In the inspection shown in the present embodiment, the determination of coincidence or mismatch between the data copied to the transmission data register and the data recorded in the reader / writer device may be performed a plurality of times. The accuracy of the inspection can be improved by performing it a plurality of times.

By adopting the above-described form, the wireless chip that supplies power supply voltage by the induced electromotive force from the communication signal and transmits / receives communication data can perform the wireless chip inspection in a short time when the operation inspection of the RF chip component is performed. It becomes possible. Therefore, the inspection process time can be shortened, the tact time of the inspection process can be reduced, and the production time can be reduced. As a result, cost can be reduced.

In addition, the wireless chip in this embodiment includes a thin film transistor that uses a semiconductor thin film formed over a substrate having an insulating surface such as a glass substrate, a quartz substrate, or a plastic substrate as an active layer. A wireless chip with low power consumption can be provided.

(Embodiment 4)
In this embodiment, a method for manufacturing a wireless chip using a thin film transistor formed over an insulating substrate will be described.

As shown in FIG. 15A, an insulating substrate 100 is prepared. Examples of the insulating substrate 100 include a glass substrate, a quartz substrate, and a plastic substrate. These substrates can be thinned by polishing the back surface. Furthermore, it is also possible to use a conductive substrate such as a metal element or a substrate in which a layer of an insulating material is formed over a semiconductor substrate such as silicon. By forming the wireless chip on, for example, a plastic substrate, a highly flexible, lightweight, and thin device can be manufactured.

A separation layer 101 is selectively formed over the insulating substrate 100. The peeling layer 101 may be formed on the entire surface of the insulating substrate 100. The release layer 101 is formed by sputtering, plasma CVD, or the like using tungsten (W), molybdenum (Mo), titanium (Ti), tantalum (Ta), niobium (Nb), nickel (Ni), cobalt (Co), zirconium ( An element selected from Zr), zinc (Zn), ruthenium (Ru), rhodium (Rh), palladium (Pd), osmium (Os), iridium (Ir), silicon (Si), or the element as a main component A layer made of an alloy material or a compound material containing the element as a main component is formed as a single layer or a stacked layer. There is no particular limitation on the crystal structure of the layer containing silicon, and any of amorphous, microcrystalline, and polycrystalline structures may be used.

A base layer 102 is formed over the peeling layer 101. The base layer 102 can be formed as a single layer or a stacked layer using an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride. In the case of stacking, a silicon oxynitride layer with a thickness of 10 nm to 200 nm (preferably 50 nm to 100 nm) is formed as the first layer of the base layer 102. The silicon oxynitride layer can be formed by a plasma CVD method using SiH ₄ , NH ₃ , N ₂ O, and H ₂ as reaction gases. Next, a silicon oxynitride layer with a thickness of 50 nm to 200 nm (preferably 100 nm to 150 nm) is formed as the second layer of the base layer 102. The silicon oxynitride layer can be formed using SiH ₄ and N ₂ O as a reaction gas by a plasma CVD method.

A semiconductor layer 104 is formed over the base layer 102. The semiconductor layer 104 can be formed using silicon or a material including silicon and germanium. There is no particular limitation on the crystal structure of the semiconductor layer 104, and the semiconductor layer 104 may be amorphous, microcrystalline, or polycrystalline.

In order to form the semiconductor layer 104 with a polycrystalline material, heat treatment may be performed on the amorphous semiconductor layer. Examples of the heat treatment include laser irradiation, a heating furnace, lamp irradiation, and the like, and any one or more of them can be used.

For laser irradiation, a continuous wave laser beam (CW laser) or a pulsed laser beam (pulse laser) can be used. As the laser beam, Ar laser, Kr laser, excimer laser, YAG laser, Y ₂ O ₃ laser, YVO ₄ laser, YLF laser, YAlO ₃ laser, glass laser, ruby laser, alexandrite laser, Ti: sapphire laser, copper vapor Lasers oscillated from one or a plurality of gold vapor lasers can be used. By irradiating either a fundamental wave of such a laser beam or a harmonic laser beam such as the second harmonic to the fourth harmonic of the fundamental wave, a silicon layer having a crystal with a large grain size is obtained. Can do. As the harmonic, a second harmonic (532 nm) or a third harmonic (355 nm) of an Nd: YVO ₄ laser (fundamental wave 1064 nm) may be used. Energy density of laser irradiation of about 0.01 to 100 MW / cm ² (preferably 0.1 to 10 MW / cm ²⁾ is required. The scanning speed is about 10 to 2000 cm / sec.

The fundamental CW laser and the harmonic CW laser may be irradiated, or the fundamental CW laser and the harmonic pulse laser may be irradiated. By irradiating a plurality of laser beams, a wide energy range can be compensated.

Also, when using a pulse laser, use a laser that oscillates a laser with an oscillation frequency that allows the laser of the next pulse to be irradiated before the amorphous silicon layer is melted by the laser and solidifies. You can also. By oscillating the laser at such a frequency, a silicon layer having crystal grains continuously grown in the scanning direction can be obtained. The oscillation frequency of such a laser is 10 MHz or more, which is significantly higher than a frequency band of several tens to several hundreds Hz that is normally used.

In the case of using a heating furnace as the heat treatment, the semiconductor layer having an amorphous state is heated at 400 to 550 ° C. for 2 to 20 hours. At this time, the temperature may be set in multiple stages in the range of 400 to 550 ° C. so that the temperature gradually increases. In the first low-temperature heating process at about 400 ° C., hydrogen and the like contained in the semiconductor layer having an amorphous state are produced, so that the layer surface can be prevented from being roughened during crystallization.

In the heat treatment process, a metal that promotes crystallization of the semiconductor layer, for example, nickel (Ni) is added. A heat treatment can be performed by applying a solution containing nickel (Ni) over a silicon layer having an amorphous state. By performing the heat treatment using the metal in this manner, the heating temperature can be reduced, and furthermore, a polycrystalline silicon layer having continuous crystal grain boundaries can be obtained. Here, as a metal for promoting crystallization, in addition to nickel (Ni), iron (Fe), ruthenium (Ru), rhodium (Rh), palladium (Pd), osmium (Os), iridium (Ir), Platinum (Pt), copper (Cu), silver (Au), or the like can also be used.

Since the metal that promotes crystallization serves as a contamination source for memory cells and the like, it is desirable to perform a gettering step for removing the metal after the semiconductor layer is crystallized. In the gettering step, after the semiconductor layer is crystallized, a layer to be a gettering sink is formed on the semiconductor layer, and the metal is moved to the gettering sink by heating. As the gettering sink, a polycrystalline semiconductor layer or a semiconductor layer to which an impurity is added can be used. For example, a polycrystalline semiconductor layer to which an inert element such as argon is added can be formed on the polycrystalline silicon layer, and this can be used as a gettering sink. By adding an inert element to the gettering sink, distortion can be generated and the metal can be captured more efficiently. In addition, a metal can be captured by adding an element such as phosphorus to a part of the semiconductor layer of the TFT without forming a new gettering sink.

The semiconductor layer 104 formed in this manner is processed into a predetermined shape, and the island-shaped semiconductor layer 104 is formed. For the processing, etching is performed using a mask formed by a photolithography method. A wet etching method or a dry etching method can be applied to the etching.

An insulating layer functioning as the gate insulating layer 105 is formed so as to cover the semiconductor layer 104. The gate insulating layer 105 can be formed using a material and a method similar to those of the base layer 102.

As shown in FIG. 15B, a conductive layer functioning as the gate electrode layer 106 is formed with the gate insulating layer 105 interposed therebetween. As the gate electrode layer 106, a film formed of an element of aluminum (Al), titanium (Ti), molybdenum (Mo), tantalum (Ta), tungsten (W), or silicon (Si) or an alloy film including these elements is used. Can do. The gate electrode layer 106 can be a single layer or a stacked layer. In the case of stacking, for example, a stacked structure in which tungsten is formed over tantalum nitride may be used. For the processing of the gate electrode layer 106, etching is performed using a mask formed by a photolithography method. A wet etching method or a dry etching method can be applied to the etching.

Sidewalls 107 functioning as insulating layers are formed on side surfaces of the gate electrode layer 106. The sidewall 107 can be formed using the same material and the same method as the base layer 102. In order to have a tapered shape at the end of the sidewall 107, isotropic etching may be performed. Since the short channel effect is particularly noticeable in the N-channel TFT, the short-channel effect is preferably provided at least on the side of the gate electrode of the N-channel TFT.

In such a state, the gate insulating layer 105 is etched. As a result, a part of the semiconductor layer 104 and the base layer 102 are exposed. A wet etching method or a dry etching method can be applied to the etching.

In the state where the gate electrode layer 106 and the sidewall 107 exist, an impurity element is added to the semiconductor layer 104 to form a high concentration impurity region 110 and a high concentration impurity region 112. In the case of forming an N-channel TFT, phosphorus can be used as the impurity element, and in the case of forming a P-channel TFT, boron can be used as the impurity element. At this time, it is preferable to adjust the addition amount of the impurity element and form a low-concentration impurity region below the sidewall 107. In this embodiment mode, the low concentration impurity region 111 is formed only in the impurity region of the N-channel TFT. The short channel effect can be prevented by the low concentration impurity region 111. A TFT structure having such a low concentration impurity region is called an LDD (Lightly Doped Drain) structure.

After that, an insulating layer 114 is formed so as to cover the base layer 102, the semiconductor layer 104, the gate electrode layer 106, and the sidewall 107. The insulating layer 114 is preferably formed using silicon oxide, silicon nitride, or the like by a CVD method.

After the insulating layer 114 is formed, heat treatment is performed as necessary. The heat treatment can be performed in the same manner as the above crystallization. By this heat treatment, the impurity region is activated. Since the insulating layer 114 formed by a CVD method contains a large amount of hydrogen, hydrogen can be diffused by the above heat treatment, and roughness formed in the film in the impurity region can be reduced.

As shown in FIG. 15C, an insulating layer 115 and an insulating layer 116 which function as interlayer films are formed. For the insulating layer 115 and the insulating layer 116, an inorganic material or an organic material can be used. As the inorganic material, silicon oxide, silicon nitride, silicon oxynitride, or the like can be used. As the organic material, polyimide, acrylic, polyamide, polyimide amide, benzocyclobutene, siloxane, or polysilazane can be used. Note that siloxane has a skeleton structure of a bond of silicon (Si) and oxygen (O). As a substituent, an organic group containing at least hydrogen (for example, an alkyl group or an aromatic hydrocarbon) is used. A fluoro group may be used as a substituent. Alternatively, an organic group containing at least hydrogen and a fluoro group may be used as a substituent. Polysilazane is formed using a polymer material having a bond of silicon (Si) and nitrogen (N) as a starting material. In general, when an inorganic material is used, entry of an impurity element can be prevented, and when an organic material is used, flatness can be improved. Therefore, in this embodiment, an inorganic material is used for the insulating layer 115 and an organic material is used for the insulating layer 116.

Next, the insulating layer 114, the insulating layer 115, and the insulating layer 116 are opened by etching, so that a contact hole is formed and a wiring 118 is formed. As the wiring 118, a film made of an element of aluminum (Al), titanium (Ti), molybdenum (Mo), tantalum (Ta), tungsten (W), or silicon (Si) or an alloy film containing these elements is used. it can. The wiring 118 can be a single layer or a stacked layer. For example, tungsten or tungsten nitride is used for the first layer, and an alloy of aluminum and silicon (Al-Si) or an alloy of aluminum and titanium (Al--) is used for the second layer. Ti) and a structure in which a titanium nitride film, a titanium film, and the like are sequentially stacked on the third layer can be applied. As a method for processing the wiring 118, there is an etching method using a mask formed by a photolithography method. As the etching method, a wet etching method or a dry etching method can be applied. The wiring 118 is connected to the high concentration impurity region 110 and the high concentration impurity region 112 of the semiconductor layer 104.

In this manner, the N-channel TFT 130 and the P-channel TFT 131 can be formed.

Thereafter, a protective layer 119 is formed over the wiring 118 as necessary. The protective layer 119 can be formed of silicon oxide, silicon nitride, or the like. For example, the protective layer 119 is formed using silicon nitride. As a result, the TFT is protected.

Here, as shown in FIG. 15D, an opening is formed at a desired position in a region where the TFT is not formed, and an etching agent 125 is introduced into the opening. The opening can be formed using a wet etching method or a dry etching method. As the etchant 125, an appropriate one is selected depending on the material of the peeling layer, that is, the layer to be etched. For example, in the case of the wet etching method, a mixture of hydrofluoric acid diluted with water or ammonium fluoride, a mixture of hydrofluoric acid and nitric acid, a mixture of hydrofluoric acid, nitric acid and acetic acid, a mixture of hydrogen peroxide and sulfuric acid, hydrogen peroxide and A mixture of ammonium water and water, a mixture of hydrogen peroxide, hydrochloric acid, and water can be used. In the case of a dry etching method, a gas containing a halogen atom or molecule such as fluorine or a gas containing oxygen is used. Preferably, a gas or liquid containing halogen fluoride or an interhalogen compound, for example, chlorine trifluoride (ClF ₃ ) is used as an etchant.

The peeling layer 101 is removed by introducing the etching agent 125. Then, the insulating substrate 100 is peeled off. In this manner, a thin and lightweight wireless chip can be manufactured.

In addition to the above method, an etching agent may be introduced by exposing the release layer 101 by a method such as laser drawing or cutting a side surface of a wireless chip. Alternatively, the insulating substrate 100 may be physically peeled off without using an etchant.

As shown in FIG. 15E, the wireless chip is completed by covering the peeled TFT with a film 127 or a film 128. At this time, the adhesive layer 129 may be used to bond the film 127 or the film 128 to each other. A protective layer may be formed on the films 127 and 128 in order to prevent entry of moisture, oxygen, and the like. Further, since the protective layer 119 is formed over the wiring 118, a protective film may be formed below the base layer 102 or the adhesive layer 129. The protective film can be formed of silicon oxide, silicon nitride, or the like.

A wireless chip formed over an insulating substrate in this manner and having the insulating substrate peeled off can be provided at a lower weight and at a lower cost. Further, since such a wireless chip has high flexibility, it can be attached to a curved surface and can be mounted on various objects.

(Embodiment 5)
In this embodiment, as an example of a semiconductor device in the present invention, a wireless chip having a cryptographic processing function will be described with reference to FIGS. 24 is a block diagram of the wireless chip, FIG. 25 is a layout diagram of the wireless chip, and FIG. 26 is a cross-sectional view of a part of the wireless chip.

First, the block configuration of the wireless chip will be described with reference to FIG. In FIG. 24, a wireless chip 2601 includes a CPU 2602, a ROM 2603, a RAM 2604, an arithmetic circuit 2606 that includes a controller 2605, an antenna 2607, a resonance circuit 2608, a power supply circuit 2609, a reset circuit 2610, a clock generation circuit 2611, a demodulation circuit 2612, and a modulation. The analog unit 2615 includes a circuit 2613 and a power management circuit 2614. The controller 2605 includes a CPU IF 2616 which is a CPU interface, a control register 2617, a code extraction circuit 2618, and an encoding circuit 2619. In FIG. 24, for simplification of description, the communication signal is divided into a reception signal (ciphertext) 2620 and a transmission signal (plaintext) 2621. However, in actuality, both are superimposed, and the wireless chip 2601 Data are simultaneously transmitted and received between the reader / writer devices. Received signal (ciphertext) 2620 is received by antenna 2607 and demodulated by demodulation circuit 2612. A transmission signal (plain text) 2621 is modulated by the modulation circuit 2613 and then transmitted from the antenna 2607. Here, plaintext refers to a signal that does not include ciphertext.

In FIG. 24, when the wireless chip 2601 is placed in a magnetic field formed by a communication signal, an induced electromotive force is generated by the antenna 2607 and the resonance circuit 2608. The induced electromotive force is held by an electric capacity in the power supply circuit 2609, and the electric potential is stabilized by the electric capacity, and is supplied as a power supply voltage to each circuit of the wireless chip 2601. The reset circuit 2610 generates a reset signal that initializes the entire wireless chip 2601. For example, a signal that rises after a rise in the power supply voltage is generated as a reset signal. The clock generation circuit 2611 changes the frequency and duty ratio of the clock signal in accordance with the control signal generated by the power management circuit 2614. The demodulation circuit 2612 detects the fluctuation of the amplitude of the ASK received signal (ciphertext) 2620 as “0” or “1” received data 2622. The demodulation circuit 2612 is a low-pass filter, for example. The modulation circuit 2613 transmits transmission data by changing the amplitude of an ASK transmission signal (plain text) 2621. For example, when the transmission data 2623 is “0”, the resonance point of the resonance circuit 2608 is changed, and the amplitude of the communication signal is changed. The power management circuit 2614 monitors the power supply voltage supplied from the power supply circuit 2609 to the arithmetic circuit 2606 or the current consumption in the arithmetic circuit 2606, and the clock generation circuit 2611 outputs a control signal for changing the frequency and duty ratio of the clock signal. Generate.

An operation of the wireless chip in this embodiment is described. First, the wireless chip 2601 receives a reception signal (ciphertext) 2620 including ciphertext data transmitted from the reader / writer. Received signal (ciphertext) 2620 is demodulated by demodulation circuit 2612, decomposed into a control command, ciphertext data, and the like by code extraction circuit 2618 and stored in control register 2617. Here, the control command is data specifying a response of the wireless chip 2601. For example, transmission of a unique ID number, operation stop, decryption, etc. are designated. Here, it is assumed that a decryption control command is received.

Subsequently, in the arithmetic circuit 2606, the CPU 2602 decrypts (decrypts) the ciphertext using the secret key 2624 stored in advance in the ROM 2603 according to the decryption program stored in the ROM 2603. The decrypted ciphertext (decrypted text) is stored in the control register 2617. At this time, the RAM 2604 is used as a data storage area. Note that the CPU 2602 accesses the ROM 2603, the RAM 2604, and the control register 2617 via the CPUIF 2616. The CPU IF 2616 has a function of generating an access signal for any of the ROM 2603, the RAM 2604, and the control register 2617 from an address requested by the CPU 2602.

Finally, in the encoding circuit 2619, transmission data 2623 is generated from the decoded text, modulated by the modulation circuit 2613, and a transmission signal (plain text) 2621 is transmitted from the antenna 2607 to the reader / writer.

In the present embodiment, as a calculation method, a method of processing in software, that is, a method of configuring a calculation circuit with a CPU and a large-scale memory and executing a program with the CPU has been described. It is also possible to select an optimal calculation method and configure based on the method. For example, as a calculation method, a method for processing the operation in hardware and a method using both hardware and software can be considered. In the method of processing in hardware, an arithmetic circuit may be configured with a dedicated circuit. In the method using both hardware and software, a dedicated circuit, a CPU, and a memory constitute an arithmetic circuit, a part of the arithmetic processing is performed by the dedicated circuit, and the remaining arithmetic processing program is executed by the CPU.

Next, the layout of the wireless chip is described with reference to FIG. In FIG. 25, parts corresponding to those in FIG. 24 are denoted by the same reference numerals and description thereof is omitted.

In FIG. 25, an FPC pad 2707 is an electrode pad group used when an FPC (Flexible Print Circuit) is attached to the wireless chip 2601, and an antenna bump 2708 is an electrode pad for attaching an antenna. Note that when the antenna is attached, excessive pressure may be applied to the antenna bump 2708. Therefore, it is desirable not to dispose a component such as a transistor under the antenna bump 2708.

The FPC pad 2707 is effective when used mainly for failure analysis. Since the wireless chip obtains the power supply voltage from the communication signal, for example, when a defect occurs in the antenna or the power supply circuit, the arithmetic circuit does not operate at all. For this reason, when there is a defect in the antenna or the power supply circuit, the defect analysis becomes extremely difficult. However, the arithmetic circuit can be operated by supplying a power supply voltage from the FPC to the wireless chip 2601 through the FPC pad 2707 and inputting an arbitrary electric signal instead of the electric signal supplied from the antenna. It becomes possible. Accordingly, failure analysis can be performed even when there is a failure in the antenna or the power supply circuit.

Further, it is more effective to arrange the FPC pad 2707 so that measurement using a prober is possible. That is, in the FPC pad 2707, by arranging the electrode pads in accordance with the pitch of the prober needle, measurement by the prober becomes possible. By using a prober, it is possible to reduce the number of steps for attaching the FPC during failure analysis. Further, since measurement can be performed even when a plurality of wireless chips are formed on a substrate, the number of steps for dividing each wireless chip can be reduced. In addition, it is possible to perform a non-defective inspection of the wireless chip immediately before the step of attaching the antenna during mass production. Accordingly, defective products can be selected at an early stage of the process, so that production costs can be reduced.

A cross-sectional view of such a wireless chip is shown in FIG. First, wiring 1804 corresponding to the wiring 118 illustrated in FIG. 15 is formed. An insulating layer 1853 is formed so as to cover the wiring 1804. The insulating layer 1853 can be formed using an inorganic material or an organic material. As the inorganic material, silicon oxide, silicon nitride, or the like can be used. As the organic material, polyimide, acrylic, polyamide, polyimide amide, benzocyclobutene, siloxane, or polysilazane can be used. Note that siloxane has a skeleton structure of a bond of silicon (Si) and oxygen (O). As a substituent, an organic group containing at least hydrogen (for example, an alkyl group or an aromatic hydrocarbon) is used. A fluoro group may be used as a substituent. Alternatively, an organic group containing at least hydrogen and a fluoro group may be used as a substituent. Polysilazane is formed using a polymer material having a bond of silicon (Si) and nitrogen (N) as a starting material.

In the connection region 1850, an opening is formed in the insulating layer 1853 so that the wiring 1851 formed at the same time as the wiring 1804 is exposed. In the opening, the upper end corner is rounded and the side is tapered. This is because it is possible to prevent disconnection of the pattern formed thereafter.

A connection wiring 1852 is formed in the opening. The connection wiring 1852 can be formed of a film made of an element such as aluminum (Al), titanium (Ti), molybdenum (Mo), tungsten (W), or silicon (Si), or an alloy film using these elements. Alternatively, a light-transmitting material such as indium tin oxide (ITO), indium tin oxide containing silicon oxide (ITSO), or indium oxide containing 2% to 20% zinc oxide can be used. At this time, the connection wiring 1852 is arranged so as not to overlap with the N-channel TFT 1821, the N-channel TFT 1822, the capacitor 1824, the resistor 1825, the P-channel TFT 1823, and the like. This is to prevent the occurrence of unintended parasitic capacitance.

An insulating layer 1854 is formed so as to cover the insulating layer 1853 and the connection wiring 1852. The insulating layer 1854 can be formed in a manner similar to that of the insulating layer 1853.

An opening is formed in the insulating layer 1854 so that the connection wiring 1852 provided over the insulating layer 1853 is exposed. An anisotropic conductor 1856 having conductive fine particles 1855 is provided in the opening, and an FPC 1858 having a conductive layer 1857 is connected.

In this manner, the wireless chip of the present invention can be manufactured.

(Embodiment 6)
The antenna may be any size or shape that meets the purpose within the range stipulated by the Radio Law. Signals to be transmitted / received include 125 kHz, 13.56 MHz, 915 MHz, 2.45 GHz, and the like, and each is standardized by the ISO standard or the like. As a type of antenna, a dipole antenna, a patch antenna, a loop antenna, a Yagi antenna, or the like may be used. In this embodiment, the shape of an antenna connected to a wireless chip is described.

FIG. 27A illustrates an antenna 1602 connected to the wireless chip 1601. In FIG. 27A, the wireless chip 1601 is provided in the center, and the antenna 1602 is connected to a connection terminal of the wireless chip 1601. In order to secure the length of the antenna, the antenna 1602 is bent at a plurality of locations.

In FIG. 27B, the wireless chip 1601 is provided on one end side, and the antenna 1603 is connected to a connection terminal of the wireless chip 1601. In order to secure the length of the antenna, the antenna 1603 is bent at a plurality of locations.

In FIG. 27C, an antenna 1604 having a plurality of bent portions is provided at both ends of the wireless chip 1601.

In FIG. 27D, linear antennas 1605 are provided at both ends of the wireless chip 1601.

As described above, the antenna shape may be selected so as to suit the structure, polarization, or application of the wireless chip. Therefore, a folded dipole antenna may be used as long as it is a dipole antenna. As long as it is a loop antenna, it may be a circular loop antenna or a square loop antenna. If it is a patch antenna, a circular patch antenna or a rectangular patch antenna may be used.

In the case of a patch antenna, an antenna using a dielectric material such as ceramic may be used. The antenna can be reduced in size by increasing the dielectric constant of the dielectric material used as the patch antenna substrate. In the case of a patch antenna, the mechanical strength is high, so that it can be used repeatedly.

The dielectric material of the patch antenna can be formed of ceramic, organic resin, a mixture of ceramic and organic resin, or the like. Representative examples of ceramics include alumina, glass, forsterite and the like. Furthermore, a plurality of ceramics may be mixed and used. In order to obtain a high dielectric constant, the dielectric layer is preferably formed of a ferroelectric material. Representative examples of the ferroelectric material include barium titanate (BaTiO ₃ ), lead titanate (PbTiO ₃ ), strontium titanate (SrTiO ₃ ), lead zirconate (PbZrO ₃ ), lithium diobate (LiNbO ₃ ). And lead zirconate titanate (PZT). Further, a plurality of ferroelectric materials may be mixed and used.

The structure described in the other embodiments and the above embodiment can be applied to the wireless chip 1601.

In this example, a test was performed using the method described in Embodiment 5, and measurement was performed with a spectrum analyzer. It was confirmed that a response signal was output to an RF signal having a frequency of 13.56 MHz input to the wireless chip.

FIG. 28 shows the measurement result of the transmission / reception signal waveform of the wireless chip measured by the spectrum analyzer. The gain vs. frequency measurement result shown in FIG. 28B shows the frequency characteristics of the gain of the wireless chip. The frequency is shown on the horizontal axis and the gain is shown on the vertical axis. A peak 2803 exists at a frequency of 13.56 MHz, indicating that the wireless chip has high sensitivity at 13.56 MHz. FIG. 28A shows the gain vs. time measurement result shown in FIG. 28A, and shows the time variation of the gain of the wireless chip at the frequency of 13.56 MHz. Time is plotted on the horizontal axis and gain is plotted on the vertical axis. A waveform in an area 2801 is a transmission signal from the reader / writer to the wireless chip, and is a reception signal (ciphertext) 2620 including ciphertext data.
A waveform in the region 2802 is a response signal from the wireless chip to the reader / writer, and is a transmission signal (plain text) 2621. The gain vs. time measurement result shown in FIG. 28C is an enlarged view of the area 2802 and shows details of the response signal from the wireless chip to the reader / writer.

According to the measurement result of this example, it is effective to perform a test using the method described in the fifth embodiment.

It is the block diagram which showed the semiconductor device of this invention It is the flowchart which showed the inspection method of this invention It is the flowchart which showed the inspection method of this invention It is the figure which showed the inspection apparatus of this invention It is an example of a display of the inspection result of the present invention. It is the figure which showed the inspection apparatus of this invention It is the figure which showed the test object of this invention It is the figure which showed the test object of this invention It is the block diagram which showed the semiconductor device of this invention It is the figure which showed the operation | movement of the liquid crystal element applied to this invention. It is the figure which showed the operation | movement of the liquid crystal element applied to this invention. It is sectional drawing which showed the liquid crystal element applied to this invention. It is the flowchart which showed the inspection method of this invention It is the figure which showed the inspection apparatus and inspection object of this invention It is the figure which showed the manufacturing process of the semiconductor layer of this invention It is the flowchart which showed the inspection method of this invention It is the flowchart which showed the inspection method of this invention It is the flowchart which showed the inspection method of this invention It is the flowchart which showed the inspection method of this invention This is an address space of the semiconductor device of the present invention. It is a data form of the test program of the present invention It is the block diagram which showed the inspection apparatus of this invention It is the flowchart which showed the inspection method of this invention It is the block diagram which showed the semiconductor device of this invention It is the block diagram which showed the semiconductor device of this invention It is sectional drawing of the semiconductor device of this invention It is the figure which showed the shape of the antenna which the semiconductor device of this invention has It is the figure which showed the result of having measured using this invention

Explanation of symbols

50 Laser light source 51 Light receiver 53 Insulating substrate 54 Wireless chip 56 Liquid crystal 57 Spacer 58 Cut region 100 Insulating substrate 101 Peeling layer 102 Underlayer 104 Semiconductor layer 105 Gate insulating layer 106 Gate electrode layer 107 Side wall 110 High concentration impurity region 111 Low-concentration impurity region 112 High-concentration impurity region 114 Insulating layer 115 Insulating layer 116 Insulating layer 118 Wiring 119 Protective layer 125 Etching agent 127 Film 128 Film 129 Adhesive layer 130 N-channel TFT
131 P-channel TFT
201 wireless chip 202 arithmetic circuit 203 state control register 204 reception circuit 205 transmission circuit 206 antenna 207 resonance circuit 208 power supply circuit 209 reset circuit 210 clock circuit 211 demodulation circuit 212 modulation circuit 213 reception signal 214 transmission signal 215 system reset signal 216 system clock signal 217 enable signal 218 enable signal 219 enable signal 221 data storage unit 222 liquid crystal drive unit 250 ROM
251 RAM
252 Control register 253 Reception data register 254 Transmission data register 260 SOF
261 Flag 262 Command 263 Data 264 CRC
265 EOF
268 SOF
269 Data 270 EOF
271 Communication signal reception 272 Status control register setting 273 Test program execution 274 Status control register setting 275 Communication signal transmission 276 Status control register setting 301 Insulating substrate 303 TFT
304 pixel electrode 305 alignment film 307 start 308 test program read 309 test routine execution 310 test result determination 311 test result write 312 end 313 liquid crystal driver voltage application 314 counter substrate 315 alignment film 317 liquid crystal molecule 318 counter electrode 319 spacer 320 sealant 330 Transmitted light 401 Prober controller 402 Cable 403 Wireless prober 404 Board 405 Stage 406 Antenna 411 Prober controller 412 Cable 413 Wireless prober 414 Board 415 Stage 416 Prober 417 Electrode pad 419 Antenna 420 Board 501 Start 502 Command code determination 503 End 504 Data copy Routine 505 ROM test routine 506 RAM test routine 600 Host computer 601 Data transmission unit 602 Data reception unit 603 Stage control unit 605 Start 606 Copy reception data register to transmission data register 607 End 611 Start 612 Copy data at selected address to transmission data register 613 End 621 Start 622 Data in reception data register Copy to any address in RAM 623 Read data from RAM 624 Write data and read data match determination 625 Write “OK” flag to transmit data register 626 Write “NG” flag to transmit data register 627 End 630 Start 631 Stage 632 to transmit the test data to the data transmission unit 633 to receive the data collected from the data reception unit 634 test result determination 635 retest determination 636 stage coordinate data And “OK” are recorded 637 Stage coordinate data and “NG” are recorded 638 End 1001 First polarizing plate 1002 Liquid crystal molecules 1003 Second polarizing plate 1004 First substrate 1005 Second substrate 1011 First Polarizer 1012 Liquid crystal molecules 1013 Second polarizer 1014 First substrate 1015 Second substrate 1601 Wireless chip 1602 Antenna 1603 Antenna 1604 Antenna 1605 Antenna 1804 Wiring 1821 N-channel TFT
1822 N-channel TFT
1823 P-channel TFT
1824 Capacitance element 1825 Resistance element 1850 Connection region 1851 Wire 1852 Connection wire 1853 Insulating layer 1854 Insulating layer 1855 Conductive fine particle 1856 Anisotropic conductor 1857 Conductive layer 1858 FPC
2601 Wireless chip 2602 CPU
2603 ROM
2604 RAM
2605 Controller 2606 Arithmetic circuit 2607 Antenna 2608 Resonance circuit 2609 Power supply circuit 2610 Reset circuit 2611 Clock generation circuit 2612 Demodulation circuit 2613 Modulation circuit 2614 Power management circuit 2615 Analog unit 2616 CPUIF
2617 Control register 2618 Code extraction circuit 2619 Encoding circuit 2620 Received signal (ciphertext)
2621 Transmission signal (plain text)
2622 Reception data 2623 Transmission data 2624 Private key 2707 FPC pad 2708 Antenna bump 2801 Area 2802 Area 2803 Peak

Claims (10)

Having a data storage and antenna,
The data storage unit includes a thin film transistor,
The semiconductor device according to claim 1, wherein a test program received via an antenna by wireless communication is recorded in the data storage unit. A data storage unit, a receiving circuit, a state control register, and an RF circuit;
The data storage unit, the receiving circuit, the state control register, and the RF circuit each have a thin film transistor,
In the data storage unit, a test program received via the RF circuit by wireless communication is recorded,
The semiconductor device according to claim 1, wherein the state control register is in a test program execution state. In claim 1 or 2,
The data storage unit includes a read-only memory and a random access memory. In claim 3,
2. A semiconductor device according to claim 1, wherein the test program data includes a test routine for performing an operation test of the read-only memory and the random access memory. In any one of Claims 2 thru | or 4,
An arithmetic circuit and a transmission circuit;
The arithmetic circuit is
Starting the test program after the status control register is in a test program execution state;
After the test program is finished, the state control register is set to the transmission processing state,
The transmission circuit processes the transmission data so as to conform to the format of the communication signal, and then outputs it to the modulation circuit.
A semiconductor device having a function of setting the state control register to a reception processing state. A method for inspecting a semiconductor device having an arithmetic circuit, a data storage unit, a state control register, and an RF circuit,
The arithmetic circuit starts operation according to the state of the state control register,
The arithmetic circuit reads a test program recorded in the data storage unit, executes a test routine in the test program,
The arithmetic circuit determines an execution result of the test routine and writes the execution result to the data storage unit.
A test method for a semiconductor device, wherein the test program is received as a communication signal via the RF circuit. A method for inspecting a semiconductor device having an arithmetic circuit, a data storage unit, a state control register, and an RF circuit,
Starting the test program after the status control register is in a test program execution state;
The arithmetic circuit reads a test program recorded in the data storage unit, executes a test routine in the test program,
The arithmetic circuit determines an execution result of the test routine and writes the execution result to the data storage unit.
After the test program is finished, the state control register is set to the transmission processing state,
After sending is complete,
A function for setting the state control register to a reception processing state;
A test method for a semiconductor device, wherein the test program is received as a communication signal via the RF circuit. An inspection method for a wireless chip having an arithmetic circuit, a state control register, a data storage unit and an RF circuit,
The wireless chip has a liquid crystal element,
The test program is received as a communication signal via the RF circuit, recorded in the data storage unit,
An inspection method for a wireless chip, comprising: performing an inspection by the test program; and displaying whether the result of the inspection is acceptable by the liquid crystal element. An inspection method for a wireless chip having an arithmetic circuit, a state control register, a data storage unit and an RF circuit,
The wireless chip has a liquid crystal element,
The wireless chip is disposed between the laser light source and the light receiver,
The test program is received as a communication signal via the RF circuit and recorded in the data storage unit.
A method for inspecting a wireless chip, comprising: determining whether or not a result of the inspection is acceptable by checking whether or not light from the laser light source is input to the light receiver after performing inspection according to the test program. In claim 8 or 9,
The method for inspecting a wireless chip, wherein the liquid crystal element includes liquid crystal molecules held between substrates provided with polarizing plates.

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