JP2007053316A - Esd protection element - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an ESD protection element which is optimal for an Fin FET. <P>SOLUTION: The ESD protection element has a semiconductor substrate, an insulating layer formed on the semiconductor substrate, a plate-like semiconductor layer provided vertically to one region on the insulating layer, a first gate electrode formed to cross and hold the plate-like semiconductor layer therebetween via the first gate insulating film, and a second gate electrode formed on the first gate electrode via a second gate insulating film. The plate-like semiconductor layer comprises a channel region in face to face with the first gate electrode via the first gate insulating film, and a pair of source/drain electrodes formed in both sides of the channel region. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device, and more particularly to an ESD protection element that protects the inside of an LSI from a surge current or the like.

  Field effect transistors in semiconductor integrated circuits have been scaled as their performance has increased, but in recent years, the thickness of the gate insulating film has been reduced to nearly 1 nm in terms of silicon dioxide. Absent. When the gate insulating film is thinned, the electrical breakdown voltage is significantly reduced depending on the film thickness. In a semiconductor device having such a thin gate insulating film, when static electricity of a machine or a human enters into an electronic circuit during manufacturing or use, the gate insulating film may be damaged due to a high voltage applied. . Such a phenomenon is called ESD (Electro-Static Discharge) destruction.

  Therefore, many semiconductor devices have a semiconductor device and a circuit called an ESD protection element for preventing a surge current from entering from the outside, and the gate insulating film is prevented from being destroyed by ESD.

  On the other hand, with the improvement in performance of semiconductor devices, research to achieve higher performance than before has been advanced by changing the structure of field effect transistors, and three-dimensional transistors are also expected as basic semiconductor elements in the future. Has been. Among them, one of the most promising at present is a transistor having a Fin-type (plate-like) active region called FinFET (see, for example, Patent Document 1).

In the case of an LSI composed of FinFETs, it is practically simple to construct an ESD protection element also using FinFETs. However, FinFET has a structural limit in the thickness of a gate insulating film that can be used, and a surge is input to the gate. When the type of ESD protection element is composed of FinFET, there is a problem that the breakdown voltage is lowered.
JP 2003-243667 A

  Thus, conventionally, it is effective to use a FinFET to realize a high-performance LSI, but there is a problem that it is difficult to realize an ESD protection element of a type in which a surge enters the gate in the FinFET.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide an ESD protection element that can be manufactured in an LSI constituted by FinFETs.

  In order to solve the above problems, a first ESD protection element according to the present invention includes a semiconductor substrate, an insulating layer formed on the semiconductor substrate, and a plate-like shape provided perpendicular to one region on the insulating layer. A semiconductor layer; a first gate electrode formed so as to straddle and sandwich the plate-like semiconductor layer via a first gate insulating film in a central portion of the plate-like semiconductor layer; And a second gate electrode formed on the gate electrode via a second gate insulating film, and the plate-like semiconductor layer is formed on the first gate electrode via the first gate insulating film. And a pair of source / drain electrodes formed on both sides of the channel region.

  The second ESD protection element of the present invention includes a semiconductor substrate, an insulating layer formed on the semiconductor substrate, a plate-like semiconductor layer provided vertically on the insulating layer, and the plate-like semiconductor layer. A first gate electrode formed so as to straddle and sandwich the plate-like semiconductor layer via a first gate insulating film, a lead pad for the first gate electrode, and the lead And a second gate electrode formed on the pad via a second gate insulating film, and the plate-like semiconductor layer is connected to the first gate electrode via the first gate insulating film. It is characterized by comprising a channel region facing each other and a pair of source / drain electrodes formed on both sides of the channel region.

  According to the present invention, since the second gate electrode is formed via the second gate insulating film by being connected to the original (first) gate of the FinFET, the ESD protection element is provided. The overall breakdown voltage of the gate insulating film can be dramatically increased while minimizing the decrease. This is extremely useful as an ESD protection element incorporated in an LSI composed of FinFETs.

  The details of the present invention will be described below with reference to the illustrated embodiments.

(First embodiment)
FIG. 1 is a schematic perspective view showing an element structure of an ESD protection element 100 according to the first embodiment of the present invention, FIG. 2 is an equivalent circuit diagram and an application circuit of the ESD protection element 100, and FIG. 3 is a top view, FIG. 3B is a cross-sectional view taken along line BB in FIG. 3A, and FIG. 3C is a front view. In the figure, the ESD protection element 100 is depicted as being formed on a rectangular semiconductor substrate 110. However, the semiconductor substrate 110 is a region of a semiconductor chip (not shown), and the ESD protection element can be incorporated into the semiconductor chip. Note that it is.

  More specifically, a buried insulating film 111 made of a silicon oxide film or the like and a Fin type (plate-like) semiconductor layer 112 are formed on the silicon substrate 110. A central portion of the semiconductor layer 112 is a channel region 112c, and a first gate electrode 114 is formed on the channel region 112c with a first gate insulating film 113 interposed between and sandwiching the first gate electrode 114. Further, source / drain regions (electrodes) 115 are formed with the channel region 112c sandwiched from the channel length direction. Further, a second gate insulating film 116 is formed in contact with the gate electrode 114, and a second gate electrode 117 is formed on the second gate insulating film 116.

  In this embodiment, when a voltage is applied to the second gate electrode 117, a voltage is also applied to the first gate electrode 114 that is capacitively coupled thereto, and the channel is turned on. By providing the second gate electrode 117 and the second gate insulating film 116, even when a high voltage is applied to the gate, the first gate insulating film is not destroyed. That is, it is possible to dramatically improve the dielectric breakdown voltage without significantly impairing the feature of the FinFET having a high driving current.

  The ESD protection element of the present embodiment can be used in, for example, an ESD protection circuit as shown in FIG. That is, one of the source / drain electrodes and the gate electrode of the ESD protection element are short-circuited, connected to the connection between the input / output pad 118 and the internal circuit 119, and the other of the source / drain electrodes is grounded. With this connection, when a surge current flows into the input / output electrode pad 118, the ESD protection element (transistor) 100 according to the present embodiment is turned on to prevent the surge current from flowing into the internal circuit 119. . Since nothing happens when a voltage lower than the threshold value is input to the pad 118 instead of a surge, a normal signal can be exchanged with the internal circuit 119.

  Desirable requirements for these structures are as follows. The first gate insulating film should be as thin as possible in order to secure driving force, and specifically, it should be about 2 nm or less. On the contrary, the second gate insulating film is preferably as thick as possible in order to ensure a withstand voltage, and specifically, it is desirable that the thickness be 4 nm or more.

  Further, if the first gate insulating film is formed of, for example, a normal silicon oxide film and the second gate insulating film is formed of a high dielectric constant (high-K) insulating film, the withstand voltage is increased and the drive current is increased. Can be bigger.

  Next, a method for manufacturing the ESD protection element of the first embodiment will be described. 4 to 7 are cross-sectional views showing the manufacturing process of the semiconductor device (ESD protection element) according to this embodiment step by step. Although an example of an n-type channel device is shown here, a p-type channel device can be manufactured in the same manner.

  First, as shown in FIGS. 4A, 4 </ b> B, and 4 </ b> C, an SOI substrate in which an insulating film 111 is formed on a support substrate 110 and an SOI layer is formed on the insulating film 111 is prepared. On this SOI substrate, silicon nitride is deposited as a channel protective film to a thickness of about 100 nm by a method such as LPCVD (Low Pressure Chemical Vapor Deposition), and element isolation is performed by a known element isolation technique. Further, the SOI layer 126 is patterned by an existing patterning technique to form a Fin (plate-like semiconductor layer 112) in which the channel 112c is formed. The width of Fin is, for example, 10 nm. In the drawing, a plurality of Fins are formed. However, the number of Fins is not essential and may be one.

  Next, as shown in FIGS. 5A, 5B, and 5C, as the first gate insulating film 113, silicon dioxide of about 1 nm is formed by RTO (Rapid Thermal Oxidation) or the like, and then plasma nitridation is performed. To increase the dielectric constant. Further, a polysilicon film to be the first gate electrode 114 is deposited by about 100 nm by LPCVD or the like, and embedded so as to straddle and sandwich the plate-like semiconductor layer 112. Further, a second gate insulating film 116 of about 5 nm and a second gate electrode 117 of about 100 nm are deposited thereon by LDCVD.

  Thereafter, a hard mask layer (not shown) made of a silicon nitride film is deposited, and the hard mask layer is patterned using a photolithography technique or the like, and then polysilicon is formed by RIE or the like using the patterned hard mask layer as a mask. When the layer is patterned, a first gate electrode 114, a second gate insulating film 116, and a second gate electrode 117 are formed (see FIGS. 5A, 5B, and 5C). Here, an offset spacer or the like may be further formed, but it is not shown. 5A is a plan view, FIG. 5B is a cross-sectional view taken along line BB in FIG. 5A, and FIG. 5C is a front view.

Next, as shown in FIGS. 6A, 6B, and 6C, boron is 1 × 10 ¹⁴ cm ⁻² at 1 keV for the p-type, and arsenic is ² × 0.5 keV for ^the n-type. Ions are implanted at about × 10 ¹⁵ cm ⁻² to form pockets or extension regions. 6A is a plan view, FIG. 6B is a cross-sectional view taken along line BB in FIG. 6A, and FIG. 6C is a front view.

  Next, as shown in FIGS. 7A, 7B, and 7C, a laminated film made of silicon dioxide 10 nm and silicon nitride 10 nm is deposited by LPCVD, and the laminated film is formed by RIE (Reactive Ion Etching) or the like. By patterning, a gate sidewall insulating film 122 is formed. 7A is a plan view, FIG. 7B is a cross-sectional view taken along line BB in FIG. 7A, and FIG. 7C is a front view.

Next, although not shown in the figure, arsenic is ion-implanted at 30 keV to about 3 × 10 ¹⁵ cm ⁻² to form a deep diffusion layer region. Thereafter, when the contact formation or the like is performed, the structure as shown in FIG. 1 can be produced. Before that, after hot phosphoric acid treatment is performed and the protective film on the Fin region 126 is removed, Co or Ni is sputtered, A self-aligned silicide layer may be formed on the Fin region 126 and the gate electrode 114 by heat treatment.

  Although the SOI substrate is used in the first embodiment, a semiconductor layer may be deposited on a bulk semiconductor substrate via an insulating layer and processed into a plate-like semiconductor layer.

  Thus, according to the first embodiment, it is possible to provide an ESD protection element that does not impair the performance of the FinFET and makes use of the high density mounting of the FinFET.

(Second Embodiment)
In the first embodiment, the second gate electrode is stacked directly on the first gate electrode. However, the present invention is not limited to this, and the second gate electrode is formed on the pad of the lead portion of the first gate electrode. The gate electrode may be provided.

  FIGS. 8A and 8B are a top view and a cross-sectional view taken along line B-B, respectively, of the ESD protection element according to the second embodiment. In the second embodiment, the second gate insulating film and the second gate electrode are formed on the gate electrode lead pad 130. Since the configuration of the ESD protection element other than the above is the same as that of the first embodiment, a duplicate description is omitted. Even with this configuration, the overall breakdown voltage of the gate insulating film can be dramatically increased while minimizing the decrease in the driving force of the FinFET.

  Also in the second embodiment, the first gate insulating film is preferably as thin as possible in order to ensure the driving force, and specifically, should be about 2 nm or less. On the other hand, the second gate insulating film is preferably as thick as possible in order to ensure a withstand voltage, and specifically, it is desirable that the thickness be 4 nm or more.

  Further, if the first gate insulating film is formed of, for example, a normal silicon oxide film and the second gate insulating film is formed of a high dielectric constant (high-K) insulating film, the withstand voltage is increased and the drive current is increased. Can be bigger.

  As described above, according to the second embodiment, by using the gate lead pad, it is possible to provide an ESD protection element with a higher degree of freedom without deteriorating the mounting density.

  In the above embodiment, all devices are formed on an SOI substrate. However, the present invention can be applied to a FinFET manufactured on a bulk Si substrate. Various modifications can be made without departing from the spirit of the present invention.

The perspective view of the ESD protection element which concerns on 1st Embodiment. FIG. 3 is an equivalent circuit diagram of the ESD protection element according to the first embodiment. BRIEF DESCRIPTION OF THE DRAWINGS (a) is a top view, (b) is sectional drawing along the BB line in (a), (c) is a side view of the ESD protection element which concerns on 1st Embodiment. It is a figure explaining the manufacturing process of the ESD protection element which concerns on 1st Embodiment, (a) is a top view, (b) is sectional drawing along the BB line in (a), (c) is ( Sectional drawing along CC line in a). FIGS. 5A and 5B are diagrams illustrating a process subsequent to FIG. 4, in which FIG. 4A is a top view, FIG. 4B is a cross-sectional view taken along the line B-B in FIG. FIG. FIGS. 6A and 6B are diagrams illustrating a process following FIG. 5, in which FIG. 5A is a top view, FIG. 5B is a cross-sectional view taken along line B-B in FIG. FIGS. 7A and 7B are diagrams illustrating a process following FIG. 6, in which FIG. 7A is a top view, FIG. 7B is a cross-sectional view taken along the line BB in FIG. (A) is a top view of the ESD protection element which concerns on 2nd Embodiment, (b) is sectional drawing along the BB line in (a).

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 ... ESD protection element 110 ... Semiconductor substrate 111 ... Embedded insulating layer 112 ... Plate-shaped semiconductor layer (Fin)
112c ... Channel region 113 ... First gate insulating film 114 ... First gate electrode 115 ... Source / drain region (electrode)
116 ... second gate insulating film 117 ... second gate electrode 118 ... input / output pad 119 ... internal circuit 126 ... SOI layer 128 ... silicon nitride film 130 ... gate lead pad

Claims (5)

A semiconductor substrate;
An insulating layer formed on the semiconductor substrate;
A plate-like semiconductor layer provided perpendicular to one region on the insulating layer;
A first gate electrode formed so as to straddle and sandwich the plate-like semiconductor layer via a first gate insulating film at a central portion of the plate-like semiconductor layer;
A second gate electrode formed on the first gate electrode through a second gate insulating film;
The plate-like semiconductor layer includes a channel region facing the first gate electrode through the first gate insulating film, and a pair of source / drain electrodes formed on both sides of the channel region. A featured ESD protection element. A semiconductor substrate;
An insulating layer formed on the semiconductor substrate;
A plate-like semiconductor layer provided vertically on the insulating layer;
A first gate electrode formed so as to straddle and sandwich the plate-like semiconductor layer via a first gate insulating film at a central portion of the plate-like semiconductor layer;
A lead pad of the first gate electrode;
A second gate electrode formed on the lead pad through a second gate insulating film;
The plate-like semiconductor layer includes a channel region facing the first gate electrode through the first gate insulating film, and a pair of source / drain electrodes formed on both sides of the channel region. An ESD protection element characterized by the above.   The ESD protection element according to claim 1, wherein the plate-like semiconductor layer is made of silicon.   4. The ESD protection element according to claim 1, wherein a film thickness of the second gate insulating film is larger than a film thickness of the first gate insulating film.   The ESD protection element according to claim 1, wherein a dielectric constant of the second gate insulating film is higher than a dielectric constant of the first gate insulating film.

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