JP2007053175A - Method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device wherein a MOS capacitor used as an anti-fuse and a MOS transistor having an LDD structure are formed on the same substrate, and by which the MOS capacitor is hard to be broken in the manufacturing step of the MOS transistor having the LDD structure. <P>SOLUTION: The capacitor electrode 4 of a MOS capacitor is covered with a silicon oxide film 6, and it is dry-etched to form the gate electrode of the MOS transistor as well as to form a side wall spacer of the MOS transistor. Thus, the silicon oxide film 6 protects the MOS capacitor, resulting in preventing the MOS capacitor from being broken by dry etching. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device in which a MOS capacitor used as an antifuse and a MOS transistor having an LDD (Lightly Doped Drain and Source) structure are provided on the same substrate.

In manufacturing a MOS transistor having an LDD structure, patterning is required in the step of forming a gate electrode and the step of forming a sidewall spacer. These patterns are generally performed by dry etching such as plasma etching. Is.
JP-A-8-340110

  Therefore, when the MOS capacitor is on the same substrate, this dry etching is also performed on the MOS capacitor portion. For this reason, there arises a problem that the MOS capacitor may be destroyed in a dry etching process necessary for manufacturing an LDD structure MOS transistor. The present invention has been made to solve this problem. A MOS capacitor used as an antifuse and a MOS transistor having an LDD structure in which the MOS capacitor is not destroyed in the manufacturing process of the LDD structure MOS transistor. The object is to provide a method of manufacturing a semiconductor device provided on the same substrate.

  In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention includes a step of forming a capacitor electrode, a step of covering the capacitor electrode with a silicon oxide film, and a gate electrode of a MOS transistor. A gate deposition process, a gate electrode formation process by dry etching, a sidewall spacer deposition process for forming a sidewall spacer of the gate electrode of the MOS transistor, and a sidewall spacer formation process by dry etching. .

  The silicon oxide film that covers the capacitor electrode is preferably 150 nm to 300 nm in thickness.

  According to the present invention, after the MOS capacitor is covered with the silicon oxide film, a dry etching process is performed in the manufacturing process of the MOS transistor, so that the MOS capacitor is protected by the silicon oxide film during the dry etching process and may be destroyed. Therefore, an appropriate semiconductor device can be manufactured. If the thickness of the silicon oxide film is 150 nm to 300 nm, the MOS capacitor is suitably protected.

  Hereinafter, preferred embodiments of the present invention will be described based on the manufacturing process diagrams of FIGS. First, as shown in FIG. 1, a LOCOS element isolation region 2, a diffusion layer 5, a capacitor insulating film 3 made of a silicon oxide film, and a capacitor electrode 4 are formed on a semiconductor substrate 1. The diffusion layer 5, the capacitor insulating film 3, and the capacitor electrode 4 constitute a MOS capacitor. By connecting the diffusion layer 5 and the capacitor electrode 4 to a write circuit or a read circuit, the MOS capacitor is used. A thin region is formed in the capacitor insulating film 3 as a data writing region (insulating film breakdown region) when used as an antifuse element. The LOCOS element isolation region 2 and the MOS capacitor can be formed by a conventionally known method.

  Subsequently, as shown in FIG. 2, the capacitor electrode 4 is covered with a silicon oxide film 6. Setting the thickness of the silicon oxide film 6 to 150 nm to 300 nm is preferable because it can reliably protect the MOS capacitor. Further, as shown in FIG. 3, after a gate oxidation process is performed to form a gate insulating film 7, a polycrystalline silicon layer 8 is formed over the entire element region in order to form a gate electrode of a MOS transistor including the wiring. accumulate. In the case of a transistor whose gate electrode is made of molybdenum, molybdenum is deposited instead of polycrystalline silicon.

  Then, as shown in FIG. 4, a gate electrode 9 is formed by patterning the polycrystalline silicon layer 8 by plasma etching. When this plasma etching is performed, the capacitor electrode 4 is covered and protected by the silicon oxide film 6 and insulated from the plasma, so that the charge induced in the capacitor electrode 4 is reduced, and the voltage applied to the capacitor insulating film 3 is reduced. The dielectric breakdown of the capacitor insulating film 3 is prevented by being kept small.

Subsequently, as shown in FIG. 5, impurity ion implantation is performed using the gate electrode 9 as a mask to form the low concentration diffusion layers 10a and 10a of the source / drain of the MOS transistor. Next, as shown in FIG. 6, a silicon oxide film 11 is deposited so as to extend to the capacitor electrode 4 portion in order to form a sidewall spacer of the gate electrode 9 of the MOS transistor. Then, as shown in FIG. 7, the silicon oxide film 11 is etched by plasma etching so that the side wall spacers 12 and 12 remain. Even when this plasma etching is performed, the capacitor electrode 4 is covered and protected by the silicon oxide film 6, so that there is no possibility that the capacitor insulating film 3 is broken down.

Next, as shown in FIG. 8, ion implantation of impurities is performed using the side wall spacers 12 and 12 as a mask to form high concentration diffusion layers 10b and 10b of source / drain, and a MOS transistor having an LDD structure is formed.

  The present invention is not limited to the above-described embodiment. For example, the capacitor insulating film 3 may be silicon nitride, silicon oxynitride, in addition to silicon oxide.

FIG. 5 is a schematic cross-sectional view showing a MOS capacitor manufacturing process in a semiconductor device manufacturing process. FIG. 5 is a schematic cross-sectional view showing one step of a MOS transistor manufacturing process in the semiconductor device manufacturing process. The schematic sectional drawing which similarly shows the 1 process. The schematic sectional drawing which similarly shows the 1 process. The schematic sectional drawing which similarly shows the 1 process. The schematic sectional drawing which similarly shows the 1 process. The schematic sectional drawing which similarly shows the 1 process. The schematic sectional drawing which similarly shows the 1 process.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 LOCOS element isolation region 3 Capacitor insulating film 4 Capacitor electrode 5 Diffusion layer 6 Silicon oxide film 7 Gate insulating film 9 Gate electrode 10a Low concentration diffusion layer (source / drain)
10b High concentration diffusion layer (source / drain)
12 Sidewall spacer

Claims (2)

In a method for manufacturing a semiconductor device in which a MOS capacitor used as an antifuse and a MOS transistor having an LDD (Lightly Doped Drain and Source) structure are provided over the same substrate,
A step of forming a capacitor electrode, a step of covering the capacitor electrode with a silicon oxide film, a step of depositing a gate for forming a gate electrode of a MOS transistor, a step of forming a gate electrode by dry etching, and a gate of the MOS transistor A method for manufacturing a semiconductor device, comprising: a side wall spacer deposition step for forming a side wall spacer of an electrode; and a side wall spacer formation step by dry etching.   2. The method of manufacturing a semiconductor device according to claim 1, wherein the silicon oxide film covering the capacitor electrode has a thickness of 150 nm to 300 nm.

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