TWI289907B - Method for fabricating metal oxide semiconductor transistor and memory device memory cell array thereof - Google Patents

Abstract

A fabricating method for metal oxide semiconductor transistor is provided. A patterned film layer is formed on a substrate to define a predetermining region for source/drain. Local oxidation structures are formed on the substrate exposed by the patterned layer that used to define a predetermining region for channels. The patterned layer is removed. The source/drain regions are formed in the substrate by using the local oxidation structures as masks. The local oxidation structures are removed to form a plurality of recess areas naturally. A gate insulating layer is formed on the substrate, and a gate is formed on a portion of the gate insulating layer above the plurality of recess areas. The recess channel with longer length can prevent short channel effect.

Description

1289907 -------_ V. INSTRUCTION DESCRIPTION (1) [Technical Field] The present invention relates to a genus of a metal oxide semiconductor method 0 [Prior Art] With the current computer micro The processor, the stronger the software, the process of making the δ mnemonic has become semi-general, the memory can be relied on, the brother and the non-volatile memory will not be eliminated due to the interruption of the power supply. Therefore, it is often used to store electricity. The current memory technology is developing in the direction of piece by piece size. However, at the same time, because of its channel length (Short Channel Effects, it is usually to reduce the quality of the channel length, to suppress the short channel effect of the dopant, but also trigger another leakage problem. Moreover, in order to improve the accumulation The distance between each memory cell. However, the process defines the mother cell memory system. The distance between the memory cells will limit the manufacturing method of the conductor elements, and in particular, the functions of the crystal and the memory device manufacturer (Microprocessor). The more and more operations are becoming more and more huge. Therefore, one of the important technologies in the conductor industry is that the type of stored data is divided into volatilization. In the case of non-volatile memory, it makes the data stored in it completely brain-like. Boot system data, etc. Gradually increasing the degree of integration and shrinking the size of the memory on the wafer to reduce the shrinkage of the memory caused by the short channel effect), causing the component to not function properly. At the same time, the mixing in the channel must be increased. However, if too much flow (1 eakagecurrent) is added to the channel, it must be reduced as much as possible in the process. It is usually lithographically/etched to make the position 'but because the lithography process limit is limited to the lithography process. Range

1289907] The addition of the channel region of the present invention and the improvement of the other element of the element is too high, and a substrate is formed on the board to form the idati 〇η out of the substrate to expose the gate region and the annihilation region. One type, and the base cell array layer is oxidized to form a regional oxidation base. After the fifth, the invention description (2) 〇 [the content of the invention, therefore, the method of increasing density, into the method of the invention, and the bit line resistance of the invention system first in the base (local 〇χ film layer exposed a film layer, a source forming source in the bottom forms a gate on the source region and a layer on the substrate. The invention provides a base substrate which is divided into a patterned film and then formed into a portion of the substrate to provide a length. Lifting element performance. The 疋 provides the problem of the increase in the degree of accumulation. The oxynitride electrically patterned film layer, referred to as L0C0S, forms the base of the oxygen portion of the region. Polar zone. Then, the substrate is further formed on the substrate, and then a region and a peripheral electrode are formed on the bottom of the memory device to expose the memory cell array in the memory structure. Then, in the memory cell array of memory cells, the memory cell in the memory cell array = the short channel effect of the fabrication of the second semiconductor transistor is crystallized, and then the region is oxidized to facilitate the process. In the patterned structure. Then, after removing, the exposed structure in the removed region oxidizes the structure, and the plurality is recessed. Next, a method of manufacturing a gate insulation over the recessed area is preceded by a plurality of isolation structures to place the base region. Then a portion of the substrate in the & column area on the substrate. a patterned film layer exposed in the cell array region to expose the regional oxide structure in the column region

13268twf.ptd Page 8 1289907 V. INSTRUCTIONS (3) Buried bit lines are formed in part of the exposed substrate. The regional oxidation structure is then removed and a plurality of recessed regions are formed in the substrate. Next, a gate insulating layer is formed on the base and the recessed region, and a conductor layer is formed on the gate insulating layer. Thereafter, the patterned conductor layer defines a plurality of word lines in the memory cell array region and defines at least one gate structure in the peripheral circuit region. A source/drain region is then formed in the substrate on either side of the gate structure. The present invention utilizes a zonal oxidation process to form a oxidized structure having a specific shape on a substrate such that a recessed region can be formed in the substrate after the step of removing the oxidized structure of the region. And since the source region and the drain region are disposed on both sides of the recessed region, the substrate under the recessed region becomes a channel region of the semiconductor element near the surface. From this, it can be seen that the present invention forms a non-linear channel region at a certain pitch to increase the length of the channel region. Therefore, the present invention can effectively solve the problem that the conventional semiconductor element causes a short channel effect due to an increase in the degree of integration. The above and other objects, features and advantages of the present invention will become more <RTIgt; [Embodiment] The process of the present invention defines the position of the recessed channel region by the area oxide structure in order to increase the length of the channel region of the semiconductor element. The following embodiments will be described by taking a memory element as an example to illustrate the process of the present invention. It is to be noted that the present invention is also applicable to the process of other MOS transistors, and it is to be understood by those skilled in the art that the following examples are merely illustrative of the invention and are not intended to limit the invention.

13268twf.ptd Page 9 1289907 V. INSTRUCTION DESCRIPTION (4) FIG. 1A to FIG. 1 are cross-sectional views showing a flow of a method of manufacturing a memory* element according to a preferred embodiment of the present invention. Referring to FIG. 1A, a plurality of isolation structures 1 〇 2 ′ are first formed on the substrate 1 以 以 to define a memory cell array region 4 a and a peripheral circuit 104 b on the substrate 1 〇 . The isolation structure 丨〇2 is, for example, a regional oxide isolation structure or a shallow trench isolation (STI) structure. The isolation structure 本 2 of the present embodiment is exemplified by a regional oxidation isolation structure. Next, a film layer 108 is formed on the substrate 1 〇 , and the material thereof is, for example, ruthenium. Moreover, in a preferred embodiment, before the formation of the film layer 8 , il rT first forms a pad oxide layer 106 on the substrate 1 〇 0 to protect the substrate.

The surface of the substrate 100 is less susceptible to damage during subsequent processes, such as etching processes. Please refer to the film layer 108a and the memory cell circuit area 1 〇4 b. If it is micro-medium, it is formed in the memory cell array. Please refer to the channel shown in Figure 18. 1B 'The film layer 1 8 is patterned to form a pattern, and the film layer 108b is formed. Wherein, the patterned film layer 8a is also in the 2 region 104a, and the patterned film layer 1〇81) is located in the periphery. In the present embodiment, the method of patterning the film layer 1〇8 is performed and etching is performed. Process. In addition, in another embodiment, the patterned film layer 1 〇 81) in the circuit region 104b may also be a = 104" patterned film layer 1 〇 8 &amp; f f is described by way of a simpler process.

The C is a regional oxidation method to form a plurality of regional oxidation structures 1 i 在 on the patterned film layer: bottom 100. Special ϊ>Π1. It is used to define a note in the subsequent process (not drawn). And in one embodiment, on the substrate

13268twf.ptd Page 10 1289907 V. Description of the Invention (5) After forming the regional oxide structure 110 on 100, the sacrificial layer 112 is further formed on the substrate 1 , the patterned film layer 108a and the patterned film layer 108b, and sacrificed The layer 11 2 exposes the patterned film layer 108b and a portion of the layer 108a as shown in FIG. 1C. For example, the sacrificial layer 112 is formed by first forming a sacrificial material layer 112a (as shown in FIG. 2A) on the substrate 1 by chemical vapor deposition (CVI), and the material thereof is, for example, There is etching selectivity between the material of the patterned ruthenium film layer 108a and the patterned film layer i 〇 8b. In the present embodiment, the material of the patterned film layer 8a and the patterned film layer 1 8b is, for example, tantalum nitride, and the material of the sacrificial material layer 1 1 2a is, for example, tantalum oxide. Then, the photoresist layer 116 is formed on the patterned film layer 8a (for example, as shown in FIG. 2B) by, for example, a lithography process, and the photoresist layer 116 is used as a mask to perform etching to remove the A portion of the sacrificial material layer 1 1 2 a on the patterned film layer 10b. In this etching process, the sacrificial material layer 1 1 2a is etched, for example, by patterning the film layer b 8 b as an etch stop layer. Then, the photoresist layer 丨丨6 is removed, and an etching process is performed to etch back a portion of the sacrificial material layer ii2a on the patterned film layer 108a to form a sacrificial layer 112°, which is based on A Zhao Erluo ^ According to #成Μ的形U 丨 丨 , 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 The internal 2B profit is used as the picture and the fan to the gods. The savvy picture is the 匕 匕 Λ Λ Λ Λ Λ Λ Λ Λ Λ Λ Λ Λ Λ Λ Λ Λ Λ Λ Λ Λ Λ Λ Λ Λ Λ Λ Λ Λ Λ Λ Λ Λ Λ Λ Λ Λ Λ Λ Λ 11 The picture is taken out by the sneak peek, please, ο ο 13268twf.ptd Page 11 1289907 V. Invention description (6) The engraving process is completed. It is worth noting that s _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ After the second patterned film layer 108b is finished, a portion of the sacrificial layer 112 is present on the region oxidized, as shown in FIG. The photoresist sound 1 〖7 is formed in the peripheral circuit area 1〇4b where Tao Mo is located, and TB ^ 1 covers the peripheral circuit area 104b of the 4 substrate 100. Then again

Kim:10 performs a deep ion implantation process for the mask, and forms a deep doped region ui eepd ο p 1 ngarea ) 1 2 0 a in the substrate 1〇〇 exposed in the recording array area l〇4a. . Referring to FIG. 1F, a portion of the sacrificial layer 112 and the region germanium structure 110 are removed again to expose more portions of the cat 2 in the memory cell array region 10, and then the region is oxidized 11 () And on the above, the shade mask is subjected to a shallow ion implantation process, and a shallow doped region (shaU〇wd〇ping aRa) i2Qb is formed on both sides of the deep push region 1 〇a. 1 20a and shallow doped region 20b constitute a line 120 of a memory element. The deep doped region 12〇a and the shallow doped region 12〇b, the doping iceness is determined by the implantation process. The energy of the ion beam. After forming the deep doped region 12〇a and the shallow doped region i2〇b, the photoresist layer 1 17 is formed. I 咏焱 sand 咏焱 Figure 1G, an etching process is performed to remove All of the film layers on the substrate 100 are, for example, a sacrificial layer 112 and a region oxide structure 11 〇. It is noted that in a preferred embodiment, if the substrate 10 is on the substrate

13268twf.ptd Page 12 1289907 V. Description of the invention (7) The enthalpy layer 106' in the peripheral circuit region l〇4b is also in the etching process and the sacrificial layer 1 1 2 The regional oxidation structure 丨丨0 is simultaneously removed. After the area oxide structure 110 is removed, a plurality of recessed regions 130 are formed on the substrate 1 . Thereafter, the gate insulating layer 1 22 and the conductor layer 1 24 are sequentially formed on the substrate 1 and the recessed region θ 1 3 0 . Among them, the conductor layer 142 is filled, for example, with the recessed region 13 〇. In the present embodiment, the conductor layer 丨 2 4 is, for example, a polysilicon layer, and the material of the gate insulating layer 12 2 is, for example, yttrium oxide, and the method for forming the gate insulating layer 12 2 is, for example, a thermal oxidation method. The method of forming the conductor layer 124 is, for example, a chemical vapor deposition method. Referring to FIG. 1 , the conductive layer 1 24 and the gate insulating layer 1 2 2 are patterned to form a gate structure 124b of the circuit component in the peripheral circuit region 10b, and simultaneously in the memory cell array region 1 〇 4a. A word line l 24a forming a memory element. At this time, the memory cell array 1 400 in the memory cell array area i 4a is completed. The region 132 below the recessed region 130 between two adjacent buried bit lines 丨2 即 is the channel region of the memory cell. The source/drain regions 26 are then formed in the substrate 100 on both sides of the gate structure 12 4b, and the subsequent processes are the same as those of the existing memory devices. Those skilled in the art can understand the detailed techniques. No longer. Those skilled in the art will appreciate that in the process of forming the gate structure 丨 24 b and the source/drain regions 1 2 6 , it is necessary to form a mask on the conductor layer 1 24 in the memory cell array 丨〇 4a. The curtain layer (not shown in green) protects the film layer within the memory cell array region 104 from being affected in this step. Of particular note is the channel area 127 and source/no of the circuit components in the peripheral circuit area l〇4b.

13268twf.ptd Page 13 1289907 V. DESCRIPTION OF THE INVENTION (8) The formation method of the polar region 1 2 6 may be a process using the present invention. That is to say, the commonly used MOS process can also be formed by the method of forming the gamma source/drain region 1 2 6 with the buried bit line 1 2 则, for example, with the channel % The method is the same, and the channel area is 1 2 7 In addition, the conductor layer is formed! The formation method of 1 3 2 is the same. Before the insulating layer 122, a layer of a silicide layer and a low conductor layer may be formed on the patterned conductor layer 1 24 and the capping layer or the conductor layer 124. The value of the metal deuteration is defined by a person skilled in the art, and the invention may not be applied to the nitridation f as determined by the actual process. In the following, an embodiment is shown in conjunction with the figure:: The process of reading only the memory element. ^ 13⁄4 η〇 Figure 3 is a diagram of another invention of the present invention. A schematic cross-section of the component. Referring to a read-only memory in the T embodiment, a gate insulating is formed on the substrate 100; according to the description of the above embodiment, the tantalum nitride layer 1 2 3 and the % date are formed on the 1 2 2 The material of the gate insulating layer 125 and then the barrier layer 125 is opened / ff (barrier layw). The material of the layer 1 25 is, for example, yttrium oxide, the array 123 and the barrier 125, that is, the insulating layer 122. Nitride layer/U f ′′: 堆叠 氧化 氧化 氧化 氧化 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆A word line θ 124a is formed in the array region 1〇4a, and a gate structure 2 24 is formed in the peripheral circuit region 〇4b. At this time, the tantalum nitride memory cell array 240 is completed. Thereafter, the gate structure is formed. The source/drain region 丨2 6 is formed in the substrate 1 0 0 on both sides, and the subsequent process is the same as the current memory device process.

1289907 V. Description of the invention (9) Since a semiconductor element having a relatively high degree of integration requires a source/drain region having a small width (that is, a bit line in a memory element) and a channel having a long length. The region, and as apparent from the above description, the present invention defines the position of the source/drain region by the patterned film layer, and the region oxidation structure between the patterns of the patterned film layer is used to define the position of the channel region. That is, the present invention first defines the position of the source/drain region of a smaller size (i.e., the position of the pattern of the patterned film layer), and then forms a region oxide structure to define the position of the channel region. Therefore, the present invention avoids the conventional problem of defining the position of the channel region by the lithography/etching process, and the size of the channel region will be limited by the range allowed by the lithography process. Therefore, the present invention can increase the degree of integration with a simpler process to save process costs. Moreover, the present invention further utilizes a zone oxidation process to form a region oxide structure having a particular shape on the substrate such that a recessed region can be naturally formed on the substrate after the step of removing the region oxide structure. And since the source/drain regions are disposed on both sides of the recessed region, the base below the recessed region becomes the channel region of the component near the surface. It can be seen that the present invention forms a non-linear channel region at a certain pitch to increase the length of the channel region. Therefore, the present invention can effectively solve the problem that the conventional semiconductor body element causes a short channel effect due to an increase in the degree of integration. Further, in the step of forming the source/drain regions of the present invention, a deep ion implantation process and a shallow ion implantation process are performed first, so that the present invention can reduce the resistance of the source/drain regions. Although the present invention has been described above by way of a preferred embodiment, it is not intended to limit the present invention, and those skilled in the art, without departing from the spirit of the invention

13268twf.ptd Page 15 1289907

13268 twf.ptd page 16 1289907 BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A to FIG. 1 are cross-sectional views showing a manufacturing process of a memory device in accordance with a preferred embodiment of the present invention. 2 is a cross-sectional view showing a manufacturing process of a sacrificial layer of a memory device in accordance with a preferred embodiment of the present invention. 3 is a cross-sectional view showing a read only memory device in another embodiment of the present invention. [Description of pattern indication] 100: Substrate 1 0 2 : isolation structure 1 0 4 a : memory cell array region 1 0 4 b · peripheral circuit region 1 0 6 : pad oxide layer 108: film layer 108a: first patterned film Layer 108b: second patterned film layer 1 1 0 : region oxide structure 1 12 : sacrificial layer 112a : sacrificial material layer 1 1 6 , 1 1 7 · photoresist layer 1 2 0 : buried bit line 1 2 0 a : deep doped region 1 2 0 b : shallow doped region 1 2 2 : gate insulating layer 1 2 3 : tantalum nitride layer

13268twf.ptd Page 17 1289907 Schematic description 124: Conductor layer 1 2 4 a: Word line 12 4b: Gate structure 1 2 5 : Barrier layer 1 2 6 : Source/drain region 1 27, 132 : channel area 1 3 0 : recessed area 1 4 0 ; memory cell array 13268twf.ptd第18页

Claims (1)

1289907 The invention relates to a method for manufacturing a MOS transistor, wherein a patterned film layer is formed on the substrate to include: · the on-out portion of the etch-based oxidation process for the patterning Exposed to form a oxidized structure on the substrate; the patterned layer is removed by the ruthenium layer, and the substrate is rained; the film layer is oxidized out of the region and oxidized in the region A substrate is formed on the two sides of the f-region, and a source region is formed to form a gasification structure, and a gap between the source region and the non-polar region is opened on the substrate in the recess region. Layer; and 2. If a special gate is formed on the insulating layer of the gate. a manufacturing method, wherein, before the ruthenium layer of the MOS transistor described in Item 1, further, after forming the oxidized structure in the region and removing the pattern, the sacrificial layer is exposed to form a layer over the substrate Sacrificial layer, which is structured. The patterned film layer is divided and covers the oxygen production method of the region, and the selectivity of the MOS transistor described in the second aspect. '&quot; between the sacrificial layer and the patterned germanium layer is etched to produce the third item of the fourth party, wherein the material of the layer of the metal oxide semiconductor transistor includes the material of the oxygen-emitting film θ including tantalum nitride. Sacrifice 13268 twf. ptd, page 19, 1289, 907. Patent Application No. 5, the method of manufacturing the MOS transistor according to claim 2, wherein the method of forming the sacrificial layer comprises: forming a sacrifice on the substrate a material layer covering the patterned film layer and the oxidized structure of the region; and removing a portion of the sacrificial material layer to expose a portion of the patterned film layer. The method for manufacturing a MOS transistor according to claim 1, wherein the step of forming the source region and the drain region comprises: performing an oxidation structure of the region as an implant mask a deep ion implantation process for respectively forming a deep doped region in the substrate on both sides of the oxidation structure of the region; removing a portion of the region oxidized structure to increase an exposed area of the substrate; and performing a shallow ion The implantation process is such that a shallow doped region is formed on one side of each of the deep doped regions. 7. The method of fabricating a MOS transistor according to claim 1, wherein after forming the gate insulating layer and before forming the gate, further comprising sequentially forming a nitride on the gate insulating layer. The enamel layer and a barrier layer. 8. The method of fabricating a MOS transistor according to claim 1, wherein before forming the patterned film layer on the substrate, further comprising forming a pad oxide layer on the substrate, and removing the The region oxidizing structure further includes removing the pad oxide layer. 9. A method of fabricating a memory device, comprising: 13268twf.ptd Page 20 1289907 6. The patent application scope provides a substrate, and a plurality of isolation structures are formed on the substrate to divide the substrate into a memory cell array region and a peripheral circuit region; forming on the substrate a patterned film layer exposing a portion of the substrate located in the memory cell array region; performing a region oxidation process to form a plurality of regional oxide structures in the exposed substrate in the memory cell array region Removing the patterned film layer to expose a portion of the substrate; forming a plurality of buried bit lines in the exposed portion of the memory cell array region; removing the oxide structures of the regions, Forming a plurality of recessed regions in the substrate of the memory cell array region; forming a gate insulating layer on the substrate and the recess regions; forming a conductor layer on the gate insulating layer; patterning the conductor layer, a plurality of word lines are defined in the memory cell array region, and at least one gate structure is defined in the peripheral circuit region, and the gate structure is The substrate is formed of a source / drain region. The method for fabricating a memory device according to claim 9, wherein after forming the regional oxide structure and before removing the patterned film layer, further comprising forming a sacrificial layer over the substrate, Wherein the sacrificial layer exposes a portion of the patterned film layer in the memory cell array region and covers the region oxide structures. The method of fabricating a memory device according to claim 1, wherein the sacrificial layer and the patterned film layer have an etch selectivity. The method for manufacturing a memory device according to the above-mentioned claim, wherein the material of the patterned film layer comprises tantalum nitride, and the sacrificial layer · Materials include yttrium oxide. The method of manufacturing the memory device of claim 10, wherein the method of forming the sacrificial layer comprises: forming a sacrificial material layer on the substrate, covering the patterned film layer and the a region oxidizing structure; removing the sacrificial material layer in the peripheral circuit region; and removing a portion of the sacrificial material layer in the memory cell array region to expose a portion of the patterned film layer in the memory cell array region come out. The method of manufacturing the memory device of claim 9, wherein the step of forming the buried bit line comprises: forming a patterned photoresist layer on the substrate to cover the substrate The peripheral circuit region; performing an ion implantation process using the patterned photoresist layer and the region oxide structure as an implant mask; and removing the patterned photoresist layer. 1. The method of manufacturing a memory device according to claim 9, wherein the step of forming the buried bit line comprises: forming a patterned photoresist layer on the substrate to cover the substrate The peripheral circuit region; using the patterned photoresist layer and the region oxide structure as an implant mask, performing a deep ion implantation process to form a plurality of deep doped regions in the substrate; 13268twf.ptd Page 22 1289907 VI. The patent application scope removes part of the thickness of the oxidized structure of the region to increase the exposed area of the substrate; performs a shallow ion implantation process for each of the deep doped regions Forming a shallow swap region on both sides; and removing the patterned photoresist layer. The method of manufacturing a memory device according to claim 9, wherein the gate insulating layer is formed on the gate insulating layer after forming the gate insulating layer and before forming the conductive layer. A tantalum nitride layer and a barrier layer are sequentially formed. The method of manufacturing a memory device according to claim 9, wherein before forming the patterned film layer on the substrate, further comprising forming a pad oxide layer on the substrate and removing the region The oxidizing structure further includes removing the ruthenium oxide layer. The method of fabricating a memory device according to claim 9, wherein the isolation structures on the substrate comprise a regional oxide isolation structure or a shallow trench isolation structure. 13268twf.ptd Page 23