JP2007052721A - Synchronous serial interface circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To simply realize a function for allowing data processing in one unit byte and adjusting width and depth of FIFO in a synchronous serial interface circuit. <P>SOLUTION: This synchronous serial interface circuit is provided with a transmission FIFO 102, a receipt FIFO 112, a data division control part 103 dividing 4-byte data output by the transmission FIFO 102 into 2-byte or 1-byte data and outputting the data in the divided byte unit, a parallel/serial conversion part 105 receiving data from the data division control part 103 and converting them into serial data to output them to the outside, a serial/parallel conversion part 115 converting serial data received from the outside into parallel data and outputting them, and a data coupling control part 113 coupling the 2-byte or 1-byte receipt data output by the serial/parallel conversion part 115 into 4-byte data and sending the data in a 4-byte unit to the receipt FIFO 112. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a synchronous serial interface circuit, and more particularly to a technique for simply realizing a function of adjusting the width and depth of a FIFO.

  There are various types of serial communication formats for connecting a computer and its peripheral devices or between computers. In general, the data length handled in the communication format is an integral multiple of 1 byte which is the minimum unit.

  The conventional serial interface has a circuit structure that processes the data length according to a specific communication format. However, it is a general-purpose device that supports various communication formats from the viewpoint of increasing the scale of LSI and sharing software assets. Serial interface has appeared.

  However, the data length that can be handled by a general-purpose serial interface needs to be adjusted to the maximum value of multiple communication formats. Therefore, when using a communication format with a small data length, a serial interface equipped with a FIFO is used. There are areas that are not used for resources.

  Here, there is a technique as disclosed in Patent Document 1 as a technique for effectively utilizing FIFO resources. This technique adjusts the depth and width of the FIFO by managing pointers in a plurality of registers, and makes the FIFO compatible with variable width data transfer.

Further, in the technique disclosed in Patent Document 2, when the data bus width is expanded and the FIFO resource is effectively used, as a solution to the problem that fractional bytes that are not originally valid are transmitted as extra data, Transmission control is performed by notifying the serial interface of the size of transmission data.
JP-A-8-235850 JP 2003-271549 A

  In general-purpose serial interface, the function that can adjust the width and depth of the FIFO according to the data length handled is useful, but considering that the required data unit is 1 byte, a patent that performs simple control of odd / even The FIFO structure as in Document 1 is not always appropriate. In addition, there is a problem that the area of the FIFO control circuit becomes large in the configuration in which the FIFO data management is performed by the pointer. In order to support full-duplex communication, it is necessary to establish a data processing method not only at the time of transmission but also at the time of reception as in Patent Document 2 in the transfer of data less than the data bus width.

  An object of the present invention is to provide a synchronous serial interface circuit capable of processing data in units of 1 byte in a FIFO used for serial communication and more simply realizing a function of adjusting the width and depth of the FIFO.

  In the present invention, a transmission FIFO for storing transmission data, a reception FIFO for storing reception data, and 4-byte data output from the transmission FIFO are output in units of 2 bytes or 1 byte, or 4 A data division control unit that outputs byte data as it is, a parallel / serial conversion unit that converts the data output from the data division control unit into serial data and outputs the data, and converts the received data into parallel data for output The serial / parallel converter and the 2-byte or 1-byte data output from the serial / parallel converter are combined into 4 bytes and output to the reception FIFO in units of 4 bytes or output from the serial / parallel converter. And a data combination control unit that transmits the 4-byte data as it is to the reception FIFO. In the present invention, the transmission FIFO has a shift register structure or the reception FIFO has a shift register structure.

  According to the above configuration, the transmission data output from the transmission FIFO can be divided into 1 byte by the data division control unit, and the reception data from 1 byte is combined by the data combination control unit and input to the reception FIFO. Therefore, data processing can be performed in units of 1 byte, and the function of adjusting the width and depth of the FIFO can be simply realized.

  In the present invention, a reception word counter for counting the number of received data is provided, and the data combination control unit receives and combines from the serial / parallel conversion unit when the number of received data matches a predetermined value set in advance. When the data is less than 4 bytes, dummy data is added to form 4 bytes of data, and the data is sent to the reception FIFO in units of 4 bytes.

  In the present invention, a terminal for recognizing the end of received data is provided, and the data combination control unit receives and combines data from the serial / parallel conversion unit when the terminal recognition operation is detected, and is less than 4 bytes. In this case, dummy data is added to form 4-byte data, and the data is sent to the reception FIFO in units of 4 bytes.

  In the present invention, comprising a reception timeout counter that detects that reception for a certain period of time is not performed, the data combination control unit, when the reception timeout counter detects that reception is not performed for a certain period of time, When the data received and combined from the serial / parallel converter is less than 4 bytes, dummy data is added to form 4-byte data, and the data is sent to the reception FIFO in units of 4 bytes.

  According to the above configuration, the function of detecting the end of received data is provided. When the end of received data is detected, dummy data is added if the data combined inside the data combination control unit is less than 4 bytes. As a result, data of less than the data bus width at the time of reception can be processed.

  According to the present invention, it is possible to process data in units of 1 byte in a FIFO used for serial communication, and to simply realize a function of adjusting the width and depth of the FIFO.

  FIG. 1 is a diagram showing a configuration of a synchronous serial interface according to an embodiment of the present invention. In FIG. 1, 100 is a synchronous serial interface circuit, 101 is a register control block, 102 is a transmission FIFO, 103 is a data division control unit, 105 is a parallel / serial conversion unit, 112 is a reception FIFO, 113 is a data combination control unit, 115 Is a serial / parallel converter, and 120 is an internal bus.

  In the above configuration, a mode at the time of transmitting serial data will be described first. A CPU (not shown) sets a transmission form in the register control block 101. The CPU or DMA (not shown) writes data to the transmission FIFO 102 via the internal bus 120. The internal bus 120 has a 32-bit width, for example.

  The transmission FIFO 102 sends the written data to the data division control unit 103. The data division control unit 103 divides the data into 1 byte, 2 bytes, and 4 bytes according to the data division parameter 104 set in the register control block 101 and sends the data to the parallel / serial conversion unit 105. The parallel / serial converter 105 serially converts the data and transmits it to the outside.

  Next, a mode when receiving serial data will be described. The CPU sets the reception mode in the register control block 101. Serial data from the outside is input to the serial / parallel converter 115. The serial / parallel converter 115 converts the data into parallel data and sends the data to the data combination controller 113.

  The data combination control unit 113 combines the 1-byte and 2-byte data into 4 bytes according to the data combination parameter 114 set in the register control block 101, and sends the 4-byte data to the reception FIFO 112 without changing the data. The CPU or DMA reads data from the reception FIFO 112.

  FIG. 2 is a diagram illustrating a configuration of the data division control unit 103. The data division control unit 103 receives the 32-bit parallel data 200 from the transmission FIFO 102. Further, the data division control unit 103 sends the data to the parallel / serial conversion unit 105 and shifts the data in the data division control unit 103 according to the data division parameter 104. The shift operation at this time is as follows.

  The internal buffers 103a, 103b, 103c, and 103d constituting the data division control unit 103 are 8-bit buffers. At the time of division from 4 bytes to 1 byte, when the data division control unit 103 outputs data to the parallel / serial conversion unit 105, the data in the internal buffer 103b is shifted to the internal buffer 103a, and the data in the internal buffer 103c is transferred to the internal buffer. The data in the internal buffer 103d is shifted to the internal buffer 103c.

  When the serial transfer is completed, the data division control unit 103 sends the shifted data 201 to the parallel / serial conversion unit 105. When this operation is repeated, the data in the internal buffer 103d is shifted to the internal buffer 103a, and when the data 201 is further sent to the parallel / serial conversion unit 105, the data in the internal buffers 103a to 103d is replaced with 32-bit parallel data 200.

  At the time of division from 4 bytes to 2 bytes, when the data division control unit 103 outputs data to the parallel / serial conversion unit 105, the data in the internal buffer 103c is shifted to the internal buffer 103a, and the data in the internal buffer 103d is transferred to the internal buffer. Shift to 103b.

  When the serial transfer is completed, the data division control unit 103 sends the shifted data 201 to the parallel / serial conversion unit 105. When the shifted data 201 is sent to the parallel / serial converter 105, the data in the internal buffers 103a to 103d is replaced with 32-bit parallel data 200.

  At this time, 32-bit data is always input to the parallel / serial conversion unit 105, but only necessary data is transmitted according to the transmission data parameter 203 output from the register control block 101, and unnecessary data is discarded. It has become.

  FIG. 3 is a diagram illustrating the configuration of the data combination control unit 113. The serial / parallel converter 115 receives the serial data 302, converts it into parallel data, and sends it to the data combination controller 113. The data combination control unit 113 shifts the input data 301 according to the data combination parameter 114. The shift operation at this time is as follows.

  The internal buffers 113a, 113b, 113c, and 113d that constitute the data combination control unit 113 are 8-bit buffers. When combining from 1 byte to 4 bytes, the data output from the serial / parallel converter 115 updates the internal buffer 113d. The data written in the internal buffer 113d is shifted in the order of the internal buffers 113c, 113b, and 113a, and when it reaches the internal buffer 113a, it waits for input of the next data.

  Next, when data is output from the serial / parallel converter 115, the buffer 113d is similarly updated. The data written in the internal buffer 113d is shifted in the order of the internal buffers 113c and 113b, and when it reaches the internal buffer 113b, it waits for input of the next data.

  Next, when data is output from the serial / parallel converter 115, the buffer 113d is similarly updated. The data written in the internal buffer 113d is shifted to the internal buffer 113c and waits for the next data input.

  Next, when data is output from the serial / parallel converter 115, the buffer 113d is updated in the same manner, and the 32-bit parallel data 300 obtained by combining the internal buffers 113a to 113d is output to the reception FIFO 112.

  When combining from 2 bytes to 4 bytes, the data output from the serial / parallel converter 115 updates the internal buffers 113c and 113d. The data written in the internal buffers 113c and 113d is shifted to the internal buffers 113a and 113b, respectively, and waits for the next data input.

  Next, when data is output from the serial / parallel converter 115, the buffers 113c and 113d are similarly updated, and the 32-bit parallel data 300 obtained by combining the internal buffers 113a to 113d is output to the reception FIFO 112.

  FIG. 4 is a view showing a FIFO structure of a pointer management method according to the prior art. Each of the buffers 400 to 415 constituting the FIFO has a width of 16 bits. A selector 416 that determines data to be output is a 16 to 1 selector.

  FIG. 5 is a diagram showing a configuration of a transmission FIFO and a reception FIFO in the synchronous serial interface of the present invention. The transmission FIFO 102 is composed of 32-bit buffers 500 to 506. Each buffer includes 1-bit flags 510 to 516. The reception FIFO 112 is composed of buffers 520 to 526 having a 32-bit width. Each buffer includes 1-bit flags 530 to 536.

  At the time of transmission, when the CPU or DMA writes to the transmission FIFO 102, the buffer 500 and the flag 510 are updated. The transmission FIFO 102 includes a shift register, and the contents of the buffer 500 and the flag 510 are shifted to the buffer 501 and the flag 511. This shift operation is repeated, and when the written data reaches the buffer 506, it is output to the data division control unit 103.

  At the time of reception, when the data combination control unit 113 writes to the reception FIFO 112, the buffer 526 and the flag 536 are updated. The reception FIFO 112 includes a shift register, and the contents of the buffer 526 and the flag 536 are shifted to the buffer 525 and the flag 535. When this shift operation is repeated and the written data reaches the buffer 520, the data can be read from the CPU or DMA.

  FIG. 6 is a diagram showing a method of processing received data less than 4 bytes in the synchronous serial interface of the present invention.

  Normally, the data combination control unit 113 does not output the 32-bit parallel data 300 to the reception FIFO until data is input to all of the internal buffers 113a to 113d. However, when the data reception end signal 600 becomes active, the data combination is in progress. Even in the next data input waiting state, dummy data is filled in the empty area and the 32-bit parallel data 300 is output to the reception FIFO.

  For example, when data exists in the internal buffers 113a and 113b, the data combination control unit 113 normally does not output the 32-bit parallel data 300 until the remaining 2 bytes of data are input, but the data reception end signal 600 is active. Then, the internal buffers 113c and 113d are filled with dummy data, and the 32-bit parallel data 300 is output to the reception FIFO.

  This data reception end signal 600 becomes active in the following cases. First, it has a reception word counter 601 that counts the number of received data, and asserts a termination notification signal 602 when a specified amount of data is received. The value set in the reception word counter 601 is parameterized and can be set freely.

  Second, it has a timeout counter 603 for detecting a period during which no data is received, and asserts a termination notification signal 604 when the reception operation is not performed for a certain period of time. The value set in the timeout counter 603 is parameterized and can be set freely.

  Thirdly, a terminal 605 for recognizing the end of received data is provided, and the end notification signal 606 input from the terminal 605 asserts the data received signal 600. The selector 607 selects the termination notification signals 602, 604, and 606 and asserts the data reception end signal 600 to the data combination control unit 113.

  The synchronous serial interface of the present invention is useful as a general-purpose serial interface of a mobile LSI because it has a data division / combination function and a reduced circuit area.

The figure which shows the structure of the synchronous serial interface concerning one embodiment of this invention. The block diagram of the data division | segmentation control part in the synchronous serial interface of this invention. The block diagram of the data combination control part in the synchronous serial interface of this invention. The figure which shows the FIFO structure of the pointer management system by a prior art. The figure which shows the structure of FIFO in the synchronous serial interface of this invention. The figure which shows the processing method of the received data less than bus width byte in the synchronous serial interface of this invention.

Explanation of symbols

100 Synchronous Serial Interface Circuit 101 Register Control Block 102 Transmission FIFO
103 Data Division Control Unit 104 Data Division Parameter 105 Parallel / Serial Conversion Unit 112 Reception FIFO
113 Data coupling control unit 114 Data coupling parameter 115 Serial / parallel conversion unit 120 Internal bus

Claims (6)

  A transmission FIFO for storing transmission data, a reception FIFO for storing reception data, and 4-byte data output from the transmission FIFO are output in units of 2 bytes or 1 byte, or data of 4 bytes is output. A data division control unit that outputs the data as it is, a parallel / serial conversion unit that converts the data output from the data division control unit into serial data and outputs the data, and a serial / parallel conversion that converts the received data into parallel data and outputs the data Unit and 2-byte or 1-byte data output from the serial / parallel converter unit into 4 bytes, and the received FIFO is in 4-byte units or 4-byte data output from the serial / parallel converter unit And a data combination control unit for transmitting the data as it is to the reception FIFO. Interface circuit.   2. The synchronous serial interface circuit according to claim 1, wherein said transmission FIFO has a shift register structure.   The synchronous serial interface circuit according to claim 1, wherein the reception FIFO has a shift register structure.   A reception word counter for counting the number of received data, wherein the data combination control unit receives 4 bytes of data received and combined from the serial / parallel conversion unit when the number of received data matches a preset specified value; 2. The synchronous serial interface circuit according to claim 1, wherein dummy data is added to form 4-byte data when the number is less than 1, and data is transmitted to the reception FIFO in units of 4 bytes.   A terminal for recognizing the end of received data, and the data combination control unit detects dummy data if the data received and combined from the serial / parallel conversion unit is less than 4 bytes when detecting the recognition operation of the terminal. The synchronous serial interface circuit according to claim 1, wherein 4 bytes of data are configured by adding and data is transmitted to the reception FIFO in units of 4 bytes.   A reception time-out counter that detects that reception has not been performed for a certain period of time; and the data combination control unit performs the serial / parallel conversion when the reception time-out counter detects that reception has not been performed for a certain period of time. 2. The synchronous serial interface circuit according to claim 1, wherein when the data received and combined from said units is less than 4 bytes, dummy data is added to form 4-byte data, and the data is sent to said receive FIFO in units of 4 bytes.

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