CN101047721B - Method for data filter process using DMA controller - Google Patents
Method for data filter process using DMA controller Download PDFInfo
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- CN101047721B CN101047721B CN200710078379A CN200710078379A CN101047721B CN 101047721 B CN101047721 B CN 101047721B CN 200710078379 A CN200710078379 A CN 200710078379A CN 200710078379 A CN200710078379 A CN 200710078379A CN 101047721 B CN101047721 B CN 101047721B
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Abstract
This invented method combines transmitted data of DMA controller with the function of data filter and process to increase filter function of the DMA controller in the read/write process of data transmission when it is enabled at the correlation control bit, when it is not enabled, the DMA controller reads and writes for data transmission directly in the process of read/write of data transmission and the write data and the read data are the same so as to lighten the operation burden of CPU and increase the operation efficiency.
Description
Technical field
The present invention relates to and adopt direct memory access (DMA) controller (abbreviating dma controller as) to carry out the method that data filter is handled in the transfer of data, specially refer to and adopt dma controller to carry out the method that data filter is handled in the High level data link control transfer of data.
Background technology
Dma controller is widely used in the various chips, and its major function is according to instruction data to be read from a certain memory space, writes another memory space (this process is commonly called transfer of data) then.After having adopted the technology of dma controller in the chip, will accelerate the transmission speed of data,, then will alleviate the operating load of CPU greatly if having the chip of central processing unit (abbreviating CPU as) by the transmission course of dma controller control data.
Usually, the transfer of data of dma controller has dual mode: the one, and CPU is after configuration finishes to the related register of dma controller, and dma controller just carries out transfer of data immediately; The 2nd, CPU is after configuration finishes to the related register of dma controller, and dma controller does not carry out transfer of data immediately, but waits for that (interrupt signal such as a certain operation dma controller is effective) just began to carry out transfer of data when the condition of enabling satisfied.Therefore, utilize dma controller transmission data, both can improve the speed of chip system transmission data, can reduce the interruption times of CPU again, improved the operational efficiency of system.
High-Level Data Link Control (abbreviating HDLC as) is a kind of control protocol of data link layer, is divided into again at the control protocol of bit with at two kinds of the control protocols of byte.At agreement in the frame format of the HDLC agreement of byte is the data of 1-2 byte, and frame check is the data of 2 bytes, information and be filled to multibyte data, and other all is the data of 1 byte.Flag data mainly is to be used for the beginning of flag data frame and the end of Frame for fixing byte data 0x7E.In the agreement, also 0x7D is defined as control escape byte.
(its main purpose is to avoid the flag data that data portion occurs or the mistake of control escape data to handle flag data or control escape data to occur for fear of the data division at Frame, as: it is considered as the end of Frame), after frame check calculating finishes, transmit leg is when sending data, check whether the data division at Frame has 0x7D, the data of 0x7E or other Synchronization Control character, if have then this byte data replaced with the byte after a control escape byte and this byte data and the 0x20 XOR, promptly change to the byte after a control escape byte and this byte data and the 0x20 XOR, as:
0x7E becomes 0x7D, 0x5E
0x7D becomes 0x7D, 0x5D
0x03 becomes 0x7D, 0x23
Above process is commonly called the data filter of data transmission procedure and handles.
Can judge each data that receives when the recipient receives data,, it be abandoned,, obtain available data byte data of its back and 0x20 XOR to the 0x7D data that occur.Through the data after handling like this, just can carry out the calculating of frame check.Above process is commonly called the data filter of DRP data reception process and handles.
After above-mentioned data filter processing, in the transmission course of data, could effectively avoid the beginning of Frame or the false judgment of end position, simultaneously, guarantee when frame data need repeatedly transmit the correct connection between the data of each time transmission.
The data filter processing capacity is to go up the software that moves by CPU to realize that dma controller does not have the data filter processing capacity in the prior art.Therefore, consumed the operation resource of CPU preciousness, the characteristic that does not make full use of the dma controller quick data transfering improves systematic function.
Summary of the invention
The inventive method combines the function that dma controller transmits data and data filter processing, and by register configuration, when enabling to be correlated with control bit, dma controller will increase filtering function in the read-write process of transfer of data; When not enabling to be correlated with control bit, dma controller directly carries out the read-write of transfer of data in the read-write process of transfer of data, and data of also promptly writing out and the data of reading in are identical.Therefore, alleviate the operation burden of CPU, improved the operational efficiency of system.
The inventive method is provided with a module (being called for short the data filter module) with data filter processing capacity in dma controller, when the data filter module enables, the data of transmission are carried out data filter handle.
The inventive method data filter module has one and enables control bit (abbreviating control bit as), this control bit have two kinds of possible values (value be 1 or value be 0) and can be by the CPU assignment, value is to represent that the data filter module was enabled at 1 o'clock, and value is that 0 expression data filter module is not enabled.
The inventive method data filter module has an inner mark variable (abbreviation indexed variable), this indexed variable have two kinds of possible values (value be 1 or value be 0) and can be by the dma controller assignment, when dma controller carries out the data transmission, the indexed variable value is to represent to send earlier the temporary data of last transmission at 1 o'clock, send data designated again, the indexed variable value is that 0 expression can directly send data designated, when dma controller carries out Data Receiving, the indexed variable value is to represent behind first data that will receive and the 0x20 XOR write memory again at 1 o'clock, and the indexed variable value is that 0 expression can be directly with the writing data into memory that receives.
The inventive method dma controller is provided with the actual length register (abbreviating length register as) that reads or write data volume, be used to store data length that dma controller reality reads or write from designated memory (for sending data channel, what indicate is the data length that reads, to receiving data channel, indication be the data length that writes).
The inventive method is to be sent or receive and to have following relation between the frequency n of the length L (comprise frame begins and frame end mark data) of data, length m that dma controller transmits data at every turn and dma controller transmission data:
L=m * n+p, wherein 0≤p＜n
When data sent, it was m that dma controller is transmitted the data length register configuration at every turn, if p is not equal to 0, then the number of times register configuration with dma controller is n; If p equals 0, then the number of transmissions register configuration with dma controller is n-1; After DMA finishes transmission, be q if CPU reads the value of length register in the dma controller, a then last L-q data are sent by CPU.
After the data filter module of the inventive method is enabled, when dma controller carries out the data transmission, when monitoring first 0x7E data, directly send these 0x7E data, if when monitoring 0x7D, 0x7E or other control byte data once more, then send earlier control escape byte 0x7D data, send the data behind these data and the 0x20 XOR again.
After the data filter module of the inventive method is enabled, when last data that sends are 0x7D, 0x7E or other control byte, in order to guarantee to send the constant of data number at every turn, then only send control escape byte data 0x7D, simultaneously, data behind these data and the 0x20 XOR are kept in, and indexed variable is changed to 1.
After the data filter module of the inventive method is enabled, when dma controller carries out the data transmission, detect indexed variable earlier, if indexed variable is 1 then sends the temporary data of last transmission earlier, send data designated again, and indexed variable is changed to 0, if indexed variable is 0 then directly sends data designated.
After the data filter module of the inventive method is enabled, when dma controller carries out Data Receiving, detect indexed variable earlier, if indexed variable is 1 then writes designated memory and indexed variable is changed to 0 behind first data that will receive and the 0x20 XOR, if the indexed variable 0 then directly data that receive are write designated memory.
After the data filter module of the inventive method is enabled, when dma controller carries out Data Receiving, if detect the 0x7E data first, then directly these 0x7E data are write designated memory, if detect the 0x7D data, then these data are abandoned and will be write designated memory behind first data after these data and the 0x20 XOR, if detected 0x7D data are exactly last data, then these data are abandoned, and indexed variable is changed to 1, if detect 0x7E once more, then these 0x7E data are write designated memory and stop Data Receiving.
Description of drawings
Fig. 1 is the chip bus structural representation that prior art has dma controller and CPU;
Fig. 2 is the HDLC protocol frame format structural representation of prior art at byte;
Fig. 3 is the schematic diagram of the prior art dma controller multichannel course of work;
Fig. 4 is that the inventive method adopts dma controller to carry out the schematic diagram of the embodiment processing procedure of data filter processing.
Below in conjunction with the drawings and the specific embodiments the inventive method is described in detail.
Accompanying drawing 1 is the chip bus structural representation that prior art has dma controller and CPU. As seen from the figure, DMA can only carry out simple transfer of data work, needs the transfer of data of filtration treatment then can only be carried out by the software of the upper operation of CPU, has consumed the operation resource of CPU preciousness.
Accompanying drawing 2 is HDLC protocol frame format structural representations of byte-oriented. As seen from the figure, agreement is the data of 1-2 byte in the frame format of HDLC agreement, and frame check is the data of 2 bytes, information and be filled to multibyte data, and other all is the data of 1 byte. Flag data mainly is the beginning of flag data frame and the end of Frame for fixing byte data 0x7E.
Accompanying drawing 3 is schematic diagrames of the prior art dma controller multichannel course of work. As seen from the figure, when dma controller carries out transfer of data, in fact exactly data are transferred to address B from address A, have a plurality of passages in the dma controller, can realize simultaneously different types of data, different addresses, the transfer of data of different data lengths. In fact, it is comparatively speaking that data receiver or data send, and as being transferred to address B from address A, is exactly that data send for address A, is exactly data receiver for address B. Data receiver comprises to be received external data, the data of receiving is write processes such as specifying memory location. If need the filtration treatment data receiver, then comprise and receive data, data are carried out filtration treatment, the data after the filtration treatment are write the processes such as assigned address. Data send and then to comprise the data that read appointment, the data that read are write (or transmission) and arrive assigned address etc. If need the filtration treatment data to send, then comprise reading out data, data are carried out filtration treatment, the data after the filtration treatment write (or transmission) to processes such as assigned addresses.
When using dma controller from the peripheral module reading out data or writing out data, can dispose respectively two passages, one is written in the register of peripheral hardware after being used for the data in the memory are read, and this passage can be called as the transmission data channel; Another is written in the memory after being used for the data from the peripheral hardware register are read, and this passage can be called as the receive data passage.
Embodiment
Fig. 4 is that the inventive method adopts dma controller to carry out the schematic diagram of the embodiment data transmission procedure of data filter processing.Below respectively from data send, the present invention is further illustrated for two processes of Data Receiving.
1, data send
When CPU needed dma controller to carry out the data transmission and need carry out filtration treatment to data, CPU was 1 with the control position at first, has promptly enabled the data filter module in the dma controller according to the inventive method.When dma controller began to send data, at first, CPU calculated the frequency n (n in this example＞1) that data needs to be sent send according to the data length L and the each data length m that sends of dma controller of data to be sent, and p is not equal to 0.CPU is changed to m with the each data length that sends of dma controller, and the number of transmissions register is changed to n, starts DMA then, and the beginning data send.Owing to be to transmit data for the first time, indexed variable is 0, therefore, will directly send data designated.When in the process of transmitting of data, monitoring the 0x7E data first, confirm the beginning that this point is a HDLC Frame, these 0x7E data are directly sent, during data subsequently send, if when monitoring 0x7D, 0x7E or other control byte data, then dma controller will be carried out two secondary data transmit operations, promptly send earlier control escape byte data 0x7D, send the data that will read and the data behind the 0x20 XOR then.If last data of current transmission are 0x7D, 0x7E or other control byte, then dma controller will send control escape byte data 0x7D, and data of reading and the data behind the 0x20 XOR are kept in, and simultaneously indexed variable will be changed to 1.When transmission beginning next time, dma controller detects indexed variable once more, and this moment, indexed variable was 1, and therefore, dma controller then sends the temporary data of last transmission earlier, and indexed variable is changed to 0, sends data designated again.So repeatedly, the number of times that sends up to the dma controller data reaches n time.
2, receive data
Need dma controller to carry out Data Receiving according to the inventive method at CPU, and in the time of need carrying out filtration treatment to data, CPU should be 1 with the control position at first, promptly enabled the data filter module in the dma controller, data procedures is identical with sending, disposed the register of dma controller as CPU after, start the DMA transmission.When dma controller carries out Data Receiving, detect indexed variable earlier, owing to be to receive first, indexed variable is 0, dma controller directly carries out Data Receiving and it is write designated memory.When detecting first 0x7E data, confirm the beginning that this point is a HDLC Frame, directly these 0x7E data are write designated memory, in Data Receiving subsequently, if detect the 0x7D data, then these 0x7D data are abandoned, write designated memory behind data that the next one is received and the 0x20 XOR.If detected 0x7D data are exactly last data, then these data are abandoned, and indexed variable is changed to 1.When dma controller carries out Data Receiving once more, detect indexed variable earlier, because this moment, indexed variable was 1, writes designated memory and indexed variable is changed to 0 behind first data that dma controller will receive and the 0x20 XOR.So repeatedly, up to receiving the 0x7E data once more, these 0x7E data are write designated memory and end data reception.
The description of above-mentioned Data Receiving and transmission is carried out at a transmission channel, and in concrete enforcement a certain passage can be set fully is Data Receiving, and a certain passage is that data send, and both carry out simultaneously.Even a plurality of transmission channels can be set carry out transfer of data simultaneously.But just wherein the transmission of a certain passage or the processing procedure of reception are identical with foregoing description.
The present invention also can have other various embodiments; under the situation that does not deviate from spirit of the present invention and essence thereof; those skilled in the art work as can make various corresponding changes or distortion according to the present invention, but these corresponding changes or distortion all belong to claim protection range of the present invention.
Claims (2)
1. one kind is adopted dma controller to carry out the method that data filter is handled, adopt dma controller to carry out transfer of data, it is characterized in that: a module with data filter processing capacity is set in dma controller, the data filter module has an inner mark variable, it is indexed variable, when the data filter module enables, the data of transmission are carried out data filter and handle, comprising:
When dma controller sends data, detecting data filter inside modules indexed variable, is 1 as indexed variable, sends the temporary data of transmission last time earlier and sends data designated again and indexed variable is changed to 0; As indexed variable is 0, then directly sends specific data;
Dma controller sends in the data procedures, monitor first these data that are used for directly sending during data 0x7E that the flag data frame begins to finish with Frame, if when monitoring 0x7D, 0x7E or other control byte data once more, then send earlier control escape byte 0x7D data, send the data behind these data and the 0x20 XOR again; When last data that sends are 0x7D, 0x7E or other control byte, then only send control escape byte data 0x7D, simultaneously that the data behind these data and the 0x20 XOR are temporary, and indexed variable is changed to 1;
When dma controller receives data, detecting data filter inside modules indexed variable, is 1 as indexed variable, writes designated memory and indexed variable is changed to 0 behind first data that then will receive and the 0X20 XOR; As indexed variable is 0, then directly the data that receive is write designated memory;
Dma controller receives in the data procedures, be used for the flag data frame and begin the data 0x7E that finishes with Frame if detect first, then directly these data are write designated memory, if detect the 0x7D data, then these data are abandoned and will be write designated memory behind first data after these data and the 0x20 XOR, if detected 0x7D data are exactly last data, then these data are abandoned, and indexed variable is changed to 1, as detecting 0X7E once more, then these 0X7E data are write designated memory and stop Data Receiving;
In addition,
Dma controller is provided with the actual length register that reads or write data volume, be used to store the data length that dma controller reality reads or writes from designated memory, and, to be sent or receive and to have following relation between the frequency n of the data length m of length L, the each transmission of dma controller of data and dma controller transmission:
L=m * n+p, wherein 0≤p＜n
When data send, it is m that dma controller is transmitted the data length register configuration at every turn, if p is not equal to 0, then the number of times register configuration with dma controller is n, if p equals 0, then the number of transmissions register configuration with dma controller is n-1, after DMA finishes transmission, if it is q that CPU reads the value of length register in the dma controller, a then last L-q data are sent by CPU.
2. according to the described method of claim 1, it is characterized in that: the data filter module has one and enables control bit, this control bit has two kinds of possible values, be value be 1 or value be 0, and can be by the CPU assignment, value is to represent that the data filter module was enabled at 1 o'clock, and value is that 0 expression data filter module is not enabled.
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| CN106209306B (en) * | 2016-06-24 | 2019-05-31 | 北京智慧云行科技有限责任公司 | A kind of road transport vehicle satellite positioning system terminal means of communication and device |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1310905A (en) * | 1999-07-14 | 2001-08-29 | 信息产业部武汉邮电科学研究院 | Data transmission apparatus and method for transmitting data between physical layer side device and network layer device |
| CN1428971A (en) * | 2001-12-27 | 2003-07-09 | 北京润光泰力科技发展有限公司 | Method using multiplex channel to implement transmission of one line of network data |
| CN1472942A (en) * | 2002-07-29 | 2004-02-04 | 华为技术有限公司 | Byte transparent processing method to data flow |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1310905A (en) * | 1999-07-14 | 2001-08-29 | 信息产业部武汉邮电科学研究院 | Data transmission apparatus and method for transmitting data between physical layer side device and network layer device |
| CN1428971A (en) * | 2001-12-27 | 2003-07-09 | 北京润光泰力科技发展有限公司 | Method using multiplex channel to implement transmission of one line of network data |
| CN1472942A (en) * | 2002-07-29 | 2004-02-04 | 华为技术有限公司 | Byte transparent processing method to data flow |
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