JP2007048941A - Semiconductor device manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the influence of the compression stress due to a buried oxide film without greatly increasing the manufacturing process in a method of manufacturing a semiconductor device, and solves the trap of carriers due to a liner SiN film. <P>SOLUTION: After forming a polish stopper layer 2 on a semiconductor substrate 1 surface, element isolating trenches 3 are formed in the semiconductor substrate 1 through the stopper layer 2; a nitride liner film 4 composed of a SiN or SiON film is deposited to cover at least the inner surface of the trench 3, and then irradiated with plasma to reduce nitrogen in the liner film 4 deposited in the trenches 3. After an oxide film 7 is deposited to fill up the trenches 3, the oxide film 7 deposited to the stopper layer 2 is removed by polishing. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device characterized by a structure for reducing compressive stress applied to a trench sidewall of a shallow trench isolation (STI) structure and reducing traps. It is about.

  As one of element isolation methods in a semiconductor device, a trench isolation technique is known in which a trench is formed on the surface of a semiconductor substrate, and an insulator or polycrystalline silicon is embedded in the trench. It has been used in bipolar transistor LSIs that require area.

  In recent years, the application of trench isolation MOS transistor LSIs has progressed, but MOS transistor LSIs do not require element isolation as deep as bipolar transistor LSIs. Therefore, relatively shallow trenches having a depth of about 0.1 to 1.0 μm. The element isolation can be performed.

This structure is called Shallow Trench Isolation (STI). Here, the STI formation process will be described with reference to FIGS.
See FIG.
First, after the buffer oxide film 52 having a thickness of, for example, 10 nm is formed on the surface of the silicon substrate 51 by thermal oxidation, the thickness is, for example, 100 to 150 nm by using a CVD (chemical vapor deposition) method. A SiN film 53 serving as a stopper is formed.

Next, a resist pattern 54 is formed on the SiN film 53, and reactive ion etching (RIE) is performed using the resist pattern 54 as a mask, thereby forming a trench 55 having a depth of about 0.3 μm.
At this time, the region of the silicon substrate immediately below the resist pattern 54 is an element formation region.

  Next, after removing the resist pattern 54, a liner oxide film 56 having a thickness of, for example, 10 nm is formed on the surface of the silicon substrate 51 exposed in the trench 55 by performing thermal oxidation.

Next, the SiO ₂ film 57 is deposited on the entire surface by, for example, high density plasma (HDP) CVD method to completely fill the trench 55, and then, for example, annealing is performed at 900 ° C. to 1100 ° C. in a nitrogen atmosphere. The SiO ₂ film 57 deposited by the above is densified.

Next, by using the SiN film 53 as a stopper, etch back by chemical mechanical polishing (CMP) or reactive ion etching is performed to remove the unnecessary SiO ₂ film 57 and only into the trench 55 defined by the SiN film 53. The SiO ₂ film 57 is left.

See FIG.
Next, after removing the SiN film 53 by etching using hot phosphoric acid, the buffer oxide film 52 on the surface of the silicon substrate 51 is removed using dilute hydrofluoric acid.
At this time, the SiO ₂ film 57 filling the trench 55 is also etched.

Then, the exposed surface of the silicon substrate 51 is thermally oxidized after forming a sacrificial SiO ₂ film 58 on the surface, a desired conductivity type impurity into the surface layer of the silicon substrate 51 by ion implantation through the sacrificial SiO ₂ film 58, It is activated to form a well region 59 of a desired conductivity type on the silicon substrate 51, and then the sacrificial SiO ₂ film 58 is removed using dilute hydrofluoric acid.
In the step of removing the sacrificial SiO ₂ film 58, the exposed portion of the SiO ₂ film 57 is etched again, and a divot 60 is formed.

Next, the exposed surface of the silicon substrate 51 is thermally oxidized to form a gate insulating film 61 made of a SiO ₂ film having a desired thickness, and then a polycrystalline silicon film 62 is deposited on the entire surface.

See FIG.
Next, after forming the gate electrode 63 by patterning the polycrystalline silicon film 62, the gate electrode 63 is used as a mask, and an impurity having a conductivity type opposite to that of the well region 59 is ion-implanted and activated to form the extension region 64. Then, after forming a sidewall 65 on the side wall of the gate electrode 63, ions of a conductivity type opposite to that of the well region 59 are ion-implanted again using the sidewall 65 as a mask, and activated to form a high concentration source / drain region. 66 is formed.

  Next, after depositing an interlayer insulating film 67 on the entire surface, a contact hole reaching the source / drain region 66 is formed, and then this contact hole is filled with W or the like through a barrier metal to form a plug 68. The basic structure of the MOSFET is completed.

Such STI element isolation is suitable for miniaturization, but as shown in the lower part of FIG. 11, the shoulder portion of the SiO ₂ film 57 constituting the element isolation region is etched so that it is below the gate electrode 63. When the divot 60 is formed, the element formation region shoulder of the silicon substrate 51 is surrounded by the gate electrode 63 not only from the upper surface but also from the side surface in the channel width direction.

  In such a shape, the shoulder of the element formation region receives an electric field concentration from the flat portion when a voltage is applied to the gate electrode, and forms a parasitic transistor having a lower threshold voltage. This causes a hump characteristic in the -V characteristic.

Further, in the contact hole forming process, when the contact hole covers the element isolation region due to the displacement of the mask, if the divot 60 is formed in the SiO ₂ film 57, the contact hole is formed deeper than the surface of the active region. As a result, the distance between the plug 68 and the well region 59 under the source / drain region 66 is reduced, and there is a possibility that a leak current is generated in a tunnel or the like.
These leaks may cause deterioration of the decrease in saturation current.

Further, when heat treatment for densification of the SiO ₂ film 57 embedded in the trench 55 is performed, the element formation region surrounded by the SiO ₂ film 57 is compressed due to the difference in thermal expansion coefficient between SiO ₂ and Si. Will receive.

  When compressive stress is applied, the mobility of electrons in the active region of the silicon substrate 51 is greatly reduced, so that the saturation drain current is reduced. In particular, as the gate width is reduced with miniaturization, it is caused by the buried oxide film. In particular, the influence of compressive stress including the above on deterioration of the saturation drain current of NMOS is becoming more serious.

  In addition, the side surface of the trench may be re-oxidized by the moisture in the buried oxide film or the high-temperature oxidation process in a later process through the liner oxide film 56 on the inner surface of the trench. As a result, the volume expands and a compressive stress further acts on the trench side wall, thereby degrading the saturated drain current.

  Therefore, in order to prevent hump characteristics and leakage, it has been proposed to form a liner SiN film on the inner surface of the trench via a liner oxide film (see, for example, Patent Document 1).

Since the SiN film acts as tensile stress on Si, forming the liner SiN film cancels the compressive stress of the SiO ₂ film, and the stress acting on the side wall of the trench 55 is reduced, so that the saturated drain current is reduced. Deterioration is suppressed.
When the liner nitride film is provided, re-oxidation is suppressed and an increase in compressive stress is suppressed. From this point, it is considered that the deterioration of the saturation drain current is also suppressed.

  In addition, since the gate electrode 63 has a liner SiN film / liner oxide film laminated structure thicker than the gate insulating film 61 at the shoulder portion of the element isolation region, electric field concentration is reduced and parasitic transistors are generated. Will be suppressed.

Further, generally, as the gate width W is reduced, the reverse narrow channel effect appears in which the threshold value _Vth gradually decreases. However, when the liner SiN film is provided, the reverse narrow channel effect is not observed, so this situation is illustrated. Explanation will be made with reference to FIG.

See FIG.
FIG. 13 is an explanatory diagram of the dependence of V _{th on} the channel width W. As the gate width W is reduced, the reverse narrow channel effect is seen in which the threshold value V _th gradually decreases.
However, it can be seen that when the liner SiN film is provided, _Vth is substantially constant and the reverse narrow channel effect is not observed.
This is presumably because the provision of the liner SiN film suppresses the generation of the above-described parasitic transistor and the contribution of the parasitic transistor is small.

However, when the liner SiN film is provided as described above, the nitride film easily traps charges such as electrons. Therefore, in the shoulder of the element formation region where the liner SiN film and the gate electrode overlap, carriers flowing in the channel However, due to the proximity to the liner SiN film, electrons are trapped in the liner SiN film due to the hot carrier effect, causing a problem that V _th shifts.

Therefore, in order to solve such a problem, the upper portion of the SiO ₂ film embedded in the trench is removed, and the exposed liner SiN film is thermally oxidized to be converted into an oxide film. It has been proposed to suppress _th shift (see, for example, Patent Document 2).
JP 2003-273206 A JP 2004-311487 A

However, in the case of the above-mentioned Patent Document 2, although the shift of V _th is suppressed, a buried oxide film removing step and a thermal oxidation step are required, and a buried oxide film removing portion is further provided. Furthermore, a process of embedding with an oxide film is required, which increases the number of manufacturing processes, resulting in a decrease in throughput and an increase in manufacturing cost.

  Accordingly, an object of the present invention is to reduce the influence of the compressive stress caused by the buried oxide film and eliminate the carrier trap caused by the liner SiN film without significantly increasing the number of manufacturing steps.

FIG. 1 is a diagram illustrating the basic configuration of the present invention. Means for solving the problems in the present invention will be described with reference to FIG.
In order to solve the above-described problem, the present invention provides a method of forming a polishing stopper layer 2 on a surface of a semiconductor substrate 1 in a method for manufacturing a semiconductor device, and an element formed on the semiconductor substrate 1 via the stopper layer 2. A step of forming the isolation trench 3, a step of depositing a nitride liner film 4 made of a SiN film or a SiON film so as to cover at least the inner surface of the trench 3, and a nitride liner deposited in the trench 3 by plasma irradiation A step of depositing an oxide film 7 after reducing nitrogen in the film 4 to fill the trench 3; and a step of removing the oxide film 7 deposited on the stopper layer 2 by polishing. And

  In this way, before the trench 3 is filled with the oxide film 7, the nitrogen concentration in the nitride liner film 4 is reduced by plasma treatment, thereby reducing the sites that are the source of charge traps and suppressing deterioration due to hot carriers. can do.

  Even when nitrogen is no longer detected due to a decrease in the nitrogen concentration in the nitriding liner film 4, deterioration of the saturation drain current is suppressed. Since the treated liner film 6 is converted into a high-quality oxide film 7 having excellent barrier properties, it is considered that the compressive stress canceling function is not impaired.

  In addition, since the plasma treatment liner film 6 exists even when the nitrogen concentration is lowered, a gate electrode is provided through the plasma treatment liner film 6 in the shoulder portion of the element formation region, so that generation of a parasitic transistor is suppressed. The

  In this case, it is desirable that the nitrogen in the nitride liner film 4 is reduced by the plasma irradiation so that the nitrogen in the nitride liner film 4 is 30% or less in terms of the atomic ratio to Si in the film. The compressive stress can be reduced without causing deterioration due to the capture of hot carriers.

As the gas species used in the plasma irradiation process, O ₂ , N ₂ O, He, Ar, CO ₂ , or a gas of H ₂ or a combination thereof is desirable. In the case of non-oxidizing plasma, An oxidation treatment may be performed after the plasma irradiation.

Further, in the step of depositing the oxide film 7, it is desirable to use a plasma vapor chemical growth method to form the dense buried oxide film 7, and a plasma CVD method using TEOS-O ₃ may be used. A high-density plasma vapor chemical growth method (HDP-CVD method) using SiH ₄ —O ₂ is desirable.

  In addition, it is desirable that the plasma irradiation process is performed in a plasma vapor phase chemical growth apparatus, so that the oxide film 7 can be continuously deposited without exposing the plasma-treated substrate to the atmosphere. , Improving quality and throughput.

  In addition, when performing an oxidation process after a plasma irradiation process, it is desirable to perform a plasma oxidation process continuously after a plasma irradiation process in a plasma vapor phase chemical growth apparatus.

In the present invention, since the nitrogen in the nitride liner film is reduced after the formation of the nitride liner film for reducing the compressive stress, the compressive stress can be reduced without causing the V _th fluctuation due to the charge trap. This makes it possible to suppress the occurrence of the hump effect and the reverse narrow channel effect.

In the present invention, after forming a polishing stopper layer on the surface of the semiconductor substrate, an element isolation trench is formed in the semiconductor substrate through the stopper layer, and then the SiN film or SiON film is formed so as to cover the inner surface of the trench. After depositing the nitride liner film to be formed, any of O ₂ , N ₂ O, He, Ar, CO ₂ , or H ₂ is preferably irradiated by plasma irradiation in a plasma CVD apparatus, particularly in an HDP-CVD apparatus. Irradiation with a plasma with a gas of these or a combination thereof reduces nitrogen in the nitride liner film deposited in the trench to 30% or less in terms of atomic ratio to Si in the film, and then deposits an oxide film. After filling the trench, the oxide film deposited on the stopper layer is removed by polishing, particularly chemical mechanical polishing (CMP).

Here, with reference to FIG. 2 thru | or FIG. 4, the manufacturing process of MOSFET of Example 1 of this invention is demonstrated.
See Figure 2
First, the surface of the p-type silicon substrate 11 is wet oxidized at a substrate temperature of 800 ° C., for example, to form a buffer oxide film 12 having a thickness of, for example, 5 nm, and then, for example, dichlorosilane as a raw material at a substrate temperature of 775 ° C. The stopper layer 13 made of a SiN film having a thickness of, for example, 110 nm is formed by a CVD method using ammonia and ammonia.

  Next, a resist pattern 14 having an opening 15 corresponding to an element isolation region formation region is formed on the stopper layer 13, and reactive ion etching is performed using the resist pattern 14 as a mask to form an STI trench 16. .

In this case, the region defined by the resist pattern 14 becomes an element formation region, and has a size of 1 μm × 1 μm, for example.
In addition, with the recent high integration of semiconductor devices, the density of semiconductor elements is also increasing. Here, the width of the trench 16 is, for example, 140 nm and the depth is 350 nm.

  Next, a liner oxide film 17 having a thickness of, for example, 3 nm is formed on the surface of the p-type silicon substrate 11 exposed in the trench 16 by dry oxidation after the resist pattern 14 is removed.

Next, a liner SiN film 18 having a thickness of 3 to 20 nm, for example, 6 nm, is formed on the entire surface by a CVD method using dichlorosilane and ammonia as source gases.
The liner SiN film 18 is used to suppress reoxidation of the trench side walls in a heat treatment in a high-temperature oxidizing atmosphere for densifying the buried oxide film described later.

  If the trench sidewall is re-oxidized after filling, the oxide film region at the interface reacts with Si during the oxide film formation and expands, causing compressive stress on the trench interface and causing deterioration of characteristics. Suppression suppresses deterioration of characteristics.

Next, in the HDP-CVD apparatus (internal capacity: 57000 cc), for example, 160 sccm of O ₂ and 500 sccm of He were flowed, and high frequency RF power of 13.56 MHz introduced in a coil shape on the outer periphery of the ceramic dome was from the time of film formation. Higher 4500 W is supplied, and plasma irradiation is performed at a substrate temperature of 450 ° C. for 90 seconds.
By this plasma irradiation, N in the liner SiN film is reduced and converted to the replacement oxide film 19.

See Figure 3
Subsequently, in the HDP-CVD apparatus, for example, SiH ₄ is flowed at 120 sccm, O ₂ is flowed at 160 sccm, and He is flowed at 500 sccm. A high frequency RF power of 13.56 MHz introduced in a coil shape on the outer periphery of the ceramic dome is 3000 W, electrostatic chuck The plasma oxide film 20 having a thickness of, for example, 450 nm is deposited so as to completely fill the trench 16 with 2000 W of high frequency RF power of 400 kHz.

Next, the plasma oxide film 20 and the replacement oxide film 19 deposited on the stopper layer 13 are removed by chemical mechanical polishing, and a buried oxide film 21 is formed in the trench 16.
At this time, a part of the stopper layer 13 may be polished.

  Next, for example, annealing is performed at 1000 ° C. in a non-oxidizing atmosphere, the buried oxide film 21 is densified to improve hydrofluoric acid resistance, and the occurrence of divots in the etching process described later is suppressed as much as possible.

  Thereafter, similarly to the conventional MOSFET manufacturing process, hot phosphoric acid is used to remove the stopper layer 13 made of the SiN film, and then the exposed buffer oxide film 12 is removed by etching with hydrofluoric acid.

See Figure 4
Next, after forming a through oxide film 22 on the exposed surface of the silicon substrate, a p-type well region 23 is formed by ion implantation of B through the through oxide film 22, and then the through oxide film 22 is removed. Thereafter, a gate oxide film 24 having a thickness of, for example, 3 nm is formed on the exposed surface of the p-type well region 23 by thermal oxidation, a polycrystalline silicon film is formed on the entire surface, and then patterned to form a gate electrode. 25 is formed.

Next, an n-type extension region 26 is formed by implanting As ions using the gate electrode 25 as a mask, and then an SiO ₂ film is deposited on the entire surface, and anisotropic etching is performed by reactive ion etching to form the sidewall 27. Form.

Next, As ions are implanted again using the sidewall 27 as a mask, thereby forming n ⁺ type source / drain regions 28.

Next, a Co film is deposited on the entire surface, and then heat treatment is performed to form Co silicide films 29 and 30 on the surfaces of the n ⁺ -type source / drain regions 28 and the gate electrode 25, and the unreacted Co film is washed out. After that, a secondary heat treatment is performed to convert the Co silicide films 29 and 30 into low resistance phase Co silicide.

Next, an etching stopper layer 31 made of a SiN film and an interlayer insulating film 32 made of a plasma TEOS-NSG film are sequentially formed on the entire surface, and then the surface of the interlayer insulating film 32 is flattened, and then n ⁺ type source / drain A contact hole reaching the region 28 is formed.

Next, for example, after depositing a glue layer 33 made of TiN, for example, a W layer 34 is deposited by CVD to completely fill the contact hole, and then an unnecessary metal layer on the interlayer insulating film 32 is formed by CMP. By removing and forming the plug 35, the basic structure of the MOSFET is completed.
Thereafter, a MOS type LSI is completed by forming a multilayer wiring structure as necessary.

Next, with reference to FIGS. 5 to 9, the effect of plasma treatment of the liner SiN film, which is a feature of the present invention, will be described.
See Figure 5
FIG. 5 is an explanatory diagram of the dependence of the nitrogen concentration reduction in the liner SiN film on the processing conditions. Nitrogen in the liner SiN film when plasma irradiation is performed on the SiN film having a thickness of 6 nm under various conditions. The result of having measured the density | concentration by XPS method is shown.

Here, two types of plasma gas, O ₂ + He and He, were used, and the plasma treatment was performed with a high frequency RF power of 13.56 MHz set to 2500 W, 4500 W, and 5500 W, and an irradiation time fixed to 90 seconds.
In this case, the flow rates of O ₂ and He were 250 sccm and 500 sccm in the case of O ₂ + He, and 500 sccm in the case of He alone.

As is apparent from the figure, the ratio of N in the liner SiN film is about 40% immediately after the growth, but it can be seen that N is significantly reduced by the plasma irradiation.
It can also be seen that the higher the RF power, the higher the N concentration reduction effect, and the addition of O ₂ as a gas species has a higher reduction effect compared to the case of He alone.
Note that the O ₂ ratio in the film in the case of He alone is due to adhesion of O ₂ or H ₂ O in the atmosphere or oxidation caused by them when taken out into the atmosphere after plasma irradiation.

Incidentally, it was found that in the system to which O ₂ was added, the N concentration could be reduced to almost zero level when the RF power was increased to 4500 W or more.
The processing time is also sensitive, and if the processing time is extended, the nitrogen concentration in the film can be reduced. However, as described above, the nitrogen concentration can be reduced by combining the power, gas type, and processing time. As can be seen, more preferably, the N concentration should be reduced to approximately zero level.

However, for the liner nitride film laid on the inner surface of the trench in the STI structure, it is considered that the effect of plasma irradiation is different between the bottom surface and the side wall. The presence of the liner nitride film by shaking was investigated using TEM and EELS.
As an example, after processing 90 seconds for He; 250 Sccm, O ₂ ; 500 sccm, and high-frequency power output of 4500 W and 5500 W, respectively, a buried oxide film by high-density plasma was grown and compared.

See FIG.
FIG. 6 is a TEM image (copy) of the element formation region when the RF power is 4500 W, and a liner SiN film 43 of 1 to ₂ nm is formed on the side surface of the Si element formation region 41 via a thin liner SiO ₂ film 42. The image of is confirmed.
In this case, since the film thickness of the liner SiN film 43 before the plasma treatment is about 6 nm, a considerable decrease is observed, but this is not reduced by the plasma etching, but N is desorbed from the liner SiN film 43. This is because the oxide film is replaced.

See FIG.
FIG. 7 is a TEM image (copy) of the element formation region when the RF power is 5500 W, and no image of the liner SiN film 43 is seen on the side surface of the Si element formation region 41.
In this case, it is considered that the liner SiN film 43 is entirely replaced with an oxide film.

See FIG.
FIG. 8 is a TEM image (schematic diagram) after removal of the stopper layer and subsequent etching of the oxide film when the RF power is 4500 W. Similar to the case of FIG. 6, the liner SiN film is formed on the side surface of the Si element formation region 41. Although an image of 43 is visible, the liner SiN film 43 is not confirmed at the bottom of the trench.
This is presumably because the effect of plasma irradiation decreases irradiation of active species at the side wall portion rather than at the flat portion.

  Next, using the EELS method for the location where the liner SiN film exists for each sample, the nitrogen reaction is observed in the 4500 W sample in accordance with the location confirmed by the TEM image when the correspondence is taken with the nitrogen element MAP. In contrast, in the 5500 W sample, the reaction of nitrogen was observed only at the background level, and it was confirmed that the 5500 W sample did not exist as a SiN film in the liner portion.

FIG. 9 is an explanatory diagram of the reverse narrow channel effect of the MOSFET prepared in Example 1, and almost no reverse narrow channel effect was observed as in the case of the MOSFET provided with the conventional liner SiN film.

As described above, in Example 1 of the present invention, after the liner SiN film is provided, nitrogen is reduced by plasma irradiation, so both improvement of characteristics against hot carriers due to charge traps and suppression of _Vth fluctuations are achieved. can do.

  Although the embodiments of the present invention have been described above, the present invention is not limited to the configurations and conditions described in the embodiments, and various modifications are possible. For example, in the embodiments, an n-channel MOSFET is used. However, this is naturally applicable to p-channel MOSFETs.

In the above embodiment, dichlorosilane and ammonia are used as the source gas in the liner SiN film deposition step, but it is also possible to use binary butylaminosilane (BTBAS) and ammonia.

  In the above embodiment, the liner film is composed of the SiN film. However, the liner film is not necessarily a pure SiN film, and the SiON film may be used as the liner film.

In the above embodiment, the buried oxide film is deposited by the HDP-CVD method, but a normal plasma CVD method using TEOS-O ₂ may be used.

In the above embodiment, the plasma treatment for reducing nitrogen is performed using O ₂ + He plasma. However, the plasma treatment is not limited to such plasma, and He alone or Ar, N ₂ may be used. O, CO ₂ , or H ₂ may be used alone or mixed with other gas species.

For example, when a parallel plate type apparatus is used as the HDP-CVD apparatus, the oxidizing gas species at the time of film formation is low reactive N ₂ O or CO in order to suppress the reaction with SiH ₄ in the shower head. _{Since 2} is used, the plasma treatment can also suppress the increase in required gas species by using N ₂ O or CO ₂ .

When plasma processing is performed using non-oxidizing plasma such as He, Ar, or H ₂ , although N is reduced, the liner film is reduced by Si, so that it is necessary to perform oxidation after the plasma processing. In particular, it is desirable to perform plasma oxidation continuously in the same CVD apparatus.
In addition, when H ₂ is used, the film is slightly reduced by the plasma etching action, so it is necessary to form a liner nitride film in anticipation of the reduced film thickness.

  In the above embodiment, the plasma irradiation and the deposition of the buried oxide film are continuously performed in the same plasma CVD apparatus. However, it is not necessarily performed in the same apparatus, for example, via a gate valve. It may be performed using a plasma processing apparatus connected to a plasma CVD apparatus.

  In the above embodiment, the interlayer insulating film is composed of the TEOS plasma oxide film, but other oxide films such as PSG, BPSG, or a high density plasma oxide film may be used.

The detailed features of the present invention will be described again with reference to FIG. 1 again.
Again see Figure 1
(Additional remark 1) The process of forming the stopper layer 2 of grinding | polishing on the semiconductor substrate 1 surface, the process of forming the element isolation trench 3 in the semiconductor substrate 1 through the said stopper layer 2, the inner surface of the said trench 3 is covered at least In this way, the nitride liner film 4 made of SiN film or SiON film is deposited, the nitrogen in the nitride liner film deposited in the trench 3 is reduced by plasma irradiation, and then the oxide film 7 is deposited to form the trench. 3. A method for manufacturing a semiconductor device, comprising: a step of embedding 3 and a step of removing the oxide film 7 deposited on the stopper layer 2 by polishing.
(Supplementary note 2) The method of manufacturing a semiconductor device according to supplementary note 1, wherein nitrogen in the nitride-based liner film 4 is reduced to 30% or less by an atomic ratio with respect to Si in the film by the plasma irradiation.
(Supplementary Note 3) The plasma irradiation _{step, O 2, N 2 O,} He, Ar, CO 2, or, characterized in that it is a step of irradiating the plasma 5 of H ₂ any or a combination thereof gases A method for manufacturing a semiconductor device according to appendix 1 or 2.
(Additional remark 4) The manufacturing method of the semiconductor device of any one of additional remark 1 thru | or 3 using the plasma vapor phase chemical growth method in the deposition process of the said oxide film 7. FIG.
(Supplementary note 5) The method for producing a semiconductor device according to supplementary note 4, wherein the plasma vapor chemical growth method is a high-density plasma vapor chemical growth method.
(Additional remark 6) The said plasma irradiation process is performed within a plasma vapor phase chemical growth apparatus, The manufacturing method of the semiconductor device of Additional remark 4 or 5 characterized by the above-mentioned.
(Additional remark 7) The manufacturing method of the semiconductor device of Additional remark 6 characterized by performing a plasma oxidation process after the said plasma irradiation process.

  As a practical example of the present invention, a MOS type integrated circuit device is typical, but it is also applied to a bipolar type integrated circuit device.

It is explanatory drawing of the fundamental structure of this invention. It is explanatory drawing of the manufacturing process to the middle of MOSFET of Example 1 of this invention. It is explanatory drawing of the manufacturing process to the middle after FIG. 2 of MOSFET of Example 1 of this invention. It is explanatory drawing of the manufacturing process after FIG. 3 of MOSFET of Example 1 of this invention. It is explanatory drawing of process condition dependence of the nitrogen concentration reduction | decrease in a liner SiN film | membrane. It is a TEM image (copy figure) of an element formation area when RF power is 4500W. It is a TEM image (copy figure) of an element formation area when RF power is 5500W. It is a TEM image (copy figure) after stopper layer removal and subsequent oxide film etching when the RF power is 4500 W. It is explanatory drawing of the reverse narrow channel effect of MOSFET produced in Example 1. FIG. It is explanatory drawing of the formation process to the middle of the conventional STI structure. It is explanatory drawing of the formation process until the middle of FIG. 10 after the conventional STI structure. It is explanatory drawing of the formation process after FIG. 11 of the conventional STI structure. It is explanatory drawing of the channel width W dependence of _Vth .

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Stopper layer 3 Trench 4 Nitride-type liner film 5 Plasma 6 Plasma processing liner film 7 Oxide film 11 P-type silicon substrate 12 Buffer oxide film 13 Stopper layer 14 Resist pattern 15 Opening 16 Trench 17 Liner oxide film 18 Liner SiN Film 19 Replacement oxide film 20 Plasma oxide film 21 Buried oxide film 22 Through oxide film 23 P-type well region 24 Gate oxide film 25 Gate electrode 26 n-type extension region 27 Side wall 28 n ⁺ type source / drain region 29 Co silicide film 30 Co silicide film 31 Etching stopper layer 32 Interlayer insulating film 33 Glue layer 34 W layer 35 Plug 41 Si element formation region 42 Liner SiO ₂ film 43 Liner SiN film 44 Buffer oxide film 45 Stopper layer 46 Buried oxide film 47 Divot G 51 Silicon substrate 52 Buffer oxide film 53 SiN film 54 Resist pattern 55 Trench 56 Liner oxide film 57 SiO ₂ film 58 Sacrificial SiO ₂ film 59 Well region 60 Divot 61 Gate insulating film 62 Polycrystalline silicon film 63 Gate electrode 64 Extension region 65 Side wall 66 Source / drain region 67 Interlayer insulating film 68 Plug

Claims (5)

A step of forming a polishing stopper layer on the surface of the semiconductor substrate, a step of forming an element isolation trench in the semiconductor substrate via the stopper layer, and a nitridation made of a SiN film or a SiON film so as to cover at least the inner surface of the trench Depositing a base liner film, reducing nitrogen in the nitride liner film deposited in the trench by plasma irradiation, depositing an oxide film and embedding the trench, and depositing on the stopper layer A method of manufacturing a semiconductor device, comprising a step of removing the oxide film by polishing. 2. The plasma irradiation step according to claim 1, wherein the plasma irradiation step is a step of irradiating plasma of a gas of any one of O ₂ , N ₂ O, He, Ar, CO ₂ , H ₂ , or a combination thereof. A method for manufacturing a semiconductor device. 3. The method of manufacturing a semiconductor device according to claim 1, wherein plasma oxide chemical growth is used in the oxide film deposition step. 4. The method of manufacturing a semiconductor device according to claim 3, wherein the plasma vapor chemical growth method is a high density plasma vapor chemical growth method. 5. The method of manufacturing a semiconductor device according to claim 3, wherein the plasma irradiation step is performed in a plasma vapor phase chemical growth apparatus.

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