JP2007048895A - Solid-state imaging apparatus and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a CCD solid-state imaging apparatus which can be improved in read-out property while being controlled with the degradation over time. <P>SOLUTION: The solid-state imaging apparatus includes a semiconductor substrate which defines a two-dimensional surface; many photoelectric conversion elements arranged in a light receiving region of the semiconductor substrate; perpendicular charge transfer device which includes a plurality of perpendicular charge transfer channels which meander between series of photoelectric conversion elements, in a direction perpendicular to the series of these elements and a plurality of transfer electrodes which are formed above the perpendicular charger transfer channels, and are arranged in a direction parallel to the series of photoelectric conversion elements; read-out electrodes which also serve for the transfer electrodes which constitute the perpendicular charge transfer device; read-out portions which correspond to the plurality of photoelectric conversion elements, respectively, each reading out signal charge accumulated, in the corresponding photoelectric conversion element to the perpendicular charge transfer channel adjacent thereto in the row direction; and gate oxide film consisting of a single layer of oxide film formed between the perpendicular charge transfer channel and the transfer electrode, with the thickness in the read-out portions being smaller than the other portions. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a solid-state imaging device and a manufacturing method thereof, and more particularly to a solid-state imaging device having an oxide film single-layer gate insulating film and a manufacturing method thereof.

  FIG. 8 is an enlarged schematic cross-sectional view of the vicinity of the gate insulating film of the solid-state imaging device 200 according to the first conventional example.

  A vertical transfer channel 54 is formed corresponding to each column of the photoelectric conversion elements 52, and signal charges read out through the read gate channel region 51c formed adjacent to each photoelectric conversion element 52 are transferred in the vertical direction. . A two-layer polysilicon transfer electrode 56 is formed above the vertical transfer channel 54 with the insulating film 55 interposed therebetween. In the cross section of this portion, only the first layer polysilicon electrode or the second layer polysilicon electrode exists above the vertical transfer channel 54.

  As the insulating film 55 including the read gate insulating film 55g formed on the read gate channel region 51c, an ONO film formed by stacking an oxide film 55a, a nitride film 55b, and an oxide film 55c is used. Yes. In such an ONO film structure, a high electric field pulse is applied at the time of reading, and hot carriers generated at that time are trapped in the ONO film, and a change in pulse voltage necessary for reading occurs with time.

  FIG. 9 is an enlarged schematic cross-sectional view of the vicinity of the gate insulating film of the solid-state imaging device 300 according to the second conventional example.

  In the second conventional example, in order to avoid the change with time of the pulse voltage at the time of reading as described above, only the gate insulating film 55g of the insulating film 55 having the ONO film structure is formed as a single oxide film layer as shown in the figure. (For example, refer to Patent Document 1). In the method in which only the gate insulating film 55g on the read gate portion 51c is formed as a single oxide film, the oxide film thickness is reduced as the single oxide film is formed. ing. However, the portion other than the gate insulating film 55g on the gate portion 51c has an ONO film structure, and the ONO film structure may start to cause deterioration of transfer over time as the solid-state imaging device is miniaturized. The problem of characteristics that easily trap carriers is becoming apparent.

  In order to solve the above-mentioned problems related to the ONO film structure, it is preferable to stop using the ONO film and form the gate insulating film as a single oxide film, but this is done with the conventional two-layer polysilicon electrode structure. In this case, there is a possibility of causing a fatal characteristic failure as a CCD such as transfer efficiency deterioration. This is because, for example, the gate insulating film under the second phase polysilicon electrode becomes thick due to the formation of the interlayer insulating film after the formation of the first layer polysilicon electrode, or the second layer polysilicon under the first layer polysilicon electrode. It is caused by the electrode remaining.

  Therefore, it can be considered that the electrode structure is a single-layer polyelectrode structure (see, for example, Patent Document 2). However, simply combining the oxide single-layer gate insulating film and the single-layer polysilicon electrode structure can solve the reliability-related problems such as transfer deterioration over time, but the effect of improving the read characteristics can be obtained. I can't.

JP 2003-332556 A JP 2005-32756 A

  An object of the present invention is to provide a CCD type solid-state imaging device capable of improving readout characteristics while suppressing the problem of deterioration over time.

  Another object of the present invention is to provide a method for manufacturing a CCD solid-state imaging device capable of improving readout characteristics while suppressing the problem of deterioration with time.

  According to one aspect of the present invention, a solid-state imaging device includes a semiconductor substrate that defines a two-dimensional surface, a large number of photoelectric conversion elements disposed in a light receiving region of the semiconductor substrate, and a row of photoelectric conversion elements. A vertical charge transfer device including a plurality of vertical charge transfer channels arranged in the vertical direction and a plurality of transfer electrodes formed above the vertical charge transfer channel and arranged in the horizontal direction, and transfer electrodes constituting the vertical charge transfer device A readout unit that also serves as a read-out electrode, corresponds to each of the plurality of photoelectric conversion elements, and reads out signal charges accumulated in the corresponding photoelectric conversion elements to the vertical charge transfer channel adjacent in the row direction; And a gate oxide film formed as a single oxide film layer between the vertical charge transfer channel and the transfer electrode, and having a thickness smaller than that of the other part in the readout portion.

  According to the present invention, it is possible to provide a CCD type solid-state imaging device capable of improving the readout characteristics while suppressing the problem of deterioration with time.

  In addition, according to the present invention, it is possible to provide a method for manufacturing a CCD solid-state imaging device capable of improving readout characteristics while suppressing the problem of deterioration with time.

  FIG. 1 is a block diagram showing a configuration of a CCD type solid-state imaging device 1 according to an embodiment of the present invention. A state where a part of the insulating film on the semiconductor substrate is peeled off to expose the photoelectric conversion element and VCCD is shown. FIG. 2 is a schematic plan view of a part of the light receiving region 2 of the solid-state imaging device 1.

  The solid-state imaging device 1 includes a light receiving region 2 in which a large number of photoelectric conversion devices 12 are arranged. The light receiving region 2 is configured by arranging a large number of photoelectric conversion elements 12 in a so-called pixel shifted arrangement. Here, the “pixel shifting arrangement” referred to in this specification refers to an arrangement in which a first lattice of a two-dimensional tetragonal matrix and a second lattice having lattice points at positions between the lattices are combined. For example, for each photoelectric conversion element 12 in the odd-numbered column (row), each of the photoelectric conversion elements 12 in the even-numbered column (row) is approximately ½ of the column (row) direction pitch of the photoelectric conversion element 12. Shifting in the (row) direction, each of the photoelectric conversion element columns (rows) includes only the photoelectric conversion elements 12 in the odd-numbered rows (columns) or even-numbered rows (columns). “Pixel shifting arrangement” is a form in which a large number of photoelectric conversion elements 12 are arranged in a matrix over a plurality of rows and columns.

  Note that the pitch “about ½” includes ½, but it is out of ½ due to factors such as manufacturing error and rounding error of pixel position that occurs in design or mask fabrication. Further, it includes values that can be regarded as substantially equivalent to ½ in view of the performance of the solid-state imaging device 1 and the image quality of the image. The same applies to the above-mentioned “about 1/2 of the pitch of the photoelectric conversion elements 12 in the photoelectric conversion element row”.

  An n-type transfer channel region (vertical transfer channel) 14 that reads out signal charges generated in the photoelectric conversion elements 12 and transfers them in the vertical direction is provided between the columns of the photoelectric conversion elements 12. It is provided to meander in the vertical direction. A meandering transfer channel is arranged in a gap formed between pixels in a pixel-shifted arrangement, and adjacent transfer channels are separated via a photoelectric conversion element or close to each other with a channel stop region 13 (FIG. 3) interposed therebetween. . Most of the area of the semiconductor substrate of the light receiving portion is effectively utilized by the photoelectric conversion element and the transfer channel.

  Above the vertical transfer channel 14, a transfer electrode 16 is formed across a plurality of rows in the horizontal direction so as to meander the gap between the photoelectric conversion elements 12 with a single-layer oxide film 15 described later interposed therebetween. The transfer electrodes 16 in each row form a vertical charge transfer path (VCCD) together with the vertical transfer channel 14, and transfer the signal charges generated in the photoelectric conversion element 12 in the vertical direction by four-phase drive pulses (Φ1 to Φ4).

An electrode gap (interelectrode gap) is provided between the transfer electrodes 16 driven at different phases (interval in the arrangement direction of the transfer electrodes 16), and an insulating film made of, for example, SiO ₂ is provided in the interelectrode gap. 17 is formed. The distance between the transfer electrodes 16 is the same in all parts, and is preferably about 0.3 μm or less, in order to make the flow of charges in the transfer channel 14 smooth, and is about 0.1 μm to about 0. A thickness of 2 μm is particularly preferable. The four transfer electrodes 16 form one transfer stage.

  Here, the single-layer electrode (structure) referred to in the present specification refers to a so-called conventional multilayer polysilicon electrode (structure), and a plurality of electrodes are the same without overlapping each other at the electrode end. It is a structure arranged with a narrow gap on a plane. Therefore, in the present specification, the single layer electrode structure includes not only a single metal material (for example, tungsten (W) etc.) but also a laminated structure of metals such as tungsten silicide and polysilicon and tungsten. Thus, by using the transfer electrode 16 as a single-layer electrode formed on the same plane, an interlayer insulating film provided between layers in the multilayer electrode structure becomes unnecessary.

  The transfer electrode 16 can be configured using an electrode material generally used in a semiconductor manufacturing process or a solid-state device. Since the transfer electrode 16 has a single-layer electrode structure, an insulating film (silicon oxide film) that insulates between the electrode layers becomes unnecessary, and the selection range of the electrode material is widened. In addition, the electrode width such as the electrode width and the electrode thickness also has a wider design width depending on the electrode material.

  In the figure, a horizontal charge transfer path (HCCD) 3 for transferring charges transferred by the VCCD to the peripheral circuit 4 for each row is formed below the light receiving region 2.

  In addition, a peripheral circuit 4 constituted by, for example, a MOS (Metal Oxide Semiconductor) transistor circuit or the like is also formed outside the light receiving region 2. The peripheral circuit 4 includes, for example, a floating diffusion amplifier (FDA).

  FIG. 3 is an enlarged cross-sectional view of the solid-state imaging device 1 shown in FIG. FIG. 4 is an enlarged view of the periphery of the readout gate channel region 11c and the gate electrode 16g in the solid-state imaging device 1 shown in FIG.

In the following description, in order to distinguish between large and small impurity concentrations between impurity doped regions having the same conductivity type, a p ⁻ type impurity doped region and a p type impurity doped region are ordered in descending order of impurity concentration. It is expressed as a region, a p ⁺ -type impurity added region, or an n ⁻ -type impurity added region, an n-type impurity added region, and an n ⁺ -type impurity added region. Except for the case where the p ⁻ -type impurity doped region 11b is formed by an epitaxial growth method, all the impurity doped regions are preferably formed by ion implantation and subsequent heat treatment.

The semiconductor substrate 11 includes, for example, an n ⁻ type silicon substrate 11a and a p ⁻ type impurity addition region 11b formed on one surface thereof. The p ⁻ -type impurity doped region 11b is formed by performing heat treatment after ion-implanting p-type impurities into one surface of the n ⁻ -type silicon substrate 11a, or by adding silicon containing p-type impurities to one surface of the n-type silicon substrate 11a. It is formed by epitaxial growth on the surface.

Next, an n-type impurity doped region (vertical transfer channel) 14 is formed in the p ⁻ -type impurity doped region 11b corresponding to one photoelectric conversion element row formed later. Each vertical transfer channel 14 has a substantially uniform impurity concentration over its entire length, and extends along a corresponding photoelectric conversion element array.

Next, the channel stop region 13 is formed around the photoelectric conversion element 12 and the vertical charge transfer channel 14 formed in a plan view after the formation of the read gate channel region 11c is removed. The channel stop region 13 is configured by, for example, a p ⁺ -type impurity doped region, or trench isolation or local oxidation (LOCOS). Thus, element isolation of the light receiving region 2 is performed in the same process.

  A part of the p-type impurity addition region 11c is left along the right edge of each photoelectric conversion element 12 (n-type impurity addition region 12a) to be formed later. The length of the p-type impurity added region 11c in the column direction is, for example, about half of the length of the corresponding photoelectric conversion element 12 in the column direction. Each p-type impurity doped region 11c is used as a read gate channel region 11c.

Next, an oxide film single-layer gate insulating film (SiO ₂ film) 15 is formed on the surface of the semiconductor substrate 11. In the step of forming the oxide single-layer gate insulating film 15, first, a silicon oxide film (first film having a thickness of 40 nm is formed by thermal oxidation, for example, in the p ⁻ -type impurity doped region 11b formed in the n-type silicon substrate 11a. Oxide film) 15a. Thereafter, patterning is performed by photolithography or the like, and the silicon oxide film 15a above the read gate channel region 11c is etched by dry etching or wet etching. Next, a silicon oxide film 15b (second oxide film) is formed by thermal oxidation so that the film thickness on the silicon substrate 11 above the read gate channel region 11c is 25 nm. Note that both or one of the first oxide film 15a and the second oxide film 15b may be formed as an HTO film by CVD instead of being formed by thermal oxidation. As a result, as shown in the drawing, it is possible to form the oxide single-layer gate insulating film 15 having different thicknesses above the reading gate channel region 11c (reading portion gate insulating film 15g) and other regions. The film thickness of each region is, for example, 25 nm above the read gate channel region 11c (read gate insulating film 15g) and 55 nm in the other regions. Thus, by forming the oxide single-layer gate insulating film 15, the thickness of the gate insulating film 15g above the reading gate channel region 11c (reading portion gate insulating film 15g) is changed to the gate insulating film 15 in other regions. 50% or less of the film thickness. Note that the thickness of the readout portion gate insulating film 15g and other regions can be changed by controlling the thickness of the silicon oxide film 15a and the thickness of the silicon oxide film 15b, respectively.

  Next, an electrode formation process is performed. In this step, the transfer electrode 16 is formed on the oxide film 15. In this embodiment, a plurality of (for example, two) transfer electrodes 16 are arranged on the same plane through a narrow gap to form a single-layer electrode structure.

  The transfer electrode 16 is formed of, for example, tungsten (W), a polycide film of low resistance polysilicon and tungsten silicide (WSi), or the like. In addition, for example, molybdenum (Mo), tungsten silicide (WSi), molybdenum silicide (MoSi), titanium silicide (TiSi), tantalum silicide (TaSi), copper silicide (CuSi), or the like is used as an electrode material. it can. Alternatively, the transfer electrode 16 may be formed by laminating these electrode materials without using an interlayer insulating film.

  The inter-electrode gap (narrow gap) provided in the arrangement direction of the transfer electrodes 16 is preferably about 0.3 μm or less in order to make the flow of charges in the transfer channel 14 smooth, and particularly about 0.1 μm. It is preferable that the thickness is about 0.2 μm.

Next, a predetermined portion of the p ⁻ type impurity doped region 11b is converted into an n type impurity doped region 12a by ion implantation. The n-type impurity addition region 12a functions as a charge storage region. By converting the p ⁺ -type impurity doped region 12b of the surface layer portion of the conversion n-type impurity doped region 12a by ion implantation, to form the photoelectric conversion element 12 is a photodiode of the buried type.

  The details of the single-layer oxide film forming step, the electrode forming step, and the photoelectric conversion element forming step will be described later with reference to FIGS.

  Next, the light shielding film 18 is formed by depositing a metal such as tungsten, aluminum, chromium, titanium, molybdenum, or an alloy composed of two or more of these metals on the insulating film 17 by PVD or CVD. The light shielding film 18 covers the transfer electrodes 16 and the like in plan view, and prevents unnecessary photoelectric conversion from being performed in a region other than the photoelectric conversion element 12.

  The light shielding film 18 has one opening above each photoelectric conversion element 12 so that light can enter each photoelectric conversion element 12. A region located on the surface of the photoelectric conversion element 12 in the above-described opening in plan view is a light incident surface of the photoelectric conversion element 12.

  Thereafter, a first planarization layer 19 including a passivation layer and a planarization insulating layer is formed on the light shielding film 18. Next, the color filter layer 20 is produced by sequentially forming layers of three or four kinds of resins (color resins) colored in different colors, for example, at predetermined positions by a method such as photolithography. . In a solid-state imaging device used for a single-plate imaging device for color photography, a primary color-based or complementary color-based color filter layer 20 is disposed. The color filter layer 20 is mainly disposed on a solid-state imaging device used in a single-plate imaging device for color photography. The color filter layer 20 can be omitted in a solid-state imaging device for monochrome photography or a solid-state imaging device used for a three-plate imaging device.

  Next, similarly to the first planarization film 19, the second planarization film 21 is formed of an organic material such as a photoresist. Microlenses 22 are formed on the upper surface of the second planarization film 21 so as to correspond to the respective photoelectric conversion elements 12. The microlens 22 is formed, for example, by forming a transparent resin layer on the second planarizing film 21, patterning the transparent resin layer into a predetermined shape by a photolithography method or the like, and then performing reflow. The second planarization film 21 is formed on the color filter layer 20 and provides a flat surface for forming the microlens 22.

  FIG. 5 is a diagram for explaining a process for forming the oxide single-layer gate insulating film 15 according to this embodiment. 5 shows the same region as the cross-sectional view shown in FIG.

First, as shown in FIG. 5A, a silicon oxide film (first oxide film) is formed in the p ⁻ -type impurity doped region 11b formed in the n-type silicon substrate 11a by thermal oxidation at 900 to 1000 ° C., for example. 15a is uniformly formed to a film thickness of 40 nm.

  Next, a photoresist film is formed so as to cover the entire surface of the silicon oxide film 15a, and a pattern 34 is formed by photolithography or the like so as to cover a region other than the region above the read gate channel region 11c. Thereafter, as shown in FIG. 5B, using the pattern 34 as a mask, the silicon oxide film 15a above the read gate channel region 11c is etched and removed by, for example, dry etching or wet etching. Thereafter, the pattern 34 is removed to obtain the state shown in FIG.

  Next, as shown in FIG. 5D, oxidation is performed by thermal oxidation so that the film thickness on the silicon substrate 11 above the read gate channel region 11c (region 15g surrounded by a broken line in the drawing) is 25 nm. A silicon film (second oxide film) 15b is formed. As a result, the thickness of the readout portion gate insulating film (region surrounded by a broken line in the drawing) 15 g is 25 nm, and the thickness is 55 nm in other regions. Note that both or one of the first oxide film 15a and the second oxide film 15b may be formed as an HTO film by CVD instead of being formed by thermal oxidation.

  Thereafter, in order to form the gate electrode (transfer electrode) 16, for example, a polycrystalline silicon film doped with high concentration phosphorus is deposited with a film thickness of about 0.3 μm, and after processing such as patterning, FIG. ).

  FIG. 6 is a cross-sectional view for explaining an electrode forming process according to an embodiment of the present invention. Note that the cross-sectional view shown in FIG. 6 is obtained by cutting the solid-state imaging device 1 along CD in FIG.

  First, a CVD (Chemical Vapor Deposition) method is applied to an electrode material 16a such as polycrystalline silicon doped with a concentration of about 0.3 μm so as to cover the entire surface of the semiconductor substrate 11 on which the oxide single-layer gate insulating film 15 is formed. The state shown in FIG.

  Next, as shown in FIG. 6B, a photoresist film is formed to cover the entire surface of the electrode material 16a, and a gap (interelectrode gap) EG of about 0.1 μm to 0.2 μm is formed by photolithography or the like. A pattern 35 is formed. Thereafter, as shown in FIG. 6C, the electrode material 16a is etched using the pattern 35 having the gap EG as a mask to form an interelectrode gap EG. Thereafter, an n-type impurity added region (vertical transfer channel) 14 and an impurity having a conductivity type opposite to that of the interelectrode gap EG are introduced by an ion implantation method. For example, p-type impurities such as boron (B) are ion-implanted at a dose of 2.0 × 10 11 cm −2 and an acceleration voltage of 50 KeV.

  In this manner, by implanting impurities having a conductivity type opposite to that of the transfer channel 14 into the interelectrode gap EG, the potential pocket generated in the interelectrode gap can be eliminated. Therefore, the flow of charges in the transfer channel 14 can be made smooth.

Immediately after ion implantation into the interelectrode gap EG, the photoresist pattern 35 is removed as shown in FIG. 5D, and then the insulating film 17 is formed as shown in FIG. 5E. . The insulating film 17 is formed by depositing (CVD-SiO ₂ ) silicon oxide (SiO ₂ ) having a film thickness of about 1500 mm by CVD, for example, plasma CVD (PECVD). The insulating film 17 may be formed by depositing a silicon nitride (SiN) film or a silicon carbide (SiC) film by CVD or the like, or may be formed by thermal oxidation. Incidentally, by forming the insulating film 17 by using a material having a dielectric constant higher than that of silicon oxide such as silicon nitride (SiN) or silicon carbide _(SiC) (SiO 2), is possible to shorten the effective length of the gap between the electrodes EG it can.

  In this way, after the ion implantation into the interelectrode gap EG, the insulating film 17 is quickly formed to fill the interelectrode gap EG, so that foreign matter is mixed into the interelectrode gap EG, or in subsequent steps. Residue etc. of the used photoresist can be prevented.

  Next, as shown in FIG. 6F, a gap width prevention film 16p is formed by depositing a silicon nitride (SiN) film having an oxygen shielding function with a film thickness of about 300 mm by CVD or the like. Note that the gap width expansion preventing film 16p may be formed using a silicon carbide (SiC) film instead of the silicon nitride film. The gap width expansion preventing film 16p has a role to prevent the transfer electrode 16 from being oxidized and the interelectrode gap EG from being expanded by the subsequent oxidation process in an oxidizing atmosphere.

  FIG. 7 is a cross-sectional view for explaining a photoelectric conversion element forming step according to an embodiment of the present invention. Note that the cross-sectional view shown in FIG. 7 is obtained by cutting the solid-state imaging device 1 along CD in FIG.

  As shown in FIG. 7A, a photoresist mask 36 is formed above the electrode material 16a to be the transfer electrode 16. Thereafter, as shown in FIG. 7B, the gap width expansion preventing film 16p and the insulating film 17 above the photoelectric conversion element portion 12p are removed by etching using the photoresist mask 36 as a mask. Further, as shown in FIG. 7C, the electrode material 16a above the photoelectric conversion element portion 12p is removed by etching. The etching of the electrode material 16a and the like is performed by, for example, the RIE (Reactive Ion Etching) method.

Thereafter, as shown in FIG. 7D, the oxide single-layer gate insulating film 15 of the photoelectric conversion element portion 12p is removed by wet etching using dilute hydrofluoric acid or the like as an etchant. At the same time, the photoresist film 36 on the transfer electrode 16 is also removed. Thereafter, an oxide film (SiO ₂ ) 15 d is formed again on the surface of the silicon substrate 11 on the photoelectric conversion element portion 12 p, and impurity ions are implanted into the photoelectric conversion element portion 12 p to form the photoelectric conversion element 12.

  As described above, according to the embodiment of the present invention, since the oxide single-layer gate insulating film 15 is formed instead of the ONO film, it is possible to avoid various problems such as deterioration of transfer over time due to the ONO film structure. At that time, the transfer electrode 16 has a single-layer electrode structure instead of a two-layer structure, thereby avoiding problems such as transfer efficiency degradation that occurs when a two-layer polysilicon electrode and an oxide single-layer gate insulating film are combined. Can do.

  In addition, according to the embodiment of the present invention, after the first oxide film 15a is formed, the oxide film 15a above the readout portion 11c from the photoelectric conversion element 12 to the transfer channel 14 is removed, and the oxide film 15b is formed again. . As a result, only the oxide film 15g above the reading portion 11c can be formed thin. Therefore, it is possible to improve read characteristics and secure low voltage driving or high saturation capacity.

  Although the present invention has been described with reference to the embodiments, the present invention is not limited thereto. It will be apparent to those skilled in the art that various modifications, improvements, combinations, and the like can be made.

1 is a block diagram showing a configuration of a CCD type solid-state imaging device 1 according to a first embodiment of the present invention. 2 is a schematic plan view of a part of a light receiving region 2 of the solid-state imaging device 1. FIG. It is the expanded sectional view which cut | disconnected the solid-state imaging device 1 shown in FIG. 2 between AB. It is an expanded sectional view near the reading part of the solid-state imaging device 1 by the Example of this invention. It is sectional drawing for demonstrating the oxide film single layer gate insulating film formation process by the Example of this invention. It is sectional drawing for demonstrating the electrode formation process by the Example of this invention. It is sectional drawing for demonstrating the photoelectric conversion element formation process by the Example of this invention. It is an expanded sectional view near the reading part of the solid-state imaging device 200 by the 1st prior art example. It is an expanded sectional view near the reading part of the solid-state imaging device 300 by the 2nd prior art example.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Solid-state imaging device, 2 ... Light reception area | region, 3 ... HCCD, 4 ... Peripheral circuit, 11 ... Semiconductor substrate, 12 ... Photoelectric conversion element, 13 ... Channel stop, 14, ... Vertical transfer channel, 15 ... Oxide film single layer gate Insulating film, 16 ... transfer electrode, gate electrode, 17 ... insulating film, 18 ... light shielding film, 19, 21 ... flattening layer, 20 ... color filter layer, 22 ... microlens, 34, 35, 36 ... photoresist mask

Claims (4)

A semiconductor substrate defining a two-dimensional surface;
A large number of photoelectric conversion elements disposed in the light receiving region of the semiconductor substrate;
A vertical charge transfer device including a plurality of vertical charge transfer channels arranged in a vertical direction between columns of photoelectric conversion elements and a plurality of transfer electrodes formed above the vertical charge transfer channels and arranged in a horizontal direction;
A readout electrode that also serves as a transfer electrode that constitutes the vertical charge transfer device is included, corresponding to each of the plurality of photoelectric conversion elements, and signal charges accumulated in the corresponding photoelectric conversion elements are adjacent in the row direction. A readout section for reading to the vertical charge transfer channel;
A solid-state imaging device having a gate oxide film formed as a single oxide film layer between the vertical charge transfer channel and the transfer electrode and having a thickness smaller than that of the other part in the readout portion. The solid-state imaging device according to claim 1, wherein the transfer electrodes are a plurality of single-layer electrodes arranged with a gap across a plurality of rows. 3. The solid according to claim 1, wherein the photoelectric conversion element is disposed at each lattice point of a first square lattice of a square matrix and a second square lattice having lattice points at interstitial positions of the first square lattice. Imaging device. (A) providing a semiconductor substrate defining a two-dimensional surface;
(B) performing impurity diffusion in a region corresponding to the photoelectric conversion element and the vertical transfer channel;
(C) forming a first oxide film on the semiconductor substrate;
(D) selectively removing the first oxide film formed above the signal charge reading portion from the photoelectric conversion element to the vertical transfer channel;
(E) forming a second oxide film on the first oxide film and the signal charge readout portion of the semiconductor substrate;
(F) A method for manufacturing a solid-state imaging device, including a step of forming a transfer electrode on the second oxide film.

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