JP2007043108A - Solid-state image sensing device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a solid-state image sensing device which can prevent any erroneous operation and reduce noise by reducing the amount of undesirable incoming light other than a photodiode among incoming light. <P>SOLUTION: In the solid-state image sensing device, light hν<SB>1</SB>is refracted at an interface (point A) between a passivation film 48 and a dielectric film 49 to be turned to the direction of an adjacent pixel signal converter 53. When a distance in an inter-plane vertical direction from the top surface of an n<SP>+</SP>-type drain region 38 to the top surface of a passivation film 48 formed at an opening area 47a on a light shielding film 47 is (h), while the shortest distance is Δx in an inter-plane horizontal direction from the endmost edge (point B) of the bottom side on a concave area as a step on the passivation film 48 to an endmost edge of a charge retention means (p-type region 37 near a source) in the adjacent pixel or a depletion layer 50, a refraction angle θ is reduced by setting a condition that satisfies an inequality:Δx<SP>2</SP>≥2ä1-(n<SB>1</SB>/n<SB>2</SB>)}h<SP>2</SP>(wherein, h/Δx≥5, and 0≤Δx≤0.6 μm) between a refractive index n<SB>1</SB>of the dielectric film 49 and a refractive index n<SB>2</SB>of the passivation film 48. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a solid-state imaging device, and more particularly to a solid-state imaging device configured to suppress excessive light intrusion into a photoelectric charge holding unit other than an element light receiving unit.

  Conventional solid-state imaging devices are roughly classified into two types, a CCD (Charge Coupled Device) type and a CMOS (Complementary MOS) type. The difference between them is not how to convert light into electric charge, but how to transmit information on the electric charge of the photodiode to the outside of each light receiving element. That is, in the CCD system, the charge generated in the photodiode is directly transferred to the outside by a charge coupled device (CCD). On the other hand, in the CMOS method, potential information due to charges generated in the photodiodes is output to the outside of the pixel circuit through an amplifier provided corresponding to each photodiode.

  Regarding the manufacturing process, the CCD system needs to be manufactured by a special process, and a dedicated line is required. On the other hand, the CMOS method can be manufactured by almost the same process as a normal CMOS-LSI (Large Scale Integrated circuit) process, so the CMOS-LSI line can be used as it is, and the area sensor and others can be used. There is an advantage that CMOS circuits can be mixed. Further, in the CCD system, a plurality of power supplies are required to execute charge transfer in the CCD system, but the CMOS system may be a single power supply and has a lower voltage than the CCD system. Therefore, there is an advantage that the power consumption of the CMOS method is less than that of the CCD method.

  A CMOS solid-state imaging device (CMOS image sensor) having such features converts electric charges obtained by photoelectric conversion with a photodiode into an electric signal such as a voltage signal or a current signal in a pixel, and the electric The signal is amplified by an amplifying transistor provided in the pixel and then output to the outside of the pixel. Many CMOS image sensors often include three or more transistors in a pixel. As a result, the CMOS image sensor is said to be disadvantageous for miniaturization as compared with the CCD, because these transistors can take a large area.

  Therefore, development of an image sensor having only one or two transistors in a pixel has been conventionally performed. A transistor of this type of image sensor is characterized by having a ring-shaped gate electrode. The diffusion at the center of the ring of a transistor having a ring-shaped gate electrode in each pixel normally functions as the source of the transistor, but is separated from other diffusions by the gate electrode, so that the configuration can be simplified. Is possible. The transistor having the ring-shaped gate electrode is an amplifying MOS field effect transistor (FET), and this type of image sensor is a kind of CMOS image sensor in the sense that each pixel has an amplifying MOSFET. .

  As a solid-state imaging device having this ring-shaped gate electrode, a light-receiving diode sharing an well region and an insulated gate field effect transistor are provided, and high in the vicinity of the source diffusion region in the well region under the channel region of the transistor. Conventionally, a solid-state imaging device having a structure including a concentration buried layer (carrier pocket) has been proposed (see, for example, Patent Document 1).

FIG. 6 is a structural cross-sectional view of an example of the solid-state imaging device described in Patent Document 1. In the figure, the n-well 12 is formed on the surface of the p ⁺ substrate 11, to form a p-well 13 embedded in the n-well 12, to form a ring-shaped gate electrode 14 thereon buried p-well 13, further p-well An n ⁺ -type drain diffusion layer 15 is formed on the surface of the ring 13 so as to surround the outer periphery of the ring-shaped gate electrode 14, and n ⁺ is formed at the surface position of the p-well 13 corresponding to the central opening of the ring-shaped gate electrode 14. A type source diffusion layer 16 is formed to form a ring-shaped MOSFET.

The buried p-well 13 below the drain diffusion layer 15 of the ring MOSFET is used as a buried photodiode. Sonouede within p-well 13 embedded in MOSFET, and, in the vicinity of the source diffusion layer 16 to form a p ⁺ region (carrier pocket) 17 is a high-concentration buried layer having an increased p-type impurity concentration. Light is made incident on the drain diffusion layer 15 by the light shielding film 21.

  In this way, since the potential of the carrier pocket 17 is the lowest in the buried p-well 13, holes generated in the buried photodiode below the drain diffusion layer 15 by the incident light move in the buried p-well 13. And concentrate in the carrier pocket 17. As a result, the potential in the vicinity of the source rises and the threshold value of the MOSFET falls, so that the change in threshold value becomes a signal. The holes collected in the carrier pocket 17 are discharged to the substrate side by applying a high voltage to the source electrode wiring 18 and the gate electrode wiring 19 after the signal is read out. A drain electrode wiring 20 is connected to the drain diffusion layer 15.

Japanese Patent Laid-Open No. 11-195778

  In the above-described conventional solid-state imaging device, the light shielding film 21 is used to prevent light from entering the portion other than the photodiode, that is, the MOSFET having the ring-shaped gate electrode 14. Since it is formed of a metal material such as aluminum, it is necessary to form a passivation film 22 on the light shielding film 21, as shown in FIG.

  However, since the passivation film 22 is formed by a film forming method such as CVD (Chemical Vapor Deposition), the step at the opening of the light shielding film 21 cannot be completely eliminated. As shown, the surface of the passivation film near the edge of the opening becomes a curved surface. There is no problem with the portion where the surface of the passivation film 22 is flat, but the light that reaches the curved surface portion A is refracted at the surface of the passivation film 22 and does not reach the light receiving portion, but enters the ring MOSFET or the like in a certain direction. As a result, noise other than the desired signal from the photodiode is generated, or in the extreme case, the MOSFET operates abnormally.

In addition, a type of CMOS image sensor that has a floating diffusion (hereinafter referred to as FD) with 3 to 4 transistors per pixel is often used. FIG. 7 is a cross-sectional view per pixel of another example of a conventional solid-state imaging device. In the figure, a transfer gate 25 is formed on a p-well 23 via a gate oxide film 24, and a photodiode 26 and an n ⁺ drain 27 are formed in a p-well 23 outside the transfer gate 25. ing.

An n ⁺ -type FD 28 is formed on the surface of the P-well 23 adjacent to the transfer gate 25 where the drain 27 is not provided. The drain of the reset transistor Q1 and the gate of the amplification transistor Q3 are sustained on the FD 28. The drain and source of the selection transistor Q2 are connected to the source of the reset transistor Q1 and the drain of the amplification transistor Q3. That is, in this solid-state imaging device, a total of four transistors each including a transfer transistor having transistors Q1 to Q3 and a transfer gate 25 are provided in one pixel.

  In this solid-state imaging device, the electric charge stored in the photodiode 26 is transferred to the FD 28 reset in advance by the reset transistor Q1, and when the selection transistor Q2 is turned on, the potential signal of the FD 28 is output to the outside of the pixel through the amplification transistor Q3. It is configured. Also at this time, the FD 28 serves as a charge holding means. If light refracted by the curved surface portion A of the passivation film 22 near the opening edge of the light shielding film 21 formed on the insulating film 29 enters the FD 28, noise or malfunction is caused. Cause.

  On the other hand, the pixel pitch of the CMOS sensor has been miniaturized year by year, and as shown in FIG. 8, the pixel pitch in 2001 was 5 μm or more, but in 2006 it was reduced to about 2 μm. Therefore, what has not been a problem in the past occurs as a new problem as the pixel pitch becomes finer.

  The finer pixel pitch can be realized by reducing the dimension in the in-plane direction on the semiconductor substrate, but there is a problem that the reduction in the direction perpendicular to the surface cannot be simplified. This is because at least three wiring layers are required to construct a CMOS sensor, and the thickness thereof must be ensured. In order to perform signal transfer and read operation by connecting to each transistor installed in the pixel, this wiring layer must pass a constant current, and has a constant cross-sectional area even when the pixel pitch is reduced. Must be secured.

  The wiring layer is generally formed of Al (aluminum) or Cu (copper), but it is necessary to ensure the film thickness so as not to exceed the current density allowed by this material. When these wiring layers and their layers are formed after securing the thickness of each wiring layer, the total thickness of the wiring layers (that is, the element height: indicated by h in FIG. 7) needs to be at least 3 μm.

  On the other hand, as the pixel pitch is reduced (miniaturized), the size of the transistor that performs signal transfer and readout operation and the width of the element isolation region are also reduced approximately proportionally. The aspect ratio (h / Δx) between the element height (h) and the element height (h) increases rapidly. This will be described with reference to FIG.

The aspect ratio in FIG. 9 is indicated by the value of h / Δx (circles in FIG. 9), and the dimension Δx in the element plane is the pixel adjacent from the position of the portion where the passivation film 22 is curved in FIG. ₂ is the sum of Δx ₂ and Δx ₁ in FIG. 2 described later. As the pixel pitch is further miniaturized, the height of the element (h: ■ in FIG. 9) is similarly reduced. However, as described above, the height of the element (h) associated with the finer pixel pitch is reduced. Since there is a limit to the reduction and at least 3 μm is required, the value of the aspect ratio h / Δx is abruptly increased as indicated by a circle in FIG.

  When the value of the aspect ratio h / Δx increases, the light refracted at the curved surface portion A of the passivation film 22 in the conventional solid-state imaging device shown in FIGS. 6 and 7 easily enters in a certain direction such as a ring MOSFET. Therefore, there arises a problem that noise other than a signal from a desired photodiode is generated, and in an extreme case, an abnormal operation of the MOSFET is promoted. The dimension Δx in the element plane at the point where the value of the aspect ratio h / Δx increases rapidly is about 0.6 μm, which is particularly enormous when the pixel pitch is further refined from this point. It becomes a problem.

  The present invention has been made in view of the above points, and provides a solid-state imaging device capable of preventing abnormal operation and reducing noise by reducing unnecessary light other than a photodiode among incident light. The purpose is to do.

  Another object of the present invention is to reduce the size of the solid-state imaging device with a small amount of noise by suppressing unnecessary light that enters other than the photodiode that is particularly likely to occur when the pixel pitch is reduced. It is to provide.

To achieve the above object, the present invention provides a photoelectric conversion unit that converts light into electric charges and accumulates, a transfer unit that transfers charges generated in the photoelectric conversion unit, and a charge that holds the charges transferred by the transfer unit A plurality of pixels each including a holding unit and an output unit that outputs a signal corresponding to the amount of charge held by the charge holding unit are arranged in a matrix on the semiconductor substrate and provided above the photoelectric conversion unit. In a solid-state imaging device in which a light-shielding film having an opening at a position corresponding to the photoelectric conversion unit and a passivation film covering the light-shielding film are formed, refraction that fills at least the stepped recess in the opening of the light-shielding film of the passivation film and the dielectric film rate n ₁ is formed, passivation - the refractive index of the passivation film and n _2, half in contact with the charge holding unit or charge holding means in the bottom endmost portion and a neighboring pixel of the stepped recess When the shortest distance in the in-plane horizontal direction between the end of the depletion layer in the body substrate is Δx, and the in-plane vertical distance from the surface of the semiconductor substrate to the surface of the opening of the passivation film is h, The following formula Δx ² ≧ 2 {1- (n ₁ / n ₂ )} h ²
(However, h / Δx ≧ 5 and 0 ≦ Δx ≦ 0.6 μm)
It is the structure which satisfy | fills these conditions.

In this invention, when the pixel pitch is further miniaturized and Δx becomes 0.6 μm or less, h / Δx becomes 5 or more, and the light reaching the charge holding means in the adjacent pixel increases rapidly. By using a dielectric film having a refractive index n ₁ that satisfies the inequality, noise generation and malfunction can be avoided.

Since the passivation film covering the light shielding film has a step recess at a position corresponding to the opening of the light shielding film, the light incident in the direction perpendicular to the element surface is incident on the curved surface portion of the step recess of the passivation film. The light is refracted and the optical path is bent in the direction of the signal conversion unit of the adjacent image collection. Therefore, in the present invention, to form the dielectric film by filling a dielectric material into the step in the recess of at least the passivation film, between the refractive index n ₂ of the refractive index n ₁ and the passivation film of the dielectric material By providing the relationship expressed by the above inequality, the refraction angle of light refracted at the interface between the dielectric film and the curved surface portion of the stepped recess of the passivation film is in contact with the charge holding means and the charge holding means in the adjacent pixels. The value is set so as not to enter the depletion layer in the semiconductor substrate.

  In order to achieve the above object, according to the present invention, the dielectric film is filled in the step recess of the passivation film, the height of the dielectric film is substantially the same as the height of the passivation film, and the step recess of the passivation film is The entire surface of the passivation film including the surface is flattened.

  In the present invention, the dielectric film is formed by being filled only in the step recesses of the passivation film, and the height of the surface of the passivation film and the height of the surface of the dielectric film are substantially matched. Therefore, the step recesses of the passivation film also have the same height as the surface of the passivation film at other positions due to the dielectric film, and the entire element surface becomes flat.

  In order to achieve the above object, the present invention is characterized in that the dielectric film covers the entire surface of the passivation film and has a flat surface. In this invention, since the entire surface of the passivation film is covered with the dielectric film, the polishing rate can be made uniform regardless of the location, and the flatness can be improved without causing a surface step.

According to the present invention, the refractive index n ₁ of the dielectric film that is at least filled with a stepped recess at the opening of the light shielding film of the passivation film, passivation - the refractive index of the passivation film and n _2, the bottom surface of the stepped recessed endmost And the shortest distance Δx in the in-plane horizontal direction between the charge holding means in one adjacent pixel or the end of the depletion layer in the semiconductor substrate in contact with the charge holding means, and from the surface of the semiconductor substrate to the surface of the opening of the passivation film By maintaining a predetermined relationship with the distance h in the in-plane vertical direction, the refraction angle of light refracted at the interface between the dielectric film and the curved surface portion of the stepped recess of the passivation film is held in the adjacent pixel. Since the light is not incident on the depletion layer in the semiconductor substrate in contact with the charge holding means and the charge holding means, the light is incident on other than the photoelectric conversion portion in the pixel provided corresponding to the opening of the light shielding film. Unnecessary light can be reduced, thereby preventing abnormal operation of the solid-state imaging device and reducing noise.

  In addition, according to the present invention, as the pixel pitch becomes finer, even if the aspect ratio (h / Δx) increases rapidly, the height (distance in the in-plane direction) h of the element is significantly reduced. In addition, unnecessary light that enters the portion other than the photoelectric conversion portion can be suppressed, and thus a solid-state imaging device that is small in size and low in noise can be provided.

Next, each embodiment of the present invention will be described with reference to the drawings.
<First Embodiment>
FIG. 1A is a top view of a first embodiment of a solid-state imaging device according to the present invention, and FIG. 1B is a longitudinal sectional view taken along line XX ′ of FIG. In the solid-state imaging device of the present embodiment, a p ⁻ type epitaxial layer 32 is grown on a p ⁻ type substrate 31, and an n well 33 is provided on the surface of the epitaxial layer 32. On the n-well 33, a gate electrode 35 having a ring shape as a first gate electrode is formed with a gate oxide film 34 interposed therebetween.

An n ⁺ -type source region 36 is formed at the surface position of the n-well 33 corresponding to the central opening of the ring-shaped gate electrode 35, and a source vicinity p-type region 37 is formed adjacent to the source region 36. ing. The source vicinity p-type region 37 does not reach the outer periphery of the ring-shaped gate electrode 35. An n ⁺ -type drain region 38 is formed on the surface of the n-well 33 at a position spaced outside the source region 36 and the p-type region 37 near the source. Further, as shown in FIG. 1B, there is a buried p ⁻ -type region 39 in the n-well 33 under the drain region 38 outside the ring-shaped gate electrode 35. The buried p ⁻ type region 39 and the drain region 38 constitute the buried photodiode 40 shown in FIG.

  Metal wirings 43, 44, 45 are connected to the ring-shaped gate electrode 35, the source region 36, and the transfer gate electrode 41, respectively (note that an electrode wiring is also connected to the drain region 38, not shown). . In addition, an insulating film 46 made of a first dielectric material is covered so as to cover the steps generated in the ring-shaped gate electrode 35, the transfer gate electrode 41, and the metal wirings 43 to 45 on the gate oxide film 34. Further, the surface of the insulating film 46 is flattened to form a light shielding film 47, and an opening 47 a is formed at a position corresponding to the embedded photodiode 40 of the light shielding film 47 to introduce light into the photodiode 40. At the same time, entry of light to portions other than the photodiode 40, that is, the ring-shaped MOSFET and the transfer gate MOSFET is prevented. The light shielding film 47 is formed of a metal or an organic film.

Further, since the light shielding film 47 is usually formed of a metal material such as aluminum, the entire upper part of the element is covered with a passivation film 48 as a protection film for preventing corrosion. As the passivation film 48, a plasma CVD film, SiO ₂ . SiOx, SiON, SiN, etc. are used. Further, the surface of the passivation film 48 has a step at a position corresponding to the opening 47a of the light shielding film 47, and the step recess is made of the same or different material as the passivation film 48 so as to fill the step recess. A dielectric film 49 filled with two dielectric materials is formed.

  The dielectric film 49 is formed by applying a SOG (Spin On Glass) material and a CMP (Chemical Mechanical Polishing) process. Alternatively, it can be formed by a combination of CVD and CMP. In some cases, the refractive index is adjusted by the composition ratio. The surface height of the dielectric film 49 substantially coincides with the surface height of the passivation film 48, and each surface is smooth, and an optical functional film such as an antireflection film or a microlens can be applied.

  The above configuration is a structure for one pixel, and an image sensor is configured by periodically aligning them in a plane. Note that some of the components of adjacent pixels are also shown on the right side of FIG. The solid-state imaging device having the structure shown in FIG. 1 is a CMOS sensor (meaning that a transistor having a ring-shaped gate electrode 35 is an amplifying MOS field effect transistor (FET)) and each pixel has an amplifying MOSFET. It can be said to be a kind of CMOS image sensor.

Next, the operation of this CMOS image sensor will be described. First, light passes through the dielectric film 49, the passivation film 48, the opening 47a of the light shielding film 47, and the insulating film 46 and enters the embedded photodiode 40, where an electron hole pair is generated by the photoelectric effect, and the photodiode Holes (charges) are accumulated in 40 p ⁻ -type regions 39. Thereafter, charges are transferred from the photodiode 40 to the back gate of the ring-shaped MOSFET (p-type region 37 in the vicinity of the source) simultaneously in all pixels. This is done by controlling the potential of the transfer gate electrode 41 and turning on the transfer gate MOSFET. Here, in the transfer gate MOSFET shown in FIG. 1B, the n-well 33 just below the transfer gate electrode 41 is the gate region, the p ⁻ type region 39 embedded in the photodiode 40 is the source region, and the p-type region 37 near the source. Is a P-channel MOSFET having a drain as a drain and constitutes a charge transfer means.

At this time, the ring-shaped gate electrode 35 near the source p-type region 37 directly under the gate region, n ⁺ -type ring-shaped gate MOSFET is a N-channel MOSFET having a source region 36 and n ⁺ -type drain region 38 of the ring The potential of the gate electrode 35 is set to a low level and remains off, so that no current flows.

  After the hole charge transfer, the transfer gate MOSFET is turned off to start accumulation of hole charge again in the photodiode 40, which continues until the next transfer. The holes accumulated in the p-type region 37 in the vicinity of the source are held until the read timing of the pixel comes. When the voltage of the ring-shaped gate electrode 35 rises at the read timing and the ring-shaped gate MOSFET is turned on, the threshold voltage of the ring-shaped gate MOSFET changes due to holes accumulated in the p-type region 37 near the source. A change in the threshold voltage is read out through the source electrode wiring 44 as a change in the source potential. That is, the ring-shaped gate MOSFET operates as an optical signal output transistor.

Thereafter, when a high voltage is applied to the ring-shaped gate electrode 35 and the n ⁺ -type source region 36, the potential of the p-type region 37 in the vicinity of the source is raised, and the hole passes through the barrier of the n-well 33 and the hole is formed into the p-type epitaxial layer. 32 is discharged. Alternatively, in another discharging method, by turning on the ring-shaped MOSFET, current is supplied from the drain, the source potential is increased, the potential of the p-type region 37 near the source is raised, and the barrier of the n-well 33 is exceeded. Holes are discharged to the p-type epitaxial layer 32.

  The feature of this CMOS image sensor is that a source vicinity p-type region 37 is provided in the vicinity of the source region 36 provided corresponding to the central opening of the ring-shaped gate electrode 35 of each pixel, and the source vicinity p-type region 37 The purpose is to realize a global shutter by transferring charges stored in the photodiode 40 all at once by a transfer gate MOSFET.

Next, the structure of the main part of the first embodiment of the present invention shown in FIG. 1 together with the sectional view of FIG. 2 will be described in more detail. In FIG. 2, the same components as those in FIG. 1B are denoted by the same reference numerals. In FIG. 2, the region shown in the right half is a signal conversion unit 53 in an adjacent pixel, which is composed of a ring-shaped gate electrode 35, an n ⁺ -type source region 36, and a source vicinity p-type region 37. An n ⁺ -type drain region 38 is provided on the surface of the n-well 33 that is separated from the source region 36 and the p-type region 37 near the source, and an isolation region 52 that separates adjacent pixels from each other is formed.

Here, the distance in the in-plane horizontal direction from the end position of the p ⁻ -type region 39 embedded in the photodiode portion 51 to the outermost end portion of the depletion layer 50 in the n-well 33 of the signal conversion portion 53 of the adjacent pixel. [Delta] x ₂ is (isolation region 52) at a distance required to separate the circuitry of the adjacent pixels, and is designed to approximately 0.3μm at minimum by using the latest technology.

In addition, the end position of the opening 47 a of the light shielding film 47 substantially coincides with the end position of the p ⁻ type region 39 of the photodiode section 51 in the planar direction. In addition, the distance (element height) from the surface of the n ⁺ -type drain region 38, which is the surface of the photodiode 51, to the surface of the stepped recess of the passivation film 48 provided in the opening 47a of the light shielding film 47 is h. . Since the CMOS image sensor of the present embodiment has a three-layer or four-layer electrode wiring structure by a semiconductor process, h is about 3 μm. The refractive index of the passivation film 48 is as _{n 2.} The end of the opening 47 a of the light shielding film 47 corresponding to the end of the bottom surface of the stepped recess of the passivation film 48 in the opening 47 a of the light shielding film 47 and the end position of the p ⁻ type region 39 embedded in the photodiode portion 51. The distance in the in-plane horizontal direction with respect to the position is represented by Δx ₁ . In general, Δx ₁ substantially coincides with the passivation film thickness and is about 0.8 μm. Furthermore, the refractive index of the dielectric film 49 filled in the stepped recess of the passivation film 48 is n _1.

In the first embodiment having such a structure, out of the light hν ₁ and hν ₂ incident on the element, the light hν ₂ passes through the dielectric film 49, the flat portion of the passivation film 48, the insulating film 46, and the gate oxide film 34, respectively. The light then passes through and enters the drain region 38 and the buried p ⁻ -type region 39 constituting the photodiode 40. On the other hand, the light hν ₁ is refracted at the interface (point A) between the passivation film 48 and the dielectric film 49 and bent toward the signal conversion unit 53 of the adjacent pixel. Here, the point A represents a point having a curved surface portion at the interface between the passivation film 48 and the dielectric film 49, but the bottom end (point B) of the recessed portion of the passivation film 48 where the degree of refraction becomes the largest. ) Is assumed.

The angle at which the light hν ₁ is refracted at the point A is Snell's law (n ₁ · sin θ ₁ = n ₂ · sin θ ₂ : θ ₁ , θ ₂ is the angle formed by the normal of the light incident surface and the incident light and outgoing light. , Not shown) and expressed as Δθ = θ ₁ −θ ₂ . Depending angle refracted light hv ₁ is determined by the [Delta] [theta], thus reaching to adjacent pixels beyond the isolation region 52. In this case, as shown in FIG. 2, when light is incident on the depletion layer 50 of the ring-shaped MOSFET of the adjacent pixel, the depletion layer 50 is in contact with the p-type region 37 near the source holding the photocharge, and near the source. Since the p-type region 37 has a lower potential, holes out of the generated charges reach the p-type region 37 near the source, causing noise and malfunction.

However, even when the dielectric film 49 having the refractive index n ₁ is used, this problem can be solved by performing the following. The method will be described in detail below. In FIG. 2, n ₁ = n ₂ −Δn, and a tangent in the lower plane of the gate oxide film 34 of Δθ is Δt. At this time, the following equation is established from Snell's law.

また、Δθ＝θ_１−θ_２であり、点Ａは屈折が最も大きくなる点であり、θ_１≒９０°であるので、次式が成立する。

Further, Δθ = θ ₁ −θ ₂ , and point A is a point where refraction becomes the largest, and θ ₁ ≈90 °, so the following equation is established.

上記のΔｔについては、Δθが小さいので、（式１）及び（式２）を使って、次式が得られる。

Since Δθ is small for the above Δt, the following equation is obtained using (Equation 1) and (Equation 2).

従って、上式にΔｎ＝ｎ_２−ｎ_１を代入して整理すると次式の関係が成り立つ。

Therefore, if Δn = n ₂ −n ₁ is substituted into the above equation and rearranged, the following relationship is established.

Δt ² = 2 {1- (n ₁ / n ₂ )} h ² (Formula 3)
Here, the condition for preventing the light hν ₁ from reaching the signal conversion unit 53 of the adjacent pixel is that the charge holding means in the bottom surface of the step recess portion of the passivation film 48 provided in the opening 47 a of the light shielding film 47 and the adjacent pixel. The shortest distance in the in-plane horizontal direction between (the source vicinity p-type region 37) or the endmost portion of the depletion layer 50 in contact with the charge holding means can be expressed as Δt ≦ Δx as Δx (= Δx ₁ + Δx ₂ ). From (Expression 3), Δx ² > 2 {1- (n ₁ / n ₂ )} h ² (Expression 4)
This is a condition for preventing the light hν ₁ from reaching the signal conversion unit 53 of the adjacent pixel.

The contents described here are particularly effective when the pixel pitch is further miniaturized and Δx becomes 0.6 μm or less. Of course, Δx ≧ 0. At this time, h / Δx becomes 5 or more, and the light hν ₁ reaching the signal conversion unit 53 increases abruptly. However, by arranging the signal conversion unit 53 at Δx that satisfies the above (Equation 4), the noise is reduced. Generation and malfunction can be avoided.

In the case of the _first embodiment, since n ₁ = 1.421, n ₂ = 1.45, and h = 3 μm, if these values are substituted into the inequality of (Expression 4), Δx is 0.6 μm. Thus, the condition of (Expression 4) is satisfied. Thereby, in the first embodiment, it is possible to suppress the light hν ₁ that reaches the signal conversion unit 53 of the adjacent pixel beyond the separation region 52.

In addition, the refractive index n ₁ of the dielectric film 49, the refractive index n _{2 of} the passivation film 48, and the step recesses of the passivation film 48 provided in the opening 47 a of the light shielding film 47 from the surface of the n ⁺ -type drain region 38. Distance to the surface (element height) h, charge holding means (source vicinity p-type region 37) or charge in the adjacent pixel at the bottom of the stepped recess bottom surface of the passivation film 48 provided in the opening 47a of the light shielding film 47 or charge The shortest distance Δx in the in-plane horizontal direction between the end of the depletion layer 50 in contact with the holding means takes, for example, the following value.

n ₁ n ₂ h Δx
1.421 1.450 3 0.60
1.440 1.450 5 0.60
1.430 1.450 3 0.50
1.434 1.450 3 0.45
1.437 1.450 3 0.40
Here, a dielectric film 49 of a specific refractive index n ₁ as an example, has been given a passivation film 48 having a refractive index n _2, the present invention is not intended to limit the dimensions and materials, only equation (4 It is the greatest feature that the structure is arranged with the values of h and Δx that satisfy (1).

  FIG. 3 is a sectional view of the structure per pixel when the above-described first embodiment of the solid-state imaging device according to the present invention is applied to a CMOS image sensor having a floating diffusion. In the figure, the same components as those in FIGS. 2 and 7 are denoted by the same reference numerals, and the description thereof is omitted. The CMOS image sensor shown in FIG. 3 is provided with a total of four transistors each consisting of a transfer transistor having transistors Q1 to Q3 and a transfer gate 25 in one pixel, and the charge stored in the photodiode 26 is transferred to the reset transistor Q1. When the data is transferred to the FD 28 that has been reset in advance and the selection transistor Q2 is turned on, the potential signal of the FD 28 is output to the outside of the pixel through the amplification transistor Q3.

In this type of CMOS image sensor, the refractive index n ₁ of the dielectric film 49, the refractive index n ₂ of the passivation film 48, and the distance from the surface of the n ⁺ -type drain region 27 to the surface of the stepped recess of the passivation film 48 ( In-plane horizontal direction between the element height h) and the bottom end of the bottom of the stepped recess of the passivation film 48 in the opening 47a of the light shielding film 47 and the end of the depletion layer 54 in contact with the FD 28 of the adjacent pixel. Is selected so as to satisfy the above (Equation 4), the light refracted by the curved surface portion A of the passivation film 48 near the opening edge of the light shielding film 47 becomes the charge holding means FD28. It is possible to suppress the depletion layer 54 without reaching it.
<Second Embodiment>
Next, a second embodiment of the solid-state imaging device according to the present invention will be described with reference to the drawings. FIG. 4 shows a cross-sectional view of the main part of the second embodiment of the solid-state imaging device according to the present invention. In the figure, the same components as those in FIG. In the first embodiment shown in FIGS. 1 and 2, the dielectric material is filled so as to fill the stepped recesses of the passivation film 48 having a stepped surface in the opening 47a of the light shielding film 47, and the surface height is increased. Whereas a dielectric film 49 is formed so as to be substantially coincident with the surface height of the passivation film 48, the second embodiment shown in FIG. 4 has the dielectric film 55 formed on the surface of the passivation film 48. It is characterized in that it is formed so as to cover the whole. Except for the dielectric film 55, the other components are the same as those shown in FIGS.

In FIG. 4, a dielectric film 55 is a dielectric material having a refractive index n ₁ which is the same as or different from that of the passivation film 48 having a refractive index n ₂ , and is formed by applying an SOG material and a CMP process. Alternatively, it can be formed by a combination of CVD and CMP. The surface of the dielectric film 55 is smooth, and an optical function film such as an antireflection film or a microlens can be applied. In addition, the dielectric film 55 may be formed by laminating a plurality of films satisfying the conditions.

In this embodiment, the light hν ₁ and hν ₂ incident in the direction perpendicular to the plane of the dielectric film 55 travels straight inside the dielectric film 55, and the light hν ₁ is the same as in the first embodiment. Furthermore, it is refracted and bent at the interface (point A) between the passivation film 48 and the dielectric film 55. Therefore, in order to this embodiment also does not reach the signal conversion unit 53 of an adjacent pixel, the refractive index n ₁ of the dielectric film 55, the refractive index n ₂ of the passivation film 48, from the surface of the n ⁺ -type drain region 38 The distance (element height) h to the surface of the step recess of the passivation film 48 provided in the opening 47a of the light shielding film 47 and the bottom end of the bottom of the step recess of the passivation film 48 provided in the opening 47a of the light shielding film 47 The shortest distance Δx in the in-plane horizontal direction between the portion (point B) and the charge holding means (source vicinity p-type region 37) in the adjacent pixel or the outermost end of the depletion layer 50 in contact with the charge holding means is It is set so as to satisfy the inequality represented by the equation 4).

The contents described here are particularly effective when the pixel pitch is further miniaturized and Δx becomes 0.6 μm or less. At this time, h / Δx becomes 5 or more, and the light hν ₁ reaching the signal conversion unit 53 in FIG. 4 increases rapidly, but the signal conversion unit 53 is arranged at Δx that satisfies the above (Equation 4). This makes it possible to avoid the occurrence of noise and malfunction.

Accordingly, in the second embodiment, n ₁ = 1.421, n ₂ = 1.45, and h = 3 μm, as in the first embodiment described above, so that the inequality of (Expression 4) If these values are substituted into Δx, Δx becomes 0.6 μm, which satisfies the condition of (Equation 4), so that the light hν ₁ that reaches the signal conversion unit 53 of the adjacent pixel beyond the separation region 52 can be suppressed. It becomes possible.

Other, the refractive index n ₁ of the dielectric film 55, the refractive index n ₂ of the passivation film 48, elements the height h, and a bottom endmost portion of stepped recess of the passivation film 48 at the opening 47a of the light shielding film 47, The distance Δx in the in-plane horizontal direction between the end of the depletion layer 50 in the n-well 33 of the signal conversion unit 53 of the adjacent pixel takes, for example, the following value.

n ₁ n ₂ h Δx
1.421 1.450 3 0.60
1.440 1.450 5 0.60
1.430 1.450 3 0.50
1.434 1.450 3 0.45
1.437 1.450 3 0.40
In this embodiment, since the material exposed on the surface of the element is a single dielectric material of the dielectric film 55, the CMP polishing rate is uniform regardless of the location and no surface step is generated. Therefore, there is an effect peculiar to the present embodiment that the flatness of the surface is improved and light scattering on the surface that causes noise can be suppressed.

Note that this embodiment can also be applied to the CMOS image sensor shown in FIG. FIG. 5 shows a sectional view of the structure per pixel when the above-described second embodiment of the solid-state imaging device according to the present invention is applied to the CMOS image sensor of the type having the floating diffusion shown in FIG. In the figure, the same components as those in FIGS. 4 and 7 are denoted by the same reference numerals, and the description thereof is omitted. In the CMOS image sensor shown in FIG. 5, the refractive index n ₁ of the dielectric film 55, the refractive index n ₂ of the passivation film 48, and the distance from the surface of the n ⁺ -type drain region 27 to the surface of the stepped recess of the passivation film 48. In-plane horizontal between (element height) h and the bottom end of the bottom surface of the step recess of the passivation film 48 in the opening 47a of the light shielding film 47 and the end of the depletion layer 54 in contact with the FD 28 of the adjacent pixel. By selecting the distance Δx in the direction so as to satisfy the above (Formula 4), the light refracted by the curved surface portion A of the passivation film 48 near the opening edge of the light shielding film 47 serves as a charge holding means. It becomes possible to suppress without reaching the FD 28 and the depletion layer 54 in contact therewith.

  Also, the present embodiment only needs to satisfy the condition of (Equation 4), and the dielectric material of the dielectric film 55 and the material of the passivation film 48 are not limited to the above example.

It is the top view of 1st Embodiment of the solid-state image sensor of this invention, and the longitudinal cross-sectional view which follows XX 'line. It is sectional drawing of the principal part of 1st Embodiment of the solid-state image sensor of this invention. FIG. 2 is a structural cross-sectional view when the first embodiment of the solid-state imaging device of the present invention is applied to a solid-state imaging device of a type having a floating diffusion. It is sectional drawing of the principal part of 2nd Embodiment of the solid-state image sensor of this invention. It is structural sectional drawing at the time of applying 2nd Embodiment of the solid-state image sensor of this invention to the solid-state image sensor of a type with a floating diffusion. It is sectional drawing of an example of the conventional solid-state image sensor. FIG. 5 is a cross-sectional view of a structure of a conventional solid-state imaging device having 3 to 4 transistors and a floating diffusion. It is a figure which shows the transition according to year of the pixel pitch of a CMOS sensor. It is a figure which shows a mode that the aspect-ratio accompanying the refinement | miniaturization of a pixel increases.

Explanation of symbols

32 p ⁻ type epitaxial layer 33 n well 35 ring-shaped gate electrode 36 n ⁺ type source region 37 near source p type region 38 n ⁺ type drain region 39 buried p ⁻ type region 40 photodiode 41 transfer gate electrode 47 light shielding film 47a Opening of light shielding film 48 Passivation film 49, 55 Dielectric film 51 Photodiode part 52 Separation region 53 Signal conversion part

Claims (3)

A photoelectric conversion unit that converts light into electric charges and stores; a transfer unit that transfers charges generated in the photoelectric conversion unit; a charge holding unit that holds charges transferred by the transfer unit; and the charge holding unit. A plurality of pixels each including an output unit that outputs a signal corresponding to the held charge amount is arranged in a matrix on a semiconductor substrate and is provided above the photoelectric conversion unit and corresponds to the photoelectric conversion unit In a solid-state imaging device in which a light shielding film having an opening and a passivation film covering the light shielding film are formed,
A dielectric film having a refractive index n ₁ filling at least a step recess in the opening of the light shielding film of the passivation film is formed, and the refractive index of the passivation film is n _2, and the bottom surface of the step recess is The shortest distance in the in-plane horizontal direction between the edge and the charge holding means in one adjacent pixel or the end of the depletion layer in the semiconductor substrate in contact with the charge holding means is Δx, and the surface of the semiconductor substrate is When the distance in the in-plane vertical direction to the surface of the opening of the passivation film is h, the following expression Δx ² ≧ 2 {1- (n ₁ / n ₂ )} h ²
(However, h / Δx ≧ 5 and 0 ≦ Δx ≦ 0.6 μm)
A solid-state imaging device characterized by satisfying the following conditions.   The dielectric film is filled in a step recess of the passivation film, the height of the dielectric film is substantially the same as the height of the passivation film, and the entire surface of the passivation film including the step recess of the passivation film is flattened. The solid-state imaging device according to claim 1. The solid-state imaging device according to claim 1, wherein the dielectric film covers the entire surface of the passivation film and has a flat surface.

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