JP2007042979A - Manufacturing method of semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor device capable of easily forming a dual-gate structure without damaging a gate insulating film. <P>SOLUTION: The n-type polysilicon region 14 of a polysilicon film 13 is constructed of an upper region 17 wherein the n-type impurity concentration is ≥1×10<SP>19</SP>atoms/cm<SP>3</SP>and a lower region 18 wherein the n-type impurity concentration is <1×10<SP>19</SP>atoms/cm<SP>3</SP>. The etching of the upper region 17 is carried out using an etching gas containing fluorine element which does not give rise to a difference between the etching speeds in the n-type polysilicon region 14 and in the other regions 15, 16. The etching of the lower region 18 is carried out on the etching condition that it has a higher selection ratio with respect to the gate insulating film 12. Thus, the damage to the gate insulating film 12 can be prevented, and the time when the etching condition is switched can easily be detected. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a method of manufacturing a semiconductor device, and in particular, manufacture of a semiconductor device having a dual gate structure in which an n-channel transistor having an n-type gate electrode and a p-channel transistor having a p-type gate electrode are formed on the same substrate. Regarding the method.

  In a semiconductor device using a MOS (Metal Oxide Semiconductor) structure element, n-type polysilicon is used as a gate electrode material for both an n-channel transistor and a p-channel transistor (so-called single gate structure). However, with the recent miniaturization of semiconductor elements, in a transistor having a gate electrode having a gate length of 0.3 μm or less, p-channel transistor gate material is used for the purpose of suppressing the short channel effect generated in the p-channel transistor. A dual gate structure in which n-type polysilicon is used for the gate electrode of the n-channel transistor is employed.

  FIG. 7 is a process sectional view showing a process of forming a gate electrode of the semiconductor device having the dual gate structure. In FIG. 7, in addition to the n-type polysilicon gate and the p-type polysilicon gate, a polysilicon pattern in which no impurity is implanted (hereinafter, this pattern is also referred to as a gate) is formed at the same time.

  As shown in FIG. 7A, first, a gate insulating film 12 having a thickness of about 3 nm made of a silicon oxide film or the like is formed on a semiconductor substrate 11 by a thermal oxidation method or the like, and about 200 nm is formed on the gate insulating film 12. A polysilicon film 13 having a thickness of 10 nm is deposited by a CVD (Chemical Vapor Deposition) method.

Next, a resist pattern 21 having an opening in a region including an n-type polysilicon gate formation region is formed on the polysilicon film 13 by photolithography. Using the resist pattern 21 as a mask, an n-type impurity such as phosphorus (P) is implanted into the polysilicon film 13 under conditions of an implantation energy of 5 keV and an implantation dose of 5 × 10 ¹⁵ atoms / cm ² , for example. As shown in FIG. 7B, an n-type polysilicon region 14 is formed.

After the resist pattern 21 is removed by an ashing process or the like, as shown in FIG. 7C, a resist pattern 22 having an opening in a region including a p-type polysilicon gate formation region is formed on the polysilicon film 13 by a photo process. It is formed by lithography. Then, using the resist pattern 22 as a mask, a p-type impurity such as boron (B) is implanted into the polysilicon film 13 under conditions of an implantation energy of 5 keV and an implantation dose of 5 × 10 ¹⁵ atoms / cm ² , for example. As a result, a p-type polysilicon region 15 is formed.

  Through the above steps, the polysilicon film 13 is divided into an n-type polysilicon region 14, a p-type polysilicon region 15, and a non-implanted region 16.

  Subsequently, as shown in FIG. 7D, a resist pattern 23 covering the gate electrode pattern formation region is formed on each of the regions 14, 15, and 16 by photolithography, and the resist pattern 23 is masked. As a result, the polysilicon film 13 is etched.

  In general, the n-type polysilicon region 14 doped with n-type impurities has a higher etching rate than the p-type polysilicon region 15 doped with p-type impurities. For this reason, it is difficult to etch the polysilicon film 13 including the n-type polysilicon region 14, the p-type polysilicon region 15, and the non-implanted region 18 simultaneously and uniformly. That is, as shown in FIG. 8A, when the n-type polysilicon region 14 is completely etched, the p-type polysilicon region 15 is not yet etched, as shown in FIG. 8B. In addition, when the etching of the p-type polysilicon region 15 is completed, the n-type polysilicon region 14 is over-etched, and a defect 80 such as a micro-trench is generated in the gate insulating film 12 below the region 14.

As a countermeasure, as shown in FIG. 7E, in the etching process of the polysilicon film 13, first, a mixed gas of Cl ₂ gas, HBr gas, and O ₂ gas is used as an etching gas, Plasma etching is performed until the etching of the n-type polysilicon region 14 is completed under etching conditions having a relatively low selectivity with the gate insulating film 12. Thereafter, plasma etching is performed under an etching condition in which the selection ratio between the polysilicon film 13 and the gate insulating film 12 is relatively large, using a mixed gas of HBr gas and O ₂ gas as an etching gas. As a result, as shown in FIG. 7F, the remaining portions of the polysilicon film in the p-type polysilicon region 15 and the non-implanted region 16 are removed without damaging the gate insulating film 12 in the n-type polysilicon region 14. The As a result, a gate electrode having a good shape is formed in each of the regions 14, 15, and 16 (see, for example, Patent Document 1).

In the above manufacturing process, the etching end point of the n-type polysilicon region 14 is detected because the etching gas needs to be switched when the etching of the n-type polysilicon region 14 is completed. Such detection of the etching end point uses the fact that the intensity of light of a specific wavelength emitted from the plasma during the etching process is measured and the light intensity fluctuates when the gate insulating film 12 is exposed. (For example, see Patent Document 2).
Japanese Patent No. 2822952 Japanese translation of PCT publication No. 2003-521126

  However, when the area occupied by the n-type polysilicon region 14 on the semiconductor substrate 11 is small, the area of the gate insulating film 12 exposed when the polysilicon film in the n-type polysilicon region 14 is removed by etching is reduced. For this reason, the light intensity of the said specific wavelength is small, and it is difficult to detect the fluctuation | variation of the said light intensity. Therefore, the conventional method for detecting the etching end point has a problem that the etching end point cannot be accurately detected when the area occupied by the p-type polysilicon region 15 and the non-implanted region 16 is large on the semiconductor substrate 11. is there.

  Therefore, in order to apply the above-described conventional technique, the area of the n-type polysilicon region 14 must be larger than the area occupied by the p-type polysilicon region 15 and the non-implanted region 16 on the semiconductor substrate. There were restrictions. Such layout restrictions are undesirable because they reduce the degree of freedom in designing the semiconductor device.

  The present invention has been proposed in view of the above-described conventional circumstances, and provides a method for manufacturing a semiconductor device capable of easily forming a dual gate structure without damaging the gate insulating film. Objective.

  In order to solve the above-described problems, the present invention employs the following technical means. That is, in the method for manufacturing a semiconductor device according to the present invention, a gate insulating film is first formed on a semiconductor layer, and a silicon film made of polysilicon or amorphous silicon is formed on the gate insulating film. Next, an n-type impurity is introduced into a part of the silicon film, and an n-type composed of an upper region where the concentration of the n-type impurity is equal to or higher than a specific concentration and a lower region where the concentration of the n-type impurity is lower than the specific concentration. Form a region. Subsequently, a mask pattern including at least a pattern covering the gate forming region of the n-type region and a pattern covering the gate forming region of the region other than the n-type region is formed on the silicon film. Thereafter, using the mask pattern as an etching mask, the upper region is dry-etched together with regions other than the n-type region using an etching species containing fluorine element. Then, using the mask pattern as an etching mask, the remaining portion of the silicon film is dry-etched with an etching species different from the dry etching.

The dry etching of the remaining silicon film can be performed by using an etching species that does not contain a fluorine element. The specific concentration is, for example, 1 × 10 ¹⁹ atoms / cm ³ , and such a concentration distribution can be formed by heat treatment at 600 ° C. to 700 ° C.

  The mask pattern can be formed as a resist or insulating film pattern. As the insulating film, for example, a film made of tetraethoxyoxosilane can be used. At this time, by forming the insulating film at a temperature of 600 to 700 ° C., the heat treatment can be performed simultaneously with the film formation.

The dry etching of the upper region can be performed with an etching gas containing a fluorine element. As the etching gas, for example, a gas selected from CF ₄ , CHF ₃ , C ₂ F ₆ , C ₃ F ₈ , C ₄ F ₈ , NF ₃ , and SF ₆ , or a mixed gas thereof is used. can do.

  Furthermore, the insulating film used as the mask pattern may be a film containing fluorine element. In this case, the fluorine element of the etching species used for the dry etching of the upper region is generated from the insulating film. When such dry etching is performed, the upper region may be dry etched using an etching gas containing at least one of chlorine element and bromine element.

According to the present invention, in the etching of the upper region where the n-type impurity concentration is 1 × 10 ¹⁹ atoms / cm ³ or more, a fluorine element that does not cause a difference in etching rate between the n-type polysilicon region and the other regions is used. Using the contained etching gas, the lower region having an n-type impurity concentration of less than 1 × 10 ¹⁹ atoms / cm ³ is etched under etching conditions having a high selectivity with respect to the gate insulating film. For this reason, it is possible to prevent damage to the gate insulating film and to easily detect the point in time when the etching conditions are switched.

(First embodiment)
Hereinafter, a semiconductor device manufacturing method according to a first embodiment of the present invention will be described in detail with reference to the drawings. FIG. 1 is a process cross-sectional view illustrating a method for manufacturing a semiconductor device according to the present embodiment. In the following, the same parts as those in the conventional semiconductor device are denoted by the same reference numerals, and only the gate electrode forming process will be described.

  First, as shown in FIG. 1A, a gate insulating film 12 is formed on a semiconductor substrate 11 made of silicon. As the gate insulating film 12, for example, a silicon oxide film formed by a thermal oxidation method can be employed. Here, a 3 nm silicon oxide film is formed at 850 ° C. Subsequently, a polysilicon film 13 is formed on the gate insulating film 12 by a CVD method or the like. In this embodiment, the polysilicon film 13 having a film thickness of 200 nm is formed by the CVD method at a film forming temperature of 600 ° C.

Next, as shown in FIG. 1B, a resist pattern 21 having an opening in an n-type impurity implantation region is formed on the polysilicon film 13 by photolithography. Then, using the resist pattern 21 as an implantation mask, n-type impurities are implanted into the polysilicon film 13 to form an n-type polysilicon region 15 in the polysilicon film 13. In this embodiment, phosphorus, which is an n-type impurity, is implanted into the polysilicon film 13 under conditions of an implantation energy of 15 keV and an implantation dose of 5 × 10 ¹⁵ atoms / cm ² .

Subsequently, after the resist pattern 21 is removed by ashing or the like, a resist pattern 22 having an opening in the implantation region of the p-type impurity is formed on the polysilicon film 13 by photolithography, and the resist pattern 22 is used as an implantation mask. As a result, p-type impurities are introduced into the polysilicon film 13. In this embodiment, boron, which is a p-type impurity, is implanted into the polysilicon film 13 under conditions of an implantation energy of 10 keV and an implantation dose of 5 × 10 ¹⁵ atoms / cm ² , thereby forming a p-type polysilicon region 15.

In this embodiment, next, as shown in FIG. 1D, the n-type polysilicon region 14 has an n-type impurity (here, phosphorus) concentration of 1 × 10 ¹⁹ atoms / cm ³ or more. A heat treatment is performed to form an upper region 17 and a lower region 18 that is less than 1 × 10 ¹⁹ atoms / cm ³ . The heat treatment is performed, for example, by raising the substrate temperature to 700 ° C. and maintaining the temperature for about 10 seconds, for example. In the present embodiment, a phosphorus concentration distribution as shown in FIG. 2 is realized by the heat treatment. In FIG. 2, the horizontal axis corresponds to the depth with the upper surface of the polysilicon film 13 as the origin, and the vertical axis corresponds to the phosphorus concentration. In FIG. 2, the region from the upper surface of the polysilicon film 13 to 150 nm is the upper region 17 having a phosphorus concentration of 1 × 10 ¹⁹ atoms / cm ³ or more, and extends from the lower end of the upper region 17 to the bottom surface of the polysilicon film 13. The region becomes the lower region 18 having a phosphorus concentration of less than 1 × 10 ¹⁹ atoms / cm ³ . The heat treatment may be performed under any conditions as long as the upper region and the lower region can be formed. For example, the heat treatment can be performed at a substrate temperature of about 600 ° C. to 700 ° C.

  When the heat treatment for forming the upper region 17 and the lower region 18 in the n-type polysilicon region 14 is completed, as shown in FIG. 1E, the n-type polysilicon region 14, the p-type polysilicon region 15, the non-implanted region A resist pattern 23 covering the gate electrode pattern formation region is formed on 16 by photolithography.

  Next, as shown in FIGS. 1F and 1G, the polysilicon film 13 is etched using the resist pattern 23 as an etching mask. In the etching step, first, etching is performed on the upper region 17 of the n-type polysilicon region 14 and the region corresponding to the upper region 17 of regions other than the n-type polysilicon region (p-type polysilicon region 15 and non-implanted region 16). A first etching process (FIG. 1E) is performed. Then, following the first etching process, a second etching process (etching of the lower region 18 of the n-type polysilicon region 14 and the region corresponding to the lower region 18 of the region other than the n-type polysilicon region ( FIG. 1F is performed.

  For these etching processes, for example, an ICP (Inductive Coupling Plasma) plasma etching apparatus can be used. As shown in FIG. 3, the ICP plasma etching apparatus 60 has a chamber 61 whose inner wall is covered with an insulating film such as ceramic, alumina, or quartz, and a substrate 70 to be processed is placed in the chamber 61. A lower electrode 62 serving as a sample stage is provided. The chamber wall facing the lower electrode 62 is constituted by a dielectric wall 67 such as quartz, and a coiled upper electrode 63 is disposed on the dielectric wall 67. A high frequency power source 65 is connected to the upper electrode 63 via a matching unit 64, and a high frequency power source 68 is connected to the lower electrode 62 via a matching unit 69.

  In addition, a gas inlet 71 through which an etching gas is introduced via a mass flow controller is communicated with the upper portion of the side wall of the chamber 61, and a gas exhaust port 72 for exhausting the gas in the chamber is connected to the lower wall of the chamber 61. Is communicated. A turbo pump (not shown) is interposed in the gas exhaust port 72, and the internal pressure of the chamber 61 is maintained at a constant pressure of about 0.1 Pa to 10 Pa. In addition, a temperature control mechanism for holding the electrode at a constant temperature is built in the lower electrode 62.

In such a plasma etching apparatus 60, first, a first etching process for etching the upper region 17 is performed. In the etching process, a gas containing fluorine element, for example, CF ₄ gas is 30 ml / min, Cl ₂ gas is 20 ml / min, HBr gas is 30 ml / min, and O ₂ gas is 6 ml / min. It is introduced at a flow rate (flow rate at 1 ° C. and 1 atm). At this time, the internal pressure of the chamber 61 is maintained at 0.7 Pa. In this state, high frequency power of 400 W is applied to the upper electrode 63 from the high frequency power supply 65, and high frequency power of 50 W is applied to the lower electrode 62 from the high frequency power supply 68. Then, the etching gas plasma is generated in the chamber 61 by the high frequency power applied to the upper electrode 62. The ions in the plasma are incident on the substrate 70 to be processed on the lower electrode 62 by the high frequency power applied to the lower electrode 62 as a bias, and etching is performed. In the present embodiment, the temperature of the lower electrode 62 is maintained at 20 ° C.

  Here, the etching of the polysilicon film will be described. FIG. 4 is a diagram showing the n-type impurity concentration dependence of the ratio of the etching rate of the p-type polysilicon film to the n-type polysilicon film. The etching rate ratio is a value calculated by (etching rate of p-type polysilicon) / (etching rate of n-type polysilicon). In FIG. 4, a solid line A indicates an etching rate ratio in a state where there is no fluorine element contributing to etching, and a broken line B indicates an etching rate ratio in a state where a fluorine element contributing to etching exists. ing.

As shown in FIG. 4, in the situation where no fluorine element exists (solid line A), when the impurity concentration in the n-type polysilicon film is 1 × 10 ¹⁹ atoms / cm ³ or more, the etching rate ratio gradually decreases. , “0.8” or less. As described above, this indicates that the etching rate of the n-type polysilicon film is about 20% faster than the etching rate of the p-type polysilicon film when the n-type impurity concentration is increased.

  On the other hand, under the situation where fluorine element exists (broken line B), the etching rate ratio does not depend on the impurity concentration introduced into the n-type polysilicon film, and is a constant value of “1.0”. This indicates that the n-type polysilicon film and the p-type polysilicon film are etched at the same etching rate under the situation where fluorine element exists.

That is, since the CF ₄ gas is introduced into the chamber 61 as the etching condition of the first etching process described above, each region of the n-type polysilicon region 14, the p-type polysilicon region 15, and the non-implanted region 16 is used. No difference occurs in the etching rate, and etching can be performed at the same etching rate. For this reason, by performing etching for a certain period of time according to the etching rate, uniform etching from the upper surface of the polysilicon film 13 to a predetermined depth in each of the regions 14, 15, and 16 is performed as shown in FIG. It can be performed. In the present embodiment, 150 nm etching corresponding to the upper region 17 of the n-type polysilicon region 14 is performed by the first etching process (a 50 nm thick polysilicon film remains). In the first etching process, there is no difference in the etching rate in each of the regions 14, 15, and 16. Therefore, a polysilicon film is detected using a known film thickness detection type EPD (End Point Detector) using reflected light. It is also possible to measure the remaining thickness of 13 and detect the etching end point.

Subsequent to the first etching process, the second etching process is performed. In the etching process, the polysilicon film 13 (here, a 50 nm thick polysilicon film) remaining in the etching region is etched. As shown in FIG. 2, since the impurity concentration in the n-type polysilicon film etched by the second etching process is less than 1 × 10 ¹⁹ atoms / cm ³ , as shown in FIG. Even in a situation where there is no etching, there is no difference in etching rate between the n-type polysilicon region 14, the p-type polysilicon region 15, and the non-implanted region 16, and etching can be performed at the same etching rate. .

In the present embodiment, the second etching process is performed by introducing HBr gas at a flow rate of 150 ml / min and O ₂ gas at a flow rate of 10 ml / min as an etching gas into the chamber 61 of the plasma etching apparatus 60 and setting the internal pressure to 1. Maintain at 3 Pa. In this state, etching is performed by applying high frequency power of 300 W to the upper electrode 63 and 30 W to the lower electrode 62. The etching conditions are etching conditions that can obtain a higher selectivity with respect to the gate insulating film 12 than the etching conditions of the first etching process.

  Accordingly, in the second etching process, the n-type polysilicon region 14, the p-type polysilicon region 15, and the non-implanted region 16 are etched at the same etching rate as in the first etching process. In addition, etching can be performed without damaging the gate insulating film 12. In addition, since there is no difference in the etching rate in each of the regions 14, 15, and 16, the etching end point of the second etching process is the light intensity when the gate insulating film 12 is exposed in the plasma radiation light during the etching process. It is possible to detect with high accuracy by always measuring the light of a specific wavelength that changes and detecting the light intensity change.

  Thereafter, the resist pattern 23 is removed, and the gate electrode pattern is completed as shown in FIG.

  As described above, according to the present embodiment, even when simultaneously etching a polysilicon film in which an n-type polysilicon region, a p-type polysilicon region, and a non-implanted region are mixed, each region is formed at the same etching rate. It can be etched. Therefore, by measuring the etching time or the remaining thickness of the polysilicon film, it is possible to easily detect when the etching gas is switched or when etching is completely completed. Therefore, the etching of the polysilicon film including the n-type polysilicon region, the p-type polysilicon region, and the non-implanted region can be easily performed without damaging the gate insulating film.

In the above description, a gas containing CF ₄ is used as the etching gas for the first etching process, but any gas may be used as long as it contains a fluorine element that can act on the etching of the polysilicon film. be able to. The etching gas may be, for example, a gas containing CHF ₃ , C ₂ F ₆ , C ₃ F ₈ , C ₄ F ₈ , NF ₃ , or SF ₆ .

(Second Embodiment)
Next, a semiconductor device manufacturing method according to the second embodiment of the present invention will be described in detail with reference to the drawings. FIG. 5 is a process cross-sectional view illustrating the method for manufacturing the semiconductor device according to the present embodiment.
In the present embodiment, unlike the first embodiment, the etching mask of the gate electrode is formed of an insulating film. The process until the n-type polysilicon region 14 and the p-type polysilicon region 15 are formed in the polysilicon film 13 is the same as that in the first embodiment.

  As shown in FIG. 5A, the n-type polysilicon region 14 and the p-type polysilicon are formed on the semiconductor substrate 11 via the gate insulating film 12 by the steps shown in FIGS. A polysilicon film 13 divided into a region 15 and a non-implanted region 16 is formed.

Next, as shown in FIG. 5B, an insulating film 31 is formed on the polysilicon film 13. As the insulating film 31, for example, a TEOS film formed by LP-CVD (Low Pressure-CVD) method using tetraethoxyoxosilane (TEOS) and O ₂ gas as raw materials can be used. Here, a TEOS film having a thickness of 100 nm is formed at a film formation temperature of 600 ° C. In the present embodiment, the n-type impurity concentration (here, phosphorus) is 1 × 10 ¹⁹ atoms / cm in the n-type polysilicon region 14 by using the temperature rise when forming the insulating film 31. ^An upper region 17 that is ³ or more and a lower region 18 that is less than 1 × 10 ¹⁹ atoms / cm ³ are formed.

  Subsequently, as shown in FIG. 5C, the insulating film 31 is formed into the gates of the n-type polysilicon region 14, the p-type polysilicon region 15, and the non-implanted region 16 using a known photolithography and etching technique. It is processed into a pattern covering the electrode pattern formation region.

  Then, as shown in FIG. 5D, using the pattern of the insulating film 31 as an etching mask, the upper region 17 of the n-type polysilicon region 14 and regions other than the n-type polysilicon region (p-type polysilicon region 15 and A first etching process is performed in which the region corresponding to the upper region 17 of the non-implanted region 16) is etched. The first etching process can be performed under the same conditions as in the first embodiment.

  Subsequent to the first etching process, as shown in FIG. 5E, the lower region 18 of the n-type polysilicon region 14 and the region corresponding to the lower region 18 other than the n-type polysilicon region are etched. A second etching process is performed. The second etching process may be performed in the same manner as in the first embodiment. Thereafter, the pattern of the insulating film 31 is removed, and the formation of the gate electrode pattern is completed as shown in FIG.

  Also in the present embodiment, as in the first embodiment, even when simultaneously etching a polysilicon film in which an n-type polysilicon region, a p-type polysilicon region, and a non-implanted region are mixed, each region is subjected to the same etching. Can be etched at a rate. For this reason, the etching of the polysilicon film in which the n-type polysilicon region, the p-type polysilicon region, and the non-implanted region are mixed can be easily performed without damaging the gate insulating film.

  In addition, in the present embodiment, the etching mask is composed of an insulating film such as a TEOS film. Since the mask made of an insulator has higher etching resistance than an etching mask made of resist, the thickness of the etching mask can be made smaller than that of the first embodiment. Therefore, the aspect ratio of the etching mask can be reduced, and the probability that ions incident on the substrate collide with the sidewall of the etching mask and are scattered during the etching process can be reduced. As a result, it is possible to prevent the ions scattered on the sidewall of the etching mask from entering the gate insulating film and damaging the gate insulating film.

(Third embodiment)
Next, a semiconductor device manufacturing method according to the third embodiment of the present invention will be described in detail with reference to the drawings. FIG. 6 is a process cross-sectional view illustrating the method for manufacturing the semiconductor device according to the present embodiment.
In the present embodiment, unlike the second embodiment, the gate electrode etching mask is formed of an insulating film containing a fluorine element. In the present embodiment, the steps from forming the n-type polysilicon region 14 and the p-type polysilicon region 15 in the polysilicon film 13 and forming the upper region 17 and the lower region 18 are the same as those in the first embodiment. Is the same.

As shown in FIG. 6A, the n-type polysilicon region 14 and the p-type polysilicon are formed on the semiconductor substrate 11 through the gate insulating film 12 by the steps shown in FIGS. A polysilicon film 13 divided into a region 15 and a non-implanted region 16 is formed. Here, the n-type polysilicon region 14, by the heat treatment described in the first embodiment, the upper region 17 is the concentration of the n-type impurity 1 × 10 ¹⁹ atoms / cm ³ or more, 1 × 10 ¹⁹ atoms A lower region 18 that is less than / cm ³ is formed.

Next, as shown in FIG. 6B, an insulating film 32 containing a fluorine element is formed on the polysilicon film 13. As the insulating film 32, for example, an FSG (Fluorosilicate Glass) film formed by HDP-CVD (High Density Plasma-CVD) method using SiH ₄ gas, SiF ₄ gas, and O ₂ gas as raw materials may be used. it can. Here, an FSG film having a thickness of 100 nm is formed at a film formation temperature of 200 ° C.

  Subsequently, as shown in FIG. 6C, the insulating film 32 is formed into the gates of the n-type polysilicon region 14, the p-type polysilicon region 15, and the non-implanted region 16 using a known photolithography and etching technique. It is processed into a pattern covering the electrode pattern formation region.

  Then, as shown in FIG. 6D, using the pattern of the insulating film 32 as an etching mask, the upper region 17 of the n-type polysilicon region 14 and regions other than the n-type polysilicon region (p-type polysilicon region 15 and A first etching process is performed in which the region corresponding to the upper region 17 of the non-implanted region 16) is etched.

In the present embodiment, the first etching process is performed in the chamber 61 of the plasma etching apparatus 60 described in the first embodiment, for example, Cl ₂ gas is 30 ml / min, HBr gas is 20 ml / min, and O ₂ gas. Is introduced at a flow rate of 6 ml / min (flow rate at 1 ° C. and 1 atm). At this time, the internal pressure of the chamber 61 is maintained at 0.7 Pa. In this state, high frequency power of 400 W is applied to the upper electrode 63 from the high frequency power supply 65, and high frequency power of 50 W is applied to the lower electrode 62 from the high frequency power supply 68. Then, the plasma of the etching gas is generated in the chamber 61 by the high frequency power applied to the upper electrode 62, and etching is performed. At this time, the temperature of the lower electrode 62 is maintained at 20 ° C.

  Since the etching conditions are low pressure and high voltage, the etching conditions are strongly anisotropic, and ions incident on the substrate 11 violently collide with the pattern of the insulating film 32 containing the fluorine element. At this time, halogen ions react with the insulating film 32 (here, FSG film) on the pattern surface of the insulating film 32 to generate fluorine. Therefore, according to the etching conditions, as in the above embodiments, there is no difference in the etching rate in each of the n-type polysilicon region 14, the p-type polysilicon region 15, and the non-implanted region 16, Etching can be performed at the same etching rate.

  Following the first etching process, as shown in FIG. 6E, the lower region 18 of the n-type polysilicon region 14 and the region corresponding to the lower region 18 other than the n-type polysilicon region are etched. A second etching process is performed.

  In the present embodiment, the second etching process is performed under the same etching conditions as in the first embodiment. The etching conditions are isotropic etching because of high pressure and low voltage. For this reason, reaction between halogen ions and the insulating film 32 containing a fluorine element does not occur on the surface of the insulating film 32, and fluorine is not generated from the pattern of the insulating film 32. Therefore, as in the above embodiments, the n-type polysilicon region 14, the p-type polysilicon region 15, and the non-implanted region 16 can be etched at the same etching rate, and the gate insulating film Etching can be performed without damaging 12.

  Thereafter, the pattern of the insulating film 32 is removed, and the formation of the gate electrode pattern is completed as shown in FIG.

  Also in this embodiment, as in the above embodiments, even when simultaneously etching a polysilicon film in which an n-type polysilicon region, a p-type polysilicon region, and a non-implanted region are mixed, each region has the same etching rate. Can be etched. For this reason, the etching of the polysilicon film in which the n-type polysilicon region, the p-type polysilicon region, and the non-implanted region are mixed can be easily performed without damaging the gate insulating film.

  In addition, in the present embodiment, an etching mask is constituted by an insulating film containing fluorine such as an FSG film, and fluorine necessary for the first etching process is generated from the insulating film. For this reason, it is not necessary to directly introduce a gas containing a fluorine element into the chamber of the plasma etching apparatus. Since the gas containing elemental fluorine is highly corrosive, the inner wall of the chamber into which the gas is introduced is corroded. Such corrosion of the inner wall of the chamber causes generation of particles that reduce the manufacturing yield of the semiconductor device. Therefore, in this embodiment, generation of such particles can be suppressed.

As described above, according to the present invention, the etching rate of the upper region where the n-type impurity concentration is 1 × 10 ¹⁹ atoms / cm ³ or more differs between the n-type polysilicon region and the other regions. Etching is performed using an etching gas containing an elemental fluorine that does not cause an n-type impurity, with an n-type impurity concentration of less than 1 × 10 ¹⁹ atoms / cm ³ under etching conditions having a high selectivity to the gate insulating film. Therefore, it is possible to easily detect the time when the etching conditions are switched and the etching end point, and it is possible to reliably prevent damage to the gate insulating film. As a result, a semiconductor device having a dual gate structure can be easily and
It can be manufactured with good yield.

  The present invention is not limited to the embodiments described above, and various modifications and applications are possible within the scope of the effects of the present invention. For example, in the above description, the present invention has been described based on an example in which the present invention is applied to a semiconductor device in which the gate electrode is made of polysilicon. The same effect can be obtained. In addition, the process employed in each process for manufacturing the semiconductor device can be replaced with another equivalent process without departing from the technical idea of the present invention.

  The present invention can form a dual gate structure easily and with high yield, and is useful as a method for manufacturing a semiconductor device.

Sectional drawing which shows the manufacturing process of the semiconductor device which concerns on the 1st Embodiment of this invention. The figure which shows the density distribution of the n-type impurity in a polysilicon film Cross section of plasma etching system The figure which shows the n-type impurity concentration dependence of the etching rate ratio of p-type polysilicon with respect to n-type polysilicon Sectional drawing which shows the manufacturing process of the semiconductor device which concerns on the 2nd Embodiment of this invention. Sectional drawing which shows the manufacturing process of the semiconductor device which concerns on the 3rd Embodiment of this invention. Sectional drawing showing the manufacturing process of a conventional semiconductor device Sectional view showing a conventional semiconductor device

Explanation of symbols

DESCRIPTION OF SYMBOLS 11 Substrate 12 Gate insulating film 13 Polo silicon film 14 N-type polysilicon region 15 P-type polysilicon region 16 Non-implanted region 17 Upper region 18 Lower region 31 TEOS film 32 FSG film 60 Dry etching apparatus

Claims (13)

In a method for manufacturing a semiconductor device having a dual gate structure,
Forming a gate insulating film on the semiconductor layer;
Forming a silicon film made of polysilicon or amorphous silicon on the gate insulating film;
An n-type region comprising an upper region in which an n-type impurity is introduced into a part of the silicon film and the concentration of the n-type impurity is equal to or higher than a specific concentration and a lower region in which the concentration of the n-type impurity is lower than the specific concentration Forming a step;
Forming a mask pattern having a pattern covering at least the gate formation region of the n-type region and a pattern covering a gate formation region other than the n-type region on the silicon film;
Using the mask pattern as an etching mask, and dry-etching the upper region together with a region other than the n-type region with an etching species containing fluorine element;
Using the mask pattern as an etching mask, dry etching the remainder of the silicon film with an etching species different from the dry etching;
A method for manufacturing a semiconductor device, comprising:   The method of manufacturing a semiconductor device according to claim 1, wherein the dry etching of the remaining silicon film is performed with an etching species that does not contain a fluorine element. The method for manufacturing a semiconductor device according to claim 1, wherein the specific concentration is 1 × 10 ¹⁹ atoms / cm ³ .   The method for manufacturing a semiconductor device according to claim 1, wherein the upper region and the lower region are formed by heat treatment at 600 ° C. to 700 ° C. 5.   The method of manufacturing a semiconductor device according to claim 1, wherein the mask pattern is a resist pattern.   The method of manufacturing a semiconductor device according to claim 1, wherein the mask pattern is an insulating film pattern.   The method of manufacturing a semiconductor device according to claim 6, wherein the insulating film is a film made of tetraethoxyoxosilane.   The method for manufacturing a semiconductor device according to claim 6, wherein the insulating film is formed at a temperature of 600 to 700 ° C.   The method for manufacturing a semiconductor device according to claim 1, wherein the dry etching of the upper region is performed using an etching gas containing a fluorine element. The etching gas includes one or more gases selected from CF ₄ , CHF ₃ , C ₂ F ₆ , C ₃ F ₈ , C ₄ F ₈ , NF ₃ , and SF _6. Semiconductor device manufacturing method.   The method for manufacturing a semiconductor device according to claim 6, wherein the insulating film is a film containing a fluorine element.   The method for manufacturing a semiconductor device according to claim 11, wherein the fluorine element of the etching species is a fluorine element generated from the insulating film.   The method for manufacturing a semiconductor device according to claim 11, wherein the dry etching of the upper region is performed using an etching gas containing at least one of chlorine element and bromine element.

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