US20020014662A1 - Fabrication method for semiconductor integrated circuit devices and semiconductor integrated circuit device - Google Patents

Fabrication method for semiconductor integrated circuit devices and semiconductor integrated circuit device Download PDF

Info

Publication number
US20020014662A1
US20020014662A1 US09/810,577 US81057701A US2002014662A1 US 20020014662 A1 US20020014662 A1 US 20020014662A1 US 81057701 A US81057701 A US 81057701A US 2002014662 A1 US2002014662 A1 US 2002014662A1
Authority
US
United States
Prior art keywords
gate electrode
integrated circuit
gas
circuit device
semiconductor integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
US09/810,577
Other versions
US6479392B2 (en
Inventor
Kazuo Yamazaki
Shinji Kuniyoshi
Kousuke Kusakari
Takenobu Ikeda
Masahiro Tadokoro
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Electronics Corp
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Assigned to HITACHI, LTD. reassignment HITACHI, LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: KUNIYOSHI, SHINJI, IKEDA, TAKENOBU, YAMAZAKI, KAZUO, TADOKORO, MASAHIRO, KUSAKARI, KOUSUKE
Priority to US09/811,589 priority Critical patent/US6633072B2/en
Publication of US20020014662A1 publication Critical patent/US20020014662A1/en
Application granted granted Critical
Publication of US6479392B2 publication Critical patent/US6479392B2/en
Priority to US10/639,465 priority patent/US7375037B2/en
Assigned to RENESAS ELECTRONICS CORPORATION reassignment RENESAS ELECTRONICS CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: HITACHI, LTD.
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
    • H01L21/02071—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers the processing being a delineation, e.g. RIE, of conductive layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/2807—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being Si or Ge or C and their alloys except Si
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H01L21/32137—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas of silicon-containing layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/823842—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/82385—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different shapes, lengths or dimensions

Definitions

  • the present invention relates to a technology of a fabrication method for semiconductor integrated circuit devices and a semiconductor integrated circuit device, particularly to a technology effectively applied to a fabrication method for semiconductor integrated circuit devices and a semiconductor integrated circuit device having an alloy of silicon (Si) and germanium (Ge) (hereinafter, simply referred to as SiGe) of polycrystal or single crystal.
  • Si silicon
  • Ge germanium
  • a processing of forming a gate electrode having an SiGe layer includes three processing steps of depositing a gate electrode forming film, patterning thereof and a postprocessing thereof. That is, first, after forming a gate insulating film over a main face of a semiconductor substrate, a gate electrode forming film having an SiGe layer is deposited thereabove. Successively, after forming a photoresist pattern over the gate electrode forming film, a gate electrode having the SiGe layer is formed by patterning the gate electrode forming film by using an etching gas including, for example, chlorine (Cl 2 ) and bromine (Br) with the photoresist pattern as an etching mask.
  • an etching gas including, for example, chlorine (Cl 2 ) and bromine (Br) with the photoresist pattern as an etching mask.
  • a plasma processing is carried out to the semiconductor substrate in an atmosphere of a predetermined gas (postprocessing).
  • the postprocessing is a processing which is also carried out after forming the gate electrode by patterning polycrystal silicon and when the postprocessing is not carried out, there causes a drawback, for example, as follows. That is, when the reaction products are not removed, occurrence of foreign matters is caused and reliability or yield of the semiconductor integrated circuit device is deteriorated.
  • the adhered matters are adhered to a main face of other semiconductor substrate before patterning the gate electrode, in patterning the gate electrode of the other semiconductor substrate, the adhered matters constitute a mask and there is produced etching residue of a gate electrode material.
  • Cl or Br adhered to the surface of the semiconductor substrate is not removed, parts of a semiconductor fabricating apparatus are corroded by Cl or Br. Further, Cl or Br is toxic and therefore, adverse influence is effected on the human body.
  • a gas in the postprocessing when SiGe is used as the gate electrode material there is used, for example, O 2 /CHF 3 since a stable electricity discharge range is provided, further, the gas is generally used in the postprocessing when polycrystal silicon is used as a gate electrode material, an amount of data is enormous and introduction thereof is facilitated. Similar to the postprocessing when the polycrystal silicon is used as a gate electrode material.
  • steps of forming a gate electrode having an SiGe layer over a semiconductor substrate by patterning a gate electrode forming film having the SiGe layer and thereafter subjecting the semiconductor substrate to a plasma processing in an atmosphere of a mixed gas of a first gas hardly reactive to Ge and a second gas having a function of etching Si.
  • steps of forming a gate electrode over a semiconductor substrate by patterning a gate electrode forming film deposited on the semiconductor substrate and thereafter subjecting the semiconductor substrate to a plasma processing in an atmosphere of a mixed gas of a first gas hardly reactive to Ge and a second gas having a function of etching Si and the step of depositing the gate electrode forming film includes a step of depositing an SiGe layer and a step of depositing a polycrystal silicon layer at a layer upward from the SiGe layer.
  • a step of forming side wall insulating films at side faces of the gate electrode a step of exposing an upper face of the gate electrode and portions of a main face of the semiconductor substrate, a step of depositing a metal film having a high melting point over the semiconductor substrate and a step of forming a metal silicide layer having a high melting point at the upper face of the gate electrode and the portions of the main face of the semiconductor substrate.
  • the metal silicide layer having the high melting point is made of cobalt silicide.
  • steps of forming a gate electrode over a semiconductor substrate by patterning a gate electrode forming film deposited over the semiconductor substrate and thereafter subjecting the semiconductor substrate to a plasma processing in an atmosphere of a mixed gas of a first gas hardly reactive to Ge and a second gas having a function of etching Si and the step of depositing the gate electrode forming film includes a step of depositing an SiGe layer and a step of depositing a metal layer at a layer upward from the SiGe layer.
  • the first gas is constituted by an inert gas.
  • the first gas is constituted by Ar, He, Kr or Xe.
  • the first gas is constituted by nitrogen gas.
  • the second gas is constituted by a gas including fluorine.
  • the second gas is constituted by CHF 3 , CF 4 , C 2 F 6 or SF 6 .
  • pressure in the atmosphere is made equal to or smaller than 70 Pa.
  • a microwave power for forming a plasma is made 750 W.
  • a concentration of the second gas is made equal to or smaller than 5% of a total.
  • the gate electrode forming film having the SiGe layer when the gate electrode forming film having the SiGe layer is patterned, there is carried out a plasma etching processing in an atmosphere of chlorine, bromine or a mixed gas of these.
  • a concentration of Ge of the SiGe layer is made equal to or larger than 10% of a total.
  • the concentration of Ge of the SiGe layer is made equal to or larger than 20% of the total.
  • the concentration of Ge of the SiGe layer is made equal to or larger than 40% of the total.
  • a step of fabricating a semiconductor integrated circuit device in which the semiconductor substrate after the step of patterning the gate electrode is transferred to the plasma processing step in a state of maintaining a vacuum state.
  • a side etching amount at two side faces of the gate electrode after the plasma processing is made equal to or smaller than 40% of a length in a channel length direction of the gate electrode at a portion thereof other than the SiGe layer.
  • a length in the channel direction of the gate electrode at the SiGe layer after the plasma processing is equal to the length in the channel length direction of the gate electrode at the portion other than the SiGe layer.
  • a gate electrode of an n-channel type field effect transistor or a p-channel type field effect transistor formed on the same semiconductor substrate for the gate electrode.
  • FIG. 1 is an explanatory view of an etching apparatus used for a fabrication method of semiconductor integrated circuit devices according to an embodiment of the invention
  • FIG. 2 is a sectional view of essential portions in a fabrication step of the semiconductor integrated circuit device according to the embodiment of the invention.
  • FIG. 3 is a sectional view of essential portions in a fabrication step of the semiconductor integrated circuit device continuous to FIG. 2;
  • FIG. 4A is a sectional view of essential portions in a fabrication step of the semiconductor integrated circuit device continuous to FIG. 3 and
  • FIG. 4B is a sectional view enlarging essential portions of an area of forming n-channel type MISFET of FIG. 4A;
  • FIG. 5A is a sectional view of essential portions in a fabrication step of the semiconductor integrated circuit device continuous to FIG. 4A and
  • FIG. 5B is a sectional view enlarging essential portions of an area of forming n-channel type MISFET of FIG. 5A;
  • FIG. 6A is a sectional view of essential portions in a fabrication step of the semiconductor integrated circuit device continuous to FIG. 5A and
  • FIG. 6B is a sectional view enlarging essential portions of an area of forming n-channel type MISFET of FIG. 6A;
  • FIG. 7A is a sectional view of essential portions in a fabrication step of the semiconductor integrated circuit device continuous to FIG. 6A and
  • FIG. 7B is a sectional view enlarging essential portions of an area of forming n-channel type MISFET of FIG. 7A;
  • FIG. 8A is a partial sectional view of a semiconductor substrate after a postprocessing for explaining a problem of a technology investigated by the inventors for carrying out the invention.
  • FIG. 8B is a sectional view enlarging essential portions of FIG. 8A;
  • FIG. 9A is a sectional view of essential portions in a fabrication step of the semiconductor integrated circuit device continuous to FIG. 7A and
  • FIG. 9B is a sectional view enlarging essential portions of an area of forming n-channel type MISFET of FIG. 9A;
  • FIG. 10 is a graph diagram showing a result of investigating whether Cl, Br or the like adhered to the semiconductor substrate has been removed by the postprocessing of the invention by total reflection type fluorescent X-ray;
  • FIG. 11A is a sectional view of essential portions in a fabrication step of the semiconductor integrated circuit device continuous to FIG. 9A and
  • FIG. 11B is a sectional view enlarging essential portions of an area of forming n-channel type MISFET of FIG. 11A;
  • FIG. 12A is a sectional view of essential portions in a fabrication step of the semiconductor integrated circuit device continuous to FIG. 11A and
  • FIG. 12B is a sectional view enlarging essential portions of an area of forming n-channel type MISFET of FIG. 12A;
  • FIG. 13A is a sectional view of essential portions in a fabrication step of the semiconductor integrated circuit device continuous to FIG. 12A and
  • FIG. 13B is a sectional view enlarging essential portions of an area of forming n-channel type MISFET of FIG. 13A;
  • FIG. 14A is a sectional view of essential portions in a fabrication step of the semiconductor integrated circuit device continuous to FIG. 13A and
  • FIG. 14B is a sectional view enlarging essential portions of an area of forming n-channel type MISFET of FIG. 14A;
  • FIG. 15 is a sectional view of essential portions in a fabrication step of the semiconductor integrated circuit device continuous to FIG. 14A;
  • FIG. 16A is a sectional view of essential portions in a fabrication step of a semiconductor integrated circuit device according to other embodiment of the invention.
  • FIG. 16B is a sectional view enlarging essential portions of an area of forming n-channel type MISFET of FIG. 16A;
  • FIG. 17A is a sectional view of essential portions in a fabrication step of the semiconductor integrated circuit device continuous to FIG. 16A and
  • FIG. 17B is a sectional view enlarging essential portions of an area of forming n-channel type MISFET of FIG. 17A;
  • FIG. 18A is a sectional view of essential portions in a fabrication step of the semiconductor integrated circuit device continuous to FIG. 17A and
  • FIG. 18B is a sectional view enlarging essential portions of an area of forming n-channel type MISFET of FIG. 18A;
  • FIG. 19A is a sectional view of essential portions in a fabrication step of the semiconductor integrated circuit device continuous to FIG. 18A and
  • FIG. 19B is a sectional view enlarging essential portions of an area of forming n-channel type MISFET of FIG. 19A;
  • FIG. 20A is a sectional view of essential portions in a fabrication step of the semiconductor integrated circuit device continuous to FIG. 19A and
  • FIG. 20B is a sectional view enlarging essential portions of an area of forming n-channel type MISFET of FIG. 20A;
  • FIG. 21A is a sectional view of essential portions in a fabrication step of the semiconductor integrated circuit device continuous to FIG. 20A and
  • FIG. 21B is a sectional view enlarging essential portions of an area of forming n-channel type MISFET of FIG. 21A.
  • FIG. 22A is a sectional view of essential portions in a fabrication step of the semiconductor integrated circuit device continuous to FIG. 21A and
  • FIG. 22B is a sectional view enlarging essential portions of an area of forming n-channel type MISFET of FIG. 22A.
  • a semiconductor wafer refers to a silicon single crystal substrate (generally, substantially in a planer circle shape) used in fabrication of a semiconductor integrated circuit, a sapphire substrate, a glass substrate, other insulating, noninsulating or semiconductor substrate as well as a substrate of a composite of these.
  • a semiconductor device includes a semiconductor device formed on a semiconductor or an insulating substrate such as a silicon wafer or a sapphire substrate as well as, a semiconductor device formed on other insulating substrate of glass or the like such as TFT (Thin-Film-Transistor) and STN (Super-Twisted Nematic) liquid crystal except a case particularly specified otherwise.
  • TFT Thin-Film-Transistor
  • STN Super-Twisted Nematic liquid crystal except a case particularly specified otherwise.
  • a constituent element is not naturally indispensable necessarily except a case particularly specified and a case regarded as clearly indispensable.
  • MISFET Metal Insulator Semiconductor Field Effect Transistor
  • MIS Metal Insulator Semiconductor Field Effect Transistor
  • pMIS pMIS
  • nMIS nMIS
  • FIG. 1 exemplifies a constitution of an etching apparatus 1 used in a fabrication method of a semiconductor integrated circuit device according to Embodiment 1.
  • the etching apparatus 1 is an apparatus for carrying out a series of processings for patterning a wiring forming film having an SiGe layer into a predetermined shape.
  • a semiconductor wafer to be subjected to an etching processing is mounted to an arbitrary location of wafer cassette bases 2 a through 2 c .
  • the semiconductor wafer at the wafer cassette bases 2 a through 2 c is transferred to an alignment unit 4 by an atmospheric transfer robot 3 .
  • aligning of a direction of a notch or an orientation flat of the semiconductor wafer is carried out.
  • the semiconductor wafer finished with the alignment processing is transferred to a load/lock chamber 5 again by the atmospheric transfer robot 3 .
  • vacuuming is carried out in the load/lock chamber 5 when the semiconductor wafer is transferred therein.
  • the semiconductor wafer passes through a vacuum transfer chamber 7 and is transferred into an etching chamber 8 by a vacuum transfer robot 6 . Further, a vacuum state is maintained in the vacuum transfer chamber 7 .
  • a wiring forming film having an SiGe layer is patterned to a predetermined shape by, for example, a plasma dry etching processing.
  • an electricity discharge system in the etching chamber 8 there can be used all of electricity discharge systems such as ECR (Electron Cyclotron Resonance), RIE (Reactive Ion Etching), two frequency RIE, magnetron RIE and ICP (Inductively Coupled Plasma).
  • Etching gas is produced by a single gas or a mixed gas of Cl 2 , HBr, O 2 as explained later in detail.
  • a first step of etching processing there is used a single gas of Cl 2 having a low selection ratio with regard to a silicon oxide film (SiO 2 ) and at and after a second step, there is a gas, for example, HBr/Cl 2 or HBr/Cl 2 /O 2 to provide an anisotropic shape.
  • a gas having a high selection ratio with regard to a silicon oxide film such as HBr/O 2 or Cl 2 /O 2 .
  • the semiconductor wafer finished with the etching processing passes through the vacuum transfer chamber 7 and is transferred into a postprocessing chamber 9 again by the vacuum transfer robot 6 . That is, the semiconductor wafer after the etching processing is transferred into the postprocessing chamber 9 while maintaining the vacuum state without being brought into contact with the outer air.
  • a plasma processing is carried out to the semiconductor wafer as is explained later in detail.
  • the electricity discharge system of the postprocessing chamber 9 similar to the etching chamber 8 , there can be used all of discharge systems such as ECR, RIE, two frequency RIE, magnetron RIE or ICP.
  • the semiconductor wafer finished with the postprocessing is transferred to an unload/unlock chamber 10 again by the vacuum transfer robot 6 and is returned to the wafer cassette bases 2 a through 2 c by the atmospheric transfer robot 3 .
  • FIG. 4B through FIG. 9B and FIG. 11B through FIG. 15B are sectional views enlarging essential portions of an nMIS forming area of FIG. 4A through FIG. 9A and FIG. 11A through FIG. 15A.
  • a gate electrode structure of a pMIS forming area is the same as a gate electrode structure of the nMIS forming area and accordingly, illustration thereof are omitted.
  • FIG. 8 is a view for explaining a problem of a technology investigated by the inventors for carrying out the invention.
  • a semiconductor substrate 11 S comprising, for example, p-type single crystal silicon.
  • the groove 12 a is formed by covering an element forming area of the semiconductor substrate 11 S with a silicon nitride film and thereafter subjecting the semiconductor substrate 11 at an element separating area to dry etching with the silicon nitride film as a mask.
  • CVD Chemical Vapor Deposition
  • CMP Chemical Mechanical Polishing
  • a p-type well 13 P is formed by ion-implanting, for example, boron thereto and at a pMIS forming area, an n-type well 13 N is formed by ion-implanting, for example, phosphor thereto.
  • an impurity for example, boron
  • an impurity for example, phosphor
  • the gate insulating film 14 may be constituted by a silicon oxynitride film in place of the silicon oxide film. That is, when the film thickness of the gate insulating film 14 is thinned, as described later, a portion of an impurity (boron) in an SiGe layer constituting a portion of a gate electrode by a heat treatment in processing, penetrates the gate insulating film 14 and is diffused into the semiconductor substrate 11 S and threshold voltage becomes liable to vary. In comparison with the silicon oxide film, the impurity is difficult to penetrate the silicon oxynitride film and accordingly, by constituting the gate insulating film 14 by the silicon oxynitride film, the threshold voltage can be restrained from varying.
  • the silicon oxynitride film in comparison with the silicon oxide film, there is provided a high effect of restraining occurrence of interfacial level or reducing electron trap in the film and accordingly, hot-carrier resistance of the gate insulating film 14 can be promoted and insulation resistance can be promoted.
  • a semiconductor substrate 1 may be subjected to a heat treatment in a nitrogen including gas atmosphere such as NO, NO 2 or NH 3 .
  • a nitrogen including gas atmosphere such as NO, NO 2 or NH 3 .
  • an effect similar to the above-described can be achieved by forming the gate insulating films 14 comprising silicon oxide at respective surfaces of the p-type well 13 P and the n-type well 13 N and thereafter subjecting the semiconductor substrate 11 S to the heat treatment in the above-described nitrogen gas including atmosphere and segregating nitrogen at an interface of the gate insulating film 14 and the semiconductor substrate 11 S.
  • the gate insulating film 14 may be formed by, for example, a silicon nitride film or a composite insulating film of a silicon oxide film and a silicon nitride film.
  • the gate insulating film 14 comprising silicon oxide is thinned to less than 5 nm, particularly, less than 3 nm by a film thickness converted into that of a silicon dioxide film, there is actualized a deterioration in insulation resistance directly by generating tunnel current or hot carriers caused by stress.
  • the silicon nitride film is provided with a dielectric constant higher than that of the silicon oxide film and accordingly, the silicon dioxide conversion film thickness becomes thinner than an actual film thickness.
  • the gate insulating film 14 by constituting the gate insulating film 14 by a single silicon nitride film or a composite film of silicon nitride and silicon oxide, the effective film thickness can be made thicker than that of the gate insulating film constituted by a silicon oxide film and accordingly, there can be improved a deterioration in insulation resistance by generation of tunnel leakage current or hot carriers.
  • the silicon dioxide conversion film thickness (hereinafter, simply referred to as converted film thickness) dr of a single insulating film or a composite insulating film is a film thickness defined by the following equation when a specific dielectric constant of an insulating film constituting an object is designated by notation ⁇ i, a film thickness thereof is designated by notation di and a specific dielectric constant of silicon dioxide is designated by ⁇ s.
  • dielectric constants of silicon oxide (SiO 2 ) and silicon nitride (Si 3 N 4 ) are respectively 4 through 4.2 and 8.
  • the silicon dioxide conversion film thickness of the silicon nitride film having a film thickness of 6 nm becomes 3 nm. That is, capacitance of the gate insulating film comprising a composite film having the silicon nitride film having the film thickness of 6 nm is equal to that of the gate insulating film comprising the silicon oxide film having the film thickness of 3 nm.
  • a gate electrode forming film 15 is formed by successively depositing a polycrystal silicon layer 15 a , an SiGe layer 15 b and a polycrystal silicon layer 15 c over the semiconductor substrate 11 S from lower layers by a CVD process.
  • the polycrystal silicon layer 15 a is provided with a function of assisting to form the SiGe layer 15 b without effecting influence on electric properties. That is, the polycrystal silicon layer 15 a assists to form nuclei at an initial stage of film formation in forming the SiGe layer 15 b thereabove and forms the SiGe layer 15 b having a uniform thickness. When there is not the polycrystal silicon layer 15 a , nuclei formation at the initial stage of film formation of the SiGe layer 15 b is difficult to carry out and irregularities of the SiGe layer 15 b are enlarged.
  • the thickness of the polycrystal silicon layer 15 a is, for example, about 3 nm.
  • the SiGe layer 15 b is deposited over the polycrystal silicon layer 15 a .
  • the thickness of the SiGe layer 15 b is, for example, about 100 through 200 nm.
  • a concentration of Ge is made to be equal to or larger than 10% of a total. The higher the concentration of Ge of the SiGe layer 15 b , the more preferable. This is, for example, from the following reason.
  • Boron is introduced to the SiGe layer 15 b to reduce the resistance and set the work function to a predetermined value and when the concentration of Ge of the SiGe layer 15 b is high, a concentration of boron can be reduced and therefore, boron depletion can be restrained and vacancy formation caused by boron depletion can be restrained or prevented.
  • the reason of capable of reducing the concentration of boron resides in that when the concentration of Ge of the SiGe layer 15 b is high, the activation efficiency of boron can be promoted and therefore, even when the concentration of boron is low, the resistance of the SiGe layer 15 b can be reduced. Further, when the concentration of Ge of the SiGe layer 15 b is high, even when the concentration of boron is low, the work function of the SiGe layer 15 b can be made a predetermined value.
  • the concentration of Ge is made equal to or larger than 20%, preferably, equal to or larger than 40%.
  • the concentration of Ge of the SiGe layer 15 b is made high, in postprocessing after patterning the SiGe layer 15 b , there is produced so-to-speak side etching in which side faces of the SiGe layer 15 b are polished, however, according to Embodiment 1, the side etching can be restrained or prevented and therefore, the concentration of Ge can be made high.
  • the gate electrode in an area in which the concentration of Ge of the SiGe layer 15 b is equal to or larger than 40%, in a CMIS (Complementary MIS) circuit, the gate electrode can be constructed by a single gate electrode structure. That is, when a gate electrode material is constituted by polycrystal silicon, there is a case of adopting so-to-speak dual gate electrode structure in which a gate electrode of nMIS of the CMOS circuit is constituted by n-type polycrystal silicon by introducing phosphor and a gate electrode of pMIS is constituted by p-type polycrystal silicon by introducing boron.
  • a reduction in threshold voltage of nMIS and pMIS can be prevented by changing the work function of the gate electrode in accordance with nMIS and pMIS without increasing the concentration of impurity of the semiconductor substrate.
  • phosphor and boron are selectively introduced with different photoresist films as masks and accordingly, fabrication steps become complicated, further, a number of fabrication steps is increased and accordingly, an increase in cost of product is brought about.
  • an impurity included in a gate electrode portion differs by nMIS and pMIS and accordingly, there is produced a difference in the shape of the gate electrode, a dispersion is caused in dimensions of fabricating the gate electrode and accuracy of fabrication dimensions is deteriorated.
  • the work function of the SiGe layer 15 b can easily be set to a value between work function of n-type polycrystal silicon (about 4.15 V) and work function of p-type polycrystal silicon (about 5.15 V) by introducing boron. Therefore, it is not necessary to introduce two kinds of impurities of phosphor and boron to the gate electrode. That is, the gate electrodes of both of nMIS and pMIS can be constructed by a p-type single gate electrode structure introducing only boron.
  • a reduction in threshold voltage of nMIS and pMIS constituting the CMOS circuit can be prevented without increasing the concentration of the impurity of the semiconductor substrate 11 S. Further, fabrication steps of a semiconductor integrated circuit device can be simplified. Further, a number of fabrication steps of a semiconductor integrated circuit device can be reduced. Therefore, development and fabrication time of a semiconductor integrated circuit device can be shortened. Further, cost of a semiconductor integrated circuit device can be reduced. Further, in patterning a gate electrode, it is not necessary to consider a difference in the shape of the gate electrode by nMIS and pMIS, a dispersion in dimensions of fabricating the gate electrode in nMIS and pMIS can be reduced and accordingly, accuracy of dimensions of fabricating the gate electrode can be promoted. Therefore, yield of a semiconductor integrated circuit device can be promoted. Further, performance of a semiconductor integrated circuit device can be promoted.
  • the SiGe layer 15 b can be formed by a CVD process using a mixed gas of monosilane (SiH 4 ) and germane (GeH 4 ). However, in forming the SiGe layer 15 b , boron may be introduced in situ in forming the SiGe layer by depositing the layer by a CVD process using silane (SiH 4 ), germane (GeH 4 ) and diborane (B 2 H 6 ) as source gases.
  • the polycrystal silicon layer 15 c is deposited over the SiGe layer 15 b .
  • the polycrystal silicon layer 15 c is provided in consideration of depositing cobalt (Co) and forming a cobalt silicide layer as described later. That is, when Co is formed directly over the SiGe layer 15 b , compatibility is low between SiGe and Co, a resistance value of the gate electrode becomes high and accordingly, the polycrystal silicon layer 15 c is provided to prevent thereof.
  • a thickness of the polycrystal silicon layer 15 c is set such that in removing a mask made of silicon oxide formed over the polycrystal silicon layer 15 c by etching as described later, the polycrystal silicon layer 15 c is not penetrated even by an overetching processing thereof and is made, for example, about 50 nm. This is for preventing the SiGe layer 15 b from being exposed directly to a cleaning solution in a cleaning processing which is carried out after removing the mask by etching.
  • boron mentioned above, is introduced to the gate electrode forming film 15 by an ion implantation process.
  • SiGe layer 15 b having the concentration of Ge equal to or larger than 40% there is constructed a single gate electrode structure of only boron. Further, when boron is introduced in situ in forming the SiGe layer 15 b as described above, it is not necessary to ion-implant boron again.
  • an insulating film 16 comprising, for example, a silicon oxide film is formed over the polycrystal silicon layer 15 c by a CVD process.
  • the insulating film 16 constitutes a mask in patterning a gate electrode forming film by a dry etching process.
  • a film thickness of the insulating film 16 needs to set to a sufficient thickness such that when the SiGe layer 15 b is etched, a matrix thereof is not etched and is, for example, about 50 nm.
  • a photoresist pattern 18 having a thickness of, for example, about 0.5 ⁇ m is formed thereabove.
  • the photoresist pattern 18 is formed by coating an organic photo resist film over the reflection preventive film 17 and exposing the photoresist film by irradiating the photoresist film with exposure beam such as excimer laser beam via a photomask.
  • the reflection preventive film 17 and the insulating film 16 exposed therefrom are etched and removed by a dry etching process.
  • etching processing of the reflection preventive film 17 and the insulating film 16 there is used, for example, an etching apparatus of a parallel flat plate type and the reflection preventive film 17 and the insulating film 16 are processed to etch by separate chambers.
  • processing to etch the reflection preventive film 17 for example, O 2 /N 2 /CF 4 is used as a process gas. Further, in processing to etch the insulating film 16 , for example, C 4 F 8 /Ar/O 2 is used as a process gas. In processing to etch the insulating film 16 , by using a gas having a high carbon rate such as C 4 F 8 , selectivity of etch rate with respect to the polycrystal silicon layer 15 c of the matrix can be provided and accordingly, an amount of polishing the polycrystal silicon layer 15 c can be reduced.
  • a gas having a high carbon rate such as C 4 F 8
  • the gate electrode forming film 15 (that is, polycrystal silicon layer 15 a , SiGe layer 15 b and polycrystal silicon layer 15 c ) exposed therefrom is etched and removed by a dry etching process.
  • the dry etching processing is carried out in the etching chamber 8 at inside of the etching apparatus 1 shown in FIG. 1.
  • the processing there are required anisotropic shape (verticalness) and high selectivity with respect to the gate insulating film 14 of the matrix. Therefore, according to Embodiment 1, there is used, for example, a microwave etcher and etching conditions are constituted by, for example, following five stage steps.
  • a first step is constituted by a condition nonselective with regard to the silicon oxide film.
  • Cl 2 is used as a process gas and a flow rate thereof is set to, for example, about 80 ml/min.
  • pressure is set to, for example, about 0.4 Pa.
  • a microwave/RF is set to, for example, about 400/80 W.
  • a processing time period is set to, for example, about 5 sec.
  • a second step is constituted by a condition mainly for providing stability of electricity discharge.
  • HBr/Cl 2 is used as a process gas and a flow rate thereof is set to, for example, about 90 through 20 ml/min.
  • pressure is set to, for example, about 0.4 Pa.
  • a microwave/RF is set to, for example, about 800/40 W.
  • a processing time period is set to, for example, about 2 sec.
  • a third step is constituted by a condition having low selectivity with regard to the silicon oxide film. Up to a thickness position at a middle of the SiGe layer 15 b is etched and removed by the third step.
  • HBr/Cl 2 /O 2 is used as a process gas and a flow rate thereof is set to, for example, about 90/20/3 ml/min.
  • pressure is set to, for example, about 0.4 Pa.
  • a microwave/RF is set to, for example, about 400/30 (or 40) W.
  • a processing time period is set to, for example, about 30 sec.
  • a fourth step is constituted by a condition having high selectivity with respect to the silicon oxide film.
  • the just etching refers to a time point at which the gate insulating film 14 is exposed at a portion thereof excluding stepped portions of the element separating portions 12 .
  • HBr/O 2 is used as a process gas and a flow rate thereof is set to, for example, about 74/3 ml/min.
  • pressure is set to, for example, about 0.4 Pa.
  • a microwave/RF is set to, for example, about 400/25 W.
  • a processing time period is made up to the just etching.
  • respective end points can be detected.
  • a fifth step is an overetching processing and is constituted by a condition of removing a residue of etching of the polycrystal silicon layers 15 a and 15 b .
  • a process gas there is used, for example, HBr/O 2 or Cl 2 /O 2 having high selectivity with respect to the silicon oxide film as mentioned above and a flow rate thereof is set to, for example, about 105/8 ml/min.
  • pressure is set to, for example, about 0.6 Pa.
  • a microwave/RF is set to, for example, about 400/45 W.
  • a processing time period is set to, for example, about 30 sec.
  • a gate electrode 15 G is formed.
  • side faces of the gate electrode 15 G are formed substantially orthogonally to the main face of the semiconductor substrate 11 S. That is, the side edge is not caused at the side faces of the gate electrode 15 G.
  • the semiconductor substrate 11 S finished with the processings is taken out from the etching chamber 8 of the etching apparatus 1 of FIG. 1 and is transferred into the postprocessing chamber 9 in a state of maintaining vacuum without exposing the semiconductor substrate 11 S to outside air.
  • the object of the postprocessing resides in removing reaction products (SiCl, SiOCl, SiOBr) including Si produced in the processing of etching the gate electrode forming film 15 and removing Cl, Br adsorbed to the surface of the semiconductor substrate 11 S or reaction products including Cl, Br.
  • reaction products particularly reaction products including Si
  • the reaction products cannot be removed only by a cleaning processing thereafter and therefore, in later steps, the reaction products are exfoliated to thereby produce foreign matters.
  • the semiconductor substrate 11 S after finishing with the etching processing is returned to a wafer cassette, the reaction products are adhered to a main face of other semiconductor substrate 11 S before the etching processing and when there is carried out etching processing of the gate electrode forming film with respect to the other semiconductor substrate 11 S, the adhered matters constitute a mask to thereby produce residue of etching.
  • the postprocessing is carried out under the same conditions. That is, similar to the postprocessing when polycrystal silicon is used as a gate electrode material, the postprocessing is carried out by using, for example, O 2 /CHF 3 gas.
  • the O 2 /CHF 3 gas is used in the post processing because a stable electricity discharge range is provided and further, the gas is generally used in the postprocessing when polycrystal silicon is used as the gate electrode material and is easy to introduce since data amount is enormous.
  • the side etching amount when the side etching amount is defined by a rate with respect to the length in the channel direction of the remaining polycrystal silicon layers 15 a and 15 b , the side etching amount can be represented by ((LA ⁇ LB)/LA) ⁇ 100(%). In FIGS. 8A and 8B, the side etching amount is about 70% (that is, 70% is polished).
  • FIGS. 8A and 8B show a case in which the Ge concentration of the SiGe layer 15 b is made, for example, 50%.
  • O 2 /CHF 3 600/40 (ml/min)
  • pressure is set to 100 Pa
  • microwave power is set to 1000 W
  • electricity discharge time is set to 20 sec.
  • the side etching is not caused under a condition of single O 2 gas. This is because etching of Si is not progressed since there is not a fluorine species gas.
  • the adhered matters on the surface of the semiconductor substrate cannot be removed only by O 2 and accordingly, the condition cannot be used in the actual process.
  • Embodiment 1 as the postprocessing condition, plasma processing is carried out under a mixed gas atmosphere of a gas hardly reactive to Ge and a gas having an etching function of Si.
  • a gas hardly reactive to Ge there is used an inert gas such as argon (Ar) gas further, as a gas having the function of etching Si, there is used a gas including fluorine such as CHF 3 .
  • FIGS. 9A and 9B a vertical shape of the side faces of the gate electrode 15 can be achieved.
  • FIGS. 9A and 9B exemplify a case of causing more or less side etching
  • the gate electrode 15 G can be formed also in a state of dispensing with the side etching.
  • a time period of the postprocessing in this case is set such that an amount of polishing the polycrystal silicon layer 15 c is set to be substantially in line with the O 2 /CHF 3 condition and it is not that the side etching is not caused because the etching amount is small.
  • Ar/CHF 3 is about 400/20 (ml/min)
  • pressure is about 70 Pa
  • a microwave power is about 750 W
  • an electricity discharge time period is about 20 sec.
  • the Ge concentration of the SiGe layer 15 b is, for example, equal to or larger than 20%.
  • the gas is not limited thereto but can be changed variously, in place of Ar, for example, there can also be used other inert gas such as helium (He), neon (Ne), krypton (Kr) or xenon (Xe). Further, nitrogen (N 2 ) gas can also be used in place of Ar.
  • the SiN film becomes a protective film and functions to prevent side etching of two side faces of the gate electrode.
  • CHF 3 is used as a gas having a function of etching Si
  • the gas is not limited thereto but can be changed variously and in place of CHF 3 , there can also be used a gas including fluorine such as CF 4 , C 2 F 6 or SF 6 .
  • a gas including fluorine such as CF 4 , C 2 F 6 or SF 6 .
  • an etching rate of the polycrystal silicon layers 15 a and 15 c is large.
  • the postprocessing time period is shortened to, for example, about 5 sec.
  • the side etching amount is larger than that of Ar/CHF 3 to be about 20%, however, side etching under the condition of O 2 /CHF 3 is not caused. That is, the side etching amount is about 20% in a gas system of Ar/CF 4 having comparatively large side etching.
  • the side etching amount can be made equal to or lower than 40%, the side etching amount can be made about 20% as an actually provided result when Ar/CF 4 gas is used and the side etching amount can be made equal to or lower than 10% as an actually provided result when Ar/CHF 3 gas is used.
  • the sectional shape of the gate electrode 15 G having the SiGe layer 15 b can be improved. That is, accuracy of dimensions of fabricating the gate electrode 15 G can be promoted. Therefore, according to Embodiment 1, the yield of the semiconductor integrated circuit device can be promoted. Further, the performance of the semiconductor integrated circuit device can be promoted.
  • FIG. 10 shows a result of investigating performance of removing Cl or Br adhered to the semiconductor substrate 11 S by total reflection fluorescent X-ray.
  • Notations A 1 through A 3 of the abscissa of FIG. 10 indicate a case of using Ar/CHF 3 as a postprocessing gas (present invention)
  • notation A 1 shows a case of the postprocessing time period of 10 sec
  • notation A 2 designates a case of the postprocessing time period of 20 sec
  • notation A 3 designates a case of the postprocessing time period of 25 sec.
  • notation B designates a case of using Ar/CF 4 as a postprocessing gas (present invention) and is a case of the postprocessing time period of 5 sec.
  • notation C designates a case of using O 2 /CHF 3 as the postprocessing gas condition (technology investigated by the inventors) and the postprocessing time period is 20 sec.
  • Notation D designates a case in which the postprocessing is not carried out
  • notation E designates a case in which patterning and postprocessing of the gate electrode are not carried out. It is apparent from FIG. 10 that under the Ar/CHF 3 condition, with regard to the performance of removing Cl and Br, there is achieved an effect equal to or higher than the O 2 /CHF 3 condition.
  • the semiconductor substrate 11 S is taken out from the etching apparatus 1 shown in FIG. 1.
  • n ⁇ -type semiconductor areas 19 a having a low concentration of impurity constituting a source and a drain (LDD; Lightly Doped Drain) of nMIS.
  • p ⁇ -type semiconductor areas 20 a having a low concentration of impurity constituting a source and a drain (LDD) of pMIS.
  • nMISQn and pMISQp each having the source and the drain of the LDD structure.
  • silicide layers 22 made of, for example, cobalt silicide (CoSi x ) (silicide process) as shown in FIG. 14.
  • CoSi x cobalt silicide
  • nMISQn, pMISQp very small elements
  • a tungsten silicide layer or a titanium silicide layer can also be constituted.
  • first layer wirings 26 a are formed.
  • FIG. 16B through FIG. 22B are sectional views enlarging essential portions of nMIS forming areas of FIGS. 16A through 22A.
  • a gate electrode structure of a pMIS forming area is the same as a gate electrode structure of an nMIS forming area and accordingly, illustration thereof is omitted.
  • the gate insulating time 14 is formed over the main face of the semiconductor substrate 11 S.
  • the polycrystal silicon layer 15 a and the SiGe layer 15 b are deposited over the semiconductor substrate 11 S successively from the lower layer.
  • boron is introduced to the SiGe layer 15 b by an ion implantation process.
  • the SiGe layer 15 b having the concentration of Ge equal to or larger than 40% there is constructed the single gate electrode structure only of boron. Further, as described above, when boron is introduced in situ in forming the SiGe layer 15 b , it is not necessary to ion-implant boron again.
  • a barrier conductor layer 15 d having a thickness of, for example, about 5 nm and made of tungsten nitride (WN) or titanium nitride (TiN) over the SiGe layer 15 b by a sputtering process and thereafter depositing a metal layer 15 e having a thickness of, for example, about 80 nm and made of tungsten (W) or molybdenum (Mo) thereabove, the gate electrode forming film 15 is formed.
  • the barrier conductive layer 15 d is provided for, for example, stress relaxation and adherence promotion of the SiGe layer 15 b and the metal layer 15 e.
  • an insulating film 28 comprising, for example, a silicon nitride film (Si 3 N 4 ) over the metal layer 15 e .
  • the insulating film 28 is constituted by depositing a silicon nitride film formed by a thermal CVD process over a silicon nitride film formed by a plasma CVD process. This is because the etching rate is lower in the silicon nitride film by the thermal CVD process than in the silicon nitride film by the plasma CVD process (selection ratio with regard to silicon oxide film is made higher). That is, in forming contact holes in later steps, even when the insulating film 28 is exposed from the contact holes, the insulating film 28 is prevented from being etched and removed.
  • the reflection preventive film 17 and the photoresist pattern 18 over the insulating film 28 similar to Embodiment 1, with the photoresist pattern 18 as an etching mask are etched and removed by a dry etching process.
  • a dry etching process in processing to etch the reflection preventive film 17 and the insulating film 28 , there is used, for example, an etching apparatus of a parallel flat plate type and the reflection preventive film 17 and the insulating film 28 are processed to etch by separate chambers.
  • processing to etch the insulating film 28 there is used, for example, CF 4 /Ar as process gas.
  • the dry etching processing is carried out in the etching chamber 8 at inside of the etching apparatus 1 shown in FIG. 1.
  • an etching processing at an elevated temperature for example, about 100 through 150° C.
  • an etching processing at normal temperature using, for example, CF 4 /O 2 /N 2 /Cl 2 gas.
  • An etching processing of the SiGe layer 15 b and the polycrystal silicon layer 15 a is the same as that in Embodiment 1 and therefore, an explanation thereof will be omitted.
  • the semiconductor substrate 11 S finished with the processings is transferred into the postprocessing chamber 9 similar to Embodiment 1 and is subjected to a postprocessing similar to that in Embodiment 1.
  • the vertical shape of the side faces of the gate electrode 15 having the polymetal structure can be achieved.
  • FIG. 20B exemplifies the case of causing more or less side etching, according to the postprocessing conditions, the gate electrode 15 G can be formed in a state of dispensing with side etching.
  • FIGS. 21A and 21B Successively, as shown by FIGS. 21A and 21B, similar to Embodiment 1, after forming n ⁇ -type semiconductor areas 19 a having a low concentration of impurity at nMIS forming areas, p ⁇ -type semiconductor areas 20 a having a low concentration of impurity are formed at pMIS forming areas. Thereafter, after depositing an insulating film made of, for example, silicon nitride over the semiconductor substrate 11 S by a CVD process and thereafter etching back thereof by anisotropic etching, there are formed the side walls 21 each comprising a silicon nitride film at the gate electrode 15 G and two side faces of the insulating film 28 . Thereafter, as shown by FIGS.
  • nMISQn and pMISQp each having the source and the drain of the LDD structure.
  • the contact holes 24 are perforated in the insulating film 23 a .
  • the contact holes 24 are formed by carrying out an etching processing under an etching condition in which the silicon oxide film is made to be easier to etch by making an etching selection ratio of the silicon oxide film higher than that of the silicon nitride film. In this case, as shown by FIG.
  • the contact hole 24 overlaps the gate electrode 15 G more or less in plane view, the gate electrode 15 G is not exposed owing to the side wall 21 and the insulating film 28 made of silicon nitride (that is, the contact hole 24 can be formed self-adjustingly with respect to the gate electrode 15 G) and accordingly, an integration degree of elements can be promoted.
  • the etching chamber for patterning the gate electrode and the postprocessing chamber are separated from each other, the invention is not limited thereto but the etching processing and the postprocessing can be carried out in the same chamber. In this case, the postprocessing chamber is dispensed with and accordingly, cost of the etching apparatus can be reduced.
  • the invention is not limited thereto but the invention is applicable also to the case in which a plurality of elements having different thicknesses of gate insulating films are formed over the same semiconductor substrate.
  • the film thickness of a gate insulating film of MIS using relatively high power source voltage is made thicker than the film thickness of a gate insulating film of MIS driven by relatively low power source voltage and requesting high-speed operation.
  • the invention is not limited thereto but the invention is applicable to a semiconductor integrated circuit device having a memory circuit of, for example, DRAM (Dynamic Random Access Memory), SRAM (Static Random Access Memory) or a flash memory (EEPROM; Electric Erasable and Programmable Read Only Memory) or a semiconductor integrated circuit device having a logic circuit such as a microprocessor.
  • DRAM Dynamic Random Access Memory
  • SRAM Static Random Access Memory
  • EEPROM Electric Erasable and Programmable Read Only Memory
  • a semiconductor integrated circuit device having a logic circuit such as a microprocessor.

Abstract

To improve a shape of a gate electrode having SiGe, after patterning a gate electrode 15G having an SiGe layer 15 b by a dry etching process, a plasma processing (postprocessing) is carried out in an atmosphere of an Ar/CHF3 gas. Thereby, the gate electrode 15G can be formed without causing side etching at two side faces (SiGe layer 15 b) of the gate electrode 15G.

Description

    BACKGROUND OF THE INVENTION
  • The present invention relates to a technology of a fabrication method for semiconductor integrated circuit devices and a semiconductor integrated circuit device, particularly to a technology effectively applied to a fabrication method for semiconductor integrated circuit devices and a semiconductor integrated circuit device having an alloy of silicon (Si) and germanium (Ge) (hereinafter, simply referred to as SiGe) of polycrystal or single crystal. [0001]
  • With regard to a technology of a semiconductor integrated circuit device using SiGe for a gate electrode material, there are descriptions in, for example, J. Vac. Sci. Technol July/August 1997 p1874 through p1880, J. Vac. Sci. Technol July/August 1998 p1833 through p1840 and Japanese Patent Laid-Open No. 330463/1999, disclosing a technology of patterning an SiGe gate electrode. [0002]
    • SUMMARY OF THE INVENTION
  • A description will be given of a result of investigating a technology of forming a gate electrode having an SiGe layer by the inventors as follows. [0003]
  • A processing of forming a gate electrode having an SiGe layer includes three processing steps of depositing a gate electrode forming film, patterning thereof and a postprocessing thereof. That is, first, after forming a gate insulating film over a main face of a semiconductor substrate, a gate electrode forming film having an SiGe layer is deposited thereabove. Successively, after forming a photoresist pattern over the gate electrode forming film, a gate electrode having the SiGe layer is formed by patterning the gate electrode forming film by using an etching gas including, for example, chlorine (Cl[0004] 2) and bromine (Br) with the photoresist pattern as an etching mask. Thereafter, in order to remove Cl, Br and reaction products including thereof and reaction products including Si adhered to a surface of the semiconductor substrate in forming the gate electrode (hereinafter, also referred to as adhered matters), a plasma processing is carried out to the semiconductor substrate in an atmosphere of a predetermined gas (postprocessing).
  • The postprocessing is a processing which is also carried out after forming the gate electrode by patterning polycrystal silicon and when the postprocessing is not carried out, there causes a drawback, for example, as follows. That is, when the reaction products are not removed, occurrence of foreign matters is caused and reliability or yield of the semiconductor integrated circuit device is deteriorated. When the adhered matters are adhered to a main face of other semiconductor substrate before patterning the gate electrode, in patterning the gate electrode of the other semiconductor substrate, the adhered matters constitute a mask and there is produced etching residue of a gate electrode material. Further, when Cl or Br adhered to the surface of the semiconductor substrate is not removed, parts of a semiconductor fabricating apparatus are corroded by Cl or Br. Further, Cl or Br is toxic and therefore, adverse influence is effected on the human body. [0005]
  • With regard to a gas in the postprocessing when SiGe is used as the gate electrode material, there is used, for example, O[0006] 2/CHF3 since a stable electricity discharge range is provided, further, the gas is generally used in the postprocessing when polycrystal silicon is used as a gate electrode material, an amount of data is enormous and introduction thereof is facilitated. Similar to the postprocessing when the polycrystal silicon is used as a gate electrode material.
  • However, according to the technology of forming the gate electrode having the SiGe layer, it has been found for the first time by experiment and evaluation of the inventors that there poses the following problem. [0007]
  • That is, there poses a problem that so-to-speak side etching is caused such that two side faces of the SiGe layer portion in the gate electrode are polished toward the center. [0008]
  • First, when the inventors have evaluated performance of etching SiGe, it has been that the side etching is liable to cause. Hence, when evaluation has been carried out further in detail, it has been found that although the side etching is not caused in a processing at an etching chamber, the side etching is caused when the postprocessing is carried out at a post processing chamber. Further, it has also been found that presence or absence of occurrence of the side etching is dependent upon a concentration of Ge. Further, a shape of the side etching has not been improved even after investigating a reduction in a concentration of CHF[0009] 3 or a reduction in electricity discharge power at the postprocessing.
  • It is an object of the invention to provide a technology capable of improving a shape of a gate electrode having SiGe. [0010]
  • It is other object of the invention to provide a technology capable of promoting an accuracy of dimensions of fabricating a gate electrode having SiGe. [0011]
  • Further, it is other object of the invention to provide a technology capable of promoting yield of a semiconductor integrated circuit device having a gate electrode having SiGe. [0012]
  • Further, it is other object of the invention to provide a technology capable of promoting function of a semiconductor integrated circuit having a gate electrode having SiGe. [0013]
  • Further, it is other object of the invention to provide a technology capable of simplifying fabrication steps of a semiconductor integrated circuit device having a gate electrode having SiGe. [0014]
  • Further, it is other object of the invention to provide a technology capable of shortening development and fabrication time period of a semiconductor integrated circuit device having a gate electrode having SiGe. [0015]
  • The above-described and other objects and novel characteristics of the invention will become apparent from description of the specification and attached drawings. [0016]
  • A simple explanation will be given of an outline of representative aspects of the invention disclosed in the application as follows. [0017]
  • That is, according to an aspect of the invention, there are provided steps of forming a gate electrode having an SiGe layer over a semiconductor substrate by patterning a gate electrode forming film having the SiGe layer and thereafter subjecting the semiconductor substrate to a plasma processing in an atmosphere of a mixed gas of a first gas hardly reactive to Ge and a second gas having a function of etching Si. [0018]
  • Further, according to another aspect of the invention, there are provided steps of forming a gate electrode over a semiconductor substrate by patterning a gate electrode forming film deposited on the semiconductor substrate and thereafter subjecting the semiconductor substrate to a plasma processing in an atmosphere of a mixed gas of a first gas hardly reactive to Ge and a second gas having a function of etching Si and the step of depositing the gate electrode forming film includes a step of depositing an SiGe layer and a step of depositing a polycrystal silicon layer at a layer upward from the SiGe layer. [0019]
  • Further, according to another aspect of the invention, there are further provided after the plasma processing, a step of forming side wall insulating films at side faces of the gate electrode, a step of exposing an upper face of the gate electrode and portions of a main face of the semiconductor substrate, a step of depositing a metal film having a high melting point over the semiconductor substrate and a step of forming a metal silicide layer having a high melting point at the upper face of the gate electrode and the portions of the main face of the semiconductor substrate. [0020]
  • Further, according to another aspect of the invention, the metal silicide layer having the high melting point is made of cobalt silicide. [0021]
  • Further, according to another aspect of the invention, there are provided steps of forming a gate electrode over a semiconductor substrate by patterning a gate electrode forming film deposited over the semiconductor substrate and thereafter subjecting the semiconductor substrate to a plasma processing in an atmosphere of a mixed gas of a first gas hardly reactive to Ge and a second gas having a function of etching Si and the step of depositing the gate electrode forming film includes a step of depositing an SiGe layer and a step of depositing a metal layer at a layer upward from the SiGe layer. [0022]
  • Further, according to another aspect of the invention, there is further provided a step of introducing boron to the SiGe layer. [0023]
  • Further, according to another aspect of the invention, the first gas is constituted by an inert gas. [0024]
  • Further, according to another aspect of the invention, the first gas is constituted by Ar, He, Kr or Xe. [0025]
  • Further, according to another aspect of the invention, the first gas is constituted by nitrogen gas. [0026]
  • Further, according to another aspect of the invention, the second gas is constituted by a gas including fluorine. [0027]
  • Further, according to another aspect of the invention, the second gas is constituted by CHF[0028] 3, CF4, C2F6 or SF6.
  • Further, according to another aspect of the invention, when the first gas is constituted by Ar gas, pressure in the atmosphere is made equal to or smaller than 70 Pa. [0029]
  • Further, according to another aspect of the invention, when the first gas is constituted by Ar gas, a microwave power for forming a plasma is made 750 W. [0030]
  • Further, according to another aspect of the invention, when the first gas is constituted by Ar gas and the second gas is constituted by CHF[0031] 3, a concentration of the second gas is made equal to or smaller than 5% of a total.
  • Further, according to another aspect of the invention, when the gate electrode forming film having the SiGe layer is patterned, there is carried out a plasma etching processing in an atmosphere of chlorine, bromine or a mixed gas of these. [0032]
  • Further, according to another aspect of the invention, a concentration of Ge of the SiGe layer is made equal to or larger than 10% of a total. [0033]
  • Further, according to another aspect of the invention, the concentration of Ge of the SiGe layer is made equal to or larger than 20% of the total. [0034]
  • Further, according to another aspect of the invention, the concentration of Ge of the SiGe layer is made equal to or larger than 40% of the total. [0035]
  • Further, according to another aspect of the invention, there is further provided a step of fabricating a semiconductor integrated circuit device in which the semiconductor substrate after the step of patterning the gate electrode is transferred to the plasma processing step in a state of maintaining a vacuum state. [0036]
  • Further, according to another aspect of the invention, a side etching amount at two side faces of the gate electrode after the plasma processing is made equal to or smaller than 40% of a length in a channel length direction of the gate electrode at a portion thereof other than the SiGe layer. [0037]
  • Further, according to another aspect of the invention, a length in the channel direction of the gate electrode at the SiGe layer after the plasma processing, is equal to the length in the channel length direction of the gate electrode at the portion other than the SiGe layer. [0038]
  • Further, according to another aspect of the invention, there is used a gate electrode of an n-channel type field effect transistor or a p-channel type field effect transistor formed on the same semiconductor substrate for the gate electrode.[0039]
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is an explanatory view of an etching apparatus used for a fabrication method of semiconductor integrated circuit devices according to an embodiment of the invention; [0040]
  • FIG. 2 is a sectional view of essential portions in a fabrication step of the semiconductor integrated circuit device according to the embodiment of the invention; [0041]
  • FIG. 3 is a sectional view of essential portions in a fabrication step of the semiconductor integrated circuit device continuous to FIG. 2; [0042]
  • FIG. 4A is a sectional view of essential portions in a fabrication step of the semiconductor integrated circuit device continuous to FIG. 3 and [0043]
  • FIG. 4B is a sectional view enlarging essential portions of an area of forming n-channel type MISFET of FIG. 4A; [0044]
  • FIG. 5A is a sectional view of essential portions in a fabrication step of the semiconductor integrated circuit device continuous to FIG. 4A and [0045]
  • FIG. 5B is a sectional view enlarging essential portions of an area of forming n-channel type MISFET of FIG. 5A; [0046]
  • FIG. 6A is a sectional view of essential portions in a fabrication step of the semiconductor integrated circuit device continuous to FIG. 5A and [0047]
  • FIG. 6B is a sectional view enlarging essential portions of an area of forming n-channel type MISFET of FIG. 6A; [0048]
  • FIG. 7A is a sectional view of essential portions in a fabrication step of the semiconductor integrated circuit device continuous to FIG. 6A and [0049]
  • FIG. 7B is a sectional view enlarging essential portions of an area of forming n-channel type MISFET of FIG. 7A; [0050]
  • FIG. 8A is a partial sectional view of a semiconductor substrate after a postprocessing for explaining a problem of a technology investigated by the inventors for carrying out the invention and [0051]
  • FIG. 8B is a sectional view enlarging essential portions of FIG. 8A; [0052]
  • FIG. 9A is a sectional view of essential portions in a fabrication step of the semiconductor integrated circuit device continuous to FIG. 7A and [0053]
  • FIG. 9B is a sectional view enlarging essential portions of an area of forming n-channel type MISFET of FIG. 9A; [0054]
  • FIG. 10 is a graph diagram showing a result of investigating whether Cl, Br or the like adhered to the semiconductor substrate has been removed by the postprocessing of the invention by total reflection type fluorescent X-ray; [0055]
  • FIG. 11A is a sectional view of essential portions in a fabrication step of the semiconductor integrated circuit device continuous to FIG. 9A and [0056]
  • FIG. 11B is a sectional view enlarging essential portions of an area of forming n-channel type MISFET of FIG. 11A; [0057]
  • FIG. 12A is a sectional view of essential portions in a fabrication step of the semiconductor integrated circuit device continuous to FIG. 11A and [0058]
  • FIG. 12B is a sectional view enlarging essential portions of an area of forming n-channel type MISFET of FIG. 12A; [0059]
  • FIG. 13A is a sectional view of essential portions in a fabrication step of the semiconductor integrated circuit device continuous to FIG. 12A and [0060]
  • FIG. 13B is a sectional view enlarging essential portions of an area of forming n-channel type MISFET of FIG. 13A; [0061]
  • FIG. 14A is a sectional view of essential portions in a fabrication step of the semiconductor integrated circuit device continuous to FIG. 13A and [0062]
  • FIG. 14B is a sectional view enlarging essential portions of an area of forming n-channel type MISFET of FIG. 14A; [0063]
  • FIG. 15 is a sectional view of essential portions in a fabrication step of the semiconductor integrated circuit device continuous to FIG. 14A; [0064]
  • FIG. 16A is a sectional view of essential portions in a fabrication step of a semiconductor integrated circuit device according to other embodiment of the invention and [0065]
  • FIG. 16B is a sectional view enlarging essential portions of an area of forming n-channel type MISFET of FIG. 16A; [0066]
  • FIG. 17A is a sectional view of essential portions in a fabrication step of the semiconductor integrated circuit device continuous to FIG. 16A and [0067]
  • FIG. 17B is a sectional view enlarging essential portions of an area of forming n-channel type MISFET of FIG. 17A; [0068]
  • FIG. 18A is a sectional view of essential portions in a fabrication step of the semiconductor integrated circuit device continuous to FIG. 17A and [0069]
  • FIG. 18B is a sectional view enlarging essential portions of an area of forming n-channel type MISFET of FIG. 18A; [0070]
  • FIG. 19A is a sectional view of essential portions in a fabrication step of the semiconductor integrated circuit device continuous to FIG. 18A and [0071]
  • FIG. 19B is a sectional view enlarging essential portions of an area of forming n-channel type MISFET of FIG. 19A; [0072]
  • FIG. 20A is a sectional view of essential portions in a fabrication step of the semiconductor integrated circuit device continuous to FIG. 19A and [0073]
  • FIG. 20B is a sectional view enlarging essential portions of an area of forming n-channel type MISFET of FIG. 20A; [0074]
  • FIG. 21A is a sectional view of essential portions in a fabrication step of the semiconductor integrated circuit device continuous to FIG. 20A and [0075]
  • FIG. 21B is a sectional view enlarging essential portions of an area of forming n-channel type MISFET of FIG. 21A; and [0076]
  • FIG. 22A is a sectional view of essential portions in a fabrication step of the semiconductor integrated circuit device continuous to FIG. 21A and [0077]
  • FIG. 22B is a sectional view enlarging essential portions of an area of forming n-channel type MISFET of FIG. 22A.[0078]
    • DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • In explaining embodiments of the invention, a semiconductor wafer (semiconductor substrate) refers to a silicon single crystal substrate (generally, substantially in a planer circle shape) used in fabrication of a semiconductor integrated circuit, a sapphire substrate, a glass substrate, other insulating, noninsulating or semiconductor substrate as well as a substrate of a composite of these. Further, in the application, a semiconductor device includes a semiconductor device formed on a semiconductor or an insulating substrate such as a silicon wafer or a sapphire substrate as well as, a semiconductor device formed on other insulating substrate of glass or the like such as TFT (Thin-Film-Transistor) and STN (Super-Twisted Nematic) liquid crystal except a case particularly specified otherwise. [0079]
  • Although in the following embodiments, as necessary for convenience, an explanation will be given of the following embodiments divided into a plurality of sections or embodiments, except a case particularly specified, these are not unrelated to each other but one of them is under a relationship of modified examples, detailed or supplemental descriptions of a portion or a total of other thereof. [0080]
  • Further, in the following embodiments, when a number of elements (including number of pieces, numerical value, amount, or range) is referred to, except a case particularly specified and a case in which the number is limited to a specific number clearly as a principle, the number is not limited to the specific number but may be equal to or larger than or equal to or smaller than the specific number. [0081]
  • Further, in the following embodiments, a constituent element (including element step) is not naturally indispensable necessarily except a case particularly specified and a case regarded as clearly indispensable. [0082]
  • Similarly, in the following embodiments, when a shape or a positional relationship of a constituent element is referred, except a case particularly specified and a case regarded otherwise clearly as a principle, a constituent element having a shape substantially proximate or similar to the shape is included. This goes the same with the numerical value and the range. [0083]
  • Further, portions having the same functions in all the drawings for explaining the embodiments are attached with the same notations and repetitive explanation thereof will be omitted. [0084]
  • Further, according to the embodiments, MISFET (Metal Insulator Semiconductor Field Effect Transistor) representing a field effect transistor is abbreviated simply as MIS, MISFET of p-channel type is abbreviated as pMIS and MISFET of n-channel type is abbreviated as nMIS. [0085]
  • A detailed explanation will be given of embodiments of the present invention in reference to the drawings as follows. [0086]
  • (Embodiment 1) [0087]
  • FIG. 1 exemplifies a constitution of an [0088] etching apparatus 1 used in a fabrication method of a semiconductor integrated circuit device according to Embodiment 1.
  • The [0089] etching apparatus 1 is an apparatus for carrying out a series of processings for patterning a wiring forming film having an SiGe layer into a predetermined shape. A semiconductor wafer to be subjected to an etching processing is mounted to an arbitrary location of wafer cassette bases 2 a through 2 c. The semiconductor wafer at the wafer cassette bases 2 a through 2 c is transferred to an alignment unit 4 by an atmospheric transfer robot 3. At the alignment unit 4, aligning of a direction of a notch or an orientation flat of the semiconductor wafer is carried out. The semiconductor wafer finished with the alignment processing is transferred to a load/lock chamber 5 again by the atmospheric transfer robot 3. vacuuming is carried out in the load/lock chamber 5 when the semiconductor wafer is transferred therein. When vacuuming at inside of the load/lock chamber 5 has been finished, the semiconductor wafer passes through a vacuum transfer chamber 7 and is transferred into an etching chamber 8 by a vacuum transfer robot 6. Further, a vacuum state is maintained in the vacuum transfer chamber 7.
  • In the [0090] etching chamber 8, a wiring forming film having an SiGe layer is patterned to a predetermined shape by, for example, a plasma dry etching processing. As an electricity discharge system in the etching chamber 8, there can be used all of electricity discharge systems such as ECR (Electron Cyclotron Resonance), RIE (Reactive Ion Etching), two frequency RIE, magnetron RIE and ICP (Inductively Coupled Plasma). Etching gas is produced by a single gas or a mixed gas of Cl2, HBr, O2 as explained later in detail. At a first step of etching processing, there is used a single gas of Cl2 having a low selection ratio with regard to a silicon oxide film (SiO2) and at and after a second step, there is a gas, for example, HBr/Cl2 or HBr/Cl2/O2 to provide an anisotropic shape. At a terminal point detecting step and an overetching step of the etching processing, there is used a gas having a high selection ratio with regard to a silicon oxide film such as HBr/O2 or Cl2/O2.
  • The semiconductor wafer finished with the etching processing passes through the [0091] vacuum transfer chamber 7 and is transferred into a postprocessing chamber 9 again by the vacuum transfer robot 6. That is, the semiconductor wafer after the etching processing is transferred into the postprocessing chamber 9 while maintaining the vacuum state without being brought into contact with the outer air. In the postprocessing chamber 9, a plasma processing is carried out to the semiconductor wafer as is explained later in detail. With regard to the electricity discharge system of the postprocessing chamber 9, similar to the etching chamber 8, there can be used all of discharge systems such as ECR, RIE, two frequency RIE, magnetron RIE or ICP. The semiconductor wafer finished with the postprocessing is transferred to an unload/unlock chamber 10 again by the vacuum transfer robot 6 and is returned to the wafer cassette bases 2 a through 2 c by the atmospheric transfer robot 3.
  • Next, in [0092] Embodiment 1, an explanation will be given of a case of applying the invention to, for example, a system LSI (Large Scale Integrated Circuit) having a logic circuit and a memory circuit on the same semiconductor substrate in reference to FIG. 2 through FIG. 15. Further, FIG. 4B through FIG. 9B and FIG. 11B through FIG. 15B are sectional views enlarging essential portions of an nMIS forming area of FIG. 4A through FIG. 9A and FIG. 11A through FIG. 15A. A gate electrode structure of a pMIS forming area is the same as a gate electrode structure of the nMIS forming area and accordingly, illustration thereof are omitted. Further, FIG. 8 is a view for explaining a problem of a technology investigated by the inventors for carrying out the invention.
  • First, as shown by FIG. 2, there is prepared a [0093] semiconductor substrate 11S comprising, for example, p-type single crystal silicon. The semiconductor substrate 11S at this stage is a semiconductor thin plate having a planar circle shape of about, for example, 8 inch (=about 20 cm), called as a semiconductor wafer. There are formed grooves 12 a having a depth of about 300 through 400 nm at a main face of the semiconductor substrate 11S. The groove 12 a is formed by covering an element forming area of the semiconductor substrate 11S with a silicon nitride film and thereafter subjecting the semiconductor substrate 11 at an element separating area to dry etching with the silicon nitride film as a mask.
  • Successively, by depositing a silicon oxide film having a film thickness of, for example, about 600 nm over the [0094] semiconductor substrate 11S including inner portions of the grooves 12 a by a CVD (Chemical Vapor Deposition) process and thereafter leaving the silicon oxide film only at the inner portions of the grooves 12 a by polishing the silicon oxide film by a CMP (Chemical Mechanical Polishing) process, at the element separating area of the semiconductor substrate 11S, there is formed an element separating portion 12 (trench isolation) of, for example, a groove type and an active area is formed at the element forming area surrounded thereby in plane view.
  • Thereafter, as shown by FIG. 3, at an nMIS forming area of the [0095] semiconductor substrate 11S, a p-type well 13P is formed by ion-implanting, for example, boron thereto and at a pMIS forming area, an n-type well 13N is formed by ion-implanting, for example, phosphor thereto. Further, at this occasion, at the nMIS forming area, an impurity (for example, boron) for controlling threshold voltage of the nMIS is ion-implanted thereto and at the pMIS forming area, an impurity (for example, phosphor) for controlling threshold voltage of the pMIS is ion-implanted.
  • Next, by cleaning respective surfaces of the p-[0096] type well 13P and the n-type well 13N by using a cleaning solution of HF (hydrofluoric acid) species and thereafter subjecting the semiconductor substrate 11S to wet oxidation at an elevated temperature of, for example, about 850° C., clean gate insulating films 14 each comprising a silicon oxide film are formed on the respective surfaces of the p-type well 13P and the n-type well 13N. The film thickness of the gate insulating film 14 is made, for example, equal to or smaller than 3 nm, for example, about 2.5 nm. Further, the film thickness of the gate insulating film 14, mentioned here, is a film thickness converted into that of a silicon dioxide film and may not be coincide with an actual film thickness.
  • The [0097] gate insulating film 14 may be constituted by a silicon oxynitride film in place of the silicon oxide film. That is, when the film thickness of the gate insulating film 14 is thinned, as described later, a portion of an impurity (boron) in an SiGe layer constituting a portion of a gate electrode by a heat treatment in processing, penetrates the gate insulating film 14 and is diffused into the semiconductor substrate 11S and threshold voltage becomes liable to vary. In comparison with the silicon oxide film, the impurity is difficult to penetrate the silicon oxynitride film and accordingly, by constituting the gate insulating film 14 by the silicon oxynitride film, the threshold voltage can be restrained from varying. Further, according to the silicon oxynitride film, in comparison with the silicon oxide film, there is provided a high effect of restraining occurrence of interfacial level or reducing electron trap in the film and accordingly, hot-carrier resistance of the gate insulating film 14 can be promoted and insulation resistance can be promoted.
  • In forming the silicon oxynitride film, for example, a [0098] semiconductor substrate 1 may be subjected to a heat treatment in a nitrogen including gas atmosphere such as NO, NO2 or NH3. Further, an effect similar to the above-described can be achieved by forming the gate insulating films 14 comprising silicon oxide at respective surfaces of the p-type well 13P and the n-type well 13N and thereafter subjecting the semiconductor substrate 11S to the heat treatment in the above-described nitrogen gas including atmosphere and segregating nitrogen at an interface of the gate insulating film 14 and the semiconductor substrate 11S.
  • Further, the [0099] gate insulating film 14 may be formed by, for example, a silicon nitride film or a composite insulating film of a silicon oxide film and a silicon nitride film. When the gate insulating film 14 comprising silicon oxide is thinned to less than 5 nm, particularly, less than 3 nm by a film thickness converted into that of a silicon dioxide film, there is actualized a deterioration in insulation resistance directly by generating tunnel current or hot carriers caused by stress. The silicon nitride film is provided with a dielectric constant higher than that of the silicon oxide film and accordingly, the silicon dioxide conversion film thickness becomes thinner than an actual film thickness. That is, in the case of providing the silicon nitride film, even when the silicon nitride film is physically thick, there can be provided a capacitance equivalent to that of the relatively thin silicon dioxide film. Therefore, by constituting the gate insulating film 14 by a single silicon nitride film or a composite film of silicon nitride and silicon oxide, the effective film thickness can be made thicker than that of the gate insulating film constituted by a silicon oxide film and accordingly, there can be improved a deterioration in insulation resistance by generation of tunnel leakage current or hot carriers.
  • In this case, the silicon dioxide conversion film thickness (hereinafter, simply referred to as converted film thickness) dr of a single insulating film or a composite insulating film, is a film thickness defined by the following equation when a specific dielectric constant of an insulating film constituting an object is designated by notation εi, a film thickness thereof is designated by notation di and a specific dielectric constant of silicon dioxide is designated by εs. [0100]
    Figure US20020014662A1-20020207-C00001
  • For example, dielectric constants of silicon oxide (SiO[0101] 2) and silicon nitride (Si3N4) are respectively 4 through 4.2 and 8. Hence, by carrying out a calculation by making the dielectric constant of silicon nitride as twice as much as the dielectric constant of silicon oxide, for example, the silicon dioxide conversion film thickness of the silicon nitride film having a film thickness of 6 nm becomes 3 nm. That is, capacitance of the gate insulating film comprising a composite film having the silicon nitride film having the film thickness of 6 nm is equal to that of the gate insulating film comprising the silicon oxide film having the film thickness of 3 nm. Further, capacitance of the gate insulating film comprising the silicon oxide film having the film thickness of 2 nm and the silicon nitride film having the film thickness of 2 nm (converted film thickness=1 nm), is the same as capacitance of the gate insulating film comprising a single silicon oxide film having the film thickness of 3 nm.
  • Successively, as shown by FIGS. 4A and 4B, a gate [0102] electrode forming film 15 is formed by successively depositing a polycrystal silicon layer 15 a, an SiGe layer 15 b and a polycrystal silicon layer 15 c over the semiconductor substrate 11S from lower layers by a CVD process.
  • The [0103] polycrystal silicon layer 15 a is provided with a function of assisting to form the SiGe layer 15 b without effecting influence on electric properties. That is, the polycrystal silicon layer 15 a assists to form nuclei at an initial stage of film formation in forming the SiGe layer 15 b thereabove and forms the SiGe layer 15 b having a uniform thickness. When there is not the polycrystal silicon layer 15 a, nuclei formation at the initial stage of film formation of the SiGe layer 15 b is difficult to carry out and irregularities of the SiGe layer 15 b are enlarged. The thickness of the polycrystal silicon layer 15 a is, for example, about 3 nm.
  • The [0104] SiGe layer 15 b is deposited over the polycrystal silicon layer 15 a. The thickness of the SiGe layer 15 b is, for example, about 100 through 200 nm. Further, according to a composition of the SiGe layer 15 b, a concentration of Ge is made to be equal to or larger than 10% of a total. The higher the concentration of Ge of the SiGe layer 15 b, the more preferable. This is, for example, from the following reason. Boron is introduced to the SiGe layer 15 b to reduce the resistance and set the work function to a predetermined value and when the concentration of Ge of the SiGe layer 15 b is high, a concentration of boron can be reduced and therefore, boron depletion can be restrained and vacancy formation caused by boron depletion can be restrained or prevented. The reason of capable of reducing the concentration of boron resides in that when the concentration of Ge of the SiGe layer 15 b is high, the activation efficiency of boron can be promoted and therefore, even when the concentration of boron is low, the resistance of the SiGe layer 15 b can be reduced. Further, when the concentration of Ge of the SiGe layer 15 b is high, even when the concentration of boron is low, the work function of the SiGe layer 15 b can be made a predetermined value.
  • Hence, according to [0105] Embodiment 1, the concentration of Ge is made equal to or larger than 20%, preferably, equal to or larger than 40%. As described later, when the concentration of Ge of the SiGe layer 15 b is made high, in postprocessing after patterning the SiGe layer 15 b, there is produced so-to-speak side etching in which side faces of the SiGe layer 15 b are polished, however, according to Embodiment 1, the side etching can be restrained or prevented and therefore, the concentration of Ge can be made high.
  • Particularly, in an area in which the concentration of Ge of the [0106] SiGe layer 15 b is equal to or larger than 40%, in a CMIS (Complementary MIS) circuit, the gate electrode can be constructed by a single gate electrode structure. That is, when a gate electrode material is constituted by polycrystal silicon, there is a case of adopting so-to-speak dual gate electrode structure in which a gate electrode of nMIS of the CMOS circuit is constituted by n-type polycrystal silicon by introducing phosphor and a gate electrode of pMIS is constituted by p-type polycrystal silicon by introducing boron. According to the structure, a reduction in threshold voltage of nMIS and pMIS can be prevented by changing the work function of the gate electrode in accordance with nMIS and pMIS without increasing the concentration of impurity of the semiconductor substrate. However, phosphor and boron are selectively introduced with different photoresist films as masks and accordingly, fabrication steps become complicated, further, a number of fabrication steps is increased and accordingly, an increase in cost of product is brought about. Further, in patterning a gate electrode by an etching processing, an impurity included in a gate electrode portion differs by nMIS and pMIS and accordingly, there is produced a difference in the shape of the gate electrode, a dispersion is caused in dimensions of fabricating the gate electrode and accuracy of fabrication dimensions is deteriorated.
  • In contrast thereto, according to [0107] Embodiment 1, by making the concentration of Ge of the SiGe layer 15 b equal to or larger than 40%, the work function of the SiGe layer 15 b can easily be set to a value between work function of n-type polycrystal silicon (about 4.15 V) and work function of p-type polycrystal silicon (about 5.15 V) by introducing boron. Therefore, it is not necessary to introduce two kinds of impurities of phosphor and boron to the gate electrode. That is, the gate electrodes of both of nMIS and pMIS can be constructed by a p-type single gate electrode structure introducing only boron. Therefore, according to Embodiment 1, a reduction in threshold voltage of nMIS and pMIS constituting the CMOS circuit can be prevented without increasing the concentration of the impurity of the semiconductor substrate 11S. Further, fabrication steps of a semiconductor integrated circuit device can be simplified. Further, a number of fabrication steps of a semiconductor integrated circuit device can be reduced. Therefore, development and fabrication time of a semiconductor integrated circuit device can be shortened. Further, cost of a semiconductor integrated circuit device can be reduced. Further, in patterning a gate electrode, it is not necessary to consider a difference in the shape of the gate electrode by nMIS and pMIS, a dispersion in dimensions of fabricating the gate electrode in nMIS and pMIS can be reduced and accordingly, accuracy of dimensions of fabricating the gate electrode can be promoted. Therefore, yield of a semiconductor integrated circuit device can be promoted. Further, performance of a semiconductor integrated circuit device can be promoted.
  • The [0108] SiGe layer 15 b can be formed by a CVD process using a mixed gas of monosilane (SiH4) and germane (GeH4). However, in forming the SiGe layer 15 b, boron may be introduced in situ in forming the SiGe layer by depositing the layer by a CVD process using silane (SiH4), germane (GeH4) and diborane (B2H6) as source gases.
  • The [0109] polycrystal silicon layer 15 c is deposited over the SiGe layer 15 b. The polycrystal silicon layer 15 c is provided in consideration of depositing cobalt (Co) and forming a cobalt silicide layer as described later. That is, when Co is formed directly over the SiGe layer 15 b, compatibility is low between SiGe and Co, a resistance value of the gate electrode becomes high and accordingly, the polycrystal silicon layer 15 c is provided to prevent thereof. A thickness of the polycrystal silicon layer 15 c is set such that in removing a mask made of silicon oxide formed over the polycrystal silicon layer 15 c by etching as described later, the polycrystal silicon layer 15 c is not penetrated even by an overetching processing thereof and is made, for example, about 50 nm. This is for preventing the SiGe layer 15 b from being exposed directly to a cleaning solution in a cleaning processing which is carried out after removing the mask by etching.
  • Next, as shown by arrow marks of FIG. 4, boron, mentioned above, is introduced to the gate [0110] electrode forming film 15 by an ion implantation process. As described above, according to the SiGe layer 15 b having the concentration of Ge equal to or larger than 40%, there is constructed a single gate electrode structure of only boron. Further, when boron is introduced in situ in forming the SiGe layer 15 b as described above, it is not necessary to ion-implant boron again.
  • Successively, as shown by FIGS. 5A and 5B, an insulating [0111] film 16 comprising, for example, a silicon oxide film is formed over the polycrystal silicon layer 15 c by a CVD process. The insulating film 16 constitutes a mask in patterning a gate electrode forming film by a dry etching process. A film thickness of the insulating film 16 needs to set to a sufficient thickness such that when the SiGe layer 15 b is etched, a matrix thereof is not etched and is, for example, about 50 nm.
  • Thereafter, after coating a reflection [0112] preventive film 17 having a thickness of, for example, 0.1 μm over the insulating film 16, a photoresist pattern 18 having a thickness of, for example, about 0.5 μm is formed thereabove. The photoresist pattern 18 is formed by coating an organic photo resist film over the reflection preventive film 17 and exposing the photoresist film by irradiating the photoresist film with exposure beam such as excimer laser beam via a photomask.
  • Next, with the [0113] photoresist pattern 18 as an etching mask, the reflection preventive film 17 and the insulating film 16 exposed therefrom are etched and removed by a dry etching process. In this case, in etching processing of the reflection preventive film 17 and the insulating film 16, there is used, for example, an etching apparatus of a parallel flat plate type and the reflection preventive film 17 and the insulating film 16 are processed to etch by separate chambers.
  • In processing to etch the reflection [0114] preventive film 17, for example, O2/N2/CF4 is used as a process gas. Further, in processing to etch the insulating film 16, for example, C4F8/Ar/O2 is used as a process gas. In processing to etch the insulating film 16, by using a gas having a high carbon rate such as C4F8, selectivity of etch rate with respect to the polycrystal silicon layer 15 c of the matrix can be provided and accordingly, an amount of polishing the polycrystal silicon layer 15 c can be reduced.
  • Successively, by removing the [0115] photoresist pattern 18 and the reflection preventive film 17 by ashing as shown by FIGS. 6A and 6B and thereafter subjecting the semiconductor substrate 11S to wet cleaning processing, polymers produced by the dry etching processing are removed.
  • Thereafter, with the insulating [0116] film 16 patterned by the dry etching processing as an etching mask, the gate electrode forming film 15 (that is, polycrystal silicon layer 15 a, SiGe layer 15 b and polycrystal silicon layer 15 c) exposed therefrom is etched and removed by a dry etching process.
  • The dry etching processing is carried out in the [0117] etching chamber 8 at inside of the etching apparatus 1 shown in FIG. 1. In the processing, there are required anisotropic shape (verticalness) and high selectivity with respect to the gate insulating film 14 of the matrix. Therefore, according to Embodiment 1, there is used, for example, a microwave etcher and etching conditions are constituted by, for example, following five stage steps.
  • A first step is constituted by a condition nonselective with regard to the silicon oxide film. For example, Cl[0118] 2 is used as a process gas and a flow rate thereof is set to, for example, about 80 ml/min. Further, pressure is set to, for example, about 0.4 Pa. Further, a microwave/RF is set to, for example, about 400/80 W. A processing time period is set to, for example, about 5 sec.
  • A second step is constituted by a condition mainly for providing stability of electricity discharge. For example, HBr/Cl[0119] 2 is used as a process gas and a flow rate thereof is set to, for example, about 90 through 20 ml/min. Further, pressure is set to, for example, about 0.4 Pa. Further, a microwave/RF is set to, for example, about 800/40 W. A processing time period is set to, for example, about 2 sec.
  • A third step is constituted by a condition having low selectivity with regard to the silicon oxide film. Up to a thickness position at a middle of the [0120] SiGe layer 15 b is etched and removed by the third step. For example, HBr/Cl2/O2 is used as a process gas and a flow rate thereof is set to, for example, about 90/20/3 ml/min. Further, pressure is set to, for example, about 0.4 Pa. Further, a microwave/RF is set to, for example, about 400/30 (or 40) W. A processing time period is set to, for example, about 30 sec.
  • A fourth step is constituted by a condition having high selectivity with respect to the silicon oxide film. By the fourth step, up to the [0121] polycrystal silicon layer 15 a of the lowermost layer are all etched and removed (just etching). The just etching, mentioned here, refers to a time point at which the gate insulating film 14 is exposed at a portion thereof excluding stepped portions of the element separating portions 12. For example, HBr/O2 is used as a process gas and a flow rate thereof is set to, for example, about 74/3 ml/min. Further, pressure is set to, for example, about 0.4 Pa. Further, a microwave/RF is set to, for example, about 400/25 W. A processing time period is made up to the just etching. In this case, when HBr/O2 is used, by detecting SiBr (wavelength=426 nm), further, when Cl2/O2 is used, by detecting SiCl (wavelength=391 nm), respective end points can be detected.
  • A fifth step is an overetching processing and is constituted by a condition of removing a residue of etching of the polycrystal silicon layers [0122] 15 a and 15 b. As a process gas, there is used, for example, HBr/O2 or Cl2/O2 having high selectivity with respect to the silicon oxide film as mentioned above and a flow rate thereof is set to, for example, about 105/8 ml/min. Further, pressure is set to, for example, about 0.6 Pa. Further, a microwave/RF is set to, for example, about 400/45 W. A processing time period is set to, for example, about 30 sec.
  • By the processing of etching the gate electrode forming film, as shown by FIGS. 7A and 7B, a [0123] gate electrode 15G is formed. After the processing, side faces of the gate electrode 15G are formed substantially orthogonally to the main face of the semiconductor substrate 11S. That is, the side edge is not caused at the side faces of the gate electrode 15G.
  • Next, the [0124] semiconductor substrate 11S finished with the processings, is taken out from the etching chamber 8 of the etching apparatus 1 of FIG. 1 and is transferred into the postprocessing chamber 9 in a state of maintaining vacuum without exposing the semiconductor substrate 11S to outside air. The object of the postprocessing resides in removing reaction products (SiCl, SiOCl, SiOBr) including Si produced in the processing of etching the gate electrode forming film 15 and removing Cl, Br adsorbed to the surface of the semiconductor substrate 11S or reaction products including Cl, Br.
  • When the postprocessing is not carried out, reaction products (particularly reaction products including Si) cannot be removed only by a cleaning processing thereafter and therefore, in later steps, the reaction products are exfoliated to thereby produce foreign matters. Further, when the [0125] semiconductor substrate 11S after finishing with the etching processing is returned to a wafer cassette, the reaction products are adhered to a main face of other semiconductor substrate 11S before the etching processing and when there is carried out etching processing of the gate electrode forming film with respect to the other semiconductor substrate 11S, the adhered matters constitute a mask to thereby produce residue of etching.
  • Further, when Cl or Br adhered to the surface of the [0126] semiconductor substrate 11S is not removed, parts of the etching apparatus are corroded by Cl or Br. Further, Cl or Br is provided with high toxicity and accordingly, adverse influence is effected on the human body. Therefore, the postprocessing after the etching processing is indispensable. Even when polycrystal silicon is used as the gate electrode material, the post processing is carried out and, for example, O2/CHF3 is used as a process gas in that case.
  • Hence, also when the SiGe layer is provided as the gate electrode material, the postprocessing is carried out under the same conditions. That is, similar to the postprocessing when polycrystal silicon is used as a gate electrode material, the postprocessing is carried out by using, for example, O[0127] 2/CHF3 gas. The O2/CHF3 gas is used in the post processing because a stable electricity discharge range is provided and further, the gas is generally used in the postprocessing when polycrystal silicon is used as the gate electrode material and is easy to introduce since data amount is enormous.
  • As a result, as shown by FIGS. 8A and 8B, it has been found by the inventors for the first time that there is caused side etching of polishing two side faces of the [0128] SiGe layer 15 b toward center. Further, an explanation will be given of an amount of side etching in the specification in reference to FIGS. 8A and 8B as follows. That is, a side etching amount (LS1+LS2) is a value produced by subtracting a length LB in a channel direction of the SiGe layer 15 b from a length LA in the channel direction (direction along main face of semiconductor substrate 11S) of the polycrystal silicon layers 15 a and 15 c of the gate electrode 15G (LS1+LS2=(LA−LB)). Here, when the side etching amount is defined by a rate with respect to the length in the channel direction of the remaining polycrystal silicon layers 15 a and 15 b, the side etching amount can be represented by ((LA−LB)/LA)×100(%). In FIGS. 8A and 8B, the side etching amount is about 70% (that is, 70% is polished).
  • FIGS. 8A and 8B show a case in which the Ge concentration of the [0129] SiGe layer 15 b is made, for example, 50%. As detailed postprocessing conditions, for example, O2/CHF3=600/40 (ml/min), pressure is set to 100 Pa, microwave power is set to 1000 W and electricity discharge time is set to 20 sec.
  • Further, although the inventors have carried out the postprocessing under the postprocessing condition by a condition of reducing an O[0130] 2 flow rate, for example, O2/CHF3=100/10 (ml/min), the side etching is caused even in that case. That is, it has been found that the side etching cannot be prevented only by reducing the O2 amount.
  • However, the side etching is not caused under a condition of single O[0131] 2 gas. This is because etching of Si is not progressed since there is not a fluorine species gas. However, the adhered matters on the surface of the semiconductor substrate cannot be removed only by O2 and accordingly, the condition cannot be used in the actual process.
  • Further, the side etching is caused even under a condition of adding a very small amount of CHF[0132] 3 to O2, for example, a condition of O2/CHF3=600/10 (ml/min). Further, by experiment by the inventors, when the Ge concentration of the SiGe layer is 20%, the side etching is not caused.
  • After a result of an investigation based on the result of experiment, the inventors have found for the first time that there is conceivable a model in which when O[0133] 2/CHF3 is used for the post processing condition, O and Ge are explosively reacted with each other in plasma and highly volatile GeO is produced (and accordingly, when the Ge concentration is increased, the side edge amount is increased), as a result, the side etching is caused.
  • Hence, according to [0134] Embodiment 1, as the postprocessing condition, plasma processing is carried out under a mixed gas atmosphere of a gas hardly reactive to Ge and a gas having an etching function of Si. As a gas hardly reactive to Ge, there is used an inert gas such as argon (Ar) gas further, as a gas having the function of etching Si, there is used a gas including fluorine such as CHF3.
  • As a result, as shown by FIGS. 9A and 9B, a vertical shape of the side faces of the [0135] gate electrode 15 can be achieved. Although FIGS. 9A and 9B exemplify a case of causing more or less side etching, according to the post processing condition, the gate electrode 15G can be formed also in a state of dispensing with the side etching. Further, a time period of the postprocessing in this case, is set such that an amount of polishing the polycrystal silicon layer 15 c is set to be substantially in line with the O2/CHF3 condition and it is not that the side etching is not caused because the etching amount is small.
  • An example of specific postprocessing conditions is shown as follows. That is, for example, Ar/CHF[0136] 3 is about 400/20 (ml/min), pressure is about 70 Pa, a microwave power is about 750 W and an electricity discharge time period is about 20 sec. Further, the Ge concentration of the SiGe layer 15 b is, for example, equal to or larger than 20%. According to a result of experiment by the inventors, under a condition of high concentration of CHF3 in the postprocessing, for example, under a condition of Ar/CHF3=600/40 (ml/min), for example, there causes deposition of a compound including Si, H (hydrogen) and F (fluorine) and the etching is not progressed and therefore, the concentration of CHF3 is pertinently equal to or lower than about 5%. Further, in comparison with O2/CHF3 condition, Ar/CHF3 is provided with a narrow electricity discharge stabilized region and electricity discharge becomes unstable under a condition in which pressure is equal to or higher than 80 Pa or the microwave power is equal to or larger than 1000 W. Therefore, from the above-described conditions, it is preferable as the postprocessing conditions that the concentration of CHF3 is about 5%, pressure is equal to or lower than 70 Pa and the microwave power is about 750 W.
  • Further, although according to the above-described postprocessing conditions, as a gas hardly reactive to Ge, there is used Ar having high electricity discharge stability, the gas is not limited thereto but can be changed variously, in place of Ar, for example, there can also be used other inert gas such as helium (He), neon (Ne), krypton (Kr) or xenon (Xe). Further, nitrogen (N[0137] 2) gas can also be used in place of Ar. In that case, as a result of forming a silicon nitride (SiN) film at surfaces (side faces or upper face) of the gate electrode in the postprocessing, the SiN film becomes a protective film and functions to prevent side etching of two side faces of the gate electrode.
  • Further, although CHF[0138] 3 is used as a gas having a function of etching Si, the gas is not limited thereto but can be changed variously and in place of CHF3, there can also be used a gas including fluorine such as CF4, C2F6 or SF6. Under a condition of postprocessing gas of Ar/CF4, an etching rate of the polycrystal silicon layers 15 a and 15 c is large. For example, the etching rate of Ar/CF4=400/40 (ml/min) is about nine times as much as that of Ar/CHF3. Hence, in this case, the postprocessing time period is shortened to, for example, about 5 sec. In this case, the side etching amount is larger than that of Ar/CHF3 to be about 20%, however, side etching under the condition of O2/CHF3 is not caused. That is, the side etching amount is about 20% in a gas system of Ar/CF4 having comparatively large side etching. In this way, according to the invention, the side etching amount can be made equal to or lower than 40%, the side etching amount can be made about 20% as an actually provided result when Ar/CF4 gas is used and the side etching amount can be made equal to or lower than 10% as an actually provided result when Ar/CHF3 gas is used.
  • In this way, according to [0139] Embodiment 1, even after the postprocessing, the sectional shape of the gate electrode 15G having the SiGe layer 15 b can be improved. That is, accuracy of dimensions of fabricating the gate electrode 15G can be promoted. Therefore, according to Embodiment 1, the yield of the semiconductor integrated circuit device can be promoted. Further, the performance of the semiconductor integrated circuit device can be promoted.
  • Further, FIG. 10 shows a result of investigating performance of removing Cl or Br adhered to the [0140] semiconductor substrate 11S by total reflection fluorescent X-ray. Notations A1 through A3 of the abscissa of FIG. 10 indicate a case of using Ar/CHF3 as a postprocessing gas (present invention), notation A1 shows a case of the postprocessing time period of 10 sec, notation A2 designates a case of the postprocessing time period of 20 sec and notation A3 designates a case of the postprocessing time period of 25 sec. Further, notation B designates a case of using Ar/CF4 as a postprocessing gas (present invention) and is a case of the postprocessing time period of 5 sec. Further, notation C designates a case of using O2/CHF3 as the postprocessing gas condition (technology investigated by the inventors) and the postprocessing time period is 20 sec. Notation D designates a case in which the postprocessing is not carried out and notation E designates a case in which patterning and postprocessing of the gate electrode are not carried out. It is apparent from FIG. 10 that under the Ar/CHF3 condition, with regard to the performance of removing Cl and Br, there is achieved an effect equal to or higher than the O2/CHF3 condition. After the above-described postprocessing, the semiconductor substrate 11S is taken out from the etching apparatus 1 shown in FIG. 1.
  • Next, as shown by FIGS. 11A and 11B, by ion-implanting, for example, phosphor to nMIS forming areas with the [0141] gate electrode 15G as a mask, there are formed n−-type semiconductor areas 19 a having a low concentration of impurity constituting a source and a drain (LDD; Lightly Doped Drain) of nMIS. Successively, by ion-implanting, for example, boron to pMIS forming areas with the gate electrode 15G as a mask, there are formed p−-type semiconductor areas 20 a having a low concentration of impurity constituting a source and a drain (LDD) of pMIS.
  • Successively, after depositing an insulating film made of, for example, silicon oxide over the [0142] semiconductor substrate 11S by a CVD process, the deposit is etched back by anisotropic dry etching. At this occasion, the insulating film 16 is also etched back and the polycrystal silicon layer 15 c is exposed. In this way, as shown by FIGS. 12A and 12B, there are formed side walls (side wall insulating films) 21 at both side faces of the gate electrode 15G.
  • Thereafter, as shown by FIGS. 13A and 13B, by ion-implanting, for example, phosphor to the nMIS forming areas with the [0143] gate electrode 15G and the side walls 21 as masks, there are formed n+-type semiconductor areas 19 b having a high concentration of impurity constituting the source and the drain of nMIS. Successively, by ion-implanting, for example, boron to the pMIS forming areas with the gate electrode 15G and the side walls 21 as masks, there are formed p+-type semiconductor areas 20 b having a high concentration of impurity constituting the source and the drain of pMIS. By the steps up thereto, there are substantially finished nMISQn and pMISQp each having the source and the drain of the LDD structure.
  • Next, by depositing, for example, cobalt (Co) over the [0144] semiconductor substrate 11S by a sputtering process and carrying out a heat treatment, at interface portions in contact with a Co layer and the semiconductor substrate 11S and the polycrystal silicon layer 15 c, there are formed silicide layers 22 made of, for example, cobalt silicide (CoSix) (silicide process) as shown in FIG. 14. By forming such silicide layers 22, contact resistance between wirings and the n+-type semiconductor areas 19 b, the p+-type semiconductor areas 20 b and the gate electrodes 15G can be reduced. Further, parasitic capacitance can be reduced. Therefore, increase of operational speed of the semiconductor integrated circuit device having very small elements (nMISQn, pMISQp) can be promoted. Further, in place of the cobalt silicide layer, a tungsten silicide layer or a titanium silicide layer can also be constituted.
  • Successively, as shown by FIG. 15, after depositing an insulating [0145] film 23 a comprising, for example, a silicon oxide film over the semiconductor substrate 11S by a CVD process, there are perforated contact holes 24 in the insulating film 23 a to expose the silicide layers 22. Thereafter, by depositing, for example, tungsten or titanium nitride (TiN) over the semiconductor substrate 11S by sputtering process and thereafter depositing, for example, tungsten thereabove by a CVD process and polishing the conductive films by a CMP (Chemical Mechanical Polish) process such that the conductive films remain only in the contact holes 24, plugs 25 a are formed in the contact holes 24.
  • Next, by depositing, for example, titanium nitride, aluminum (or aluminum alloy) and titanium nitoride over the insulating [0146] film 23 a and the plugs 25 a successively from lower layers by a sputtering process, and thereafter patterning thereof by normal photolithography technology and dry etching technology, first layer wirings 26 a are formed.
  • Successively, after depositing an insulating [0147] film 23 b comprising, for example, a silicon oxide film over the insulating film 23 a by a CVD process, there are perforated through holes 27 such that portions of the first layer wirings 26 a are exposed in the insulating film 23 b. Thereafter, after forming plugs 25 b in the through holes 27 similar to the plugs 25 a, second layer wirings 26 b are formed over the insulating film 23 b similar to the first layer wirings 26 a. Thereafter, by a normal fabrication method of the semiconductor integrated circuit device, there is fabricated the system LSI having a multiple layer wiring structure.
  • (Embodiment 2) [0148]
  • In Embodiment 2, an explanation will be given of a case of applying the invention to a fabrication method of a system LSI having a polymetal gate electrode structure including, for example, an SiGe layer in reference to FIG. 16A through FIG. 22B. Further, FIG. 16B through FIG. 22B are sectional views enlarging essential portions of nMIS forming areas of FIGS. 16A through 22A. Also in this case, a gate electrode structure of a pMIS forming area is the same as a gate electrode structure of an nMIS forming area and accordingly, illustration thereof is omitted. [0149]
  • First, after having been processed at the steps of FIG. 2 and FIG. 3 used in [0150] Embodiment 1, as shown by FIGS. 16A and 16B, similar to Embodiment 1, the gate insulating time 14 is formed over the main face of the semiconductor substrate 11S. Successively, similar to Embodiment 1, the polycrystal silicon layer 15 a and the SiGe layer 15 b are deposited over the semiconductor substrate 11S successively from the lower layer. Thereafter, as shown by arrow marks of FIGS. 16A and 16B, similar to Embodiment 1, boron, mentioned above, is introduced to the SiGe layer 15 b by an ion implantation process. As described above, also in Embodiment 2, in the SiGe layer 15 b having the concentration of Ge equal to or larger than 40%, there is constructed the single gate electrode structure only of boron. Further, as described above, when boron is introduced in situ in forming the SiGe layer 15 b, it is not necessary to ion-implant boron again.
  • Next, as shown by FIGS. 17A and 17B, in order to constitute a polymetal gate electrode structure, by depositing a [0151] barrier conductor layer 15 d having a thickness of, for example, about 5 nm and made of tungsten nitride (WN) or titanium nitride (TiN) over the SiGe layer 15 b by a sputtering process and thereafter depositing a metal layer 15 e having a thickness of, for example, about 80 nm and made of tungsten (W) or molybdenum (Mo) thereabove, the gate electrode forming film 15 is formed. The barrier conductive layer 15 d is provided for, for example, stress relaxation and adherence promotion of the SiGe layer 15 b and the metal layer 15 e.
  • Successively, there is formed an insulating [0152] film 28 comprising, for example, a silicon nitride film (Si3N4) over the metal layer 15 e. In this case, the insulating film 28 is constituted by depositing a silicon nitride film formed by a thermal CVD process over a silicon nitride film formed by a plasma CVD process. This is because the etching rate is lower in the silicon nitride film by the thermal CVD process than in the silicon nitride film by the plasma CVD process (selection ratio with regard to silicon oxide film is made higher). That is, in forming contact holes in later steps, even when the insulating film 28 is exposed from the contact holes, the insulating film 28 is prevented from being etched and removed.
  • Thereafter, after forming the reflection [0153] preventive film 17 and the photoresist pattern 18 over the insulating film 28 similar to Embodiment 1, with the photoresist pattern 18 as an etching mask, the reflection preventive film 17 and the insulating film 28 exposed therefrom are etched and removed by a dry etching process. In this case, in processing to etch the reflection preventive film 17 and the insulating film 28, there is used, for example, an etching apparatus of a parallel flat plate type and the reflection preventive film 17 and the insulating film 28 are processed to etch by separate chambers. In processing to etch the insulating film 28, there is used, for example, CF4/Ar as process gas.
  • Next, similar to [0154] Embodiment 1, after removing the photoresist pattern 18 and the reflection preventive film 17 by ashing as shown by FIGS. 18A and 18B, subjecting the semiconductor substrate 11S to a wet cleaning processing and removing polymers produced by the dry etching processing, with the insulating film 28 patterned by the dry etching processing as an etching mask, the gate electrode forming film 15 (that is, metal layer 15 e, barrier conductor layer 15 d, SiGe layer 15 b and polycrystal silicon layer 15 a) exposed therefrom is etched and removed by a dry etching processing.
  • The dry etching processing is carried out in the [0155] etching chamber 8 at inside of the etching apparatus 1 shown in FIG. 1. In processing to etch the metal layer 15 e and the barrier conductor layer 15 d, there is carried out an etching processing at an elevated temperature (for example, about 100 through 150° C.) using, for example, Cl/O2 gas or an etching processing at normal temperature using, for example, CF4/O2/N2/Cl2 gas. An etching processing of the SiGe layer 15 b and the polycrystal silicon layer 15 a is the same as that in Embodiment 1 and therefore, an explanation thereof will be omitted.
  • By the etching processing of the gate [0156] electrode forming film 15, as shown by FIGS. 19A and 19B, there is formed the gate electrode 15G of a polymetal structure having the metal layer 15 e over the SiGe layer 15 b. Also after the processing, the side faces of the gate electrode 15G are formed substantially orthogonal to the main face of the semiconductor substrate 11S. That is, the side etching is not caused at the side faces of the gate electrode 15G.
  • Next, the [0157] semiconductor substrate 11S finished with the processings is transferred into the postprocessing chamber 9 similar to Embodiment 1 and is subjected to a postprocessing similar to that in Embodiment 1. Thereby, as shown by FIGS. 20A and 20B, the vertical shape of the side faces of the gate electrode 15 having the polymetal structure can be achieved. Although FIG. 20B exemplifies the case of causing more or less side etching, according to the postprocessing conditions, the gate electrode 15G can be formed in a state of dispensing with side etching. After the above-described postprocessing, the semiconductor substrate 11S is taken out from the etching apparatus 1 shown in FIG. 1.
  • Successively, as shown by FIGS. 21A and 21B, similar to [0158] Embodiment 1, after forming n−-type semiconductor areas 19 a having a low concentration of impurity at nMIS forming areas, p−-type semiconductor areas 20 a having a low concentration of impurity are formed at pMIS forming areas. Thereafter, after depositing an insulating film made of, for example, silicon nitride over the semiconductor substrate 11S by a CVD process and thereafter etching back thereof by anisotropic etching, there are formed the side walls 21 each comprising a silicon nitride film at the gate electrode 15G and two side faces of the insulating film 28. Thereafter, as shown by FIGS. 22A and 22B, similar to Embodiment 1, after forming n+-type semiconductor areas 19 b having a high concentration of impurity at the nMIS forming areas, there are formed p+-type semiconductor areas 20 b having a high concentration of impurity at pMIS forming areas. By steps up to this stage, there are substantially completed nMISQn and pMISQp each having the source and the drain of the LDD structure.
  • Next, after depositing the insulating [0159] film 23 a comprising, for example, a silicon oxide film over the semiconductor substrate 11S by a CVD process, the contact holes 24 are perforated in the insulating film 23 a. At this occasion, the contact holes 24 are formed by carrying out an etching processing under an etching condition in which the silicon oxide film is made to be easier to etch by making an etching selection ratio of the silicon oxide film higher than that of the silicon nitride film. In this case, as shown by FIG. 22B, although the contact hole 24 overlaps the gate electrode 15G more or less in plane view, the gate electrode 15G is not exposed owing to the side wall 21 and the insulating film 28 made of silicon nitride (that is, the contact hole 24 can be formed self-adjustingly with respect to the gate electrode 15G) and accordingly, an integration degree of elements can be promoted.
  • Thereafter, there is fabricated a system LSI having a multiple layer wiring structure similar to [0160] Embodiment 1.
  • An effect similar to that of [0161] Embodiment 1 can be achieved also in Embodiment 2.
  • Although a specific explanation has been given of the invention carried out by the inventors based on the embodiments as described above, the invention is not limited to the embodiments but can naturally be changed variously within a range not deviated from a gist thereof. [0162]
  • For example, although in [0163] Embodiments 1 and 2, the etching chamber for patterning the gate electrode and the postprocessing chamber are separated from each other, the invention is not limited thereto but the etching processing and the postprocessing can be carried out in the same chamber. In this case, the postprocessing chamber is dispensed with and accordingly, cost of the etching apparatus can be reduced.
  • Further, although in [0164] Embodiments 1 and 2, an explanation has been given of the case of applying the invention to a fabrication technology of the gate electrode having the SiGe layer, the invention is not limited thereto but the invention is applicable, for example, a fabrication technology of wirings having Ge compounds.
  • Further, although in [0165] Embodiments 1 and 2, an explanation has been given of the case of forming only the elements having the same thickness of the gate insulating film (SiO2 converted film thickness), the invention is not limited thereto but the invention is applicable also to the case in which a plurality of elements having different thicknesses of gate insulating films are formed over the same semiconductor substrate. In this case, the film thickness of a gate insulating film of MIS using relatively high power source voltage is made thicker than the film thickness of a gate insulating film of MIS driven by relatively low power source voltage and requesting high-speed operation.
  • Although in the above-described explanation, an explanation has been given of the case of applying the invention carried out by the inventors to the fabrication technology of the system LSI which is a field of use constituting the background of the invention, the invention is not limited thereto but the invention is applicable to a semiconductor integrated circuit device having a memory circuit of, for example, DRAM (Dynamic Random Access Memory), SRAM (Static Random Access Memory) or a flash memory (EEPROM; Electric Erasable and Programmable Read Only Memory) or a semiconductor integrated circuit device having a logic circuit such as a microprocessor. [0166]
  • A simple explanation will be given of effects achieved by representative aspects of the invention disclosed in the application as follows. [0167]
  • (1) According to one of the embodiments, by patterning a gate electrode having an SiGe layer and thereafter subjecting a semiconductor substrate to a plasma processing in an atmosphere of a mixed gas of a first gas hardly reactive to Ge and a second gas having a function of etching Si, a shape of a gate electrode having the SiGe layer can be improved. [0168]
  • (2) According to one of the embodiments, by patterning the gate electrode having the SiGe layer and thereafter subjecting the semiconductor substrate to the plasma processing in the atmosphere of the mixed gas of the first gas hardly reactive to Ge and second gas having the function of etching Si, accuracy of dimensions of fabricating the gate electrode having the SiGe layer can be promoted. [0169]
  • (3) By (1) or (2), mentioned above, yield of the semiconductor integrated circuit device having the gate electrode having the SiGe layer can be promoted. [0170]
  • (4) By (1) or (2), mentioned above, performance of the semiconductor integrated circuit device having the gate electrode having the SiGe layer can be promoted. [0171]
  • (5) According to one of the embodiments, in a fabrication method of a semiconductor integrated circuit device having n-channel type and p-channel type field effect transistors over a semiconductor substrate, by patterning the gate electrode having the SiGe layer of the respective field effect transistor and thereafter subjecting the semiconductor substrate to a plasma processing in an atmosphere of a mixed gas of a first gas hardly reactive to Ge and a function of etching Si, development and fabrication time period of the semiconductor integrated device having the gate electrode having the SiGe layer can be shortened. [0172]
  • (6) According to one of the embodiments, in the fabrication method of the semiconductor integrated circuit device having the n-channel type and the p-channel type field effect transistors over the semiconductor substrate, by patterning the gate electrode having the SiGe layer of the respective field effect transistor and thereafter subjecting the semiconductor substrate to the plasma processing in the atmosphere of the mixed gas of the first gas hardly reactive to Ge and the second gas having the function of etching Si, fabrication steps of the semiconductor integrated circuit device having the gate electrode having the SiGe layer can be simplified. [0173]

Claims (33)

What is claimed is:
1. A method of fabricating a semiconductor integrated circuit device comprising the steps of:
(a) forming a gate insulating film over a semiconductor substrate;
(b) depositing a gate electrode forming film having an SiGe layer over the gate insulating film;
(c) forming a gate electrode having the SiGe layer by patterning the gate electrode forming film; and
(d) subjecting the semiconductor substrate to a plasma processing in an atmosphere of a mixed gas of a first gas hardly reactive to Ge and a second gas having a function of etching Si after the step (c).
2. The method of fabricating the semiconductor integrated circuit device according to claim 1:
wherein the first gas is an inert gas.
3. The method of fabricating a semiconductor integrated circuit device according to claim 2:
wherein the inert gas is argon gas.
4. The method of fabricating a semiconductor integrated circuit device according to claim 1:
wherein the first gas is nitrogen gas.
5. The method of fabricating a semiconductor integrated circuit device according to claim 1:
wherein the second gas is a gas including fluorine.
6. The method of fabricating a semiconductor integrated circuit device according to claim 5:
wherein the gas including fluorine is CHF3.
7. The method of fabricating a semiconductor integrated circuit device according to claim 1:
wherein a concentration of the first gas is relatively higher than a concentration of the second gas.
8. The method of fabricating a semiconductor integrated circuit device according to claim 1:
wherein a concentration of Ge of the SiGe layer is equal to or larger than 10% of a total thereof.
9. The method of fabricating a semiconductor integrated circuit device according to claim 1:
wherein a concentration of Ge of the SiGe layer is equal to or larger than 20% of a total thereof.
10. The method of fabricating a semiconductor integrated circuit device according to claim 1:
wherein a concentration of Ge of the SiGe layer is equal to or larger than 40% of a total thereof.
11. The method of fabricating a semiconductor integrated circuit device according to claim 1:
wherein a side etching amount at two side faces of the gate electrode after the step (d) is equal to or smaller than 40% of a length in a channel length direction at a portion of the gate electrode forming film left after the step (c) other than the SiGe layer.
12. The method of fabricating a semiconductor integrated circuit device according to claim 1:
wherein a length in a channel length direction at the SiGe layer of the gate electrode after the step (d) is equal to a length in the channel length direction at a portion of the gate electrode after the step (d) other than the SiGe layer.
13. The method of fabricating a semiconductor integrated circuit device according to claim 1:
wherein a field effect transistor of an n-channel type and a field effect transistor of a p-channel type having the gate electrodes are formed at the semiconductor substrate.
14. The method of fabricating a semiconductor integrated circuit device according to claim 1:
wherein the semiconductor substrate after the step (c) is transferred to the step (d) in a state of maintaining a vacuum state.
15. The method of fabricating a semiconductor integrated circuit device according to claim 1:
wherein the step (b) includes a step of introducing boron to the gate electrode forming film.
16. The method of fabricating a semiconductor integrated circuit device according to claim 1:
wherein the step (b) includes a step of depositing a polycrystal silicon layer over the SiGe layer and after the step (d), further comprising the steps of:
(e) forming side wall insulating films at side faces of the gate electrode;
(f) exposing an upper face of the gate electrode and portions of a main face of the semiconductor substrate;
(g) depositing a metal film having a high melting point over the semiconductor substrate; and
(h) forming a metal silicide layer having a high melting point at the upper face of the gate electrode and the portions of the main face of the semiconductor substrate.
17. A method of fabricating a semiconductor integrated circuit device comprising the steps of:
(a) forming a gate insulating film over a main face of a semiconductor substrate;
(b) depositing a gate electrode forming film over the gate insulating film;
(c) forming a gate electrode by patterning the gate electrode forming film; and
(d) after the step (c), subjecting the semiconductor substrate to a plasma processing in an atmosphere of a mixed gas of a first gas hardly reactive to Ge and a second gas having a function of etching Si;
wherein the step (b) includes a step of depositing an SiGe layer and depositing a polycrystal silicon layer at a layer upward from the SiGe layer.
18. The method of fabricating the semiconductor integrated circuit device according to claim 17:
wherein the first gas is an inert gas.
19. The method of fabricating a semiconductor integrated circuit device according to claim 18:
wherein the inert gas is argon gas.
20. The method of fabricating a semiconductor integrated circuit device according to claim 17:
wherein the first gas is nitrogen gas.
21. The method of fabricating a semiconductor integrated circuit device according to claim 17:
wherein the second gas is a gas including fluorine.
22. The method of fabricating a semiconductor integrated circuit device according to claim 21:
wherein the gas including fluorine is CHF3.
23. The method of fabricating a semiconductor integrated circuit device according to claim 17:
wherein a concentration of Ge of the SiGe layer is equal to or larger than 10% of a total thereof.
24. The method of fabricating a semiconductor integrated circuit device according to claim 17:
wherein a side etching amount at two side faces of the gate electrode after the step (d) is equal to or smaller than 40% of a length in a channel length direction of the polycrystal silicon layer left after the step (c).
25. The method of fabricating a semiconductor integrated circuit device according to claim 17:
wherein after the step (d), further comprising the steps of:
(e) forming side wall insulating films at side faces of the gate electrode;
(f) exposing an upper face of the gate electrode and portions of a main face of the semiconductor substrate;
(g) depositing a metal film having a high melting point over the semiconductor substrate; and
(h) forming a metal silicide layer having a high melting point at the upper face of the gate electrode and the portions of the main face of the semiconductor substrate.
26. The method of fabricating a semiconductor integrated circuit device according to claim 17 further comprising the steps of:
after the step (d), introducing a first impurity to an area of forming a field effect transistor of an n-channel type of the semiconductor substrate; and
after the step (d), introducing a second impurity for forming a semiconductor area of a conductive type reverse to a conductive type of a semiconductor area formed by the first impurity at an area of forming a field effect transistor of a p-channel type of the semiconductor substrate.
27. A method of fabricating a semiconductor integrated circuit device comprising the steps of:
(a) forming a gate insulating film over a main face of the semiconductor substrate;
(b) depositing a gate electrode forming film over the gate insulating film;
(c) forming a gate electrode by patterning the gate electrode forming film; and
(d) after the step (c), subjecting the semiconductor substrate to a plasma processing in an atmosphere of a mixed gas of a first gas hardly reactive to Ge and a second gas having a function of etching Si;
wherein the step (b) comprises the steps of depositing an SiGe layer and depositing a metal layer at a layer upward from the SiGe layer.
28. The method of fabricating a semiconductor integrated circuit device according to claim 27:
wherein a side etching amount at two side faces of the gate electrode after the step (d) is equal to or smaller than 40% of a length in a channel length direction of the metal layer left after the step (c).
29. The method of fabricating a semiconductor integrated circuit device according to claim 27:
wherein the step (b) includes a step of depositing the metal layer after introducing boron to the SiGe layer.
30. A semiconductor integrated circuit device comprising:
(a) a gate insulating film formed over a main face of a semiconductor substrate; and
(b) a gate electrode formed over the gate insulating film;
wherein the semiconductor substrate is subjected to a plasma processing in an atmosphere of a mixed gas of a first gas hardly reactive to Ge and a second gas having a function of etching Si after the step of forming the gate electrode;
wherein the gate electrode includes an SiGe layer and a polycrystal silicon layer formed at a layer upward therefrom; and
wherein a side etching amount at two side faces of the gate electrode is equal to or smaller than 40% of a length in a channel length direction of the polycrystal silicon layer constituting the gate electrode.
31. A semiconductor integrated circuit device comprising:
(a) a gate insulating film formed over a main face of a semiconductor substrate; and
(b) a gate electrode formed over the gate insulating film;
wherein the semiconductor substrate is subjected to a plasma processing in an atmosphere of a mixed gas of a first gas hardly reactive to Ge and a second gas having a function of etching Si;
wherein the gate electrode includes an SiGe layer and a polycrystal silicon layer formed at a layer upward therefrom; and
wherein a length in a channel length direction of the gate electrode at the SiGe layer, is equal to a length in the channel length direction of the polycrystal silicon layer constituting the gate electrode.
32. A semiconductor integrated circuit device comprising:
(a) a gate insulating film formed over a main face of a semiconductor substrate; and
(b) a gate electrode formed over the gate insulating film;
wherein the semiconductor substrate is subjected to a plasma processing in an atmosphere of a mixed gas of a first gas hardly reactive to Ge and a second gas having a function of etching Si after the step of forming the gate electrode;
wherein the gate electrode includes an SiGe layer and a metal layer formed at a layer upward therefrom; and
wherein a side etching amount at two side faces of the gate electrode is equal to or smaller than 40% of a length in a channel length direction of the metal layer constituting the gate electrode.
33. A semiconductor integrated circuit device comprising:
(a) a gate insulating film formed over a main face of a semiconductor substrate; and
(b) a gate electrode formed over the gate insulating film;
wherein the semiconductor substrate is subjected to a plasma processing in an atmosphere of a mixed gas of a first gas hardly reactive to Ge and a second gas having a function of etching Si after the step of forming the gate electrode; and
wherein a length in a channel length direction of the gate electrode at an SiGe layer, is equal to a length in the channel length direction of a metal layer constituting the gate electrode.
US09/810,577 2000-03-30 2001-03-19 Fabrication method for semiconductor integrated circuit devices and semiconductor integrated circuit device Expired - Fee Related US6479392B2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US09/811,589 US6633072B2 (en) 2000-03-30 2001-03-20 Fabrication method for semiconductor integrated circuit devices and semiconductor integrated circuit device
US10/639,465 US7375037B2 (en) 2000-03-30 2003-08-13 Fabrication method for semiconductor integrated circuit device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2000-094986 2000-03-30
JP2000094986A JP4056195B2 (en) 2000-03-30 2000-03-30 Manufacturing method of semiconductor integrated circuit device

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US09/811,589 Division US6633072B2 (en) 2000-03-30 2001-03-20 Fabrication method for semiconductor integrated circuit devices and semiconductor integrated circuit device

Publications (2)

Publication Number Publication Date
US20020014662A1 true US20020014662A1 (en) 2002-02-07
US6479392B2 US6479392B2 (en) 2002-11-12

Family

ID=18609946

Family Applications (3)

Application Number Title Priority Date Filing Date
US09/810,577 Expired - Fee Related US6479392B2 (en) 2000-03-30 2001-03-19 Fabrication method for semiconductor integrated circuit devices and semiconductor integrated circuit device
US09/811,589 Expired - Fee Related US6633072B2 (en) 2000-03-30 2001-03-20 Fabrication method for semiconductor integrated circuit devices and semiconductor integrated circuit device
US10/639,465 Expired - Fee Related US7375037B2 (en) 2000-03-30 2003-08-13 Fabrication method for semiconductor integrated circuit device

Family Applications After (2)

Application Number Title Priority Date Filing Date
US09/811,589 Expired - Fee Related US6633072B2 (en) 2000-03-30 2001-03-20 Fabrication method for semiconductor integrated circuit devices and semiconductor integrated circuit device
US10/639,465 Expired - Fee Related US7375037B2 (en) 2000-03-30 2003-08-13 Fabrication method for semiconductor integrated circuit device

Country Status (4)

Country Link
US (3) US6479392B2 (en)
JP (1) JP4056195B2 (en)
KR (1) KR100721086B1 (en)
TW (1) TW495876B (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6762463B2 (en) * 2001-06-09 2004-07-13 Advanced Micro Devices, Inc. MOSFET with SiGe source/drain regions and epitaxial gate dielectric
US20060205129A1 (en) * 2005-02-25 2006-09-14 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor device
US20070131652A1 (en) * 2003-01-12 2007-06-14 Mitsuhiro Okune Plasma etching method
US20080111153A1 (en) * 2006-11-14 2008-05-15 Freescale Semiconductor, Inc. Electronic device including a heterojunction region and a process for forming the electronic device
US20170040584A1 (en) * 2014-02-18 2017-02-09 Sumitomo Chemical Company, Limited Laminated porous film and non-aqueous electrolyte secondary cell

Families Citing this family (163)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1265279B1 (en) * 2000-03-13 2009-10-14 OHMI, Tadahiro Method of fabricating a flash memory device
JP4056195B2 (en) * 2000-03-30 2008-03-05 株式会社ルネサステクノロジ Manufacturing method of semiconductor integrated circuit device
US6762129B2 (en) * 2000-04-19 2004-07-13 Matsushita Electric Industrial Co., Ltd. Dry etching method, fabrication method for semiconductor device, and dry etching apparatus
JP2001358233A (en) * 2000-06-15 2001-12-26 Hitachi Ltd Semiconductor integrated circuit device and its manufacturing method
JP4447128B2 (en) * 2000-07-12 2010-04-07 富士通マイクロエレクトロニクス株式会社 Insulated gate type semiconductor device manufacturing method
JP2002353205A (en) * 2000-08-28 2002-12-06 Mitsubishi Electric Corp Method for fabricating semiconductor device and wafer treatment equipment used therefor and semiconductor device
US6770521B2 (en) * 2001-11-30 2004-08-03 Texas Instruments Incorporated Method of making multiple work function gates by implanting metals with metallic alloying additives
JPWO2004017418A1 (en) * 2002-08-15 2005-12-08 株式会社ルネサステクノロジ Semiconductor integrated circuit device and manufacturing method thereof
US6727127B1 (en) * 2002-11-21 2004-04-27 Cree, Inc. Laterally diffused MOS transistor (LDMOS) and method of making same
US6838695B2 (en) 2002-11-25 2005-01-04 International Business Machines Corporation CMOS device structure with improved PFET gate electrode
JP4098225B2 (en) * 2003-12-01 2008-06-11 松下電器産業株式会社 Plasma etching method
JP2004253778A (en) 2003-01-30 2004-09-09 Nec Electronics Corp Semiconductor device and its manufacturing method
US7157337B2 (en) * 2003-02-03 2007-01-02 Koninklijke Philips Electronics N.V. Method of manufacturing a semiconductor device and semiconductor device obtained by means of such a method
US20040209468A1 (en) * 2003-04-17 2004-10-21 Applied Materials Inc. Method for fabricating a gate structure of a field effect transistor
US6905976B2 (en) * 2003-05-06 2005-06-14 International Business Machines Corporation Structure and method of forming a notched gate field effect transistor
TWI242232B (en) * 2003-06-09 2005-10-21 Canon Kk Semiconductor substrate, semiconductor device, and method of manufacturing the same
JP4580657B2 (en) * 2004-01-30 2010-11-17 株式会社東芝 Semiconductor device and manufacturing method thereof
US7682985B2 (en) * 2004-03-17 2010-03-23 Lam Research Corporation Dual doped polysilicon and silicon germanium etch
KR100532509B1 (en) * 2004-03-26 2005-11-30 삼성전자주식회사 Trench capacitor using SiGe layer and method of fabricating the same
KR101258864B1 (en) * 2004-12-07 2013-04-29 썬더버드 테크놀로지스, 인코포레이티드 Strained silicon, gate engineered Fermi-FETs
JP4767641B2 (en) * 2005-09-27 2011-09-07 大日本スクリーン製造株式会社 Substrate processing apparatus and substrate transfer method
JP4854317B2 (en) * 2006-01-31 2012-01-18 東京エレクトロン株式会社 Substrate processing method
TW200809980A (en) * 2006-03-10 2008-02-16 Koninkl Philips Electronics Nv Method of manufacturing a bipolar transistor
JP2008118017A (en) * 2006-11-07 2008-05-22 Hitachi High-Technologies Corp Method of plasma treatment and treatment apparatus
KR100842675B1 (en) * 2006-12-27 2008-06-30 동부일렉트로닉스 주식회사 Method for etching out the poly gate of transistor
KR100859113B1 (en) * 2007-02-13 2008-09-18 홍익대학교부설과학기술연구소 Organic Thin Film Transistor with a Controlled threshold Voltage and Preparing the Same
JP5386810B2 (en) * 2007-09-13 2014-01-15 沖電気工業株式会社 MIS FET and manufacturing method thereof
JP5232512B2 (en) * 2008-03-26 2013-07-10 東京エレクトロン株式会社 Plasma processing apparatus and plasma processing method
US9324576B2 (en) 2010-05-27 2016-04-26 Applied Materials, Inc. Selective etch for silicon films
US10283321B2 (en) 2011-01-18 2019-05-07 Applied Materials, Inc. Semiconductor processing system and methods using capacitively coupled plasma
US9064815B2 (en) 2011-03-14 2015-06-23 Applied Materials, Inc. Methods for etch of metal and metal-oxide films
US8999856B2 (en) 2011-03-14 2015-04-07 Applied Materials, Inc. Methods for etch of sin films
US8808563B2 (en) 2011-10-07 2014-08-19 Applied Materials, Inc. Selective etch of silicon by way of metastable hydrogen termination
JP2013125955A (en) * 2011-12-16 2013-06-24 Elpida Memory Inc Semiconductor device and method for manufacturing the same
KR101900042B1 (en) 2012-05-10 2018-09-18 삼성전자주식회사 Semiconductor device and method for fabricating the same
US9267739B2 (en) 2012-07-18 2016-02-23 Applied Materials, Inc. Pedestal with multi-zone temperature control and multiple purge capabilities
US9373517B2 (en) 2012-08-02 2016-06-21 Applied Materials, Inc. Semiconductor processing with DC assisted RF power for improved control
US9034770B2 (en) 2012-09-17 2015-05-19 Applied Materials, Inc. Differential silicon oxide etch
US9023734B2 (en) 2012-09-18 2015-05-05 Applied Materials, Inc. Radical-component oxide etch
US9390937B2 (en) 2012-09-20 2016-07-12 Applied Materials, Inc. Silicon-carbon-nitride selective etch
US9132436B2 (en) 2012-09-21 2015-09-15 Applied Materials, Inc. Chemical control features in wafer process equipment
US8969212B2 (en) 2012-11-20 2015-03-03 Applied Materials, Inc. Dry-etch selectivity
US8980763B2 (en) 2012-11-30 2015-03-17 Applied Materials, Inc. Dry-etch for selective tungsten removal
US9111877B2 (en) 2012-12-18 2015-08-18 Applied Materials, Inc. Non-local plasma oxide etch
US8921234B2 (en) 2012-12-21 2014-12-30 Applied Materials, Inc. Selective titanium nitride etching
US10256079B2 (en) 2013-02-08 2019-04-09 Applied Materials, Inc. Semiconductor processing systems having multiple plasma configurations
US9362130B2 (en) 2013-03-01 2016-06-07 Applied Materials, Inc. Enhanced etching processes using remote plasma sources
US9040422B2 (en) 2013-03-05 2015-05-26 Applied Materials, Inc. Selective titanium nitride removal
US20140271097A1 (en) 2013-03-15 2014-09-18 Applied Materials, Inc. Processing systems and methods for halide scavenging
US9493879B2 (en) 2013-07-12 2016-11-15 Applied Materials, Inc. Selective sputtering for pattern transfer
US9773648B2 (en) 2013-08-30 2017-09-26 Applied Materials, Inc. Dual discharge modes operation for remote plasma
JP6138653B2 (en) 2013-10-08 2017-05-31 株式会社日立ハイテクノロジーズ Dry etching method
JP2015079793A (en) * 2013-10-15 2015-04-23 東京エレクトロン株式会社 Plasma processing method
US9236265B2 (en) * 2013-11-04 2016-01-12 Applied Materials, Inc. Silicon germanium processing
US9576809B2 (en) 2013-11-04 2017-02-21 Applied Materials, Inc. Etch suppression with germanium
US9520303B2 (en) 2013-11-12 2016-12-13 Applied Materials, Inc. Aluminum selective etch
US9245762B2 (en) 2013-12-02 2016-01-26 Applied Materials, Inc. Procedure for etch rate consistency
US9287095B2 (en) 2013-12-17 2016-03-15 Applied Materials, Inc. Semiconductor system assemblies and methods of operation
US9287134B2 (en) 2014-01-17 2016-03-15 Applied Materials, Inc. Titanium oxide etch
US9293568B2 (en) 2014-01-27 2016-03-22 Applied Materials, Inc. Method of fin patterning
US9396989B2 (en) 2014-01-27 2016-07-19 Applied Materials, Inc. Air gaps between copper lines
US9385028B2 (en) 2014-02-03 2016-07-05 Applied Materials, Inc. Air gap process
US9499898B2 (en) 2014-03-03 2016-11-22 Applied Materials, Inc. Layered thin film heater and method of fabrication
US9299575B2 (en) 2014-03-17 2016-03-29 Applied Materials, Inc. Gas-phase tungsten etch
US9299537B2 (en) 2014-03-20 2016-03-29 Applied Materials, Inc. Radial waveguide systems and methods for post-match control of microwaves
US9903020B2 (en) 2014-03-31 2018-02-27 Applied Materials, Inc. Generation of compact alumina passivation layers on aluminum plasma equipment components
US9269590B2 (en) 2014-04-07 2016-02-23 Applied Materials, Inc. Spacer formation
US9309598B2 (en) 2014-05-28 2016-04-12 Applied Materials, Inc. Oxide and metal removal
US9406523B2 (en) 2014-06-19 2016-08-02 Applied Materials, Inc. Highly selective doped oxide removal method
US9378969B2 (en) 2014-06-19 2016-06-28 Applied Materials, Inc. Low temperature gas-phase carbon removal
US20150371889A1 (en) * 2014-06-20 2015-12-24 Applied Materials, Inc. Methods for shallow trench isolation formation in a silicon germanium layer
US9425058B2 (en) 2014-07-24 2016-08-23 Applied Materials, Inc. Simplified litho-etch-litho-etch process
US9378978B2 (en) 2014-07-31 2016-06-28 Applied Materials, Inc. Integrated oxide recess and floating gate fin trimming
US9496167B2 (en) 2014-07-31 2016-11-15 Applied Materials, Inc. Integrated bit-line airgap formation and gate stack post clean
US9659753B2 (en) 2014-08-07 2017-05-23 Applied Materials, Inc. Grooved insulator to reduce leakage current
US9553102B2 (en) 2014-08-19 2017-01-24 Applied Materials, Inc. Tungsten separation
US9355856B2 (en) 2014-09-12 2016-05-31 Applied Materials, Inc. V trench dry etch
US9368364B2 (en) 2014-09-24 2016-06-14 Applied Materials, Inc. Silicon etch process with tunable selectivity to SiO2 and other materials
US9355862B2 (en) 2014-09-24 2016-05-31 Applied Materials, Inc. Fluorine-based hardmask removal
US9613822B2 (en) 2014-09-25 2017-04-04 Applied Materials, Inc. Oxide etch selectivity enhancement
US9355922B2 (en) 2014-10-14 2016-05-31 Applied Materials, Inc. Systems and methods for internal surface conditioning in plasma processing equipment
US9966240B2 (en) 2014-10-14 2018-05-08 Applied Materials, Inc. Systems and methods for internal surface conditioning assessment in plasma processing equipment
US11637002B2 (en) 2014-11-26 2023-04-25 Applied Materials, Inc. Methods and systems to enhance process uniformity
US9299583B1 (en) 2014-12-05 2016-03-29 Applied Materials, Inc. Aluminum oxide selective etch
US10224210B2 (en) 2014-12-09 2019-03-05 Applied Materials, Inc. Plasma processing system with direct outlet toroidal plasma source
US10573496B2 (en) 2014-12-09 2020-02-25 Applied Materials, Inc. Direct outlet toroidal plasma source
US9502258B2 (en) 2014-12-23 2016-11-22 Applied Materials, Inc. Anisotropic gap etch
US9343272B1 (en) 2015-01-08 2016-05-17 Applied Materials, Inc. Self-aligned process
US11257693B2 (en) 2015-01-09 2022-02-22 Applied Materials, Inc. Methods and systems to improve pedestal temperature control
US9373522B1 (en) 2015-01-22 2016-06-21 Applied Mateials, Inc. Titanium nitride removal
US9449846B2 (en) 2015-01-28 2016-09-20 Applied Materials, Inc. Vertical gate separation
US20160225652A1 (en) 2015-02-03 2016-08-04 Applied Materials, Inc. Low temperature chuck for plasma processing systems
US9728437B2 (en) 2015-02-03 2017-08-08 Applied Materials, Inc. High temperature chuck for plasma processing systems
US9881805B2 (en) 2015-03-02 2018-01-30 Applied Materials, Inc. Silicon selective removal
KR20160148795A (en) * 2015-06-16 2016-12-27 삼성전자주식회사 Semiconductor device and method for manufacturing the same
JP6457896B2 (en) * 2015-07-09 2019-01-23 株式会社ジャパンディスプレイ Semiconductor device and manufacturing method of semiconductor device
US9741593B2 (en) 2015-08-06 2017-08-22 Applied Materials, Inc. Thermal management systems and methods for wafer processing systems
US9691645B2 (en) 2015-08-06 2017-06-27 Applied Materials, Inc. Bolted wafer chuck thermal management systems and methods for wafer processing systems
US9349605B1 (en) 2015-08-07 2016-05-24 Applied Materials, Inc. Oxide etch selectivity systems and methods
US10504700B2 (en) 2015-08-27 2019-12-10 Applied Materials, Inc. Plasma etching systems and methods with secondary plasma injection
US10522371B2 (en) 2016-05-19 2019-12-31 Applied Materials, Inc. Systems and methods for improved semiconductor etching and component protection
US10504754B2 (en) 2016-05-19 2019-12-10 Applied Materials, Inc. Systems and methods for improved semiconductor etching and component protection
US9865484B1 (en) 2016-06-29 2018-01-09 Applied Materials, Inc. Selective etch using material modification and RF pulsing
US10629473B2 (en) 2016-09-09 2020-04-21 Applied Materials, Inc. Footing removal for nitride spacer
US10062575B2 (en) 2016-09-09 2018-08-28 Applied Materials, Inc. Poly directional etch by oxidation
US9934942B1 (en) 2016-10-04 2018-04-03 Applied Materials, Inc. Chamber with flow-through source
US10062585B2 (en) 2016-10-04 2018-08-28 Applied Materials, Inc. Oxygen compatible plasma source
US10546729B2 (en) 2016-10-04 2020-01-28 Applied Materials, Inc. Dual-channel showerhead with improved profile
US9721789B1 (en) 2016-10-04 2017-08-01 Applied Materials, Inc. Saving ion-damaged spacers
US10062579B2 (en) 2016-10-07 2018-08-28 Applied Materials, Inc. Selective SiN lateral recess
US9947549B1 (en) 2016-10-10 2018-04-17 Applied Materials, Inc. Cobalt-containing material removal
US10163696B2 (en) 2016-11-11 2018-12-25 Applied Materials, Inc. Selective cobalt removal for bottom up gapfill
US9768034B1 (en) 2016-11-11 2017-09-19 Applied Materials, Inc. Removal methods for high aspect ratio structures
US10026621B2 (en) 2016-11-14 2018-07-17 Applied Materials, Inc. SiN spacer profile patterning
US10242908B2 (en) 2016-11-14 2019-03-26 Applied Materials, Inc. Airgap formation with damage-free copper
US10566206B2 (en) 2016-12-27 2020-02-18 Applied Materials, Inc. Systems and methods for anisotropic material breakthrough
US10431429B2 (en) 2017-02-03 2019-10-01 Applied Materials, Inc. Systems and methods for radial and azimuthal control of plasma uniformity
US10403507B2 (en) 2017-02-03 2019-09-03 Applied Materials, Inc. Shaped etch profile with oxidation
US10043684B1 (en) 2017-02-06 2018-08-07 Applied Materials, Inc. Self-limiting atomic thermal etching systems and methods
US10319739B2 (en) 2017-02-08 2019-06-11 Applied Materials, Inc. Accommodating imperfectly aligned memory holes
US10943834B2 (en) 2017-03-13 2021-03-09 Applied Materials, Inc. Replacement contact process
US10319649B2 (en) 2017-04-11 2019-06-11 Applied Materials, Inc. Optical emission spectroscopy (OES) for remote plasma monitoring
US11276559B2 (en) 2017-05-17 2022-03-15 Applied Materials, Inc. Semiconductor processing chamber for multiple precursor flow
US11276590B2 (en) 2017-05-17 2022-03-15 Applied Materials, Inc. Multi-zone semiconductor substrate supports
US10497579B2 (en) 2017-05-31 2019-12-03 Applied Materials, Inc. Water-free etching methods
US10049891B1 (en) 2017-05-31 2018-08-14 Applied Materials, Inc. Selective in situ cobalt residue removal
US10920320B2 (en) 2017-06-16 2021-02-16 Applied Materials, Inc. Plasma health determination in semiconductor substrate processing reactors
US10541246B2 (en) 2017-06-26 2020-01-21 Applied Materials, Inc. 3D flash memory cells which discourage cross-cell electrical tunneling
US10727080B2 (en) 2017-07-07 2020-07-28 Applied Materials, Inc. Tantalum-containing material removal
US10541184B2 (en) 2017-07-11 2020-01-21 Applied Materials, Inc. Optical emission spectroscopic techniques for monitoring etching
US10354889B2 (en) 2017-07-17 2019-07-16 Applied Materials, Inc. Non-halogen etching of silicon-containing materials
US10043674B1 (en) 2017-08-04 2018-08-07 Applied Materials, Inc. Germanium etching systems and methods
US10170336B1 (en) 2017-08-04 2019-01-01 Applied Materials, Inc. Methods for anisotropic control of selective silicon removal
US10297458B2 (en) 2017-08-07 2019-05-21 Applied Materials, Inc. Process window widening using coated parts in plasma etch processes
US10283324B1 (en) 2017-10-24 2019-05-07 Applied Materials, Inc. Oxygen treatment for nitride etching
US10128086B1 (en) 2017-10-24 2018-11-13 Applied Materials, Inc. Silicon pretreatment for nitride removal
US10256112B1 (en) 2017-12-08 2019-04-09 Applied Materials, Inc. Selective tungsten removal
US10903054B2 (en) 2017-12-19 2021-01-26 Applied Materials, Inc. Multi-zone gas distribution systems and methods
US10615166B2 (en) * 2017-12-19 2020-04-07 International Business Machines Corporation Programmable device compatible with vertical transistor flow
US11328909B2 (en) 2017-12-22 2022-05-10 Applied Materials, Inc. Chamber conditioning and removal processes
US10854426B2 (en) 2018-01-08 2020-12-01 Applied Materials, Inc. Metal recess for semiconductor structures
US10964512B2 (en) 2018-02-15 2021-03-30 Applied Materials, Inc. Semiconductor processing chamber multistage mixing apparatus and methods
US10679870B2 (en) 2018-02-15 2020-06-09 Applied Materials, Inc. Semiconductor processing chamber multistage mixing apparatus
TWI766433B (en) 2018-02-28 2022-06-01 美商應用材料股份有限公司 Systems and methods to form airgaps
US10593560B2 (en) 2018-03-01 2020-03-17 Applied Materials, Inc. Magnetic induction plasma source for semiconductor processes and equipment
US10319600B1 (en) 2018-03-12 2019-06-11 Applied Materials, Inc. Thermal silicon etch
US10497573B2 (en) 2018-03-13 2019-12-03 Applied Materials, Inc. Selective atomic layer etching of semiconductor materials
US10573527B2 (en) 2018-04-06 2020-02-25 Applied Materials, Inc. Gas-phase selective etching systems and methods
US10490406B2 (en) 2018-04-10 2019-11-26 Appled Materials, Inc. Systems and methods for material breakthrough
US10699879B2 (en) 2018-04-17 2020-06-30 Applied Materials, Inc. Two piece electrode assembly with gap for plasma control
US10886137B2 (en) 2018-04-30 2021-01-05 Applied Materials, Inc. Selective nitride removal
US10872778B2 (en) 2018-07-06 2020-12-22 Applied Materials, Inc. Systems and methods utilizing solid-phase etchants
US10755941B2 (en) 2018-07-06 2020-08-25 Applied Materials, Inc. Self-limiting selective etching systems and methods
US10672642B2 (en) 2018-07-24 2020-06-02 Applied Materials, Inc. Systems and methods for pedestal configuration
US11049755B2 (en) 2018-09-14 2021-06-29 Applied Materials, Inc. Semiconductor substrate supports with embedded RF shield
US10892198B2 (en) 2018-09-14 2021-01-12 Applied Materials, Inc. Systems and methods for improved performance in semiconductor processing
US11062887B2 (en) 2018-09-17 2021-07-13 Applied Materials, Inc. High temperature RF heater pedestals
US11417534B2 (en) 2018-09-21 2022-08-16 Applied Materials, Inc. Selective material removal
US11682560B2 (en) 2018-10-11 2023-06-20 Applied Materials, Inc. Systems and methods for hafnium-containing film removal
US11121002B2 (en) 2018-10-24 2021-09-14 Applied Materials, Inc. Systems and methods for etching metals and metal derivatives
US11437242B2 (en) 2018-11-27 2022-09-06 Applied Materials, Inc. Selective removal of silicon-containing materials
US11721527B2 (en) 2019-01-07 2023-08-08 Applied Materials, Inc. Processing chamber mixing systems
US10920319B2 (en) 2019-01-11 2021-02-16 Applied Materials, Inc. Ceramic showerheads with conductive electrodes

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2740087B2 (en) * 1992-08-15 1998-04-15 株式会社東芝 Method for manufacturing semiconductor integrated circuit device
FR2765395B1 (en) * 1997-06-30 1999-09-03 Sgs Thomson Microelectronics METHOD FOR PRODUCING A GRID OF MOS TRANSISTORS WITH A HIGH GERMANIUM CONTENT
JP3998765B2 (en) * 1997-09-04 2007-10-31 シャープ株式会社 Method for manufacturing polycrystalline semiconductor layer and method for evaluating semiconductor device
US6200866B1 (en) * 1998-02-23 2001-03-13 Sharp Laboratories Of America, Inc. Use of silicon germanium and other alloys as the replacement gate for the fabrication of MOSFET
JPH11330463A (en) 1998-05-15 1999-11-30 Sony Corp Semiconductor device and its manufacture
US6674134B2 (en) * 1998-10-15 2004-01-06 International Business Machines Corporation Structure and method for dual gate oxidation for CMOS technology
US6348420B1 (en) * 1999-12-23 2002-02-19 Asm America, Inc. Situ dielectric stacks
FR2805924A1 (en) * 2000-03-06 2001-09-07 France Telecom Polycrystalline silicon layer etching process used in production of emitter self-aligned with extrinsic base of bipolar transistor involves stopping plasma-etching on or in germanium or silicon-germanium intermediate layer, to form grooves
JP4056195B2 (en) * 2000-03-30 2008-03-05 株式会社ルネサステクノロジ Manufacturing method of semiconductor integrated circuit device
US6319840B1 (en) * 2000-06-29 2001-11-20 International Business Machines Corporation For mol integration

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6762463B2 (en) * 2001-06-09 2004-07-13 Advanced Micro Devices, Inc. MOSFET with SiGe source/drain regions and epitaxial gate dielectric
US20070131652A1 (en) * 2003-01-12 2007-06-14 Mitsuhiro Okune Plasma etching method
US20060205129A1 (en) * 2005-02-25 2006-09-14 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor device
US20080111153A1 (en) * 2006-11-14 2008-05-15 Freescale Semiconductor, Inc. Electronic device including a heterojunction region and a process for forming the electronic device
US8390026B2 (en) * 2006-11-14 2013-03-05 Freescale Semiconductor, Inc. Electronic device including a heterojunction region
US20170040584A1 (en) * 2014-02-18 2017-02-09 Sumitomo Chemical Company, Limited Laminated porous film and non-aqueous electrolyte secondary cell

Also Published As

Publication number Publication date
US20010028093A1 (en) 2001-10-11
US20040033692A1 (en) 2004-02-19
JP4056195B2 (en) 2008-03-05
KR100721086B1 (en) 2007-05-22
KR20010094985A (en) 2001-11-03
TW495876B (en) 2002-07-21
JP2001284283A (en) 2001-10-12
US6633072B2 (en) 2003-10-14
US6479392B2 (en) 2002-11-12
US7375037B2 (en) 2008-05-20

Similar Documents

Publication Publication Date Title
US6633072B2 (en) Fabrication method for semiconductor integrated circuit devices and semiconductor integrated circuit device
EP1615265B1 (en) Semiconductor device and fabrication method thereof
KR100867565B1 (en) Semiconductor device and a method therefor
US6838695B2 (en) CMOS device structure with improved PFET gate electrode
US7368392B2 (en) Method of fabricating a gate structure of a field effect transistor having a metal-containing gate electrode
JP3210359B2 (en) Dry etching method
US7531461B2 (en) Process and system for etching doped silicon using SF6-based chemistry
US20040038436A1 (en) Method of manufacturing a semiconductor integrated circuit device
KR19980064255A (en) Selective Removal of ＴｉｘＮｙ
US6878646B1 (en) Method to control critical dimension of a hard masked pattern
US6083815A (en) Method of gate etching with thin gate oxide
US6723652B1 (en) Dry etching method and method of manufacturing semiconductor apparatus
US7229929B2 (en) Multi-layer gate stack
US6998303B2 (en) Manufacture method for semiconductor device with patterned film of ZrO2 or the like
US20050019992A1 (en) Method for manufacturing gate electrode for use in semiconductor device
JP3646718B2 (en) Manufacturing method of semiconductor device
JP3646723B2 (en) Manufacturing method of semiconductor device
US6783997B2 (en) Gate structure and method
KR101062835B1 (en) Method for manufacturing gate electrode of semiconductor device using double hard mask
US20080233747A1 (en) Semiconductor Device Manufactured Using an Improved Plasma Etch Process for a Fully Silicided Gate Flow Process
JP3399111B2 (en) Method for manufacturing semiconductor device
JP4951585B2 (en) Manufacturing method of semiconductor integrated circuit device
JP2007053391A (en) Method of manufacturing semiconductor integrated circuit device
JPH11186547A (en) Manufacture of semiconductor device
JP2002270535A (en) Method of manufacturing semiconductor device

Legal Events

Date Code Title Description
AS Assignment

Owner name: HITACHI, LTD., JAPAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:YAMAZAKI, KAZUO;KUNIYOSHI, SHINJI;KUSAKARI, KOUSUKE;AND OTHERS;REEL/FRAME:011636/0415;SIGNING DATES FROM 20010206 TO 20010222

FEPP Fee payment procedure

Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

FEPP Fee payment procedure

Free format text: PAYER NUMBER DE-ASSIGNED (ORIGINAL EVENT CODE: RMPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

FPAY Fee payment

Year of fee payment: 4

FPAY Fee payment

Year of fee payment: 8

AS Assignment

Owner name: RENESAS ELECTRONICS CORPORATION, JAPAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:HITACHI, LTD.;REEL/FRAME:026109/0528

Effective date: 20110307

REMI Maintenance fee reminder mailed
LAPS Lapse for failure to pay maintenance fees
STCH Information on status: patent discontinuation

Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362

FP Lapsed due to failure to pay maintenance fee

Effective date: 20141112