JP2007042805A - Wiring board, its manufacturing method, and semiconductor device - Google Patents

Wiring board, its manufacturing method, and semiconductor device Download PDF

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Publication number
JP2007042805A
JP2007042805A JP2005224415A JP2005224415A JP2007042805A JP 2007042805 A JP2007042805 A JP 2007042805A JP 2005224415 A JP2005224415 A JP 2005224415A JP 2005224415 A JP2005224415 A JP 2005224415A JP 2007042805 A JP2007042805 A JP 2007042805A
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Prior art keywords
protruding electrode
wiring
conductor wiring
plating layer
conductor
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Japanese (ja)
Inventor
Koichi Nagao
浩一 長尾
Yoshifumi Nakamura
嘉文 中村
Michinari Tetani
道成 手谷
Hiroyuki Imamura
博之 今村
Michiharu Torii
道治 鳥居
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Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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Priority to JP2005224415A priority Critical patent/JP2007042805A/en
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector

Abstract

<P>PROBLEM TO BE SOLVED: To provide a wiring board capable of securing high connection reliability by restraining corrosion of a projected electrode caused by moisture at an interface between the protruded electrode of a portion formed in a region on an insulating base member on opposite sides of conductive wiring and the insulating base member. <P>SOLUTION: There are provided the insulated base member 1; a plurality of conductive wirings 2 provided in alignment on the insulating base member 1; protruded electrodes 3 each formed on the conductive wiring and formed over a region on the insulating base member 1, on opposite sides of the conductive wiring 2 traversing the conductive wiring 2 longitudinally of the same 2; and a metal plating layer 4 applied on the conductive wiring 2 and the protruded electrode 3, and consisting of a metal more unlikely to be ionized than the metal of the protruded electrode 3. A metal plating layer 4a is formed also on the interface between the protruded electrode 3 of a portion formed in a region on the insulating base member 1 on opposite sides of the conductive wiring 2 and the insulating base member 1. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、テープキャリア基板のような、柔軟な絶縁性の基材に導体配線を設け、その導体配線上に接続用の突起電極を形成した構成を有する配線基板に関し、特に突起電極の耐腐食性の向上に関する。   The present invention relates to a wiring board having a configuration in which a conductive wiring is provided on a flexible insulating base material, such as a tape carrier board, and a protruding electrode for connection is formed on the conductive wiring, and in particular, corrosion resistance of the protruding electrode. It relates to the improvement of sex.

テープキャリア基板を使用したパッケージモジュールの一種として、COF(Chip On Film)が知られている。COFは、テープキャリア基板上に半導体素子を搭載し、樹脂で封止することにより搭載部を保護した構造を有する。COFに用いられるテープキャリア基板は、絶縁性のフィルム基材と、その面上に形成された多数本の導体配線から構成される。フィルム基材としては一般的にポリイミドが、導体配線としては銅が使用される。必要に応じて導体配線上には、金属めっき被膜および絶縁樹脂であるソルダーレジストの層が形成される。テープキャリア基板上の導体配線と半導体素子の電極パッドは、突起電極を介して接続される。特許文献1には、この突起電極をあらかじめ導体配線上に形成したテープキャリア基板が開示されている。   COF (Chip On Film) is known as a type of package module using a tape carrier substrate. The COF has a structure in which a semiconductor element is mounted on a tape carrier substrate and the mounting portion is protected by sealing with a resin. A tape carrier substrate used for COF is composed of an insulating film base material and a large number of conductor wirings formed on the surface thereof. Generally, polyimide is used as the film substrate, and copper is used as the conductor wiring. If necessary, a metal plating film and a solder resist layer which is an insulating resin are formed on the conductor wiring. The conductor wiring on the tape carrier substrate and the electrode pad of the semiconductor element are connected via the protruding electrode. Patent Document 1 discloses a tape carrier substrate in which this protruding electrode is previously formed on a conductor wiring.

特許文献1に記載されたテープキャリア基板の構造について、図5を参照して説明する。図5(a)は、テープキャリア基板の一部を示す斜視図である。フィルム基材1の上に、複数本の導体配線2が整列して設けられ、各導体配線2上に突起電極3が形成されている。突起電極3の平面形状は、導体配線2を横切って導体配線2の両側の領域に亘っている。図5(b)は、同テープキャリア基板の平面図である。図5(c)は、図5(b)におけるD−d線に沿って示した断面図であり、突起電極3の位置において、導体配線2を横切る方向における断面図である。導体配線2の幅方向における突起電極3の断面形状は、導体配線2の上面および両側面に接合され、中央部が両側よりも高くなった中高形状である。また突起電極3は、導体配線2の両側部でフィルム基材1の面に接するように形成されている。特許文献1に図示されてはいないが、図5(c)に示すように、導体配線2および突起電極3の表面に、Auめっき、あるいはSn等の、金属めっき層4を施すことが記載されている。   The structure of the tape carrier substrate described in Patent Document 1 will be described with reference to FIG. FIG. 5A is a perspective view showing a part of the tape carrier substrate. A plurality of conductor wirings 2 are provided in alignment on the film substrate 1, and protruding electrodes 3 are formed on the respective conductor wirings 2. The planar shape of the protruding electrode 3 extends across the regions on both sides of the conductor wiring 2 across the conductor wiring 2. FIG. 5B is a plan view of the tape carrier substrate. FIG. 5C is a cross-sectional view taken along the line D-d in FIG. 5B, and is a cross-sectional view in a direction crossing the conductor wiring 2 at the position of the protruding electrode 3. The cross-sectional shape of the protruding electrode 3 in the width direction of the conductor wiring 2 is a medium-high shape bonded to the upper surface and both side surfaces of the conductor wiring 2 and having a central portion higher than both sides. Further, the protruding electrode 3 is formed so as to be in contact with the surface of the film base 1 at both sides of the conductor wiring 2. Although not shown in Patent Document 1, as shown in FIG. 5C, it is described that a metal plating layer 4 such as Au plating or Sn is applied to the surfaces of the conductor wiring 2 and the protruding electrode 3. ing.

突起電極3を上述のような形状とすることにより、突起電極3は、実用的に十分な強さで導体配線2上に保持される。すなわち、突起電極3は、導体配線2の上面だけではなく両側面にも接合されているので、横方向に加わる力に対して十分な安定性が得られる。   By forming the protruding electrode 3 as described above, the protruding electrode 3 is held on the conductor wiring 2 with a practically sufficient strength. That is, since the protruding electrode 3 is bonded not only to the upper surface of the conductor wiring 2 but also to both side surfaces, sufficient stability against the force applied in the lateral direction can be obtained.

また、突起電極3の上面が平坦ではなく中高であることにより、半導体素子の電極パッドとの接続に好適である。すなわち、突起電極3と電極パッドとの位置合わせにずれがあっても、上面が平坦である場合と比べて、突起電極3は隣接する不適当な電極パッドと接続され難い。また、電極パッドとの接続に際して、電極パッドの表面に形成された酸化膜を、突起電極3の凸状の上面により容易に破砕することができ、酸化されていない内部と良好な電気的接続が得られる。
特開2004−327936号公報
In addition, since the upper surface of the protruding electrode 3 is not flat but medium-high, it is suitable for connection to the electrode pad of the semiconductor element. That is, even if there is a misalignment in the alignment between the protruding electrode 3 and the electrode pad, the protruding electrode 3 is less likely to be connected to the adjacent inappropriate electrode pad as compared with the case where the upper surface is flat. Further, when connecting to the electrode pad, the oxide film formed on the surface of the electrode pad can be easily crushed by the convex upper surface of the protruding electrode 3, and a good electrical connection can be made with the non-oxidized interior. can get.
JP 2004-327936 A

しかしながら、上記構造の突起電極3において、高温多湿の環境下で湿気に起因するイオン分解により、突起電極3に腐食が発生するおそれがある。すなわち、突起電極3の表面には金属めっき層4が施されており、金属めっき層4がイオン化し難い材質となっているため、高温多湿の環境下でも十分な耐候性を維持することができる。一方、フィルム基材1の面と金属めっき層4の界面では、湿気が浸入する可能性がある。突起電極3は通常、銅により形成されるので、湿気が浸入した状態で電圧が印加されると、イオン分解してマイグレーションし易くなる。その結果、突起電極3が腐食を受けて、接続状態に不良が発生する可能性がある。   However, in the protruding electrode 3 having the above structure, the protruding electrode 3 may be corroded due to ion decomposition caused by moisture in a high-temperature and high-humidity environment. That is, since the metal plating layer 4 is provided on the surface of the protruding electrode 3 and the metal plating layer 4 is made of a material that is difficult to ionize, sufficient weather resistance can be maintained even in a high temperature and high humidity environment. . On the other hand, moisture may enter at the interface between the surface of the film substrate 1 and the metal plating layer 4. Since the protruding electrode 3 is usually formed of copper, if a voltage is applied in a state where moisture has penetrated, the ionized electrode 3 is easily decomposed and migrated. As a result, the protruding electrode 3 may be corroded and a defective connection may occur.

そのような突起電極3における腐食の問題は、導体配線2の狭ピッチ化が進み、突起電極3のサイズが小さくなると、接続の信頼性に対する影響が極めて大きなものとなる。   Such a problem of corrosion in the protruding electrode 3 has a very large influence on connection reliability when the pitch of the conductor wiring 2 is reduced and the size of the protruding electrode 3 is reduced.

本発明は、導体配線の両側の絶縁基材上の領域に形成された部分の突起電極と絶縁基材との界面における、湿気に起因する突起電極の腐食を抑制し、高い接続信頼性を確保できる配線基板を提供することを目的とする。   The present invention suppresses the corrosion of the protruding electrode caused by moisture at the interface between the protruding electrode and the insulating substrate in the region on the insulating substrate on both sides of the conductor wiring and ensures high connection reliability. An object of the present invention is to provide a wiring board that can be used.

また、そのような配線基板の製造に適した製造方法、およびそのような配線基板を用いた半導体装置を提供することを目的とする。   It is another object of the present invention to provide a manufacturing method suitable for manufacturing such a wiring board, and a semiconductor device using such a wiring board.

本発明の配線基板は、絶縁基材と、前記絶縁基材上に整列して設けられた複数の導体配線と、前記導体配線に各々形成され、前記導体配線の長手方向を横切って前記導体配線の両側の前記絶縁基材上の領域に亘り形成された突起電極と、前記導体配線および前記突起電極に施された金属めっき層とを備え、前記金属めっき層は前記突起電極の金属よりもイオン化し難い金属からなり、前記導体配線の両側の前記絶縁基材上の領域に形成された部分の前記突起電極の前記絶縁基材との界面にも、前記金属めっき層が形成されていることを特徴とする。   The wiring board of the present invention includes an insulating base material, a plurality of conductor wirings arranged in alignment on the insulating base material, and the conductor wirings formed on the conductor wirings, respectively, across the longitudinal direction of the conductor wirings. A protruding electrode formed over a region on the insulating base on both sides of the insulating substrate, and a metal plating layer applied to the conductive wiring and the protruding electrode, the metal plating layer being ionized more than the metal of the protruding electrode The metal plating layer is also formed at the interface between the protruding electrode and the insulating base material in the portion formed on the insulating base material on both sides of the conductor wiring. Features.

本発明の配線基板の製造方法は、複数本の導体配線を絶縁基材上に整列して設ける工程と、前記絶縁基材の前記導体配線が設けられた面にフォトレジストを形成する工程と、前記フォトレジストに、前記導体配線を横切って前記導体配線の両側に広がる開口部を形成して、前記開口部中に前記導体配線の一部を露出させる工程と、前記露出した前記導体配線の一部にめっき法により突起電極を形成する工程と、前記フォトレジストを除去する工程と、前記導体配線および前記突起電極に、前記突起電極の金属よりもイオン化し難い金属からなる金属めっき層を形成する工程とを備える。前記導体配線および前記突起電極に金属めっき層を形成する工程では、前記絶縁基材の前記導体配線とは反対側の面を、前記導体配線を横切る方向における断面が凸となった湾曲形状を有する面に沿わせた状態で、金属めっきを施すことにより、前記導体配線の両側の前記絶縁基材上の領域に形成された部分の前記突起電極の、前記絶縁基材との界面にも前記金属めっき層を形成する。   The method for manufacturing a wiring board of the present invention includes a step of arranging a plurality of conductor wirings on an insulating base material, a step of forming a photoresist on the surface of the insulating base material on which the conductor wiring is provided, Forming in the photoresist an opening extending across the conductor wiring across the conductor wiring to expose a part of the conductor wiring in the opening; and one of the exposed conductor wirings Forming a protruding electrode on a portion by plating, removing the photoresist, and forming a metal plating layer on the conductor wiring and the protruding electrode, which is made of a metal that is more difficult to ionize than the metal of the protruding electrode. A process. In the step of forming a metal plating layer on the conductor wiring and the protruding electrode, the surface of the insulating base opposite to the conductor wiring has a curved shape with a convex cross section in a direction crossing the conductor wiring. By applying metal plating in a state along the surface, the metal is also applied to the interface between the protruding electrode and the insulating base of the portion formed in the region on the insulating base on both sides of the conductor wiring. A plating layer is formed.

本発明によれば、導体配線の両側の絶縁基材上の領域に形成された部分の突起電極と絶縁基材との界面に形成された金属めっき層により、湿気の浸入に起因する突起電極の腐食が抑制され、高い接続信頼性を確保できる。   According to the present invention, the metal plating layer formed at the interface between the part of the projecting electrode formed in the region on the insulating base on both sides of the conductor wiring and the insulating base allows the projecting electrode due to moisture intrusion to occur. Corrosion is suppressed and high connection reliability can be secured.

本発明の配線基板において、前記絶縁基材上の領域に形成された部分の前記突起電極の外側縁と前記導体配線の測縁との間の間隔をLとし、前記絶縁基材上の領域に形成された部分の前記突起電極と前記絶縁基材との界面に形成された前記金属めっき層の内側縁と、前記突起電極の外側縁との間の間隔をLpとするとき、L/10<Lpであることが好ましい。より好ましくは、L/2<Lpとする。   In the wiring board according to the present invention, the interval between the outer edge of the protruding electrode and the edge of the conductor wiring in the portion formed in the region on the insulating base is L, and the region on the insulating base is When the interval between the inner edge of the metal plating layer formed at the interface between the protruding electrode and the insulating base in the formed portion and the outer edge of the protruding electrode is Lp, L / 10 < Lp is preferable. More preferably, L / 2 <Lp.

また、前記突起電極と前記絶縁基材との界面に形成された前記金属めっき層の厚さは、前記導体配線および前記突起電極の露出した面に形成された金属めっき層厚より薄いことが好ましい。   Moreover, it is preferable that the thickness of the metal plating layer formed at the interface between the protruding electrode and the insulating substrate is thinner than the thickness of the metal plating layer formed on the exposed surface of the conductor wiring and the protruding electrode. .

前記導体配線および前記突起電極は銅により形成することができる。   The conductor wiring and the protruding electrode can be formed of copper.

前記金属めっき層は、金めっき層とすることができる。   The metal plating layer can be a gold plating layer.

上記いずれかの構成の配線基板と、前記配線基板上に搭載された半導体素子と、前記配線基板と前記半導体素子との間に介在された絶縁性樹脂とを備え、前記突起電極を介して、前記半導体素子の電極パッドと前記導体配線とが接続されている半導体装置を構成することができる。   A wiring board having any one of the above structures, a semiconductor element mounted on the wiring board, and an insulating resin interposed between the wiring board and the semiconductor element, through the protruding electrode, A semiconductor device in which the electrode pad of the semiconductor element and the conductor wiring are connected can be configured.

以下に、本発明の実施の形態について、図面を参照してより具体的に説明する。   Hereinafter, embodiments of the present invention will be described more specifically with reference to the drawings.

図1を参照して、実施の形態1におけるテープキャリア基板の構造について説明する。図1(a)は、テープキャリア基板の一部を示す平面図、図1(b)は、図1(a)のA−A線に沿った断面図である。図1(c)は、図1(b)の部分Bの拡大図である。   With reference to FIG. 1, the structure of the tape carrier substrate in the first exemplary embodiment will be described. Fig.1 (a) is a top view which shows a part of tape carrier board | substrate, FIG.1 (b) is sectional drawing along the AA line of Fig.1 (a). FIG.1 (c) is an enlarged view of the part B of FIG.1 (b).

図1(a)に示すように、絶縁性のフィルム基材1の上には、複数本の導体配線2が整列して設けられ、各導体配線2の先端部に各々、突起電極3が電解めっきにより形成されている。従来例と同様に、突起電極3は、導体配線2の長手方向を横切って導体配線2の両側のフィルム基材1上の領域に亘り形成されている。   As shown in FIG. 1A, a plurality of conductor wirings 2 are arranged on an insulating film substrate 1, and a protruding electrode 3 is electrolyzed at the tip of each conductor wiring 2, respectively. It is formed by plating. Similar to the conventional example, the protruding electrode 3 is formed across a region on the film substrate 1 on both sides of the conductor wiring 2 across the longitudinal direction of the conductor wiring 2.

図1(b)に示すように、突起電極3の導体配線2の幅方向の断面形状は、中央部が両側よりも高くなっている。また、突起電極3の表面には、金属めっき層4が形成されている。図1(b)には図示されていないが、導体配線2の、突起電極3が形成された部分以外の表面にも、突起電極3と同様に金属めっき層4が形成されている。本実施の形態においては、さらに、導体配線2の両側のフィルム基材1上の領域に形成された部分の突起電極3と、フィルム基材1との界面にも、金属めっき層4aが形成されている。   As shown in FIG. 1B, the cross-sectional shape in the width direction of the conductor wiring 2 of the protruding electrode 3 is higher at the center than at both sides. A metal plating layer 4 is formed on the surface of the protruding electrode 3. Although not shown in FIG. 1B, the metal plating layer 4 is formed on the surface of the conductor wiring 2 other than the portion where the protruding electrode 3 is formed, similarly to the protruding electrode 3. In the present embodiment, a metal plating layer 4a is also formed at the interface between the protruding electrode 3 and the film substrate 1 in the region formed on the film substrate 1 on both sides of the conductor wiring 2. ing.

導体配線2は、通常、厚みが3〜20μmの範囲で、銅を用いて形成する。突起電極3の厚みは通常、5〜10μmの範囲である。突起電極3の材料としては、例えば銅を用いることができる。金属めっき層4の厚みは0.5〜1μmの範囲である。金属めっき層4、4aとしては、Auめっき、Snめっき等が用いられる。   The conductor wiring 2 is usually formed using copper in a thickness range of 3 to 20 μm. The thickness of the protruding electrode 3 is usually in the range of 5 to 10 μm. As a material of the protruding electrode 3, for example, copper can be used. The thickness of the metal plating layer 4 is in the range of 0.5 to 1 μm. As the metal plating layers 4 and 4a, Au plating, Sn plating, or the like is used.

このように、金属めっき層4aを形成することにより、高温多湿の環境下で導体配線2の両側部のフィルム基材1の面との界面に湿気が浸入しても、湿気に起因する突起電極3の腐食を抑制することができる。すなわち、突起電極3の下面に金属めっき層4aが形成されているので、湿気が浸入しても、金属めっき層4aによりブロックされて、突起電極3に対する水分の接触が抑制される。そのような効果を得るためには、金属めっき層4aは、突起電極3を形成する金属よりもイオン化し難い材質により形成しなければならない。上述のように、Auめっき、あるいはSnめっきであれば、本実施の形態の効果を得ることができる。   Thus, by forming the metal plating layer 4a, even if moisture enters the interface with the surface of the film substrate 1 on both sides of the conductor wiring 2 in a high-temperature and high-humidity environment, the protruding electrode caused by the moisture 3 corrosion can be suppressed. That is, since the metal plating layer 4 a is formed on the lower surface of the protruding electrode 3, even if moisture enters, the metal plating layer 4 a is blocked and moisture contact with the protruding electrode 3 is suppressed. In order to obtain such an effect, the metal plating layer 4a must be formed of a material that is less likely to be ionized than the metal forming the protruding electrode 3. As described above, the effect of the present embodiment can be obtained by Au plating or Sn plating.

金属めっき層4aは、突起電極3とフィルム基材1の界面全体に亘って形成されていれば、耐腐食性を向上させるために最も効果的であるが、周縁部からある程度内部に至る一部の領域に形成されていれば、実用的に十分な効果が得られる。ここで、フィルム基材1上の領域に形成された部分の突起電極3の外側縁と導体配線2の測縁との間の間隔をLとする。また、フィルム基材1上の領域に形成された部分の突起電極3とフィルム基材1との界面に形成された金属めっき層4aの内側縁と、突起電極3の外側縁との間の間隔をLpとする。間隔Lpの間隔Lに対する割合を、L/10<Lpとすれば、突起電極3の腐食抑制に実用上十分な効果が得られる。より好ましくは、L/2<Lpとする。   If the metal plating layer 4a is formed over the entire interface between the bump electrode 3 and the film substrate 1, it is most effective for improving the corrosion resistance, but a part extending from the peripheral part to the inside to some extent. If it is formed in this region, a practically sufficient effect can be obtained. Here, the interval between the outer edge of the protruding electrode 3 and the edge measurement of the conductor wiring 2 in the part formed in the region on the film substrate 1 is L. Further, a distance between the inner edge of the metal plating layer 4 a formed at the interface between the protruding electrode 3 and the film substrate 1 in the region formed on the film substrate 1 and the outer edge of the protruding electrode 3. Is Lp. If the ratio of the distance Lp to the distance L is L / 10 <Lp, a practically sufficient effect for suppressing corrosion of the protruding electrode 3 can be obtained. More preferably, L / 2 <Lp.

また、金属めっき層4aの厚さは、導体配線2および突起電極3の露出した面に形成された金属めっき層4の厚さより薄いことが望ましい。   In addition, the thickness of the metal plating layer 4 a is preferably thinner than the thickness of the metal plating layer 4 formed on the exposed surfaces of the conductor wiring 2 and the protruding electrode 3.

フィルム基材1としては、一般的な材料であるポリイミドを用いることができる。他の条件に応じて、PET、PEI等の絶縁フィルム材料を用いても良い。必要に応じて、フィルム基材1と導体配線2の間に、エポキシ系の接着剤を介在させてもよい。   As the film substrate 1, polyimide which is a general material can be used. Depending on other conditions, an insulating film material such as PET or PEI may be used. If necessary, an epoxy-based adhesive may be interposed between the film base 1 and the conductor wiring 2.

図2は、上述の配線基板に半導体素子を実装して構成された半導体装置の構造の一例を示す断面図である。配線基板の導体配線2に形成された突起電極3と、半導体素子5の電極パッド6を接合することにより、半導体素子5が実装される。配線基板上に搭載された半導体素子5と配線基板の間に介在させて、絶縁性樹脂層7が設けられている。   FIG. 2 is a cross-sectional view showing an example of the structure of a semiconductor device configured by mounting a semiconductor element on the above-described wiring board. The semiconductor element 5 is mounted by bonding the protruding electrode 3 formed on the conductor wiring 2 of the wiring board and the electrode pad 6 of the semiconductor element 5. An insulating resin layer 7 is provided so as to be interposed between the semiconductor element 5 mounted on the wiring board and the wiring board.

次に、上記構成の配線基板の製造方法について、図3、4を参照して、以下に説明する。図3は、配線基板を製造する各工程における、導体配線に突起電極が形成される部分を示す平面図である。   Next, a method for manufacturing the wiring board having the above configuration will be described below with reference to FIGS. FIG. 3 is a plan view showing a portion where the protruding electrode is formed on the conductor wiring in each step of manufacturing the wiring board.

まず、図3(a)に示すように、複数の導体配線2が表面に整列して形成されたフィルム基材1を用意する。このフィルム基材1の全面に、図3(b)に示すように、フォトレジスト10を形成する。次に図3(c)に示すように、フィルム基材1上に形成されたフォトレジスト10の上部に、突起電極形成用の露光マスク11を対向させる。露光マスク11の光透過領域12は、複数の導体配線2の整列方向に、複数の導体配線2を横切るように連続した長孔形状を有する。   First, as shown to Fig.3 (a), the film base material 1 in which the several conductor wiring 2 was formed in alignment with the surface is prepared. A photoresist 10 is formed on the entire surface of the film substrate 1 as shown in FIG. Next, as shown in FIG. 3C, an exposure mask 11 for forming projecting electrodes is opposed to the upper part of the photoresist 10 formed on the film substrate 1. The light transmission region 12 of the exposure mask 11 has a long hole shape that is continuous across the plurality of conductor wirings 2 in the alignment direction of the plurality of conductor wirings 2.

露光マスク11の光透過領域12を通して露光し、現像することにより、図3(d)に示すように、フォトレジスト10に、導体配線2を横切る長孔状パターン13が開口される。それにより長孔状パターン13中に、導体配線2の一部が露出する。次に、フォトレジスト10の長孔状パターン13を通して、導体配線2の露出した部分に金属めっきを施して、図3(e)に示すように突起電極3を形成する。次に、フォトレジスト10を除去すれば、図3(f)に示すように、導体配線2に突起電極3が形成された構造が得られる。   By exposing and developing through the light transmission region 12 of the exposure mask 11, a long hole-like pattern 13 across the conductor wiring 2 is opened in the photoresist 10 as shown in FIG. Thereby, a part of the conductor wiring 2 is exposed in the long hole pattern 13. Next, the exposed portion of the conductor wiring 2 is subjected to metal plating through the long hole pattern 13 of the photoresist 10 to form the protruding electrode 3 as shown in FIG. Next, if the photoresist 10 is removed, a structure in which the protruding electrode 3 is formed on the conductor wiring 2 is obtained as shown in FIG.

次に、図3(g)に示すように、導体配線2および突起電極3の表面に、Au、あるいはSn等からなる金属めっき層4を形成する。その際、フィルム基材1を、図4に示すように、支持台14の表面に沿わせた状態で、金属めっきを施す。支持台14の表面は、導体配線2を横切る方向の断面において、曲率15の凸状の湾曲面を形成している。そのため、フィルム基材1上に形成された突起電極3における導体配線2の両側部に位置する部分では、フィルム基材1と突起電極3の界面が剥離されるような力が作用する。その結果、めっき液がフィルム基材1と突起電極3の間に侵入して、突起電極3の下面にも金属めっき4aが形成される。このようにして、支持台14の表面の曲率、フィルム基材1の沿わせ方等を調整することにより、金属めっき4aの厚さや、図1(c)に示した間隔Lpの大きさ等を調整することが可能である。   Next, as shown in FIG. 3G, a metal plating layer 4 made of Au, Sn, or the like is formed on the surfaces of the conductor wiring 2 and the protruding electrode 3. At that time, as shown in FIG. 4, the film base 1 is subjected to metal plating in a state where it is along the surface of the support base 14. The surface of the support base 14 forms a convex curved surface having a curvature of 15 in a cross section in a direction crossing the conductor wiring 2. For this reason, in the protruding electrodes 3 formed on the film base 1 at portions located on both sides of the conductor wiring 2, a force acts so that the interface between the film base 1 and the protruding electrodes 3 is peeled off. As a result, the plating solution enters between the film substrate 1 and the protruding electrode 3, and the metal plating 4 a is also formed on the lower surface of the protruding electrode 3. In this way, the thickness of the metal plating 4a, the size of the distance Lp shown in FIG. It is possible to adjust.

以下に、上記配線基板の突起電極3が形成された領域について、各部寸法の一例を示す。
(基材1)
幅:35〜70mm、厚さ:30〜60μm、弾性率:4〜10GPa
(導体配線2)
本数:300〜900本/pcs、ピッチ:30〜100μm
幅:15〜50μm、厚さ:6〜12μm、長さ:5〜15mm
弾性率:130〜140GPa
(突起電極3)
幅:20μm〜50μm、高さ:10〜30μm、長さ:20〜50μm
Below, an example of each part dimension is shown about the area | region in which the protruding electrode 3 of the said wiring board was formed.
(Substrate 1)
Width: 35-70 mm, thickness: 30-60 μm, elastic modulus: 4-10 GPa
(Conductor wiring 2)
Number: 300-900 / pcs, Pitch: 30-100 μm
Width: 15-50 μm, thickness: 6-12 μm, length: 5-15 mm
Elastic modulus: 130-140 GPa
(Projection electrode 3)
Width: 20-50 μm, Height: 10-30 μm, Length: 20-50 μm

本発明の配線基板によれば、湿気の浸入に起因する突起電極の腐食が抑制され、高い接続信頼性を確保できるので、パッケージモジュールの構成に好適である。   According to the wiring board of the present invention, corrosion of the protruding electrode due to moisture intrusion is suppressed, and high connection reliability can be secured, which is suitable for the configuration of the package module.

(a)は本発明の実施の形態における配線基板の平面図、(b)は(a)におけるA−A断面図、(c)は(b)におけるB部の拡大図(A) is a top view of the wiring board in embodiment of this invention, (b) is AA sectional drawing in (a), (c) is an enlarged view of the B section in (b). 本発明の実施の形態における半導体装置の平面図The top view of the semiconductor device in an embodiment of the invention 本発明の実施の形態における配線基板の製造工程を示す断面図Sectional drawing which shows the manufacturing process of the wiring board in embodiment of this invention 図3におけるC−C断面の要部を拡大して示す断面図Sectional drawing which expands and shows the principal part of CC cross section in FIG. (a)は従来例の配線基板の平面図、(b)は同配線基板の平面図、(c)は(b)におけるD−D線に沿った拡大断面図(A) is a plan view of a conventional wiring board, (b) is a plan view of the wiring board, and (c) is an enlarged cross-sectional view along the line DD in (b).

符号の説明Explanation of symbols

1 基材
2 導体配線
3 突起電極
4、4a 金属めっき層
5 半導体素子
6 電極パッド
7 絶縁性樹脂層
10 フォトレジスト
11 露光マスク
12 光透過領域
13 長孔状パターン
14 支持台
15 曲率
DESCRIPTION OF SYMBOLS 1 Base material 2 Conductor wiring 3 Protruding electrode 4, 4a Metal plating layer 5 Semiconductor element 6 Electrode pad 7 Insulating resin layer 10 Photoresist 11 Exposure mask 12 Light transmission area 13 Elongated pattern 14 Support stand 15 Curvature

Claims (8)

絶縁基材と、
前記絶縁基材上に整列して設けられた複数の導体配線と、
前記導体配線に各々形成され、前記導体配線の長手方向を横切って前記導体配線の両側の前記絶縁基材上の領域に亘り形成された突起電極と、
前記導体配線および前記突起電極に施された金属めっき層とを備え、
前記金属めっき層は前記突起電極の金属よりもイオン化し難い金属からなる配線基板において、
前記導体配線の両側の前記絶縁基材上の領域に形成された部分の前記突起電極の前記絶縁基材との界面にも、前記金属めっき層が形成されていることを特徴とする配線基板。
An insulating substrate;
A plurality of conductor wirings arranged in alignment on the insulating substrate;
Protruding electrodes formed on the insulating base material on both sides of the conductor wiring across the longitudinal direction of the conductor wiring, each formed on the conductor wiring,
A metal plating layer applied to the conductor wiring and the protruding electrode;
In the wiring board made of a metal that is harder to ionize than the metal of the protruding electrode, the metal plating layer,
The wiring board, wherein the metal plating layer is also formed at an interface between the protruding electrode and the insulating base material in a portion formed in a region on the insulating base material on both sides of the conductor wiring.
前記絶縁基材上の領域に形成された部分の前記突起電極の外側縁と前記導体配線の測縁との間の間隔をLとし、前記絶縁基材上の領域に形成された部分の前記突起電極と前記絶縁基材との界面に形成された前記金属めっき層の内側縁と、前記突起電極の外側縁との間の間隔をLpとするとき、L/10<Lpである請求項1に記載の配線基板。   The distance between the outer edge of the protruding electrode of the portion formed in the region on the insulating base and the edge of the conductor wiring is L, and the protrusion in the portion formed in the region on the insulating base 2. L / 10 <Lp, where Lp is an interval between the inner edge of the metal plating layer formed at the interface between the electrode and the insulating substrate and the outer edge of the protruding electrode. The wiring board described. L/2<Lpである請求項2に記載の配線基板。   The wiring board according to claim 2, wherein L / 2 <Lp. 前記突起電極と前記絶縁基材との界面に形成された前記金属めっき層の厚さは、前記導体配線および前記突起電極の露出した面に形成された金属めっき層厚より薄い請求項1〜3のいづれか1項に記載の配線基板。   The thickness of the said metal plating layer formed in the interface of the said protruding electrode and the said insulating base material is thinner than the metal plating layer thickness formed in the said conductor wiring and the exposed surface of the said protruding electrode. The wiring board according to any one of the above. 前記導体配線および前記突起電極は銅により形成されている請求項1〜4のいづれか1項に記載の配線基板。   The wiring board according to claim 1, wherein the conductor wiring and the protruding electrode are made of copper. 前記金属めっき層は、金めっき層である請求項1〜5のいづれか1項に記載の配線基板。   The wiring board according to claim 1, wherein the metal plating layer is a gold plating layer. 複数本の導体配線を絶縁基材上に整列して設ける工程と、
前記絶縁基材の前記導体配線が設けられた面にフォトレジストを形成する工程と、
前記フォトレジストに、前記導体配線を横切って前記導体配線の両側に広がる開口部を形成して、前記開口部中に前記導体配線の一部を露出させる工程と、
前記露出した前記導体配線の一部にめっき法により突起電極を形成する工程と、
前記フォトレジストを除去する工程と、
前記導体配線および前記突起電極に、前記突起電極の金属よりもイオン化し難い金属からなる金属めっき層を形成する工程とを備えた配線基板の製造方法において、
前記導体配線および前記突起電極に金属めっき層を形成する工程では、前記絶縁基材の前記導体配線とは反対側の面を、前記導体配線を横切る方向における断面が凸となった湾曲形状を有する面に沿わせた状態で、金属めっきを施すことにより、前記導体配線の両側の前記絶縁基材上の領域に形成された部分の前記突起電極の、前記絶縁基材との界面にも前記金属めっき層を形成することを特徴とする配線基板の製造方法。
A step of providing a plurality of conductor wirings in alignment on an insulating substrate;
Forming a photoresist on the surface of the insulating substrate provided with the conductor wiring;
Forming an opening extending on both sides of the conductor wiring across the conductor wiring in the photoresist, and exposing a part of the conductor wiring in the opening;
Forming a protruding electrode on a part of the exposed conductor wiring by a plating method;
Removing the photoresist;
In the method of manufacturing a wiring board, comprising the step of forming a metal plating layer made of a metal that is harder to ionize than the metal of the protruding electrode on the conductor wiring and the protruding electrode.
In the step of forming a metal plating layer on the conductor wiring and the protruding electrode, the surface of the insulating base opposite to the conductor wiring has a curved shape with a convex cross section in a direction crossing the conductor wiring. By applying metal plating in a state along the surface, the metal is also applied to the interface between the protruding electrode and the insulating base of the portion of the conductive wiring that is formed in the region on the insulating base on both sides of the conductor wiring. A method of manufacturing a wiring board, comprising forming a plating layer.
請求項1〜6のいずれか1項に記載の配線基板と、前記配線基板上に搭載された半導体素子と、前記配線基板と前記半導体素子との間に介在された絶縁性樹脂とを備え、前記突起電極を介して、前記半導体素子の電極パッドと前記導体配線とが接続されていることを特徴とする半導体装置。   The wiring board according to claim 1, a semiconductor element mounted on the wiring board, and an insulating resin interposed between the wiring board and the semiconductor element, An electrode pad of the semiconductor element and the conductor wiring are connected via the protruding electrode.
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