JP2007042181A - Automatic equalizer and automatic equalizing method, and reproducing apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an automatic equalizer capable of reducing an adjusting time of automatic equalization even if it is a reproducing apparatus using the maximum likelihood decoder as a binarizing means. <P>SOLUTION: A SAM value calculating part 77 calculates a SAM value of binary data detected by a maximum likelihood decoder 76 in real time. A reproduced signal evaluation value calculating part 78 calculates an evaluation value of the reproduced signal based on the SAM value calculated by the SAM value calculating part 77. A control part 79 sets parameters of an equalizer 75 based on the evaluation value of the reproduced signal calculated by the reproduced signal evaluation value calculating part 78, and varies the parameters of the equalizer 75 in the prescribed range. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an automatic equalizer and an automatic equalization method for a reproduction adjustment system module such as an equalizer in a reproduction system of a data storage device such as an optical disk, a magnetic disk, and a two-dimensional code, and reproduction using the automatic equalizer. Relates to the device.

  In general, in a transmission circuit such as a recording / reproducing device or a communication device, an equalizer characteristic suitable for the transmission characteristic is applied to the transmission analog signal or transmission digital data in order to reduce distortion of the transmission analog signal or transmission digital data error. A feed equalizer is used. For example, in a magnetic recording / reproducing apparatus such as an audio recorder and a video recorder, and an optical disc recording / reproducing apparatus, an equalizer that gives a characteristic that emphasizes a high frequency to a reproduction signal by a reproducing head is provided in the reproducing system. The recording density of tapes and optical disks can be increased.

  Conventionally, in such an equalizer, the coefficient for determining the characteristic is appropriately adjusted at the time of product shipment or the like and fixed in that state. More specifically, the optimum value of the coefficient is derived at the stage of evaluation for evaluating the reproduction signal, and the coefficient is shipped fixed to the optimum value.

  However, there are variations in the market due to mass production of recording media such as sets and optical disks. Due to this variation, there is a possibility that the coefficient value considered to be the optimum value may not be the optimum value depending on the set, the recording medium, or a combination of both. For this reason, problems such as reading errors may occur in the playback apparatus.

  Therefore, according to the following Patent Document 1 and Patent Document 2, the applicant of the present application varies the coefficient of the equalizer in the automatic equalizer, extracts the degree of change in the error rate, and determines the degree of change in the error rate. A technique for optimally setting coefficients based on the above is disclosed.

Japanese Patent No. 2805645 Japanese Patent No. 3169370

  By the way, in the above-mentioned patent documents 1 and patent documents, in order to optimize the coefficient, the degree of change of the error rate (error rate) is obtained and based on the degree of change of the error rate. Error rate detection is required to be accurate and at the same time fast. However, a relatively long time is required to stably measure the error rate.

  On the other hand, in recent years, with the development of LSI (Large Scale Integrated circuit) technology, it is easy to use a maximum likelihood decoder such as a Viterbi decoder as a binarization means of a reproduction signal for achieving a high recording density. Became. In the maximum likelihood decoder, binarization is performed by detecting the most probable sequence when reproducing a data string recorded with correlation between data.

  The present invention has been made in view of the above circumstances, and an automatic equalizer and an automatic equalization method capable of reducing the adjustment time even in a reproducing apparatus using a maximum likelihood decoder as a binarization unit, and An object is to provide a playback device.

  In order to solve the above-described problems, the automatic equalizer according to the present invention has at least two parameters that can be variably set by the equalizer, and the binarization means optimizes the reproduction signal output from the equalizer. Decoding is performed by the likelihood decoding process to detect binarized data, the reproduction signal evaluation value calculating unit calculates an evaluation value for evaluating the binarized data detected by the binarizing unit, and the control unit evaluates the reproduction signal At least two parameters of the equalizer are set based on the evaluation value of the reproduction signal calculated by the value calculation means.

  In order to solve the above-described problem, the automatic equalization method according to the present invention decodes a reproduction signal output from an equalizer having at least two parameters in which the binarization step can be variably set by maximum likelihood decoding processing. The binarized data is detected, the reproduction signal evaluation value calculation step calculates an evaluation value for evaluating the binarized data detected by the binarization step, and the setting step is calculated by the reproduction signal evaluation value calculation step The at least two parameters of the equalizer are set based on the evaluation value of the reproduction signal.

  In order to solve the above problems, a reproducing apparatus according to the present invention reproduces a signal recorded on a recording medium and binarizes the reproduced signal, and a reading means for reading the signal recorded on the recording medium; An equalizer that performs equalization processing with at least two parameters that can be variably set on a signal read from the recording medium by the reading means, and a reproduction signal output from the equalizer Binarizing means for decoding by maximum likelihood decoding and detecting binarized data; and reproduction signal evaluation value calculating means for calculating an evaluation value for evaluating the binarized data detected by the binarizing means; Control means for setting the at least two parameters of the equalizer based on the evaluation value of the reproduction signal calculated by the reproduction signal evaluation value calculation means.

  According to the present invention, the adjustment time for automatic equalization can be shortened even in a reproducing apparatus using a maximum likelihood decoder as binarization means.

  The best mode for carrying out the present invention will be described below with reference to the drawings.

  This embodiment is a magneto-optical disk reproducing apparatus to which the automatic equalizer of the present invention is applied. FIG. 1 is a schematic configuration diagram of a magneto-optical disk reproducing apparatus. As shown in FIG. 1, the magneto-optical disk reproducing device 71 converts a signal read from the magneto-optical disk 72 by an optical system (reading unit) (not shown) into a digital signal by an A / D converter 73 and then performs automatic equalization. Supply to the vessel 74. The automatic equalizer 74 outputs a digital signal that has been subjected to equalization processing, and supplies the digital signal to the error correction unit 85 via the DPLL 82, the synchronization detection unit 83, and the demodulation unit 84. The digital signal error-corrected by the error correction unit 85 is output from the output terminal 86.

  The automatic equalizer 74 includes an equalizer (equalizer EQ) 75 connected between the A / D converter 73 and the DPLL 82, and is connected to the equalizer 75 via the DPLL 82. A maximum likelihood decoder 76 that binarizes the output reproduced signal by partial response maximum likelihood (PRML) decoding processing, and a SAM value of the binarized data detected by the maximum likelihood decoder 76 in real time. And a SAM value calculation unit 77 for calculating. The automatic equalizer 74 is calculated by a reproduction signal evaluation value calculation unit 78 that calculates an evaluation value of the reproduction signal based on the SAM value calculated by the SAM value calculation unit 77 and a reproduction signal evaluation value calculation unit 78. And a control unit 79 that sets the parameters of the equalizer 75 based on the evaluation value of the reproduced signal and varies the parameters of the equalizer 75 within a predetermined range. The control unit 79 sets the parameter of the equalizer 75 based on the evaluation value of the reproduction signal, and varies the parameter of the equalizer within a predetermined range according to the parameter set by the setting unit 80. And a variable portion 81.

  The equalizer 75 is, for example, a 3-tap FIR digital filter whose characteristics are controlled by three parameters C1, C2, and C3. The equalizer 75 converts the parameter C1 into the digital signal supplied from the A / D converter 73. , C2, and C3 are given equalization processing and sent to the DPLL 82.

  As such an equalizer 75, for example, a 3-tap FIR digital filter as shown in FIG. 2 can be used. In this FIR type digital filter, the digital signal (ADRFC) 91 supplied from the A / D converter 73 is supplied to the first multiplier (B) 94 and the second and second delay elements 92 and 93 are sequentially passed through the second and second delay elements 92 and 93, respectively. The multipliers (B) 94, (A) 95, and (C) 96 are respectively weighted according to the parameters C1, C2, and C3. Are added by the adder 97 and output as equalizer output data (EQRF) 98 via the output terminal. In the figure, A, B, and C indicate respective tap coefficients, and D is a delay element having a period of one clock CLK.

  As the equalizer 75, for example, a 5-tap FIR digital filter shown in FIG. 3 can be used. In this FIR type digital filter, the digital signal (ADRFC) 401 supplied from the A / D converter 73 is supplied to the first multiplier (B) 406 and sequentially passes through the delay elements 402, 403, 404, and 405. Are supplied to the second, third, fourth and fifth multipliers (A) 407, (C) 408, (A) 409, and (B) 410, respectively, and these multipliers (B) 406 and (A) 407, (C) 408, (A) 409, and (B) 410 are weighted according to the parameters C1, C2, and C3, respectively, are added by an adder 411, and the equalizer output data ( EQRF) 412 is output.

  Next, the partial response maximum likelihood decoder (PRML) 76 will be described. The maximum likelihood decoder is a decoder that outputs a binary data sequence with respect to an input waveform. In recent years, with the development of codec technology and the continuation of conventional methods, there are integration type and differential type maximum likelihood decoders to deal with various types of data and media, etc., and some of the same systems have different characteristics. . Thus, there are one or more types of maximum likelihood decoders, and it is necessary to use an appropriate maximum likelihood decoder in order to cope with various types of data and media.

  For example, the maximum likelihood decoder based on PR (1,2,1) has a partial response detection that records and reproduces data in a narrow frequency band without suppressing waveform interference with respect to the input signal, and a plurality of This is a combination of a decoding technique for decoding the most probable bit string from the signal string with Maximum Likelihood decoding. The maximum likelihood decoder based on PR (1, -1) is a combination of similar decoding techniques, but the assumed waveform is different from (1, -1) with respect to (1,2,1).

  As described above, the maximum likelihood decoder based on PR (1,2,1) uses binarized data based on non-return to zero (NRZ) and non-return tow zero as the binarization output. Two types of invert (Non Return to Zero Invert: NRZI) are generated. The binarized data NRZI is supplied to the synchronization detecting unit 83, while the binarized data NRZ is supplied to the SAM value calculating unit 77.

  In this embodiment, the evaluation value suitable for the reproduction system using the maximum likelihood decoder is obtained based on the SAM value as described above. The SAM value is the difference between the correct path metric and the closest other path metric at the maximum likelihood decoder, eg, Tim Perkins and Zachary A. Keirn, “A Window-Margin-Like Procedure for Evaluating PRML Channel Performance ", IEEE Trans.Magn.Vol.31, No.2, pp1109-1114. Conventionally, the SAM has been obtained by a method of calculating data once captured by a computer with an evaluation system using a storage oscilloscope or the like. In the present invention, the SAM calculation is performed in substantially real time by the data reproduction apparatus itself, a reproduction signal evaluation value is obtained based on the obtained SAM value, and the automatic equalizer 74 is adjusted based on the reproduction signal evaluation value. I have to.

  The SAM is a noise margin that is allowed until the maximum likelihood decoder outputs an erroneous binary data sequence. Actually, it is difficult to obtain a completely correct binarized data sequence with a small delay time in the reproduction signal processing process. Therefore, the difference (Mr−Mw) between the degree of probability of the data series determined by the maximum likelihood decoder to be most likely (path metric Mr) and the degree of likelihood of the data series determined to be error (path metric Mw). ) Is a practical SAM value. Usually, in a situation where the reproduction signal quality is to be evaluated, the error rate of the data sequence that the maximum likelihood decoder has determined to be most likely is considered to be small. Therefore, the SAM value obtained by such a method and the SAM in a strict sense are used. The difference from the value is small.

  Next, details of the calculation of the SAM value will be described. In the following description, it is assumed that an RLL (1,7) code (minimum run limit = 1) is used as a modulation code and a PR (1,2,1) Viterbi decoder is used as a maximum likelihood decoder.

FIG. 4 shows a trellis diagram corresponding to the combination of RLL (1,7) and PR (1,2,1). FIG. 4 shows a state transition from time k to time k + 1. The states S00, S01, S10, and S11 are states determined by a combination of data for the past two bits from the present time. The value a _k represents binary data, and the value y _k represents an ideal reproduction signal.

  FIG. 5 is a detailed configuration diagram of the PR (1,2,1) maximum likelihood decoder according to the trellis diagram of FIG. A reproduction signal reproduced by a reproducing head from a recording medium such as the magneto-optical disk 72 is supplied to the branch metric calculation circuit 105. In the branch metric calculation circuit 105, the metric of the actual reproduction signal for the four types of ideal reproduction signal levels is calculated for each channel bit.

In an actual Viterbi decoder, the Euclidean distance × (−1) between the ideal reproduction signal y _k and the actual reproduction signal z _k is often adopted as a metric. That is, as the branch metric BM (y) for the ideal reproduction signal level y,
BM (y) = − (y−z _k ) ² (1)
Should be calculated.

  On the other hand, the path metric memory 130 stores a path on a trellis selected by a method to be described later, that is, a cumulative value of branch metrics corresponding to a data series pattern. In the path metric memory 130, four values are stored corresponding to the type of state where the path finally arrives. In FIG. 5, four corresponding values are stored in the areas PMM (11), PMM (10), PMM (01), and PMM (00) in the path metric memory 130, respectively. That is, the value of the state S11 is stored in the area PMM (11). Similarly, the value of state S10 is stored in area PMM (10), the value of state S01 is stored in area PMM (01), and the value of state S00 is stored in area PMM (00).

  In the following, the values stored in the areas PMM (11), PMM (10), PMM (01), and PMM (00) are represented as PMM (11), PMM (10), PMM (01), and PMM, respectively. Called (00).

When moving from time k to k + 1, it is stored in each area PMM (11), PMM (10), PMM (01) and PMM (00) of the path metric memory 130 according to the following equations (2) to (5). The updated value is updated. In the equations (2) to (5), the path metric corresponding to the path that finally reaches the state S00 at time k is expressed as PM (00) _k .

PMM (00) _{k + 1} = max {PMM (00) _k + BM (-2), PM (10) _k + BM (-1)} (2)
PMM (01) _{k + 1} = PMM (00) _k + BM (−1) (3)
PMM (10) _{k + 1} = PMM (11) _k + BM (+1) (4)
PMM (11) _{k + 1} = max {PMM (01) _k + BM (+1), PM (11) _k + BM (+2)} (5)
In equations (2) and (5), max {X, Y} indicates that the larger value is selected by comparing X and Y.

  In the configuration of FIG. 5, the branch metrics BM (+2) and BM (+1) obtained by the branch metric calculation circuit 105 by the adders 110A to 110C and 120A to 120C, the comparators 112 and 122, and the selectors 113 and 123 are used. ), BM (-1) and BM (-2), and the values PMM (11), PMM (10), PMM (01) and PMM (00) stored in each area of the path metric memory 130 The calculations of the above formulas (2) to (5) are performed, and the stored contents of the path metric memory 130 are updated.

  For example, Equation (5) indicates that the selector 113 compares the outputs of the adders 110A and 110B with the comparator 112, and the selector 113 selects the outputs of the adders 110A and 110B based on the comparison result. Desired. Similarly, Expression (2) is obtained by comparing the outputs of the adders 120A and 120B by the comparator 122 and selecting the outputs of the adders 120A and 120B by the selector 123 based on the comparison result.

  When PMM (00) and PMM (11) are updated, comparators 112 and 122 select the one with the larger path metric out of the two candidate values. By repeating this selection, all the paths that reach each of the four states share the same path at some point in time. This shared portion is the path that was most likely estimated by the Viterbi decoder 100. Based on the selection results by the comparators 112 and 122, the remaining path is stored in the path memory 140, and binarized data corresponding to the path is output from the path memory 140.

  Note that if the stored contents of the path metric memory 130 are continuously updated according to the above-described equations (2) to (5), the value of the path metric tends to increase overall. For this reason, a mechanism for preventing the overflow of the path metric memory 130 is required. Several methods have been proposed for this mechanism, but since they are not directly related to the essential part of the present invention, description thereof is omitted here.

  In FIG. 5, the outputs of the adders 110 </ b> A and 110 </ b> B are supplied to the comparator 112 and also supplied to the differentiator 111 as described above. The difference unit 111 obtains the difference between the outputs of the adders 110A and 110B, that is, the difference between the values compared by the comparator 112. The difference value obtained by the differentiator 111 is output as a path metric difference (11). Similarly, the outputs of the adders 120A and 120B are supplied to the comparator 122 and also supplied to the difference unit 121, and the difference between the outputs of the adders 120A and 120B, that is, the difference between the values compared by the comparator 122. Is output as the path metric difference (00). These path metric differences (11) and (00) are used for SAM calculation.

  Prior to a specific configuration of the SAM calculation unit, first, an algorithm of the SAM calculation will be described. As described above, the SAM here is the difference between the path metric of the data series that the Viterbi decoder has determined to be most likely and the path metric of the data series that has been determined to be in error. If the 2 bits of the data series output from the Viterbi decoder are 0 → 0, the corresponding state on the trellis should have transitioned as state S00 → S00 or state S10 → S00. For example, when a path that passes through the state S00 is selected, it means that it has been determined whether it has transitioned from the state S00 or from the state S10. At this time, the path metric difference based on this is a path metric difference (00). Similarly, when the data sequence 2 bits is 1 → 1, the path metric difference that is the basis for path selection is the path metric difference (11).

  On the other hand, for example, when the data series 2 bits are 0 → 1, this corresponds to the state transition from state S00 → S01, and the path passing through the state S01 is in the state S00 → S01 → without any choice. S11. Similarly, if the 2 bits of the data series are 1 → 0, the path passes through the states S11 → S10 → S00 with no room for selection. In summary, the SAM value may be output as shown in FIG. 6 according to the data series.

  FIG. 7 shows an exemplary configuration of the SAM calculation unit 77. The path metric difference (11) and the path metric difference (00) output from the Viterbi decoder are input to the two selection input terminals of the selection circuit 212 via the shift registers 210 and 211, respectively. The shift registers 210 and 211 are for compensating for the difference between the timing at which the path metric differences (00) and (11) are calculated and the timing at which the binarized data is output.

  The binarized data output from the Viterbi decoder path memory 140 is input to the selection circuit 212 together with the value delayed by one clock by the D-flip flop circuit 213. In the selection circuit 212, parametric differences (11) and (00) are selected and output as SAM values based on the data series indicated by the binarized data according to FIG. 6 described above, and the validity / invalidity of the SAM values is indicated. A SAM valid signal is output. The SAM valid signal is, for example, a signal that is in the “H (high level)” state when the SAM value is valid and in the “L (low level)” state when the SAM value is invalid.

  FIG. 8 shows an example of a configuration of an evaluation value calculation circuit 79 for obtaining a reproduction evaluation value from the SAM value output from the SAM value calculation unit 77. The constant generation circuit 311 generates a minimum SAM value for the ideal reproduction signal. For example, for the Viterbi decoder according to the trellis diagram of FIG. 4, the minimum value of the SAM value for the ideal reproduction signal is 6. The SAM value output from the selection circuit 212 of the SAM value calculation unit 77 and the minimum value of the SAM value for the ideal reproduction signal generated by the constant generation circuit 311 are respectively input to one and the other input terminals of the subtractor 310. Entered.

  The difference value obtained by subtracting the SAM value from the output value of the constant generation circuit 311 output from the subtractor 310 is squared by the squaring circuit 312 and supplied to the averaging circuit 315. The averaging circuit 315 averages the output value of the squaring circuit 312 when the enable signal supplied from the AND circuit 314 is “H”. The average value of the output values of the square circuit 312 is output from the averaging circuit 315 as a reproduction signal evaluation value.

  Note that the averaging circuit 315 may calculate an average value by averaging the output values of the square circuit 312 within a fixed time or a fixed number of samples, or calculate a moving average of the output values of the square circuit 312. You may do it.

  On the other hand, the SAM value and the output value of the constant generation circuit 311 are compared by the comparator 313. The output of the comparator 313 is input to one input terminal of the AND circuit 314. The other input terminal of the AND circuit 314 is supplied with the SAM valid signal output from the selection circuit 212 of the SAM calculation unit 200. As a result of the comparison by the comparator 313, if (SAM value) <= (output value of the constant generation circuit 311), the output of the comparator 313 is set to the “H” state, for example.

  Therefore, if the SAM valid signal is a value (“H”) indicating that the SAM value is valid and (SAM value) <= (output value of the constant generation circuit 311), the output from the AND circuit 314 is output. The enable signal is set to the “H” state, and the output value of the square circuit 312 is averaged by the averaging circuit 315.

  When the SAM value is larger than the output value of the constant generation circuit 311, the enable signal is in the “L” state, and the output value of the squaring circuit 312 is ignored. Therefore, it is not necessary to perform the square calculation correctly at this time.

  As described above, in the magneto-optical disk reproducing apparatus shown in FIG. 1, the SAM value calculating unit 77 calculates the SAM value of the binarized data NRZ obtained from the maximum likelihood decoder 76, and the reproduction is performed based on the SAM value. The signal evaluation value calculation unit 78 calculates a reproduction signal evaluation value, and the control unit 79 sets a parameter of the equalizer 75 based on the reproduction signal evaluation value, and varies the parameter of the equalizer 75 within a predetermined range.

  Next, details of the automatic equalization processing of the automatic equalizer 74 will be described. FIG. 9 is a transition diagram of automatic equalization performed by the automatic equalizer 74. There are four modes (states) in all, which are an idle (IDLE) mode, a search (SEARCH) mode, a wobble (WOBBLE) mode, and a hold (HOLD) mode, respectively. The IDLE mode is a conventional mode in which a fixed value is output as it is without automatic equalization. The SEARCH mode is a mode for searching for an initial value of automatic equalization, and when it falls below a certain threshold value, it becomes a WOBBLE mode. The WOBBLE mode performs wobbling from the initial value obtained in the SEARCH mode, and returns to the SEARCH mode when a predetermined threshold is exceeded in the middle. Finally, in the HOLD mode, if there is no change in the coefficient for a certain period in the WOBBLE mode, the value is held. Again, if the threshold value is exceeded, the SEARCH mode is resumed. Any mode will return to IDLE mode if reset is applied.

  First, the wobble (WOBBLE) mode will be described in detail. The WOBBLE mode is a mode of “watching over and over” in the peripheral search, as indicated by the meaning of “stagger, flutter, and wobble”. Based on the Gradient method as a basic concept, a new coefficient is determined according to the increase / decrease of the evaluation function value caused by changing the two coefficients C1 and C2 of the FIR filter.

With respect to the evaluation function value E, if the change due to ΔC1 is ΔE1, and the change due to ΔC2 is ΔE2, the new coefficients C1 ′ and C2 ′ are expressed by the appropriate feedback gain K as follows.
C1 ′ = C1 + KΔE1
C2 ′ = C2 + KΔE2
Therefore, in order to obtain ΔE1 and ΔE2, it is necessary that C1 ′ and C2 ′ always vibrate appropriately. The advantages of this Gradient method are: 1) easy processing for calculating the feedback value, 2) the target value is handled directly, so the system can be considered as a black box, and 3) the convergence is fast if a good initial value is given. In addition, 1) If there is a pseudo peak, it does not necessarily converge to the optimum value. 2) The input vibration range needs to be allowed as a system. 3) If the initial value is bad, it takes time until convergence. .

  Therefore, in the present invention, the 2-coefficient orthogonal wobbling is adopted. The 2-coefficient orthogonal wobbling can ingest the SAM value necessary for calculating the gradient of the evaluation value with respect to C1 and C2 (hereinafter referred to as Gradient) in 4Trace Cycle.

As shown in FIG. 10, Gradient (C1) and Gradient can be obtained by changing the coefficients P1 → P2 → P3 → P4 according to the trace order and ingesting the SAM Counter values at that time as SAM1, SAM2, SAM3, SAM4. (C2) can be obtained as follows.
Gradient (C1) ≡ΔSAM / ΔC1 = (SAM2 + SAM3)-(SAM1 + SAM4) / 2
Gradient (C2) ≡ΔSAM / ΔC2 = (SAM3 + SAM4)-(SAM1 + SAM2) / 2
In addition, as shown in FIG. 11, it is possible to cope with time fluctuation by alternately rotating the trace in the forward direction and the reverse direction. Then, using the above Gradient, C1new and C2new are calculated as follows, and are used as new coefficients every 4 Trace.
C1new = C1old + K x Gradient (C1)
C2new = C2old + K x Gradient (C2)
By changing the feedback gain K, the influence of the tilt can be changed. Here, the new coefficient is always included in one square surrounded by P1 to P4 in the C1, C2 plane including the decimal point. For Wobbling, the difference from the virtual center P0 is ± 0.5 at the maximum (both C1 and C2).

  Next, the SEARCH mode will be described in detail. The SEARCH mode is a mode necessary for dealing with the problem related to the initial value of the Gradient method “when initial value is bad, it takes time to converge”. FIG. 12 shows the SAM value on the C1 and C2 planes by a contour map (line division), and the white area is an area where the SAM value = 0. Accordingly, P1 to P4 in FIG. 12 are all SAM values = 0, therefore Gradient is all 0, and the new coefficient is the old coefficient itself. It's not a straightforward situation such as "it takes time to converge" as mentioned in the disadvantages, but P1 is a slight movement. Therefore, several initial value candidates are prepared in the C1 and C2 planes, and the best initial value is selected to avoid the above situation.

  The SEARCH operation is as follows: 1) Search the search point (SEARCH POINT) once, and if the best SAM value is below a certain threshold, enter the WOBBLE mode with the coefficient at that time as the initial value. 2) Search the SEARCH POINT once. If the best SAM value is greater than a certain threshold, the search is performed again. By performing the SEARCH mode processing as described above, the accuracy of the WOBBLE mode is improved.

  As described above, the HOLD mode is a mode in which the value is held if there is no change in the coefficient for a certain period in the WOBBLE mode. When the threshold value is exceeded, return to SEARCH mode. Any mode will return to IDLE mode if reset is applied.

  Next, the processing procedure of the automatic equalization operation in the automatic equalizer 74 will be described with reference to FIG. First, in step S1, automatic equalization is turned on in the IDLE mode, and automatic equalization is started.

  In step S2, the SEARCH mode is entered, and SAM values are calculated at all search points on the magneto-optical disk. FIG. 14 shows the search operation when the search points are set to 7 points, for example. The search area 422 is an area excluding the search prohibited (invalid) areas 420 and 421. The invalid area 420 is a limiter processing part for automatic equalization. With limiter processing, the coefficient may change from “0f → 10” in the calculation. However, in the case of kma, the value suddenly starts from the right end (kmb is the lower end) and the left end (kmb is the upper end). This is to prevent a completely different behavior. The invalid area 421 is a search prohibited area based on the specifications of the digital equalizer. When trying to enter the invalid areas 420 and 421 during the wobble, the value of the nearest valid area 422 is applied. The center 423 has kma = 5′h00 and kmb = 5′h00. Search points (1) to (7) are set in the search area 422, and the SAM value is calculated at all these search points.

  In step S3, it is checked whether or not the SAM value of the search point calculated in step S2 is below a predetermined threshold value. Specifically, as described above, if the best SAM value is equal to or less than a predetermined threshold, the coefficient at that time is set as an initial value. In this way, the best initial value is selected.

  In step S4, when the best initial value is selected in step S3, the process shifts to the wobble mode and starts wobbling from the minimum SAM value coefficient to calculate the SAM value. FIG. 15 is a diagram showing an example of contour lines of the SAM value for showing a specific example of the wobble operation. FIG. 5A shows an operation example in which the SAM value reaches the smallest point when the start point is determined in the search mode. The calculation of the SAM value is repeated counterclockwise and clockwise. The contour lines indicate that the SAM value decreases from 4 to 1 as the hatched line becomes denser. The smaller the SAM value, the better the evaluation value. In FIG. 15A, the SAM value is obtained in the counterclockwise direction P1-> P2-> P3-> P4. At P2, the SAM value is 3, and the other P1, P3, and P4 are all 4. Therefore, the inclination is closer to P2 as shown in FIG. In FIG. 15B, the SAM value is obtained in the clockwise direction by P1, P2, P3, and P4. P1 and P4 have a SAM value of 2, which is smaller than the SAM value 3 of P2 and P3. Therefore, it tilts more than P1 and P4. Then, in (c) of FIG. 15, P2 becomes the SAM value 1, which is better than 2 of P1, P3, and P4. Therefore, it tilts more than P2. Then, in (d) of FIG. 15, P1, P2, and P4 become SAM value 1 and P3 becomes 2. Then, the inclination becomes (e) in FIG. 15 from P1. In FIG. 15E, only P3 has a SAM value of 1, and P1, P2, and P4 have a SAM value of 2. In this state, since it is retracted from FIG. 15 (d), it is inclined to P3. Then, (f) in FIG. 15 is obtained, and P1, P2, and P4 become the SAM value 1 and P3 becomes the SAM value 2 as in (d) of FIG. 15D and FIG. 15F are repeated.

  In step S5, it is determined whether the SAM value exceeds a predetermined threshold value. Here, if it is determined that the SAM value exceeds a predetermined threshold value, the process returns to step S2, and the search mode is again entered, and the SAM value is calculated at all search points. In this way, the wobble mode performs wobbling from the initial value obtained in the search mode, and returns to the search mode when a predetermined threshold is exceeded in the middle.

  If it is determined in step S5 that the SAM value is equal to or smaller than the predetermined threshold value, the process proceeds to step S6, the inclination is calculated from the SAM value, and wobbling is performed again using a new coefficient based on the inclination as a base point. SAM counter values corresponding to P1, P2, P3, and P4 are ingested as SAM1, SAM2, SAM3, and SAM4, and the gradient of evaluation values for C1 and C2 is calculated as described above. . Then, as described above, new coefficients C1new and C2new are calculated using the gradient of the calculated evaluation value, and set as new coefficients every four traces. The wobbling is performed again using the new coefficient as a base point.

  Next, in step S7, it is checked whether or not the same coefficient has continued for a certain period of time. If it is determined that the same coefficient has continued for a certain period of time, the process proceeds to step S8. If it is determined that the same coefficient does not continue for a certain period of time, the process returns to step S4 and the wobble mode is repeated.

  In step S8, the mode is changed to the hold mode, and the coefficient is held. In other words, the hold mode holds the value if there is no change in the constant period coefficient in the wobble mode.

  In step S9, it is checked whether or not the SAM value exceeds a predetermined threshold value. If the SAM value exceeds the predetermined threshold value, the process returns to step S2 to shift to the search mode. If it is below the predetermined threshold value, the coefficient is kept held in step S8.

  If automatic equalization is turned off, transition to the idle mode is made in step S10, and automatic equalization is terminated.

  Taking the 3-tap FIR type digital filter shown in FIG. 2 as an example, in the automatic equalizer 74, the parameters that determine the characteristics of the equalizer 75 are such that the parameter C3 is always fixed to a predetermined value. C1 and C2 are variable. These variable parameters C1 and C2 are made variable according to the output from the variable unit 81.

  As will be described later, the variable unit 81 varies the parameters C1 and C2 set by the setting unit 80 within a predetermined range every predetermined short period and gives them as the parameters C1 and C2 of the equalizer 75. ing.

  The multiplier (A) 95 performs weighting of C1 / 16 (A = C1 / 16). The multiplier (B) 94 performs weighting of C2 / 16 (B = C2 / 16). The multiplier (C) weights 1− (A + B) = 1− (C1 + C2) / 16 (C = 1− (A + B) = 1− (C1 + C2) / 16). However, −16 <C1 + C2 <+16. Also, C1 [4: 0] and C2 [4: 0], and possible values are −16 to 15.

  Further, taking the 5-tap FIR type digital filter shown in FIG. 3 as an example, the parameter C3 is always fixed to a predetermined value, and the parameters C1 and C2 are variable. These variable parameters C1 and C2 are made variable according to the output from the variable unit 81.

  The multiplier (A) 407 weights C1 / 16 (A = C1 / 16). The multiplier (B) 406 performs weighting of C2 / 16 (B = C2 / 16). The multiplier (C) performs weighting of 1-2 × (A + B) = 1− (C1 + C2) / 8 (C = 1−2 × (A + B) = 1− (C1 + C2) / 8). However, −16 <C1 + C2 <+16. Also, C1 [4: 0] and C2 [4: 0], and possible values are −16 to 15. Here, C1 [4: 0] and C2 [4: 0], and possible values are −16 to 15.

  Next, referring to FIG. 16, the result of the experiment comparing the result of the optimum value (fixed value) determined at the evaluation stage, which is the conventional method, with the result of the automatic equalization using the SAM value of the present invention. explain. In the figure, the fixed value equalizer dominant region is indicated when the optimum value is selected by the operator as a fixed value. Further, the automatic equalization equalizer dominant region is when the parameters are automatically converged to the optimum values without artificially giving an initial value. From the experimental results, it can be seen that the method using automatic equalization has the same performance as the optimal fixed value set artificially.

  Of course, the present invention can also be used for adjustment at the stage of evaluation at the time of development and adjustment at the time of use as an actual product. That is, the automatic equalizer and automatic equalization method of the present invention can be used in all phases from development to user use.

  As described above, in this magneto-optical disk reproducing apparatus, the parameters C1 and C2 can be automatically adjusted using the automatic equalizer of the present invention, so that the maximum likelihood decoder is used as a binarizing means. Even with the playback device used, it is possible to always reproduce with high reliability in response to variations in production and market. Further, since the optimum value is automatically calculated, the adjustment time can be shortened. It also leads to cost reduction.

  By the way, in recent years, it has become possible to increase the maximum likelihood decoder in order to support various types of data and media in the same device by continuing the development of codec technology and the conventional system.

  Therefore, a case where a plurality of maximum likelihood decoders are used in place of PRML 76 in the magneto-optical disk reproducing apparatus shown in FIG.

  FIG. 17 is a diagram illustrating a configuration of a binarized decoding & evaluation value calculation unit used in place of the PRML 76. Two different types of integrated maximum likelihood decoder (including Viterbi decoder) 5 based on PR (1,2,1) and differential maximum likelihood decoder 6 based on PR (1, -1) This is a block for evaluating each reproduction signal of a reproduction signal processing unit that binarizes the reproduction signal using the decoder of FIG. Up to the SAM value is calculated by the maximum likelihood decoders 5 and 6, and statistical processing is performed by the same circuit (reproduction signal evaluation value calculation circuit 8). Thereby, the number of reproduction signal evaluation value calculation circuits of “(the number of maximum likelihood decoders) −1”, in this example, one reproduction signal evaluation value calculation circuit can be omitted. In addition, since one or more maximum likelihood decoders are used, there are cases in which there are two types of binarization output: binarized data by NRZ and binarized data by NRZI. As the subsequent process, the binarized data is preferably NRZI, but in the reproduction signal evaluation value calculation circuit 8, it is preferably NRZ. Therefore, the binarized data is sorted by type by the selection circuit 7, NRZI becomes the final binarized output, and NRZ becomes the input of the reproduction signal evaluation value calculation circuit 8.

  The maximum likelihood decoder 5 based on PR (1,2,1) and the maximum likelihood decoder 6 based on PR (1, -1) are input via the input terminal 2 and selected by the changeover switch 3. Switched signal is supplied. Each of the maximum likelihood decoders 5 and 6 performs different kinds of decoding processing on the input signal by selectively switching the switching piece 3a to the selected terminal 3b or 3c.

  The maximum likelihood decoder 5 based on PR (1,2,1) detects partial response (Partial Response) for recording and reproducing data in a narrow frequency band without suppressing waveform interference with respect to an input signal, and a plurality of signals. This is a combination of a decoding technique for decoding the most probable bit string from the string with maximum likelihood decoding. The maximum likelihood decoder 6 based on PR (1, -1) is a combination of similar decoding techniques, but the assumed waveform is different from (1, -1) with respect to (1,2,1).

  As described above, the maximum likelihood decoder 5 based on PR (1,2,1) generates two types of output of binarization, Non Return to Zero: NRZ and Non Return to Zero Invert: NRZI, This is supplied to the selection circuit 7. The maximum likelihood decoder 6 based on PR (1, -1) also generates two types of NRZ and NRZI and supplies them to the selection circuit 7.

  The decoder 5 based on PR (1,2,1) and the maximum likelihood decoder 6 based on PR (1, -1) generate SAMs and supply them to the reproduction signal evaluation value calculation circuit 8. .

  The selection circuit 7 selects NRZI and supplies it to a demodulator described later, and selects NRZ and supplies it to the reproduction signal evaluation value calculation circuit 8.

  The reproduction signal evaluation value calculation circuit 8 calculates a reproduction signal evaluation value for evaluating the reproduction signal based on the SAM value. A description of the SAM value is omitted.

  FIG. 18 shows a schematic configuration inside the PR (1,2,1) maximum likelihood decoder 5 according to the trellis diagram of FIG. The Viterbi decoding unit 12 that outputs the path metric difference (11), the path metric difference (00), and the binarized data, and the path metric difference (11), the path metric difference (00), and the binarized data as inputs. It has a SAM calculator 13 that calculates a SAM and outputs a SAM value and a SAM valid signal from output terminals 14 and 15. The binarized data is supplied from the output terminal 16 to a demodulator described later.

  FIG. 19 is a schematic configuration diagram of the reproduction signal evaluation value calculation circuit 8. The reproduction signal evaluation value calculation circuit 8 includes a first SAM value (from the input terminal 20) output from the maximum likelihood decoder 5 based on PR (1, 2, 1) and a first SAM valid signal (input). Terminal 22) and the second SAM value (from input terminal 21) and the second SAM valid signal (from input terminal 23) from maximum likelihood decoder 6 based on PR (1, -1). Is done.

  The first SAM value and the first SAM valid signal, and the second SAM value and the second SAM valid signal are selected from either one of the two maximum likelihood decoders 5 or 6. According to the use of the likelihood decoder, the changeover switches 26 and 29 are used to switch the connection terminals 24-28.

  The connection terminal 24 or 25 is switched and selected by the changeover switch 26, and the first SAM value or the second SAM value is supplied to the FGC mode evaluation value generation unit 30 and the AGC mode evaluation value generation unit 31. In addition, the connection terminal 27 or 28 is switched by the changeover switch 29, and the first SAM effective value or the second SAM effective value is also supplied to the FGC mode evaluation value generation unit 30 and the AGC mode evaluation value generation unit 31. . Details of generation of evaluation values in the FGC evaluation value generation unit 30 and the AGC evaluation value generation unit 31 will be described later.

  The evaluation value generated by the FGC mode evaluation value generation unit 30 and the evaluation value generated by the AGC mode evaluation value generation unit are selectively switched by the changeover switch 32 and output.

  The changeover switches 26, 27 and 32 are controlled by the change control unit 33. The reproduction signal evaluation value selected by the changeover switch 32 is fed back to the changeover control unit 33.

  20 and 21 show detailed configurations of the FGC mode evaluation value generation unit 30 and the AGC evaluation value calculation generation unit 31. FIG. First, in FIG. 20, a constant generation circuit 311 generates a minimum SAM value for an ideal reproduction signal. For example, for the Viterbi decoder according to the trellis diagram of FIG. 4, the minimum value of the SAM value for the ideal reproduction signal is 6. The SAM value output from the selection circuit 212 of the SAM calculation unit 200 via the input terminal 308 and the SAM value for the ideal reproduction signal generated by the constant generation circuit 311 are input to one and the other input terminals of the subtractor 310. The minimum value of each is input.

  The difference value obtained by subtracting the SAM value from the output value of the constant generation circuit 311 output from the subtractor 310 is squared by the square circuit 312 and supplied to the FGC averaging circuit 315. The FGC averaging circuit 315 averages the output value of the squaring circuit 312 when the enable signal supplied from the AND circuit 314 is in the “H” state. The average value of the output values of the square circuit 312 is output from the FGC averaging circuit 315 as a reproduction signal evaluation value.

  Note that the FGC averaging circuit 315 calculates an average value by averaging the output values of the square circuit 312 within a certain time or a certain number of samples.

  On the other hand, the SAM value supplied from the input terminal 308 and the output value of the constant generation circuit 311 are compared by the comparator 313. The output of the comparator 313 is input to one input terminal of the AND circuit 314. The other input terminal of the AND circuit 314 is supplied with the SAM valid signal output from the selection circuit 212 of the SAM calculation unit 200 and supplied via the input terminal 309. As a result of the comparison by the comparator 313, if (SAM value) <= (output value of the constant generation circuit 311), the output of the comparator 313 is set to the “H” state, for example.

  Therefore, if the SAM valid signal is a value (“H”) indicating that the SAM value is valid and (SAM value) <= (output value of the constant generation circuit 311), the output from the AND circuit 314 is output. The enable signal is set to the “H” state, and the output value of the square circuit 312 is averaged by the FGC averaging circuit 315.

  When the SAM value is larger than the output value of the constant generation circuit 311, the enable signal is in the “L” state, and the output value of the squaring circuit 312 is ignored. Therefore, it is not necessary to perform the square calculation correctly at this time.

  The FGC mode in the FGC mode evaluation value generation unit 30 will be described. The FGC mode is a mode for outputting the same value as the normal average by dividing the integration register value by the integration cycle. FIG. 22 is a block diagram when the bit width of the integration result is 24 bits and the bit width of the reproduction signal evaluation value is 16 bits as an example of the FGC mode. If the integration period is 256, the lower 8 bits are taken. This is equivalent to dividing by 256. When the integration cycle is 512, the lower 9 bits are taken and “0” is added to the MSB. This is to align the bit width of the output value to 16 bits. When the integration cycle is 1024, the lower 10 bits are taken and “0” is added to the MSB and 2SB. This is because the bit width of the output value is made 16 bits as in the case where the integration cycle is 512. As described above, the FGC mode is used when the reproduction signal evaluation value is desired to be fixed (Static).

  Next, the AGC evaluation value calculation unit 31 will be described with reference to FIG. A difference from the FGC evaluation value calculation unit 30 in FIG. 20 is that an AGC averaging circuit 317 is used instead of the FGC averaging circuit 315.

  The AGC mode is a mode in which an output value is obtained by shifting the priority so as to improve the calculation accuracy. Since the value entering the integration register is the square of the difference between the minimum value of the SAM value with respect to the ideal reproduction signal and the selected SAM value, it is always a positive value, and the MSB is always "0" from 2'sC. Therefore, “1” is searched in order from 2SB to the lower bit, and the bit width of the reproduction signal evaluation value is output from the found position. Since the output value is shifted to the MSB side, the influence of the lower bit value is very small. Therefore, the value of the shift width is put in the lower bit of the output so that the actual value and the shift width can be understood.

  FIG. 23 shows a specific example of the AGC mode when the integration result bit width is 24 bits, the reproduction signal evaluation value bit width is 16 bits, and the shift width is 3 bits. As described above, the AGC mode is used when it is desired to dynamically view the reproduction signal evaluation value.

  As described above, the reproduction signal evaluation value calculation circuit 8 shown in FIG. 19 uses two types of square averaging methods, that is, the FGC mode evaluation value generation unit 30 and the AGC mode evaluation value generation unit 31, and It is possible to switch by letting the user select them. When the difference in evaluation value cannot be confirmed so much in the FGC mode, it is possible to check even a small difference in evaluation value by switching to the AGC mode. Of course, in the configuration shown in FIG. 19, the reproduction signal evaluation value is returned to the switching control unit 33, and the evaluation value may be automatically switched by comparison with a predetermined threshold value.

  Next, a specific example in which the binary decoding & evaluation value calculation unit 1 of FIG. 17 is applied to a magneto-optical disk reproducing device will be described. This magneto-optical disk reproducing apparatus is a reproducing apparatus for reproducing high-density small magneto-optical disks Hi-MD1 and Hi-MD3.

  At present, a small-diameter optical disk having a diameter of about 64 mm and having a storage capacity that enables recording of, for example, a musical sound signal for 74 minutes or more has come to be widely known. This small-diameter optical disk is called a mini-disc MD (registered trademark), a read-only type in which data is recorded by pits, and a recording / reproduction in which data is recorded by a magneto-optical recording (MO) method and can be reproduced. There are two types of molds. The following description relates to a recording / reproducing small-diameter optical disk (hereinafter referred to as a magneto-optical disk). In order to increase the recording capacity of the magneto-optical disk, the track pitch, the recording wavelength of the recording laser light, the NA of the objective lens, and the like have been improved.

  As shown in FIG. 24, an initial magneto-optical disk in which groove recording is performed at a track pitch of 1.6 μm and the modulation method is EFM is referred to as a first generation MD. The physical format of the first generation MD is defined as follows. The track pitch is 1.6 μm and the bit length is 0.59 μm / bit. The laser wavelength λ is λ = 780 nm, and the aperture ratio of the optical head is NA = 0.45. As a recording system, a groove recording system that uses grooves (grooves on the disk board surface) as tracks for recording and reproduction is adopted. The address system employs a system using a wobbled groove in which a single spiral groove is formed on the disk surface and wobbles as address information are formed on both sides of the groove. In this specification, the absolute address recorded by wobbling is also referred to as ADIP (Address in Pregroove). This first generation MD employs an EFM (8-14 conversion) modulation system as a recording data modulation system. As an error correction method, ACIRC (Advanced Cross Interleave Reed-Solomon Code) is used. In addition, a convolution type is adopted for data interleaving. As a result, the data redundancy is 46.3%. The data detection method in the first generation MD is a bit-by-bit method, and CLV (Constant Linear Verocity) is adopted as the disk drive method. The linear velocity of CLV is 1.2 m / s. The standard data rate at the time of recording / reproducing is 133 kB / s, and the recording capacity is 164 MB (140 MB in MD-DATA). The minimum data rewrite unit (cluster) is composed of 36 sectors including 32 main sectors and 4 link sectors.

  Further, in recent years, a high density MD (Hi-MD1) having a higher recording capacity than the first generation MD has been developed. A conventional medium (disk or cartridge) is an MD in which the modulation method, logical structure, etc. are changed to double the user area and the recording capacity is increased to, for example, 300 MB. The physical specifications of the recording medium are the same, the track pitch is 1.6 μm, the laser wavelength λ is λ = 780 nm, and the aperture ratio of the optical head is NA = 0.45. As a recording method, a groove recording method is adopted. The address system uses ADIP. Thus, the configuration of the optical system, the ADIP address reading method, and the servo processing in the disk drive device are the same as those in the first generation MD. This high-density MD1 uses the RLL (1-7) PP modulation method (RLL: Run Length Limited, PP: Parity preserve / Prohibit rmtr (repeated minimum transition runlength)) suitable for high-density recording as the modulation method of recording data. Adopted. Further, PR (1,2,1) ML is adopted as a detection method for detecting binarized data from reproduced data. As an error correction method, an RS-LDC (Reed Solomon-Long Distance Code) method with a BIS (Burst Indicator Subcode) with higher correction capability is used.

  Furthermore, as the high-density MD, the high-density MD3 (Hi-MD3), which has a higher recording capacity than the high-density MD1, reduces the track pitch to 1.25 μm while maintaining the compatibility of the outer shape and the optical system. The recording mark was developed from the groove by detecting a recording mark by domain wall displacement detection (DWDD). This high-density MD3 uses the RLL (1-7) PP modulation method (RLL: Run Length Limited, PP: Parity preserve / Prohibit rmtr (repeated minimum transition runlength)) suitable for high-density recording as the modulation method of recording data. Adopted. As an error correction method, an RS-LDC (Reed Solomon-Long Distance Code) method with a BIS (Burst Indicator Subcode) with higher correction capability is used. Data interleaving is a block-complete type. As a result, the data redundancy becomes 20.50%. As a data detection method, a Viterbi decoding method based on PR (1, -1) ML is used. A cluster which is the minimum data rewrite unit is composed of 16 sectors and 64 kB. A ZCAV system is used as the disk drive system, and the linear velocity is 2.0 m / s. The standard data rate at the time of recording / reproducing is 9.8 MB / s. Therefore, in the high-density MD3, the total recording capacity can be reduced to 1 GB by adopting the DWDD method and this driving method.

  FIG. 25 shows a magneto-optical disk reproducing apparatus 40 for reproducing high-density small magneto-optical disks Hi-MD1 and Hi-MD3. The magneto-optical disk reproducing device 40 discriminates the disc type by the disc discrimination technique disclosed in WO 03/088228 by the applicant. This disc discrimination technology is a laser beam while moving an objective lens or an optical block (optical pickup) from an inner circumference side to an outer circumference side at a constant speed to, for example, a high-density MD-1 or high-density MD-3 that is rotationally driven. The type of each disk is determined by detecting the tracking error signal of the light and the total light quantity signal from the reflected light of the wobbled groove obtained with the focus on, and comparing the phases. The optical disc type is determined by comparing the phase of the binarized signal of the tracking error signal detected by the tracking error detecting means and the binarized signal of the total light quantity signal detected by the total light quantity signal detecting means. is there.

  In the magneto-optical disk reproducing device 40, a loaded disk 41 (high density MD1 or high density MD3) is rotationally driven by a spindle motor 42 in a CLV system or a ZCAV system. During reproduction, the disk 41 is irradiated with laser light from the optical head 43.

  At the time of reproduction, the optical head 43 performs a relatively low level laser output for detecting data from reflected light by the magnetic Kerr effect. For this reason, the optical head 43 is equipped with a laser diode as a laser output means, an optical system including a polarization beam splitter, an objective lens, and the like, and a detector for detecting reflected light. The objective lens provided in the optical head 43 is held so as to be displaceable in the radial direction of the disk and in the direction of contacting and separating from the disk, for example, by a biaxial mechanism. The optical head 43 is provided with a photodetector PD that supplies a light reception signal A and a light reception signal B to a built-in optical disc discrimination device. The objective lens or the entire optical head 43 is moved from the inner periphery to the outer periphery at a constant speed, which is necessary to determine the traveling direction when discriminating the optical disk. The received light signals A and B can be detected at a speed that overcomes the amount of movement due to eccentricity.

  Although not shown, a sled motor and a sled mechanism are provided for moving the entire optical head 43 in the disk radial direction. The sled motor and sled mechanism move the optical head 43 from the inner circumference to the outer circumference when the built-in optical disc discrimination device discriminates the optical disc.

  In the magneto-optical disk reproducing device 40, a reproducing processing system, a servo system, and the like are provided in addition to the reproducing head system by the optical head 43 and the disk rotation driving system by the spindle motor.

  As a reproduction processing system, a PR (1,2,1) ML decoder and PR (1, -1) corresponding to RLL (1-7) PP modulation when reproducing high-density MD-1 and high-density MD-3 A decoder, an RLL (1-7) demodulator that demodulates data decoded by these decoders (decoding in this case is binarized), and a circuit unit that performs RS-LDC decoding as error correction processing Provided.

  Information detected as reflected light by the laser irradiation of the optical head 43 on the disk 41 (photocurrent obtained by detecting the laser reflected light with a photodetector) is supplied to the RF amplifier 44. The RF amplifier 44 performs current-voltage conversion, amplification, matrix calculation, and the like on the input detection information, and performs reproduction RF signal, tracking error signal TE, focus error signal FE, groove information (on the disc 41) as reproduction information. (ADIP information recorded by track wobbling) and the like are extracted.

  When reproducing the high density MD-1 or high density MD-3, the reproduction RF signal obtained by the RF amplifier 44 is converted into an A / D conversion circuit 45, an equalizer 46, a digital PLL circuit 47, a changeover switch 3, PR (1, 2, a maximum likelihood decoder 5 based on 2) or a maximum likelihood decoder 6 based on PR (1, -1), a selection circuit 7, an RLL (1-7) PP demodulator 48 and an RS-LDC decoder 49. The signal is processed and output from the output terminal 50. The binarized data in the maximum likelihood decoder 5 based on PR (1,2,1) or the maximum likelihood decoder 6 based on PR (1, -1) is binarized as shown in FIG. Evaluation is performed by the decoding & evaluation value calculation unit 1. In FIG. 25, the reproduction signal evaluation apparatus 1 using one reproduction signal evaluation value calculation circuit 8 is inserted between the DPLL 47 and the RLL (1-7) PP demodulation unit 48. The reproduction signal evaluation value calculated by the reproduction signal evaluation value calculation circuit 8 is supplied to the controller 55. The evaluation method of the reproduction signal is as described above, and the description is omitted here.

  The reproduction data NRZ from the decoder 5 or 6 selected according to the use of Hi-MD1 or Hi-MD3 in the selection circuit 7 is PR (1,2,1) ML or PR (1, − It was obtained as an RLL (1-7) code string by data detection using 1) and Viterbi decoding. The RLL (1-7) PP demodulator 48 performs RLL (1-7) demodulation processing on this RLL (1-7) code string. Further, the RS-LDC decoder 49 performs error correction and deinterleave processing. At this time, the RS-LDC decoder 49 detects whether or not there is an unreadable error in the block unit data to be read from the reproduction data (compressed data) from any of the high-density disks 41. The error detection result by the RS-LDC decoder 49 is supplied to the controller 55.

  When the controller 55 detects an unreadable error in the block unit data that the playback device tried to read during playback of the high-density MD-1 or high-density MD-3, In a short predetermined time, for example, the audio signal is muted through an audio decoder in a personal computer.

  The tracking error signal TE and the focus error signal FE output from the RF amplifier 44 are supplied to the servo circuit 53, and the groove information is supplied to the ADIP decoder 51.

  The ADIP decoder 51 extracts the wobble component by band-limiting the groove information with a band pass filter, and then performs FM demodulation and biphase demodulation to extract the ADIP address. The extracted ADIP address, which is absolute address information on the disk, is supplied to the address decoder 52. The address decoder 52 includes a Hi-MD1 address decoder unit 52a and a Hi-MD3 address decoder unit 52b. In the case of Hi-MD1, it is supplied to the controller 55 via the Hi-MD1 address decoder unit 52a, and in the case of Hi-MD3, it is supplied to the controller 55 via the Hi-MD3 address decoder unit 52b.

  The controller 55 executes predetermined control processing based on each ADIP address. The groove information is returned to the servo circuit 53 for spindle servo control.

  For example, the servo circuit 53 is based on an error signal obtained by integrating a phase error with the reproduction clock (PLL clock at the time of decoding) with respect to the groove information, and a spindle error for the CLV servo control and the above-described ZCAV servo control. Generate a signal.

  The servo circuit 53 performs various servo control signals (tracking signals) based on the spindle error signal, the tracking error signal supplied from the RF amplifier 44 as described above, the focus error signal, the track jump command from the controller 55, the access command, or the like. Control signal, focus control signal, thread control signal, spindle control signal, etc.) are generated and output to the motor driver 54. That is, various servo control signals are generated by performing necessary processing such as phase compensation processing, gain processing, and target value setting processing on the servo error signal and command.

  The motor driver 54 generates a predetermined servo drive signal based on the servo control signal supplied from the servo circuit 53. The servo drive signal here includes a biaxial drive signal for driving the biaxial mechanism (two types of focus direction and tracking direction), a sled motor drive signal for driving the sled mechanism, and a spindle motor drive signal for driving the spindle motor 42. It becomes. By such servo drive signals, focus control and tracking control for the disk 41 and CLV control or ZCAV control for the spindle motor 21 are performed.

  Based on the reproduction signal evaluation value calculated by the reproduction signal evaluation value calculation circuit 8, the controller 55 sends a control signal to the servo circuit 53 so that, for example, the reproduction laser power by the optical head 43 is optimized.

  FIG. 26 is a characteristic diagram showing the relationship between the reproduced signal evaluation value and the bit error rate (BER) for Hi-MD1. FIG. 27 is a characteristic diagram showing the relationship between the reproduction signal evaluation value and the bit error rate for Hi-MD3. In both cases, the horizontal axis represents the reproduction signal evaluation value, and the vertical axis represents BER. In the case of Hi-MD1, the reproduction signal evaluation value is 600 to 1250 and the BER is 1.E-02 to 1.E-01, whereas in the case of Hi-MD3, the reproduction signal evaluation value is 170 to 400. The BER is from 1.E-04 to 1.E-01. It can be seen that the smaller the reproduction signal evaluation value, the better the BER and the change in a substantially linear manner.

  FIG. 28 is a characteristic diagram of the reproduction signal evaluation value (horizontal axis) and the occurrence frequency (vertical axis) showing the variation between Hi-MD1 and Hi-MD3. The occurrence frequency on the vertical axis is the number of occurrences of the reproduction signal evaluation value (value itself). It shows the variation when the integration cycle when taking the average in the reproduction signal evaluation value calculation circuit is changed. The integration cycle is 256, 512, 1024. In the case of Hi-MD1, it can be seen that the characteristics are improved as the integration period becomes longer as 256, 512, and 1024. The average reproduction signal evaluation value is 562, which is 2.7E-3. Similarly, in the case of Hi-MD3, it can be seen that the characteristics are improved as the integration period becomes 256, 512, and 1024. The average reproduction signal evaluation value is 243.44, which is 2.0E-3.

  In other words, if the integration period is long (1024), the frequency of occurrence of the central reproduction signal evaluation value increases, the frequency of occurrence of the base reproduction signal evaluation value decreases, and the variation of the reproduction signal evaluation value decreases. Conversely, if the integration cycle is short (256), the frequency of occurrence of the central playback signal evaluation value is less than when the integration cycle is long, and the frequency of occurrence of the base playback signal evaluation value is when the integration cycle is long. Compared to this, the variation in the evaluation value of the reproduction signal becomes large. That is, in both Hi-MD1 and Hi-MD3, if the integration cycle is lengthened, the variation is reduced. Conversely, when the integration period is short, the variation increases. However, the shorter the integration cycle, the shorter the total time. It is possible to select whether to give priority to time or variation.

  Next, FIG. 29 is a configuration diagram of the binarized decoding & evaluation value calculation unit 61 in the reproducing apparatus using a plurality of m kinds of maximum likelihood decoders.

  For example, the PR (1,2,1) maximum likelihood decoder 64 of the integration system, the PR (1, -1) maximum likelihood decoder 65 of the differentiation system, and the differential system PR4 [PR (1,0, -1)] Shown is a case where the maximum likelihood decoder 66 is designed according to conditions so as to exhibit the most ability among the m ways. Similarly to the above, up to the SAM value is calculated by each maximum likelihood decoder 64, 65... 66, and statistical processing is performed by the same circuit (reproduced signal evaluation value calculation circuit 68). As a result, the number of reproduction signal evaluation value calculation circuits of “(the number of maximum likelihood decoders) −1” can be omitted. In addition, since one or more maximum likelihood decoders are used, there are cases where there are two types of binarization outputs, Non Return to Zero: NRZ and Non Return to Zero Invert: NRZI. As the subsequent processing, the binarized data is preferably NRZI, but in the reproduction signal evaluation value calculation circuit 68, it is preferably NRZ. Therefore, the binarized data is sorted by type by the selection circuit 67, NRZI becomes the final binarized output, and NRZ becomes the input of the reproduction signal evaluation value calculation circuit 68.

  The above-described binarization decoding & evaluation value calculation unit is not limited to the application only to the magneto-optical disk reproducing device. For example, the binarized decoding & evaluation value calculating unit is a device that binarizes a reproduction signal read from a hard disk drive or other media. Of course, is also applicable.

  Further, the evaluation value for evaluating the reproduction signal of the maximum likelihood decoder is not limited to the SAM value, and may be, for example, jitter. Desirably, an evaluation value having a high correlation with the error rate is good.

1 is a configuration diagram of a magneto-optical disk reproducing apparatus to which an automatic equalizer of the present invention is applied. FIG. It is a circuit diagram of a 3-tap FIR type digital filter. It is a circuit diagram of a 5-tap FIR type digital filter. It is a trellis diagram corresponding to the combination of RLL (1,7) and PR (1,2,1). It is a detailed block diagram of a Viterbi decoding part. It is a figure which shows the example of an output of a SAM value. It is a block diagram of an example of a SAM calculation part. It is a schematic block diagram of a reproduction signal evaluation value calculation circuit. It is a transition diagram of the automatic equalization which an automatic equalizer performs. It is a figure which shows changing a coefficient with P1-> P2-> P3-> P4 according to trace order. It is a figure which shows rotating the trace alternately with the forward direction and the reverse direction. It is the figure which showed the SAM value on the C1 and C2 plane by the contour map (line division). It is a figure which shows the process sequence of the automatic equalization operation | movement in an automatic equalizer. It is a figure for demonstrating search operation when a search point is made into 7 points | pieces, for example. It is a figure for demonstrating the operation | movement of a wobble. It is a comparison figure of the error rate of a fixed / automatic equalization equalizer. It is a block diagram of a binarization decoding & evaluation value calculation part. It is a block diagram of a maximum likelihood decoding part. It is a block diagram of a reproduction signal evaluation value calculation circuit. It is a block diagram of a FGC mode evaluation value production | generation part. It is a block diagram of an AGC mode evaluation value generation unit. It is a figure for demonstrating FGC mode. It is a figure for demonstrating AGC mode. It is a figure for demonstrating the specification of 1st generation MD and two types of high density MD. It is a block diagram of a magneto-optical disk reproducing apparatus. It is a characteristic view which shows the relationship between the reproduction signal evaluation value regarding Hi-MD1, and a bit error rate (BER). It is a characteristic view which shows the relationship between the reproduction signal evaluation value regarding Hi-MD3, and a bit error rate (BER). It is a characteristic view of the reproduction signal evaluation value and the occurrence frequency showing the variation between Hi-MD1 and Hi-MD3. It is a block diagram of the reproduction | regeneration signal evaluation apparatus 61 in the reproducing | regenerating apparatus using several m kinds of maximum likelihood decoders mutually different.

Explanation of symbols

  71 magneto-optical disk reproducing device, 74 automatic equalizer, 75 equalizer (equalizer), 76 maximum likelihood decoder, 77 SAM value calculation unit, 78 evaluation value calculation unit, 79 control unit, 80 setting unit, 81 variable unit , 82 DPLL

Claims (4)

An equalizer having at least two parameters that can be variably set;
Binarizing means for decoding the reproduced signal output from the equalizer by maximum likelihood decoding processing and detecting binarized data;
Reproduction signal evaluation value calculation means for calculating an evaluation value for evaluating the binarized data detected by the binarization means;
An automatic equalizer comprising: control means for setting the at least two parameters of the equalizer based on the evaluation value of the reproduction signal calculated by the reproduction signal evaluation value calculation means.   SAM value calculating means for calculating in real time a sequence amplitude margin (SAM) value of the binarized data detected by the binarizing means, and the reproduction signal evaluation value calculating means is calculated by the SAM value calculating means. The automatic equalizer according to claim 1, wherein an evaluation value of the reproduction signal is calculated based on the SAM value. A binarization step of decoding binarized data by decoding a reproduction signal output from an equalizer having at least two variably settable parameters by a maximum likelihood decoding process;
A reproduction signal evaluation value calculating step for calculating an evaluation value for evaluating the binarized data detected by the binarization step;
An automatic equalization method comprising: a setting step of setting the at least two parameters of the equalizer based on the evaluation value of the reproduction signal calculated by the reproduction signal evaluation value calculation step. In a reproducing apparatus for reproducing a signal recorded on a recording medium and binarizing the reproduced signal,
Reading means for reading the signal recorded on the recording medium;
An equalizer that performs equalization processing on at least two parameters that can be variably set with respect to the signal read from the recording medium by the reading means;
Binarizing means for decoding the reproduced signal output from the equalizer by maximum likelihood decoding processing and detecting binarized data;
Reproduction signal evaluation value calculation means for calculating an evaluation value for evaluating the binarized data detected by the binarization means;
And a control means for setting the at least two parameters of the equalizer based on the evaluation value of the reproduction signal calculated by the reproduction signal evaluation value calculation means.

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