JP2009110656A - Method of evaluating readout signal and optical disc apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of evaluating the quality of a read signal from the viewpoint of detection margin of a Viterbi decoder in a PRML method in which a target level varies depending on a read signal, and an optical disc apparatus implementing the method. <P>SOLUTION: From the target signal level that varies depending on the read signal, a target signal is generated based on a decoding result, and an error target signal is generated in which the decoding result and a decoding result edge-shifted. Thus, the signal quality is evaluated by calculating a Euclidean distance between these signals and the read signal. A virtual state that is not included in the Viterbi decoder and that is less than the minimum run length is defined, and a target signal level for the virtual state is generated using a target signal level table inside the Viterbi decoder, base on the concept of convolution. Thus, the signal quality can be evaluated by the same method even when the pattern of a combination of the minimum run lengths has edge-shifted. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an optical disc apparatus for recording information by forming a recording mark having a physical property different from that of other portions on a recording medium.

  PRML (Partial Response Maximum Likelihood) playback signal processing method has become an indispensable technology as the speed and density of optical discs increase. As one of the PRML systems, there is an adaptive PRML system or a compensated PRML system that adaptively changes a target signal level according to a reproduction signal. According to “Tech. Digest ISOM'03, pp. 34”, the PRML system is used to compensate for the asymmetry of the playback signal and the thermal interference during recording. It has been shown that considerable densification is feasible.

  It is important to properly learn (1) playback equalization conditions, (2) focus position and tilt conditions, and (3) recording power and pulse conditions, etc., in the optical disk apparatus using PRML devices as in the past. It is. In such a case, it is necessary to optimize various parameters so as to make this the best condition using an evaluation index of the reproduction signal quality. Conventionally, when the direct slice reproduction method is used, jitter is used as an evaluation index of reproduction signal quality. “Tech. Digest ODS'03, pp.93” and “Tech. Digest ISOM '03, pp.116” are PR (1,2,2,1) as evaluation indexes of playback signal quality corresponding to the PRML system. MLSE (Maximum Likelihood Sequence Error) is shown corresponding to the ML channel. The decoded signal is evaluated from the viewpoint of error probability by calculating the reproduced signal and the Euclidean distance between the two by using the decoding result positive bit string and the erroneous bit string shifted by 1 bit. In addition, since MLSE focuses on data edges, the MLSE value target for each element of the table corresponds to a recording strategy that uses an adaptive recording pulse condition tabulated by preceding and following space lengths and mark lengths. It is shown that the recording strategy can be optimized by measuring and evaluating the deviation from the value. In “Tech. Digest ISOM '03, pp. 164”, PRSNR (Partial Response Signal to Noise Ratio) is shown corresponding to the PR (1, 2, 2, 2, 1) ML channel. This is because the PR (1,2,2,2,1) channel extracts three patterns with low Euclidean distance and high error frequency, and calculates each Euclidean distance value from the viewpoint of error probability. This is to calculate the reproduction signal SNR and evaluate the signal quality, and it is shown that there is an excellent correlation between the PRSNR and the bit error rate.

Here, in order to deepen the understanding of the invention about the erroneous detection evaluation of the PRML method, explanation will be added.
FIG. 2 shows a part of bit error patterns in the case of decoding using the PR (1,2,2,1) class in the RLL (1,7) code. In this case, since the number of bits representing a class (hereinafter referred to as class bit number N) is 4, in order to consider the effect of a 1-bit error, a 7-bit (2N-1) pattern may be considered. At this time, patterns with different center bits in the correct pattern are called erroneous patterns, and when the conditions in which the correct pattern and the erroneous pattern satisfy the run length restriction are extracted, as shown in the figure, there are 8 combinations of patterns for 1-bit error. There are streets. A value obtained by adding the square value of the difference between the target signal levels of the correct pattern and the incorrect pattern for each time is called the Euclidean distance between the two, and in the case of 1-bit error, (1 ² +2 ² +2 ² +1 ² = 14) 14 When normalized so that the amplitude of the target signal is 2, the Euclidean distance is 1.11. The Euclidean distance is the distance between two points in the space where the transition of the target value with respect to the two-bit pattern according to the time is regarded as an M-dimensional (M = 4 in this case) vector and these vectors are used as position vectors. You can also. Similarly, there are 12 types of 2-bit errors, and the Euclidean distance is 14. Similarly, when considering more complicated error patterns, the Euclidean distance continues infinitely as 16, 18, 20, 22,. Statistically, all these pattern errors will occur. However, in order to evaluate the signal quality including all these error patterns, enormous processing is required, and it cannot be mounted on an optical disk drive. Here, since the Euclidean distance is the distance between the positive pattern and the erroneous pattern, it can be considered as an index indicating the difficulty of error occurrence. In fact, in the range in which error correction is possible, for example, in the range where the bit error rate is about 10 ⁻⁴ or less, errors in the pattern of the minimum Euclidean distance are dominant. Therefore, it can be said that evaluating only the pattern of the minimum Euclidean distance is sufficient for evaluating the signal quality. MLSE measures the error probability distribution at each location, focusing only on the minimum Euclidean distance pattern, and PR (1,2,2,1) with only 1T edge shift. The deviation is evaluated.

  Similarly, the error patterns and Euclidean distances for PR (1,2,1,2) and PR (1,2,2,2,1) corresponding to the RLL (1,7) code are respectively shown in the figure. 3 and FIG.

  FIG. 3 summarizes the error pattern and Euclidean distance of PR (1,2,1). As shown in the figure, the pattern of the minimum Euclidean distance is also 1T edge shift, and the Euclidean distance is 6. This can be evaluated by MLSE as well as PR (1,2,2,1).

  FIG. 4 summarizes the PR (1,2,2,2,1) error pattern and Euclidean distance. As shown in the figure, the Euclidean distance for a 1-bit error is 14, whereas the Euclidean distance is 12 for a 2-bit and 3-bit error pattern. In this case, it is considered that MLSE, which evaluates only 1T shift errors, cannot perform accurate signal quality evaluation. Therefore, “Tech. Digest ISOM'03 pp.164” quantifies the error-proneness of these three patterns from the viewpoint of S / N, and among them, the one with the smallest S / N and the most prone to error. It is used to evaluate signal quality. This is the PRSNR described above.

  FIG. 5 summarizes a part of bit error patterns in the case of decoding using the generally used PR (1,1,1,1) class in the RLL (1,7) code. In this case, since the class bit number N is 4, as in the case of the PR (1, 2, 2, 1) class, a 7-bit pattern may be considered in order to consider the effect of a 1-bit error. As shown in the figure, there are 8 combinations of patterns for 1-bit errors, and the Euclidean distance is 4. There are 18 cases in which a 2-bit error occurs for a 10-bit pattern, and the Euclidean distance is 4. Similarly, when considering more complicated error patterns, the Euclidean distance continues infinitely as 6, 10, ..., respectively. In this case, the minimum Euclidean distance pattern needs to consider not only 1-bit errors but also 2-bit errors.

Tech. Digest ISOM '03, pp.34 Tech. Digest ODS'03, pp.93 Tech. Digest ISOM '03 pp.116 Tech. Digest ISOM '03 pp.164

  As described above, the adaptive PRML or compensated PRML system that adaptively changes the target signal level according to the reproduction signal has a great effect on improving the reproduction performance. On the other hand, both MLSE and PRSNR shown above depend on the PR class, such as PR (1,2,2,1) and PR (1,2,2,2,1), and The target signal level corresponds to a fixed PRML channel.

  From the viewpoint of optimizing the recording strategy, MLSE is an excellent method for evaluating the playback signal by decomposing it into tables according to the mark length and space length, but MLSE is one of the PRML decoders. Since it is based on the probability of bit shift error, the data pattern cannot be evaluated from the minimum run length space and the minimum run length mark as shown in the above-mentioned document. Taking the conventional direct slice method as an example, the repetitive data pattern with the minimum run length has the smallest S / N and is prone to error. Also, from the viewpoint of recording control, since the data pattern is a pattern in which the thermal interference from the adjacent mark is maximized, the recording pulse condition must be well controlled. As described above, from the viewpoint of recording / reproduction, a data pattern composed of a combination of minimum run lengths is an important data pattern. Therefore, a signal evaluation index that can evaluate this is desired.

The problems to be solved by the present invention are the following two points.
(Problem 1) To provide an evaluation index of a reproduction signal corresponding to a PRML channel whose target signal level adaptively changes according to the reproduction signal, and an optical disc apparatus using the evaluation index.
(Problem 2) Providing an evaluation index of a reproduction signal corresponding to a combination data pattern of minimum run length and an optical disc apparatus using the evaluation index.

First, means for solving (Problem 1) will be described.
The reason why MLSE cannot support a variable target level is that the generation of the target signal corresponding to the correct bit sequence that is the decoding result and the erroneous bit sequence shifted by 1 bit, and the calculation of the Euclidean distance from the playback signal are based on the fixed target level. Because. Therefore, if the generation of the target signal and the calculation of the Euclidean distance are enabled with reference to the target level that adaptively changes according to the reproduction signal, the problem is solved. The former can be realized by taking out a bit string constituting a target level from a correct / incorrect bit string and sequentially loading a corresponding target signal level from the target signal level table. If a target signal corresponding to a variable target level can be generated, the latter calculation of the Euclidean distance can be obtained by adding the square value of the difference between the reproduction signal and the target signal at each time. According to the definition of MLSE, the difference between these two Euclidean distances needs to be normalized with the reference Euclidean distance. Here, the reference Euclidean distance can be calculated by calculating an average value corresponding to the changing target level, or by calculating the Euclidean distance of the target signal generated from the correct / incorrect bit string. The former is superior in terms of reducing the amount of computation.

  Here, the direction of edge shift will be described. Since the Euclidean distance is always a positive value, it has no sign. However, the direction of the edge shift changed from the correct pattern to the incorrect pattern can be uniquely determined for each pattern.

  FIG. 6 summarizes the direction of the edge shift with respect to the minimum Euclidean distance pattern of PR (1,2,2,1). For example, when “0001110” becomes “0000110”, it is understood that the front edge of the 3T mark is shifted to the right. On the contrary, when the reproduction data is an erroneous pattern “0000110” in the figure, the shift direction is left. Similarly, the direction of edge shift can be defined for all patterns. Therefore, for example, by defining that the Euclidean distance is “+” when the shift direction is right and the Euclidean distance is “−” when the shift direction is left, the definition of MLSE is extended to define the edge shift. It can be improved so that direction information can be evaluated. Here, according to convention, bit “1” represents a mark. If “0” represents a mark depending on the configuration of the decoder, the shift direction may be redefined.

Hereinafter, the new signal evaluation index shown here will be called S-SEAT (Signed-Sequenced Error for Adaptive Target). The definition of S-SEAT is shown below.
The Euclidean distance between two bit patterns "pat1" and "pat2" by definition and the ED _B (pat1, pat2), is expressed by the following equation.

Here, V _target [B] represents a target signal level for bit string B, pat [n] represents a bit string at time n of bit pattern “pat”, and N represents the number of class bits.
The standard Euclidean distance for normalizing the evaluation index is defined as the average value of the Euclidean distance for the 1-bit error pattern as follows.

Here, M represents the total number of combinations of 1-bit error patterns, and Pat _T and Pat _F represent a positive bit pattern and an erroneous bit pattern, respectively.
The Euclidean distance ED (pat) between the reproduction signal and the designated bit pattern “pat” is expressed by the following equation.

Here, V _signal [t] is the reproduction signal level at time t, and the binarization result at time t is the bit pattern “pat”.
The value of S-SEAT is obtained as follows as an edge shift value D corresponding to PRML and its standard deviation σ.

Here, Sign (Shift-Direction) represents the edge shift direction when the binarization result Pat _T becomes 1 bit error (edge shift) and becomes Pat _F , and P is within the specified calculation period. Represents the number of bit patterns. The definition of the sign in (Equation D-5) may seem strange because it is different from the natural definition that it is negative for the right edge shift and positive for the left edge shift. Because there is no, add explanation. In (Equation D-4), the term (ED (Pat _F [m])-ED (Pat _T [m])) is derived from (Euclidean distance between the reproduced signal and the erroneous bit pattern), This is a difference value of the Euclidean distance. This value is usually a positive value because the positive bit pattern has been decoded. When the reproduction signal completely matches the target signal of the positive bit pattern, the difference value of the Euclidean distance becomes the reference Euclidean distance _dmin . On the other hand, when this value is zero, the reproduction signal is decoded into a positive bit pattern and an erroneous bit pattern with a probability of 1/2. On the other hand, in the conventional direct slice method, the shift amount between the edge position of the reproduction signal and the edge position of the clock signal is called an edge shift amount. When the edge shift amount in the direct slicing method is ½ of the detection window width (clock signal period), the reproduced signal is binarized with a probability of ½. From these comparisons, as shown by the following equation, when a value Do obtained by subtracting the reference Euclidean distance d _min from the difference value of the Euclidean distance is introduced, this is an amount equivalent to the edge shift amount in the direct slice method. It can be seen that it can be treated as an edge shift in the PRML method.

  Up to this point, the basic concept of the MLSE value described above has been followed. As described above, when the reproduction signal approaches the target signal of the erroneous bit pattern, the Do value becomes a negative value without depending on the edge shift direction. Therefore, it is necessary to devise in order to make the edge shift direction coincide with the physical shift direction of the mark formed on the disk. The direction of edge shift can be uniquely determined by comparing correct and incorrect bit patterns. Therefore, in the present invention, the edge shift direction is determined from the correct / incorrect bit pattern, and the value obtained by multiplying the Do value by +1 or −1 corresponding to the shift direction as shown in (Equation D-5) is the edge shift value. D. According to (Equation D-5), the D value is positive when the edge shift direction is right, and the D value is negative when it is left. By doing so, the physical shift direction of the mark formed on the disc can be matched with the sign of the edge shift value D corresponding to the PRML method. Here, the D value is defined to be positive when the shift direction is the right side, but the opposite direction can also be defined. In that case, the sign of (Equation D-5) may be reversed. In the direct slice method, the RMS value of the edge shift amount at each edge is called a jitter value and is used as a representative evaluation index of signal quality. Also in the present invention, the S-SEAT value is an RMS value of the edge shift amount D corresponding to the PRML method. This corresponds to the jitter value in the PRML method.

Now, the evaluation index of the present invention can be expanded according to the situation. The specific expansion method is shown below.
As will be described in detail later, in the PRML channel in which the target signal level adaptively changes according to the reproduction signal, the Euclidean distance between the reproduction signal and the target signal is calculated as the reproduction signal at each time in order to prevent an increase in circuit scale. It is effective to calculate the sum of absolute values, not the sum of the squares of the target signal level differences. Hereinafter, such a PRML channel is called an absolute value system. Since the object of the present invention is to provide an evaluation index of a reproduction signal in conformity with PRML, it is better to calculate the Euclidean distance as the sum of absolute values of level differences in the PRML channel of the absolute value system. For this purpose, instead of (Equation D-1) and (Equation D-3), the Euclidean distance is used as the sum of the absolute values of the differences at each time, and the following (Equation D-7) and (D- Calculate in 8).

Also, instead of (Equation D-2), the instantaneous value of the Euclidean distance in the pattern represented by the following (Equation D-9) can be used as the reference Euclidean distance _dmin .

Here, ED _B is or (wherein D-1), shall be calculated by (Formula D-7).
When using (Equation D-7) and (Equation D-8), the PRML channel where the target signal level changes adaptively according to the playback signal, the Euclidean distance depends on the pattern, or the sensitivity of the medium is uneven. When the signal amplitude or asymmetry value changes with time, there is a merit that a more accurate evaluation value at that time can be obtained. However, it is necessary to pay attention to the demerit that the power consumption increases because the number of blocks that operate at high speed increases when the circuit is made into an LSI or the like. In the case of a PRML channel with a fixed target signal level, the reference Euclidean distance d _min is also a fixed value, so there is no need to calculate the d _min value using (Equation D-2) or (Equation D-7). A constant may be used after calculation.

  Next, calculation of an evaluation value for one edge will be considered. For the MLSE calculation method using the PR (1,2,2,1) ML class for the RLL (1,7) code, refer to Reference 2 (Tech. Digest ODS'03, pp.93). And Reference 3 (Tech. Digest ISOM '03 pp.116). From Figure 1 and Table 2 in Reference 3, two correct and incorrect patterns (in the literature, P2B / P2A) are also applied to edges consisting of combinations of marks and spaces longer than 5T (T is the detection window width). And the evaluation value of the edge shift described above (indicated by MD in the literature) from the combination of P7B / P7A). Specific calculation system blocks and patterns are described in FIG. The 7-bit bit strings shown as Path A and Path B in Table 1 of Document 2 correspond to P1A / P1B, P2A / P2B,. Here, pay attention to P2A (bit string “1110000”) and P2B (bit string “1111000”). This shows the trailing edge of a mark of a pattern having a subsequent space length of 4T or more and a mark length of 4T or more. In the RLL (1,7) code, the longest mark and space length are 8T. Therefore, let us consider the trailing edge of a pattern with a subsequent space length of 8T and a mark length of 8T based on the block diagram in Figure 1 of Reference 2.

  FIG. 59 shows the pattern / detector determination status and evaluation value calculation operation for time t. As shown in the figure, at the two times t = 4 and t = 5, the pattern detector detects P2B and P2A, respectively, so that the MD value is calculated twice. Such cases occur in combinations of marks and spaces longer than 5T, as can be seen easily from Fig. 59 and Table 2 of Reference 3. More generally, this occurs when the number of PRML class bits (constraint length) is N and a combination of a mark and a space having a length of (N + 1) T or more. It is not natural to calculate the shift amount twice for one mark edge physically. In order to avoid this, it is only necessary to store that the calculation of the MD value is executed at t = 4 and not to execute the calculation at t = 5. In the PRML system with a fixed target signal level such as PR (1,2,2,1) ML, the calculated value at t = 4 and the calculated value at t = 5 are the same value, so the evaluation value is calculated twice. It is enough to limit it to one time. Actually, the occurrence frequency of 5T or more mark and space combination patterns in the RLL (1,7) code is low, so the effect of the two-time calculation is small, and the problem is less likely to occur when the MLSE value is used for signal evaluation in practice.

  Next, we consider an adaptive PRML system that adaptively changes the target signal level according to the playback signal. As described in Reference 2, the definition of MLSE does not include the edge shift direction. On the other hand, in the present invention, the direction of edge shift D can be detected as shown in (Equation D-5). When calculating the edge shift D in FIG. 59, the case where the edge shift direction is left at t = 4 is evaluated, and the case where the edge shift is right at t = 5 is evaluated. When the respective values are DL and DR, generally DL and DR are approximately equal. On the other hand, when the reference Euclidean distance is calculated according to (Equation D-8), the target signal level changes from moment to moment, so DL ≠ DR. In this case, in order to avoid the calculation twice, it is not sufficient to restrict the calculation not to be performed at t = 5 if the calculation is performed at t = 4 as in the method shown above. However, in practice, the difference between the absolute values of DL and DR may be considered to be small. For example, in the case of RLL (1,7) code, if the number of class bits N is 4 or more, the frequency of occurrence of two calculations Is small. Based on these assumptions, if simplification of the circuit configuration or importance of definition compatibility with MLSE, DL and DR should be added according to (Equation D-6) in the calculation of the S-SEAT value. .

  On the other hand, when the RLL (2,10) code is used as in DVD and CD, or when the number of class bits is 3 or less, the influence of the calculation twice becomes large. In addition, when using codes with minimum run length of 2T or more, such as RLL (1,7) code and RLL (2,10) code, V-SEAT introducing virtual states as shown below (details will be described later) In this case, calculation is performed twice for all the edges.

Next, a method for calculating only one shift amount for one physical edge while avoiding the calculation twice in S-SEAT and V-SEAT will be described. There are three methods as shown below.
(1) When both the evaluation values DL and DR for the left and right edge shifts can be calculated as the shift amount D of one edge of interest instead of (Equation D-4), the following (Equation D-10 When using the average shift amount represented by).

This is the most natural definition.

(2) When both the evaluation values DL and DR for the left and right edge shifts can be calculated as the shift amount D of one edge of interest instead of (Equation D-4), the following (Equation D-11 ) When using the shift amount with the smaller absolute value as shown by).

  Since errors always accompany measurement, for example, in cases where there is a relatively large amount of spike noise such as clock leakage in a drive device, it is effective to select a device with a small absolute value in this way. .

(3) When both the evaluation values DL and DR for the left and right edge shifts can be calculated as the shift amount D of one edge of interest instead of (Equation D-4), the following (Equation D-12 ) When using the shift amount with the larger absolute value as represented by).

  Although details will be described later, in the PRML channel of the absolute value system, the Do value shown in (Supplemental expression-1) can only be zero or negative. This is a feature of the absolute value PRML channel. Depending on this feature, either DL or DR may become zero. In order to avoid this, it is effective to select the larger absolute value. This is a definition that includes selecting the other when either is zero.

Next, means for solving (Problem 2) will be described.
FIG. 7 summarizes the target signal levels of the PR (1,2,2,1) ML decoder corresponding to the RLL (1,7) code. In this case, since the number of bits representing the PR class is 4, the target signal level is defined corresponding to 2 ⁴ (= 16) combinations of bit strings. At this time, the bit length including 1T-length bits is removed due to the run length limitation, and the number of valid bit sequences becomes 10. In the Viterbi decoder circuit, an arithmetic unit corresponding to only a valid bit string is mounted. In the case of Viterbi decoding, a 4-bit bit string is divided into a 3-bit state and 1-bit data for decoding. Although it is essentially the same, the description will be complicated if it is described, so the following description will be made using a 4-bit bit string. Here, it is emphasized that the bit string removed from the Viterbi decoder circuit does not depend on the length of the physical mark, but is removed only to satisfy the run-length limit.

  The reason why the combination data pattern of the minimum run length cannot be evaluated in MLSE or S-SEAT is because it is based on the configuration of the Viterbi decoder. As described above, the effective data corresponding to the decoder is effective. This is because there is no bit string. In order to solve this, only when signal quality is evaluated, a target signal can be generated by validating a bit string including 1T-length bits without being limited by the run length restriction.

  FIG. 8 summarizes the signal levels corresponding to each bit string of the Viterbi decoder unit and the reproduction signal quality evaluation unit and the status of whether they are valid or invalid. In the decoder, the effective bit string is 10 because of the run length limitation. On the other hand, when evaluating the reproduced signal quality, the bit string excluded due to the run length restriction is validated and the valid bit string is returned to the original 16 so that, for example, in the RLL (1,7) code, The front edge of “0110” (2T mark) is shifted, and it becomes possible to generate a target signal of an erroneous bit string when it is erroneously detected in the bit string “0010” (1T mark). As described above, when the reproduced signal is evaluated, the combination pattern of the minimum run length can be evaluated if the bit string and the target signal level are determined excluding the run length restriction.

  Hereinafter, the new signal evaluation index shown here is referred to as V-SEAT (Virtual-state-based-Sequenced Error for Adaptive Target). The calculation formula of V-SEAT is the same as S-SEAT. Basically, it is calculated from (Equation D-1) to (Equation D-6), but from (Equation D-7) to (Equation D-12) Can be extended according to V-SEAT, like S-SEAT, is compatible with a Viterbi decoder with a variable target level, but it goes without saying that it can also handle a Viterbi decoder with a fixed target level.

  FIG. 9 summarizes error patterns when V-SEAT is calculated for PR (1, 2, 2, 1). As shown in the figure, the introduction of the 1T mark simplifies the calculation pattern, and there are only four. In the figure, “X” indicates that it may be “0” or “1”. Thus, there is an advantage that the configuration of the pattern detection circuit can be simplified.

  Like V-SEAT, there are other merits to remove the run length restriction and evaluate the signal quality. As described above, in the case of PR (1,2,2,2,1), the signal quality cannot be evaluated by MLSE or S-SEAT because the pattern of the minimum Euclidean distance is not an edge shift. It was. This problem occurs because the correct pattern and the incorrect pattern each satisfy the run length limit. For example, the 2-bit error pattern No. 1 in FIG. 4 will be described. This is a case where the pattern “0000110000000” has an error of “0000011000000” and represents that the 2T mark is shifted to the right by 1T. Consider the marks recorded on an optical disc. Assume that only the front edge of the 2T mark is shifted to the right and recorded. In order to correct to the optimum recording condition, the pulse or power may be optimized so as to correct the position of the front edge of the 2T mark. On the other hand, the bit string pattern decoded by the Viterbi decoder must be shifted to the right by 1T as shown above due to the run length restriction. It is true that the signal quality is evaluated based on the Viterbi decoder error frequency. However, since the evaluation index obtained in this way can provide only incorrect information that the 2T mark has shifted to the right, the 2T mark that was in the normal position when the recording conditions were corrected based on this evaluation index. Including the trailing edge, the recording pulse or power condition is corrected. There may be no problem when viewed from an optical disc apparatus that performs recording and reproduction. However, for example, it can be easily imagined that errors are likely to occur when played back on an optical disc apparatus equipped with PR (1, 2, 1) or direct slice method. Since an optical disk is a medium-replaceable storage system, care must be taken to prevent such playback compatibility problems. In V-SEAT, signal quality is evaluated beyond the run length limit, so attention is paid to each edge of the mark, so it is possible to correctly evaluate the leading edge of the 2T mark even in the above case. There are advantages from the viewpoint of recording / playback compatibility and recording control. Similarly, a unified edge shift-based evaluation index can be used for PRML decoders such as R (1,2,2,2,1) whose minimum Euclidean distance is not an edge shift pattern. The advantage is that the configuration of the signal evaluation circuit can be used almost as it is.

  In order to cope with a Viterbi decoder having a variable target signal level using V-SEAT, it is necessary to indicate how to obtain the target signal level for a bit string including a 1T mark. Since there is no state corresponding to the 1T-length bit string in the Viterbi decoder, the target value cannot be directly referred to the target level table in the Viterbi decoder. The PR class, for example (1,2,2,1), approximates the impulse response of a 1T signal. The target signal level of the fixed target PRML is defined by impulse response and bit string convolution. Therefore, if it is assumed that convolution by linear addition is established even for PRML having a variable target level, a target signal level corresponding to a bit string including a virtual 1T can be obtained.

FIG. 10 summarizes the PRML bit string of the variable target level with 4 class bits and the target signal level. Such variable target level PRML is expressed as PR (a, b, c, d) below. As shown in the figure, for example, the target signal level v2 of the bit string “0010” is “0010” = “0011” using the target signal levels v0, v1, v3 of the bit strings “0000”, “0001”, “0011”. ”-“ 0001 ”and considering that the target signal level of“ 0000 ”is not zero,
v2 = v3-v1 + v0 (Formula 1)
Can be obtained as Similarly, the levels of other bit strings including 1T are:
v4 = v6-v2 + v0 (Formula 2)
v5 = v7-v2 + v0 (Equation 3)
v10 = v8-v13 + v15 (Formula 4)
v11 = v9-v13 + v15 (Formula 5)
v13 = v12-v14 + v15 (Formula 6)
Can be obtained as

The formula for calculating the target signal level for the bit string including 1T shown here is an example. Speaking of (Formula 1), for example, using “0010” = “1111” − “1101”,
v2 = v15-v13 + v0 (Equation 7)
It can also be. When linear addition is established between target levels, the values of (Equation 1) and (Equation 7) are the same, but generally there is an effect such as non-linear thermal interference in the recording process. , Linear addition does not hold. Basically, a target signal level for a bit string including 1T is calculated by (Expression 1) to (Expression 6). Preferably, it is better to average the values obtained by using a plurality of calculation formulas by weighting them with the number of occurrence events. The experimental results shown in the following examples are a method of calculating the target level by the latter.
To deal with any class with a larger number of class bits, the following concept should be followed.

(Process 1) The target level of the isolated impulse of “1” is calculated. An isolated impulse of “1” includes only one “1” in the bit string, and the other is a target level of the bit string of “0”. These bit string values can be expressed as 2 ⁿ . Here, 0 ≦ n <N, where N is the number of class bits. The target levels of these bit strings are obtained by adding or subtracting the target levels according to the run length restriction.
(Process 2) The target level of the isolated impulse of “0” is calculated. An isolated impulse of “0” refers to the target level of a bit string of “1” that includes only one “0” in the bit string. The values of these bit strings can be expressed as 2 ^N −2 ⁿ . Here, 0 ≦ n <N, where N is the number of class bits. The target levels of these bit strings are obtained by adding or subtracting the target levels according to the run length restriction.
(Process 3) A target level of an arbitrary bit string is obtained. Arbitrary bit string B is calculated by the following formula as a superposition of isolated impulses of “1”.

Where V1 [B] is the target signal level for bit string B, Vzero is the target level corresponding to bit string "00 ... 00", I1 [n] is the level of the isolated impulse of "1" whose bit string is represented by 2 ⁿ , NotZero (x) is a function that returns 1 when the value of x is not zero, and 0 when it is zero, and “&&” is an operator that represents the logical product of integers.
Similarly, an arbitrary bit string is calculated by the following formula as a superimposition of “0” isolated impulses.

Where V0 [B] is the target signal level for bit string B, Vone is the target level corresponding to bit string "11 ... 11", and I0 [n] is an isolated "0" whose bit string is represented by 2 ^N -2 ⁿ The impulse level, IsZero (x), is a function that returns 1 when the value of x is zero and 0 when it is not zero. From the (Equation 8) and (Equation 9), the obtained target level is averaged as an overlap of the impulse of “1” and the impulse of “0”, and the target level is obtained by the following equation.

Like S-SEAT, the above-mentioned extensions can be applied to V-SEAT. Specifically, this is as described using (Formula D-7) to (Formula D-12).
FIG. 11 summarizes the definitions and features of MLSE, S-SEAT, and V-SEAT.

  In the above, the solution of (Problem 1) and (Problem 2) of the present invention was described. In the following examples, specific methods corresponding to differences in PR classes and experimental results will be described in detail.

  Hereinafter, in the present invention, unless otherwise specified, the calculation of the S-SEAT value and the V-SEAT value is assumed to be the RMS value of all the values of the edge shift D calculated in the same manner as the MLSE value. To summarize. Similarly, unless otherwise specified, the PRML channel is assumed to be a square system.

If the reproduction signal evaluation method provided by the present invention and an optical disk apparatus using the same are used,
(1) Evaluation of a reproduction signal corresponding to a PRML channel whose target signal level adaptively changes according to the reproduction signal,
(2) The reproduction signal corresponding to the combination data pattern of the minimum run length can be evaluated.

  Hereinafter, details of the present invention will be described using examples.

Correspondence to various PR classes In the above explanation, the calculation method of S-SEAT and V-SEAT is described for PR (1,2,2,1) decoder corresponding to RLL (1,7) code. It was. Hereinafter, PR (1,2,1), PR (12221), PR (123321) class corresponding to RLL (1,7) code, and PR (3,4,4) corresponding to RLL (2,10) code are described below. 3) An example of a class is shown.

First, the PR class corresponding to RLL (1,7) code such as Blu-ray Disc is described.
Figure 12 summarizes the Euclidean distance and edge shift direction for 1-bit error patterns for the PR (1,2,1) and PR (a, b, c) classes corresponding to the RLL (1,7) code. It is. As shown in the figure, there are two combinations of patterns for 1-bit errors, and the Euclidean distance is 6 in the case of a fixed target level. The definition of the edge shift direction for each pattern is as shown in the figure.

First, calculation of S-SEAT will be described.
FIG. 13 summarizes the target signal levels of the PR (a, b, c) ML decoder having variable target levels corresponding to the RLL (1, 7) code. When calculating S-SEAT, the bit pattern in FIG. 12 may be extracted and the evaluation value calculated according to the above definition.

Next, calculation of V-SEAT will be described.
FIG. 14 summarizes V-SEAT detection patterns and edge shift directions for the PR (1,2,1) and PR (a, b, c) classes corresponding to the RLL (1,7) code. . As shown in the figure, there are four combinations of patterns for 1-bit errors, and the Euclidean distance is 6 for the fixed target level. The definition of the edge shift direction for each pattern is as shown in the figure.

  FIG. 15 summarizes the target signal levels of the PR (1,2,1) ML decoder having a fixed target level corresponding to the RLL (1,7) code. Here, the target signal level is standardized to ± 1. When calculating V-SEAT, the bit pattern in FIG. 14 may be extracted and the evaluation value calculated according to the above definition.

  FIG. 16 summarizes the target signal levels of the PR (a, b, c) ML decoder with variable target levels corresponding to the RLL (1, 7) code. When calculating V-SEAT, the target signal level corresponding to the bit string including 1T length is calculated according to the definition of the figure, the bit pattern of FIG. 14 is extracted, and the evaluation value is calculated according to the above definition. .

  FIG. 17 shows the Euclidean distance and edge for the 1-bit error pattern for the PR (1,2,2,2,1) and PR (a, b, c, d, e) classes corresponding to the RLL (1,7) code.・ Summary of shift direction. As shown in the figure, there are 18 combinations of patterns for 1-bit errors, and the Euclidean distance is 14 in the case of a fixed target level. The definition of the edge shift direction for each pattern is as shown in the figure.

First, calculation of S-SEAT will be described.
FIG. 18 summarizes the target signal levels of the PR (a, b, c, d, e) ML decoder with variable target levels corresponding to the RLL (1, 7) code. When calculating S-SEAT, the bit pattern in FIG. 17 may be extracted and the evaluation value calculated according to the above definition.

Next, calculation of V-SEAT will be described.
FIG. 19 shows V-SEAT detection patterns and edge shifts for the PR (1,2,2,2,1) and PR (a, b, c, d, e) classes corresponding to the RLL (1,7) code. This is a summary of the directions. As shown in the figure, there are four combinations of patterns for 1-bit errors, and the Euclidean distance is 14 for the fixed target level. The definition of the edge shift direction for each pattern is as shown in the figure.

  FIG. 20 summarizes the target signal levels of the PR (1,2,2,2,1) ML decoder having a fixed target level corresponding to the RLL (1,7) code. Here, the target signal level is standardized to ± 1. When calculating V-SEAT, the bit pattern in FIG. 19 may be extracted and the evaluation value calculated according to the definition.

  FIG. 21 summarizes the target signal levels of the PR (a, b, c, d, e) ML decoder having variable target levels corresponding to the RLL (1, 7) code. When calculating V-SEAT, the target signal level corresponding to the bit string including 1T length is calculated according to the definition of the figure, the bit pattern of FIG. 19 is extracted, and the evaluation value is calculated according to the above definition. .

  FIG. 22 shows a 1-bit error pattern for PR (1,2,3,3,2,1) and PR (a, b, c, d, e, f) classes corresponding to the RLL (1,7) code. This is a summary of the Euclidean distance and the direction of edge shift. As shown in the figure, there are 18 combinations of patterns for 1-bit errors, and the Euclidean distance is 28 for the fixed target level. The definition of the edge shift direction for each pattern is as shown in the figure.

First, calculation of S-SEAT will be described.
FIG. 23 summarizes the target signal levels of a PR (a, b, c, d, e, f) ML decoder with variable target levels corresponding to the RLL (1, 7) code. When calculating S-SEAT, the bit pattern in FIG. 22 may be extracted and the evaluation value calculated according to the above definition.

Next, calculation of V-SEAT will be described.
FIG. 24 shows a V-SEAT detection pattern for PR (1,2,3,3,2,1) and PR (a, b, c, d, e, f) classes corresponding to the RLL (1,7) code. And the direction of edge shift. As shown in the figure, there are four combinations of patterns for 1-bit errors, and the Euclidean distance is 28 in the case of a fixed target level. The definition of the edge shift direction for each pattern is as shown in the figure.

  FIG. 25 summarizes the target signal levels of the PR (1,2,3,3,2,1) ML decoder having a fixed target level corresponding to the RLL (1,7) code. Here, the target signal level is standardized to ± 1. When calculating V-SEAT, the bit pattern in FIG. 24 may be extracted and the evaluation value calculated according to the definition.

  FIG. 26 summarizes the target signal levels of the PR (a, b, c, d, e, f) ML decoder with variable target levels corresponding to the RLL (1, 7) code. When calculating V-SEAT, the target signal level corresponding to the bit string including 1T length is calculated according to the definition of the figure, the bit pattern of FIG. 24 is extracted, and the evaluation value is calculated according to the above definition. . Here, after calculating the target level for the impulse of “1” and the impulse of “0” by (Equation 8) and (Equation 9), the other target levels are calculated by (Equation 10). Shows the case. The target level of the impulse of “1” is v2, v4, v8, v16, and the target level of the impulse of “0” is v61, v59, v55, 47.

  Finally, PR (1,2,2,1) is summarized as a PR class corresponding to the RLL (1,7) code. Although it overlaps with the above explanation, it is judged that the understanding of the invention will be deepened by summarizing here, and it will be described below.

  FIG. 27 shows the Euclidean distance and the direction of edge shift for 1-bit error patterns for the PR (1,2,2,1) and PR (a, b, c, d) classes corresponding to the RLL (1,7) code. Is a summary. As shown in the figure, there are 8 combinations of patterns for 1-bit errors, and the Euclidean distance is 10 for the fixed target level. The definition of the edge shift direction for each pattern is as shown in the figure.

First, calculation of S-SEAT will be described.
FIG. 28 summarizes the target signal levels of the PR (a, b, c, d) ML decoder with variable target levels corresponding to the RLL (1, 7) code. When calculating S-SEAT, the bit pattern in FIG. 27 may be extracted and the evaluation value calculated according to the above definition.

Next, calculation of V-SEAT will be described.
Figure 29 summarizes V-SEAT detection patterns and edge shift directions for PR (1,2,2,1) and PR (a, b, c, d) classes corresponding to RLL (1,7) codes. It is a thing. As shown in the figure, there are four combinations of patterns for 1-bit errors, and the Euclidean distance is 10 for the fixed target level. The definition of the edge shift direction for each pattern is as shown in the figure.

  FIG. 30 summarizes the target signal levels of the PR (1,2,2,1) ML decoder having a fixed target level corresponding to the RLL (1,7) code. Here, the target signal level is standardized to ± 1. When calculating V-SEAT, the bit pattern shown in FIG. 29 may be extracted and the evaluation value calculated according to the above definition.

  FIG. 31 summarizes the target signal levels of the PR (a, b, c, d) ML decoder having variable target levels corresponding to the RLL (1, 7) code. When calculating V-SEAT, the target signal level corresponding to the bit string including 1T length is calculated according to the definition of the figure, the bit pattern of FIG. 29 is extracted, and the evaluation value is calculated according to the above definition. .

Next, the PR class corresponding to the RLL (2,10) code of CD / DVD is described.
Figure 32 shows the Euclidean distance and the direction of edge shift for 1-bit error patterns for the PR (3,4,4,3) and PR (a, b, c, d) classes corresponding to the RLL (2,10) code. Is a summary. As shown in the figure, there are two combinations of patterns for a 1-bit error, and the Euclidean distance is 50 for a fixed target level. The definition of the edge shift direction for each pattern is as shown in the figure.

First, calculation of S-SEAT will be described.
FIG. 33 summarizes the target signal levels of the PR (a, b, c, d) ML decoder with variable target levels corresponding to the RLL (2, 10) code. When calculating S-SEAT, the bit pattern in FIG. 32 may be extracted and the evaluation value calculated according to the above definition.

Next, calculation of V-SEAT will be described.
FIG. 34 summarizes V-SEAT detection patterns and edge shift directions for the PR (3,4,4,3) and PR (a, b, c, d) classes corresponding to the RLL (2,10) code. It is a thing. As shown in the figure, there are four combinations of patterns for 1-bit errors, and the Euclidean distance is 50 for a fixed target level. The definition of the edge shift direction for each pattern is as shown in the figure.

  FIG. 35 summarizes the target signal levels of the PR (3,4,4,3) ML decoder having a fixed target level corresponding to the RLL (2,10) code. Here, the target signal level is standardized to ± 1. When calculating V-SEAT, the bit pattern shown in FIG. 34 may be extracted and the evaluation value calculated according to the above definition.

  FIG. 36 summarizes the target signal levels of the PR (a, b, c, d) ML decoder with variable target levels corresponding to the RLL (2, 10) code. When V-SEAT is calculated, the target signal level corresponding to the bit string including 1T length and 2T length is calculated according to the definition of the figure, the bit pattern of FIG. 35 is extracted, and the evaluation value is calculated according to the above definition. What is necessary is just to calculate.

  In the above embodiments regarding V-SEAT, the general case where the asymmetry of the reproduction signal is not zero and the magnitudes of the impulses “1” and “0” are not equal is shown. The following embodiment shows a more simplified method for obtaining a variable target level when the asymmetry of a reproduction signal is small and the magnitudes of “1” and “0” impulses are considered to be equal.

  In the present invention, for convenience, the PR class of the variable target level is represented as PR (a, b, c, d), for example. When the asymmetry can be assumed to be zero, the time change of the impulse response of “1” is (a, b, c, d), and if the signal amplitude is normalized to ± 1, the impulse response of “0” Becomes (-a, -b, -c, -d). Therefore, if each value of a, b, c, and d is obtained from the target level table, the target signal level for an arbitrary bit string can be calculated by the convolution operation of the bit string and the impulse response, so that the processing can be simplified. Here, the PR class having the values of a, b, c, and d obtained from the target level table is referred to as an integrated PR class. In the following, PR (a, b, c), PR (a, b, c, d) corresponding to the RLL (1,7) code, and PR (a, b, c, An embodiment for each class of c, d) is shown.

FIG. 37 shows a case where the target signal level of the PR (a, b, c) ML decoder having a variable target level corresponding to the RLL (1, 7) code is obtained assuming that the asymmetry amount is zero. Here, the target signal level is standardized to ± 1. To find an integrated PR class, as shown in the figure:
a = {(v1-v0)-(v6-v7)} / 2 (Formula 11)
b = {(v3-v1)-(v4-v6)} / 2 (Formula 12)
c = {(v4-v0)-(v3-v7)} / 2 (Formula 13)
Ask from. Each is an average of the magnitudes of “1” impulses and “0” impulses, and can be easily calculated with reference to FIG. When the asymmetry is zero and the amplitude is normalized to ± 1, v0 = + 1 and V7 = -1. If these are used, an arbitrary target level can be calculated, for example, v1 = v0 + a. The method for obtaining all target levels is as shown in the figure.

FIG. 38 shows a case where the target signal level of the PR (a, b, c, d) ML decoder having a variable target level corresponding to the RLL (1, 7) code is obtained assuming that the asymmetry amount is zero. Here, the target signal level is standardized to ± 1. To find an integrated PR class, as shown in the figure:
a = {(v1-v0)-(v14-v15)} / 2 (Formula 14)
b = {(v3-v1)-(v12-v14)} / 2 (Formula 15)
c = {(v6-v2)-(v9-v13)} / 2 (Equation 16)
d = {(v8-v0)-(v7-v15)} / 2 (Equation 17)
Ask from. Each is an average of the magnitudes of “1” impulses and “0” impulses, and can be easily calculated with reference to FIG. When the asymmetry is zero and the amplitude is normalized to ± 1, v0 = + 1 and V15 = -1. If these are used, an arbitrary target level can be calculated, for example, v1 = v0 + a. The method for obtaining all target levels is as shown in the figure.

FIG. 39 shows a case where the target signal level of the PR (a, b, c, d) ML decoder having a variable target level corresponding to the RLL (2, 10) code is obtained assuming that the asymmetry amount is zero. Here, the target signal level is standardized to ± 1. To find an integrated PR class, as shown in the figure:
a = {(v1-v0)-(v14-v15)} / 2 (Equation 18)
b = {(v3-v1)-(v12-v14)} / 2 (Equation 19)
c = {(v6-v2)-(v9-v13)} / 2 (Equation 20)
d = {(v8-v0)-(v7-v15)} / 2 (Formula 21)
Ask from. These are the same as (Equation 14) to (Equation 17). Each is an average of the magnitudes of “1” impulses and “0” impulses, and can be easily calculated with reference to FIG. When the asymmetry is zero and the amplitude is normalized to ± 1, v0 = + 1 and V15 = -1. If these are used, an arbitrary target level can be calculated, for example, v1 = v0 + a. The method for obtaining all target levels is as shown in the figure.

  In other cases, the same applies to PR (a, b, c, d, e), PR (a, b, c, d, e, f), etc. Are averaged, an integrated PR class is calculated from the target signal level table, and a target level for an arbitrary bit string can be defined using these. Such a result is the same as that obtained by averaging the level of the bit string obtained by exchanging “1” and “0” of the bit string with respect to the target signal level when the asymmetry is not zero. This operation corresponds to zero asymmetry.

Circuit Configuration Next, an example of a circuit configuration suitable for calculating S-SEAT and V-SEAT will be described with reference to the drawings.
FIG. 1 shows the configuration of the S-SEAT calculation circuit mounted on the optical disk apparatus of the present invention. The overall configuration includes a decode unit 10, a target level learning unit 20, and a signal evaluation unit 30.

  First, the decode unit 10 will be described. The decode unit 10 includes a waveform equalizer 11, a branch metric calculation unit 12, an ACS (Add Select Compare) unit 13, a path memory 14, and a target level table 17. The reproduction signal 50 is converted into a digital value by an AD converter in advance, and after being equalized by the FIR filter in the waveform equalizer 11, an error from the target value is detected for each bit string in the branch metric calculation unit 12. A square value (branch metric value) is calculated. For the target value for each bit string, refer to what is stored in the target level table 17. In ACS unit 13, the branch metric corresponding to each bit string is added to the state one time before and the metric value in each state (the branch metric value is sequentially added and processed so as not to diverge with the state transition). Add a value. At this time, a process of selecting the smaller metric value from the transition processes (usually two, sometimes depending on the run length) leading to the current time state is performed. The state is a bit string stored for a transition at one time. For example, when the PR class bit is 4, the bit string is represented by 4 bits and the state is represented by 3 bits. The binarization result decoded for each bit string is stored in the path memory 14 for a sufficiently long time, and the latest result is always stored by shifting the memory contents as the time is updated. Yes. The ACS unit 13 rearranges the information stored in the path memory according to the selection result during the selection process of the transition process. By repeating such processing, the information in the path memory is gradually integrated, and after a sufficiently long time, so-called path merging is completed in which the same value is obtained regardless of the bit string. The binarization result 51 is binarization information extracted from the path memory when the time is updated.

  Next, the target level learning unit 20 will be described. The target level learning unit 20 includes a pattern detector 24 and an averaging unit 25. The pattern detection unit 24 stores the binarization result 51 by the number of class bits, and sends address information corresponding to the bit string to the averaging unit 25. The averaging unit 25 is a process for averaging the level of the reproduction signal output from the waveform equalizer 11 for each address information at that time, that is, for each corresponding bit string, and storing it in the corresponding memory table in the target level table 17 do.

  Finally, the signal evaluation unit 30 will be described. The signal evaluation unit 30 includes a pattern selection unit 31, target level calculation units 32 and 33, and a sequence error evaluation unit 34. The pattern selection unit 31 stores the binarization result 51 corresponding to the 1-bit error by “class bit number x2-1” as described above, and determines whether or not it is the S-SEAT calculation pattern. If it is determined as a calculation pattern, it is sent to the target level calculation unit 32 as a “True” pattern 53, and at the same time, the aforementioned 1-bit error pattern is generated and set as the “False” pattern 54 as the target level calculation unit 33. Send to. The target level calculation units 32 and 33 refer to the target level table 17 and output target signal levels corresponding to the “True” pattern 53 and the “False” pattern 54. The sequence error evaluation unit 34 uses the outputs of the target level calculation units 32 and 33 and the output of the waveform equalizer 11 to determine the S-SEAT value according to the definitions of (Equation D-1) to (Equation D-6). 55 is calculated. As described above, the S-SEAT value 55 can be expanded according to (Formula D-7) to (Formula D-12).

  FIG. 40 shows the configuration of a V-SEAT calculation circuit mounted on the optical disc apparatus of the present invention. The overall configuration includes a decode unit 10, a target level learning unit 20, and a signal evaluation unit 30. The basic operation is the same as the above embodiment. A virtual target level calculation unit 35 is added as a component peculiar to V-SEAT calculation. The virtual target level calculation unit 35 executes a process of calculating and storing the target signal levels for all the bit strings by using the table values of the target level table 17 by the above-described method without being restricted by the run length restriction. The pattern selection unit 31 performs processing for selecting a bit pattern corresponding to V-SEAT. The sequence error evaluation unit 34 uses the outputs of the target level calculation units 32 and 33 and the output of the waveform equalizer 11 to determine the V-SEAT value according to the definitions of (Equation D-1) to (Equation D-6). 55 is calculated. As described above, the V-SEAT value 55 can be expanded according to (Formula D-7) to (Formula D-12).

  Finally, the signal evaluation unit 30 will be described. The signal evaluation unit 30 includes a pattern selection unit 31, target level calculation units 32 and 33, and a sequence error evaluation unit 34. The pattern selection unit 31 stores the binarization result 51 corresponding to the 1-bit error by “class bit number x2-1” as described above, and determines whether or not it is the S-SEAT calculation pattern. If it is determined as a calculation pattern, it is sent to the target level calculation unit 32 as a “True” pattern 53, and at the same time, the aforementioned 1-bit error pattern is generated and set as the “False” pattern 54 as the target level calculation unit 33. Send to. The target level calculation units 32 and 33 refer to the target level table 17 and output target signal levels corresponding to the “True” pattern 53 and the “False” pattern 54. The sequence error evaluation unit 34 uses the outputs of the target level calculation units 32 and 33 and the output of the waveform equalizer 11 to determine the S-SEAT value according to the definitions of (Equation D-1) to (Equation D-6). 55 is calculated. As described above, the S-SEAT value 55 can be expanded according to (Formula D-7) to (Formula D-12).

  In the above two embodiments, the target level learning unit 20 has always been shown to operate when the signal is reproduced. However, when the quality of the reproduced signal is evaluated, the target level is preferably fixed. , Which is preferable in terms of stability of evaluation. Therefore, when evaluating the signal quality, it is desirable that the operation of the target level learning unit 20 is stopped so that the value of the target level table 17 is not updated.

  FIG. 41 shows another configuration of the S-SEAT calculation circuit mounted on the optical disc apparatus of the present invention. A difference in configuration from the above-described embodiment resides in the target level learning unit 20. In the present embodiment, a target level calculation unit 21, an error calculation and operation control unit 26, and a switch 27 are added to the target level learning unit 20. In a PRML decoder having a variable target level, the value of the target level table 17 is updated according to the reproduction signal. In order to ensure the stability of the operation of the optical disc apparatus, it is necessary to limit the case where the update process is performed. For example, (1) During seek, (4) If the operation of the PLL (Phase Locked Loop) circuit that extracts the clock from the playback signal is not stable, but not shown, (3) Dust, fingerprints, defects on the disk medium If the reproduction signal is significantly distorted and the target signal level is updated, etc., a so-called runaway state occurs and the normal operation of the decoder is hindered. In order to avoid this, it is necessary to provide a detection circuit for each of the various cases described above and stop the updating process. In the method shown in this embodiment, the error between the target signal and the reproduction signal is always calculated, and the update process of the target signal level is performed only when the absolute value of the error is not more than a predetermined value. It is simply realized. The operation is as follows. The target level calculation unit 21 always receives the binarization result 51 and outputs the target signal level. The error calculation and operation control unit 26 evaluates the output of the waveform equalizer 11 and the error of the target level calculation unit 21, and closes the switch 27 only when the absolute value of the error is equal to or less than a predetermined value to Control to perform level update processing. In this embodiment, the switch 27 is introduced in order to deepen the understanding of the invention. However, for example, a method for controlling the operation by turning on / off the clock supplied to the averaging unit 25, and the output of the averaging unit 25 are described. The method of controlling operation by adding an AND circuit to the stage is simpler, and it is desirable to use this method in an actual circuit.

  In the following, regarding the variable target level type PRML, the compensation type PRML method excellent in increasing the recording density and the target level limited type PRML method for improving the reproduction compatibility performance, their operation principle and the S-of the present invention. An example of a calculation circuit for SEAT and V-SEAT is shown.

  The problem to improve the PRML system and realize a large capacity optical disc is suppression of nonlinear edge shift due to thermal interference during recording. As described above, in the PRML method, a target signal is determined by selecting a PR class. Therefore, we recorded signals with different recording densities on one optical disk, and examined the difference in density enhancement performance by various PR classes.

  The prepared optical disk is obtained by laminating a phase change film on a land / groove substrate having a track pitch of 0.34 μm. In the experiment, a DDU-1000 type optical disk evaluation apparatus manufactured by Pulstec was used. The wavelength of the light source is 405 nm, and the NA of the objective lens is 0.85. RLL (1,7) was used as the modulation code, and the detection window width Tw was varied in the range from 53 nm to 80 nm. The recording capacity on one side of a CD-size disc is assumed to be 35 GB when Tw = 53 nm.

The following three series were selected to examine the differences in PR classes.
(1) (1 + D) ⁿ sequence This is the most basic class sequence, PR (1,1), PR (1,2,1), PR (1,3,3,1),.
(2) (1,2, ..., 2,1) sequence This sequence includes PR (1,2,2,1) often used in optical disks.
Compared to the above series, the high-frequency emphasis is reduced, and an improvement in the S / N ratio can be expected.
(3) Impulse response approximate series
The PR class basically approximates the impulse response of the read head.
Here, the impulse response of the optical head calculated using an optical simulator was used for the PR class.

Using each selected PR class, the ideal reproduction signal calculated by the optical simulator is used, and the equalization condition is determined for each PR class so that the RMS error between the target and the reproduction signal is minimized. The optical disc signal was reproduced. The number of taps in the equalizer is 11.
The measurement results of the reproduction performance of the optical disc for each PR class series are shown in FIGS. 44 to 46, respectively.

FIG. 45 (a) shows the relationship between the recording capacity and the bit error rate for the (1 + D) ⁿ series. FIG. 45 (b) summarizes the bit representation of each PR class, the number of valid bit strings, the number of valid states, the number of independent target levels, and the upper limit of the recording capacity. The upper limit of the recording capacity indicates a range where the bit error rate is 10 ⁻⁴ or less. If the number of class bits (number of elements included in the PR class expression) is N, the total number of bit strings will be 2 ^N , but the run length restriction excludes the minimum run length of 1T from the set of bit strings. Is the number of valid bit strings. The number of valid states is obtained in the same manner. In order to realize these, since the circuit scale is proportional to the number of effective bit strings, a system with as few class bits as possible is desired. In this series, the higher the class bit number, the higher the density, but the performance improvement is saturated when the class bit number is 6 or more. The maximum recording capacity was 31GB when the class bit number was 7.

  FIG. 46A shows the relationship between the recording capacity and the bit error rate for the (1, 2,..., 2, 1) series. FIG. 46 (b) summarizes the details. In this series, if the number of class bits is too large, the recording capacity decreases. If the number of class bits is large, it will be possible to express the temporal transition of the playback signal more precisely, but at the same time the number of independent target levels will also increase, so the difference between the target levels for two different paths will be reduced. This is probably because errors increase when a path is selected. The maximum recording capacity of this series was 31GB when the class bit number was 5.

  FIG. 47A shows the relationship between the recording capacity and the bit error rate with respect to the impulse response approximate series. FIG. 47 (b) summarizes the details. If this class also has too many class bits, the recording capacity will decrease. The maximum recording capacity was 32GB for 5 class bits.

As a result of examining three possible PR class sequences, it was found that there was a limit in improving the performance even if the number of PR class bits was simply increased and the configuration was complicated. This is because the reproduction signal of the optical disc has a non-linear edge shift due to intersymbol interference due to the shape of the light spot and thermal interference during recording. In order to cope with such non-linear intersymbol interference and edge shift, the basic PRML method for determining a target value by linear convolution is insufficient, and it is necessary to compensate for the non-linear component by some method. . From the above results, the following two points are important for realizing higher density.
(1) The target number of levels is not increased by not increasing the number of class bits.
(2) The compensation value corresponding to the bit string is added to the target value determined by the convolution operation to compensate the target value, thereby dealing with the non-linear component included in the reproduction signal.

  In order to satisfy these requirements and realize a large capacity, a target value is determined by adding a compensation amount according to a bit string of N (N> NN) bits to the target value determined by the NN bit convolution operation. The PRML system that binarizes the most probable N-bit bit string, that is, the bit string that minimizes the error between the reproduced signal and the target value, may be used.

  FIG. 48 shows an embodiment showing the basic concept of the above information reproducing method. In order to simplify the description, the most basic class PR (1, 1) will be described as an example. Method 1 is a basic PRML method. As shown in the configuration example, the target value corresponding to two consecutive bit strings at a time is compared with the value of the reproduction signal, and the bit string with the smallest error is selected. In this example, the number of target levels is 3, which cannot cope with asymmetry of the reproduction signal and nonlinear intersymbol interference.

Method 2 is an adaptive PRML method disclosed in Technical Digest of ISOM 2002, 269-271 (2002). The compensation value V corresponding to the 2-bit bit string is added to the target value determined by the convolution calculation and used as a new target value, and binarization is advanced while selecting the bit string that minimizes the error from the value of the reproduction signal. The number of compensation values V is 4 (= 2 ² ). Although the target value can be adaptively changed corresponding to the asymmetry of the reproduced signal, nonlinear intersymbol interference cannot be sufficiently removed.

Method 3 is one in which pattern compensation bits are added one by one before and after the bit string of PR (1,1), and is called compensation type PRML. Unlike the method 2, the feature is that a compensation value V corresponding to a 4-bit bit string including pattern compensation bits is added to the target value. Then, binarization is advanced while selecting the bit string that minimizes the error while comparing the reproduction signal with the target value corresponding to the 4-bit bit string. In this method, since the number of target levels determined by the convolution operation remains 3 and does not increase, the number of compensation values V is 16 (= 2 ⁴ ), so nonlinear intersymbol interference within the 4-bit bit string range Can be compensated. In order to distinguish this from the conventional PRML method, the PR class expression is described as Compensated-PR (0,1,1,0) or CPR (0,1,1,0). This is a PRML method with a class bit number of 4, and the target value is calculated by convolution of the coefficient sequence (0,1,1,0) and the 4-bit bit sequence as in the conventional description. Since the coefficient for 1 bit is zero, it is the same as the target value defined by the 2-bit coefficient sequence (1,1). The coefficient “0” before and after the pattern represents a pattern compensation bit, and the meaning of CPR means that a compensation value V determined by a 4-bit bit string is added to the target value. The conventional method 1 can be expressed as PR (1,1) by the same method, and the method 2 can be described as CPR (1,1).

The experimental results in the figure are the results of recording on the above-mentioned optical disk under the condition of the detection window width Tw = 57 nm (storage capacity 32.5 GB) and reproducing by each method. Here, the basic PR class is PR (1, 2, 2, 1), and the data transfer rate is 100 Mbps. If the bit error rate of the system 1 (PR (1,2,2,1)) is 50 × 10 ^-4, method 2 If the (CPR (1,2,2,1)) is 15 × 10 ^-4, scheme 3 (CPR In the case of (0,1,2,2,1,0)), 0.05 × 10 ⁻⁴ was obtained. It was confirmed that Method 3 can reduce the bit error rate to 1/100 or less. In addition, the eye pattern of the reproduction signal shows an effective signal (compensation reproduction signal) when each method is used, and it can be seen that in method 3, the eye is clearly opened. The S / N ratio of the 2Tw signal included in the compensated playback signal is 3.6 dB for method 1, 6.1 dB for method 2, and 9.5 dB for this method.

FIG. 49 (a) shows the experimental results showing the difference in capacity increase performance between the compensated PRML system and other PRML systems. PR (1,2,2,1) was selected as the basic PR class. If the allowable value of the bit error rate is 10 ⁻⁴ , the upper limit of the recording capacity is obtained. The upper limit of the recording capacity of the conventional method is 30 GB for PR (1, 2, 2, 1) and 32 GB for CPR (1, 2, 2, 1). The maximum recording capacity of the compensated PRML system is 32.5GB for CPR (0,1,2,2,1,0) ML4, 34.5GB for CPR (0,1,2,2,1,0), CPR (0 , 0,1,2,2,1,0,0) and CPR (0,0,0,1,2,2,1,0,0,0) were over 35GB. CPR (0,1,2,2,1,0) ML4 is a 6-bit compensation value only, and the number of maximum likelihood decoding (ML bit number) to select the most probable bit string remains 4 bits. It shows the method to be performed. Although superior to the prior art, since the maximum likelihood decoding process is performed without including pattern compensation bits, the ability to suppress nonlinear shift is reduced. In order to maximize the capability of the compensated PRML system, maximum likelihood decoding processing including pattern compensation bits is important. The results obtained here show that the basic PR class is not limited to PR (1, 2, 2, 1), and the recording capacity can be increased more than the various PR classes shown above.

  FIG. 49 (b) summarizes the number of bit strings, the number of states, the number of levels, the number of pattern compensation bits, and the number of ML bits for each method shown in FIG. 49 (a). Since the scale of the circuit for realizing the PRML method is roughly proportional to the number of bit strings, CPR (0,0,0,1,2,2,1,0,0 , 0) requires more than 10 times the circuit scale compared to PR (1,2,2,1), and it is important to balance performance and circuit scale.

  Here, we described a method in which PR (1, 2, 2, 1) was selected as the basic PR class and the same number of pattern compensation bits were added before and after. However, the present invention is not limited to this. Basic PR classes include PR (1,1), PR (1,2,1), PR (3,4,4,3), PR (1,1,1,1), PR (1,2, Any basic PR class such as 2,2,1) can be selected. The number of pattern compensation bits is not limited to the symmetrical ones, but CPR (0,1,2,2,1), CPR (0,0,1,2,2,1), CPR (1,2 , 2,1,0), CPR (1,2,2,1,0,0), etc., an asymmetric bit number can be added. For example, when reproducing a signal that is physically obvious that the influence of thermal interference during recording is concentrated on the front edge, it is best to add pattern compensation bits only to the front side. There is a case.

FIG. 42 shows another configuration of the S-SEAT calculation circuit mounted on the optical disc apparatus of the present invention. This corresponds to compensated PRML.
The decode unit 10 includes a waveform equalizer 11, a branch metric calculation unit 12, an ACS unit 13, a path memory 14, a PR target table 15, and a pattern compensation table 16. The reproduction signal 50 is converted into a digital value by an AD converter in advance, and after being equalized by the FIR filter in the waveform equalizer 11, an error from the target value is detected for each bit string in the branch metric calculation unit 12. A square value (branch metric value) is calculated. At this time, the initial target value corresponding to the bit string is referred to the PR target table 15 as the target value, and the compensation value corresponding to the bit string is referred to the pattern compensation table 16 and the value obtained by adding both values is used. The operations of the ACS unit 13 and the path memory 14 are as described above. The gist of the present embodiment is to add a compensation value to a target value to obtain a new target value, thereby binarizing the most probable result.

  The target level learning unit 20 includes a target level calculation unit 21 and an error calculation and averaging unit 22. In the target level calculation unit 21, the binarization result 51 is input, the initial target value corresponding to the bit string is referred to the PR target table 15, the compensation value corresponding to the bit string is referred to the pattern compensation table 16, and both values Is added as a target signal level. The error calculation and averaging unit 22 calculates an error between the output of the waveform equalizer 11 and the output of the target level calculation unit 21, averages the error amount for each bit string, and updates the value of the pattern compensation table 16 do.

  For S-SEAT calculation, refer to the PR target table 15 for the initial target value corresponding to the bit string, and refer to the pattern compensation table 16 for the compensation value corresponding to the bit string. As described above, the target level calculation units 31 and 32 may be operated, and the calculation of the S-SEAT value is as described above.

  The PRM system with variable target level, including the compensated PRML system, can perform decoding according to the playback signal and improve playback performance. On the other hand, for example, even when the light spot is distorted due to tangential tilt or when there is distortion such as group delay in the I-V amplifier of the reproduction signal, reproduction is performed in accordance with the distortion. For this reason, it is conceivable that the reproduction signal quality deteriorates when the reproduction is performed by the optical disk apparatus equipped with another fixed target level PRML system. Thus, the problem with the PRM method with variable target level is that playback compatibility cannot be guaranteed. In order to solve this, it is necessary not to change the target level of all bit strings in accordance with the reproduction signal, but to make the target level not follow elements that impair reproduction compatibility. One of the methods for realizing this is to measure the asymmetry amount of the reproduction signal and use a target level table determined in advance according to the asymmetry amount. The second method to be realized is to set the target level of a set of bit strings symmetrical to time reversal to the same value. Since the representative examples of the distortion of the reproduction signal described above both distort the reproduction signal asymmetrically in the time direction, for example, the target signal level of the bit string “1000” is different from the target signal level of the bit string “0001”. become. Therefore, by averaging the target signal level corresponding to the bit string contrasted with these time inversions and making the same value, the target signal level can be made to follow the distortion of the reproduction signal in the time direction. Playback compatibility can be improved. The PRML scheme with these restrictions is called a target level restricted PRML scheme.

FIG. 43 shows another configuration of the S-SEAT calculation circuit mounted on the optical disc apparatus of the present invention. This corresponds to the target level restricted PRML.
The decode unit 10 includes a waveform equalizer 11, a branch metric calculation unit 12, an ACS unit 13, a path memory 14, a target level table 17, a limited target level table 18, a mode control unit 19, and a switch 191. The reproduction signal 50 is converted into a digital value by an AD converter in advance, and after being equalized by the FIR filter in the waveform equalizer 11, a branch metric value is calculated for each bit string in the branch metric calculation unit 12. Is done. At this time, either the value of the target level table 17 or the value of the restricted target level table 18 is used as the target value. As described above, the target level table 17 changes in accordance with the reproduction signal, and the value of the limited target level table 18 is the target of the set of bit strings contrasting with time reversal as described above. It is averaged so that the level becomes the same value. The mode control unit 19 controls the operation of the switch 191 to control which target level is used. For example, the values in the restricted target level table 18 are used at the time of focus / offset learning, at the time of trial writing to learn the recording conditions, and at the time of verification to check the reproduction signal quality. If an error occurs during data reproduction, the value in the target level table 17 is used. Either target level may be used during normal data reproduction. By such an operation of selecting the target signal level by the mode control unit 19, it is possible to improve reproduction compatibility and learning accuracy.

  The target level learning unit 20 includes a pattern detector 24, an averaging unit 25, and a limit control unit 23. The operations of the pattern detection unit 24 and the averaging unit 25 and the update procedure of the target level table 17 are as described above. The limit control unit 23 receives the output of the averaging unit 25, performs an averaging process so that the target level of the set of bit strings contrasted against the time inversion becomes the same value, and stores the result in the limited target level table 18. Process to store.

  For the calculation of S-SEAT, the target level calculation units 31 and 32 are used by using the value of the target level table 17 or the restricted target level table 18 as determined by the mode control unit 19 as the target level value corresponding to the bit string. The value calculation method is as described above.

  In this embodiment, an example is shown in which a table is selected by the mode control unit 19 and the switch 191 in order to help understanding of the invention. The target level table 17 and the limited target level table 18 have the same hardware configuration except that the stored target level values are different. Therefore, in order to simplify the circuit configuration, only the target level table 17 is mounted, and each value is backed up to S-RAM and D-RAM under the control of the CPU (not shown). Thus, the target level table 17 may be loaded with either of these values. As a result, the mode control unit 19 and the switch 191 are not required, and the circuit scale can be reduced.

  The circuit configuration of the present invention has been described above. The embodiment shown in FIGS. 41 to 43 shows the configuration of the S-SEAT calculation circuit. In order to make these correspond to V-SEAT, the virtual target level calculation unit 35 shown in FIG. 40 may be added, and the selection pattern of the pattern selection unit 31 may be changed to V-SEAT.

Finally, the configuration of a circuit having a function of calculating S-SEAT and V-SEAT with one circuit will be described.
FIG. 44 shows the configuration of the S-SEAT and V-SEAT calculation circuits mounted on the optical disc apparatus of the present invention. The difference from the configuration in FIG. 40 is in the signal evaluation unit 30.
The signal evaluation unit 30 includes a pattern selection unit 31, target level calculation units 32 and 33, a sequence error evaluation unit 34, a virtual target level calculation unit 35, an S-SEAT pattern table 36, and a V-SEAT pattern table 37. The pattern selection unit 31 switches between the S-SEAT and V-SEAT calculation functions in accordance with a CPU instruction (not shown). Specifically, when calculating the S-SEAT, the S-SEAT bit table is stored with reference to the S-SEAT pattern table 36, the “True” pattern 53, and the “False” pattern 54. Works to output. When calculating V-SEAT, refer to the V-SEAT pattern table 37 containing the V-SEAT bit pattern, and output the pattern selection and the “True” pattern 53 and “False” pattern 54 Operate. When the “True” pattern 53 and the “False” pattern 54 are output, the subsequent calculation processing is as described above, and there is no change between S-SEAT and V-SEAT. Although it is a stagger, the influence of the virtual target level calculation unit 35 at the time of S-SEAT calculation is described. Since the S-SEAT pattern satisfies the run length limit, the run length limit in the virtual target level calculation unit 35 is set. The target signal level for the removed bit string is not referenced and is not affected by these. The target signal level that satisfies the run length limit is the same for both S-SEAT and V-SEAT. Therefore, in this configuration, the S-SEAT and V-SEAT can be calculated correctly without the virtual target level calculation unit 35 being adversely affected during S-SEAT calculation.

  In the present embodiment, a circuit configuration for calculating S-SEAT and V-SEAT corresponding to a PRML decoder of a fixed target level is shown. In order to make this correspond to the PRML decoder having a variable target level, the signal evaluation unit 30 may be changed to that of the present embodiment with reference to the configuration of FIGS.

When the branch metric calculation is performed with absolute values As described above, the Viterbi decoder integrates the square value of the difference between the reproduced signal and the target value to obtain the most reliable result. • Use metric values. Such a Viterbi decoder is called a square system. The square value Δ ² of the difference between the playback signal and the target level is

It becomes. Here, V _signal [t] is the level of the reproduction signal at time t, and V _target [n] is the target signal level corresponding to bit string n. In the Viterbi decoder, binarization is performed so that the Δ ² integrated value is minimized. The first term on the right side is the level of the reproduction signal and is common to all bit strings, so there is no need to calculate. For a Viterbi decoder with a fixed target signal level, the following may be calculated.

Where A [n] = _-2 V _target [n], B [n] = (V _target [n]) ² is a constant, and the value of A [n] is 1, 2, 4, etc. Since the bit shift can be used instead of the integration, in many cases (A-2) can greatly simplify the calculation amount, that is, the circuit scale, compared to (Equation A-1).

Viterbi with variable target level. In the decoder, the target level is a variable, so
Can only be simplified. Since V _target [n] is a variable, it is difficult to simplify the circuit configuration that replaces integration with bit shift. For this reason, in a Viterbi decoder with a variable target level, the circuit scale must be large.

In order to simplify this, it is effective to substitute the absolute value of the difference for the branch metric value instead of the square value of the difference between the reproduction signal and the target level. At this time,
As a result of the Viterbi decoding using | Δ |, the integration is unnecessary compared to (Equation A-3), so the number of bits of the arithmetic unit can be reduced, and the circuit scale can be reduced. The power consumption can be reduced.

The method of calculating S-SEAT and V-SEAT for the absolute value Viterbi decoder is summarized below.
As for the detection pattern, the same absolute value system and square system can be used.
For the calculation of S-SEAT, the Euclidean distance may be redefined using the absolute value system. The definition is shown below.
The Euclidean distance between two bit patterns "pat1" and "pat2" by definition and the ED _B (pat1, pat2), is expressed by the following equation. This is the same as (Formula D-7) described above.

Here, V _target [B] represents a target signal level for bit string B, pat [n] represents a bit string at time n of bit pattern “pat”, and N represents the number of class bits.
The average minimum Euclidean distance is an average value of the Euclidean distance for a 1-bit error pattern, and is defined as follows. This is the same as (Equation D-2).

Here, M represents the total number of combinations of 1-bit error patterns, and Pat _T and Pat _F represent a positive bit pattern and an erroneous bit pattern, respectively.
The Euclidean distance between the reproduction signal and the specified bit pattern “pat” is expressed by the following equation.

Here, V _signal [t] is the reproduction signal level at time t, and the binarization result at time t is the bit pattern “pat”.
The S-SEAT value σ is obtained as follows. These are the same as (Formula D-4) to (Formula D-6).

Here, Sign (Shift-Direction) represents the edge shift direction when the binarization result Pat _T becomes 1 bit error (edge shift) and becomes Pat _F , and P is within the specified calculation period. Represents the number of bit patterns.

Since the definition formula of V-SEAT is the same as S-SEAT, V-SEAT can be calculated using (Equation D-13) to (Equation D-18). The detection pattern is the same as that shown in the square system.
As described above, the S-SEAT value and the V-SEAT value can be expanded according to (Formula D-8) to (Formula D-12).
An example of an absolute value Viterbi decoder will be described in the next embodiment.

Experimental results First, the experimental results using a DVD-RAM disc are shown as an application example to the RLL (2,10) code.
FIG. 51 shows the actual measurement results of MLSE, S-SEAT, and V-SEAT when a DVD-RAM disc is reproduced using the PR (3,4,4,3) class. The disc was a commercially available 2x DVD-RAM medium. The evaluation device is a LM330A manufactured by Shiba-Sok Corporation, which has a laser wavelength of 658 nm and a numerical aperture of 0.60. For the reproduction circuit, DVD-RAM standard equalization conditions (3-tap FIR filter and Bessel sixth-order low-pass filter) were used as the equalizer. The boost amount is 5.5dB. The recording power was 10.3 mW and the erasing power was 4.7 mW, and the groove track was overwritten 10 times, and the playback signal quality was evaluated by each method. The jitter value was 8.5%. Each evaluation value has a Gaussian distribution as shown in the figure, and the horizontal axis is ± Tw / 2 with the detection window width. From these definitions of evaluation values, edge events that exceed the range of ± Tw / 2 cause playback errors and can be handled in the same way as jitter values. The evaluation values were MLSE = 11.0%, S-SEAT = 11.0%, and V-SEAT = 12.5%, respectively. The reason why the MLSE distribution is offset from the center to the left is mainly because the 3T signal in the playback signal is smaller than the target signal level of the PR (3,4,4,3) ML class.

  FIG. 60 shows the result of operating the automatic equalizer consisting of a 5-Tap FIR filter for the above measurement. The jitter value of the reproduction signal has deteriorated to 13.2% because of the result of automatic equalization so as to approach the target signal of the PR (3,4,4,3) ML class. The measured results of MLSE, S-SEAT, and V-SEAT are small compared to the above case without automatic equalization, and an improvement effect appears.

  FIG. 61 shows the result when playback is performed using the PR (a, b, c, d) ML class for the same measurement. The automatic equalizer is not operating. For calculating the MLSE value, PR (3,4,4,3) at a fixed target level was used as the target signal. The S-SEAT value has been further improved to a small value of 7.3%. On the other hand, the V-SEAT value is larger than that in the case of using the fixed PR (3,4,4,3) ML class shown in FIG. This is because the calculation is performed twice.

  FIG. 62 shows a result of reproducing the same measurement using the PR (a, b, c, d) ML class of the absolute value system. The automatic equalizer is not operating. Since the MLSE value is not defined for the absolute value PRML channel, the unsigned S-SEAT value is shown here instead. The unsigned S-SEAT value is identically defined in the defining equation (Equation D-5),

Calculate as The unsigned S-SEAT value has the same definition as MLSE for the fixed target class in the square system. As described above, the distribution of the unsigned S-SEAT value is distributed on the left half of the zero point as a feature of the absolute value system. Although it will not be described in detail because it deviates from the gist of the present invention, it can be proved that this distribution is explicitly obtained according to the calculation definition of the branch metric value. Now, the S-SEAT and V-SEAT values are distributed to the left and right across the zero point because the edge shifts to the right side due to the sign of the definition formula (Equation D-5). Is also mapped to the right side. From these examples, it is shown that the S-SEAT and V-SEAT of the present invention can be applied to the absolute value PRML channel.

  FIG. 63 shows the change in the V-SEAT value due to the difference in handling of the edge portion for the same measurement. Playback is performed using the PR (a, b, c, d) ML class, and the automatic equalizer is not operated. As described above, since the V-SEAT evaluation index introduces a virtual state, evaluation values for left shift and right shift are calculated for all edges. As mentioned above, there are four types of handling of the edge shift evaluation values, as shown in the figure. Regarding the magnitude of the value, the RMS value decreases in the order of selecting a large value> selecting all values> selecting an average value> selecting a small value, and a natural result is obtained. When using the edge shift evaluation value of the present invention as a phase comparison result of a PLL (Phase Locked Loop) circuit, for example, it is preferable to select an average value. Using normal edge shift evaluation values, for example, when the S / N is poor or the signal amplitude of the minimum run length is small, the command voltage to the VCO (Voltage Controlled Oscilator) is increased (frequency UP / DOWN). Direction). On the other hand, if the evaluation value of edge shift by V-SEAT is used, even in the above case, attention will be paid to the balance of left and right shift, so the command voltage to the VCO is stable and the clock signal is good. Can be obtained. Such a PLL circuit can also be used in an optical disk device described later.

  FIG. 64 shows the change in the V-SEAT value due to the difference in handling of the edge portion for the same measurement. Reproduction is performed using the PR (a, b, c, d) ML class of the absolute value system, and the automatic equalizer is not operated. The above results and trends are the same, except that the RMS value is the smallest when the average value is selected as the edge shift evaluation value. The reason for this can be explained by the feature that, as described above, in the PRML channel of the absolute value system, the branch metric value is only equal to or less than the Euclidean distance, and the unsigned S-SEAT values are distributed to the left of the zero point. Because of these features, the distribution of S-SEAT values is symmetrical with respect to the zero point, so the average of edge shift evaluation values in the horizontal direction is smaller than the minimum value. It is a result.

  FIG. 52 shows the result of evaluating the edge shift amount of the pattern sorted according to the relationship between the preceding and following spaces and marks in the above measurement by MLSE, S-SEAT, and V-SEAT. In the figure, SFP (s, m) represents the leading edge shift, s is the length of the preceding space, and m is the length of the mark. Similarly, ELP (s, m) represents the trailing edge shift, s is the length of the following space, and m is the length of the mark. The definition of edge shift is described below. As pointed out above, the front edge shift SFP (3,3) and the rear edge shift ELP (3,3) cannot be evaluated for MLSE and S-SEAT captured by the run length restriction. On the other hand, it has been shown that V-SEAT with virtual states can evaluate these edge shifts. In addition, in V-SEAT, the hatched portion in the figure that does not include the minimum run length (= 3Tw) does not consider the virtual state, so it is noted that the value is exactly the same as S-SEAT. Thus, it was shown that the shift amount of each edge pattern can be evaluated using S-SEAT or V-SEAT. At the time of recording, a recording condition suitable for PRML can be obtained by performing trial writing to determine a pulse parameter including a width of a recording pulse and an edge position so that these values approach zero most. Similarly, at the time of reproduction, reproduction conditions suitable for PRML can be obtained by performing reproduction equalization conditions and trial reading to determine the focus / offset amount so that they approach zero most.

  FIG. 53 is a schematic diagram showing the flow of test writing for optimizing the recording pulse conditions. In DVD-RAM, recording pulse parameters are defined in a 4 × 4 table for each of the front and rear edges. SFP (s, m) and ELP (s, m) shown above correspond to the recording pulse parameters. The shift amount can be evaluated using the S-SEAT or V-SEAT of the present invention for the edge pattern of the 4 × 4 table. The simple sequence is to first change the recording pulse conditions, record on the optical disk medium, reproduce the sector, evaluate the corresponding S-SEAT or V-SEAT value, and make it approach zero most. In addition, the parameter of the recording pulse is determined. As is clear from this example, the recording pulse parameter and its evaluation value S-SEAT value or V-SEAT value have a one-to-one correspondence, so multiple recording pulse parameters can be changed at once. By performing recording / reproduction, it is possible to shorten the trial writing time by optimizing a plurality of recording pulse parameters in parallel at the same time. Specifically, when the recording pulse parameters are determined in order from the end, the processing time is about 30 seconds to 1 minute in the double speed drive device, whereas when parallel processing is performed according to the present invention, 1 second is required. Trial writing can be completed with a degree. In trial writing using S-SEAT, SFP (3,3) and ELP (3,3) cannot be measured, so the corresponding recording pulse parameter is SFP (3,3) = SFP (3 , 4). However, since this method is only an approximation, it is desirable to use V-SEAT, which can directly measure SFP (3, 3) and ELP (3, 3).

  FIG. 54 shows experimental results obtained by measuring the relationship between the shift amount of the recording pulse position and each evaluation value as an example of test writing using S-SEAT or V-SEAT of the present invention. Here, the experiment was performed by shifting the start position of the DVD-RAM 3Tw mark recording pulse without changing its width. 54 (a), 54 (b), 54 (c), and 54 (d) show MLSE, V-SEAT, PR (a, PR) using the PR (3,4,4,3) class, respectively. b, c, d) Indicates S-SEAT and V-SEAT using classes. In the figure, only SPF (3, 3), SPF (6, 3), ELP (3, 3), and ELP (6, 3) are shown. Although not shown in the above example, as described above, V-SEAT can also be applied to the PR (3,4,4,3) class with a fixed target level. FIG. 54 (b) shows an actual example. As shown in the figure, the linear relationship is established between the position shift of the recording pulse and each evaluation value, and the optimization of the recording pulse parameter can be easily realized by making these close to zero. is there. However, regarding MLSE and S-SEAT, SPF (3, 3) and ELP (3, 3) cannot be evaluated as described above.

  FIG. 55 shows experimental results showing the relationship between the equalization boost amount, the bit error rate, and each evaluation value as an example of trial reading using S-SEAT or V-SEAT of the present invention. Here, the PR (a, b, c, d) class was used as the PR class, and the boost amount was changed by changing the coefficient of the 3-tap FIR filter of the standard equalizer of DVD-RAM. 55 (a), 55 (b), and 55 (c) show the measurement results of MLSE, S-SEAT, and V-SEAT, respectively. Here, PR (a, b, c, d) whose PR class is variable target level was used, but MLSE was calculated by calculating the target level from PR (3,4,4,3). As can be seen in the figure, the marginal center condition of the bit error rate is almost obtained by selecting an equalization boost amount that minimizes each index. In trial reading, it is recommended to measure S-SEAT or V-SEAT while changing the equalization boost amount, and determine the equalization boost amount so that they are minimized.

Next, as an example of application to the RLL (1,7) code, an experimental result at a recording density equivalent to 25 GB of Blu-ray Disc is shown.
The prepared optical disc is the same as described above. A light-once phase change film is laminated on a land / groove structure substrate with a track pitch of 0.34 μm. In the experiment, a DDU-1000 type evaluation device manufactured by Pulstec was used. The wavelength of the light source is 405 nm, and the NA of the objective lens is 0.85. RLL (1,7) was used as the modulation code, and the detection window width Tw was 74.5 nm.

  Fig. 56 shows the measurement results of MLSE, S-SEAT, and V-SEAT when the prototype disc was played back using PR (1, 2, 2, 1) and PR (a, b, c, d) classes. ing. A Blu-ray Disc conventional equalizer was used as the equalizer, and the boost amount was 6.0 dB. A recording power of 3.2 mW and an erasing power of 0.35 mW were recorded once on the groove track, and the reproduction signal quality was evaluated by each method. MLSE is measured with a PR (1,2,2,1) decoder at a fixed target level, measured with a PR (a, b, c, d) decoder at a variable target level, and S-SEAT and V- SEAT was measured. Each evaluation value has a Gaussian distribution as shown in the figure, and the horizontal axis is ± Tw / 2 with the detection window width. The evaluation values were MLSE = 11.4%, S-SEAT = 6.6%, and V-SEAT = 7.0%, respectively. Here, the MLSE value is large and the distribution deviates from the center because the Blu-ray Disc conventional equalizer used as the equalizer is changed to the target signal of PR (1,2,2,1) class. The reason is that it is not equalized so that it is close enough. For example, if automatic equalization using the LSE (Least Square Error) method, etc. is performed using an FIR filter of 7 taps or more, the distribution will be improved, but the booth and amount of 2Tw signal will be increased. This has the negative effect of increasing noise in the high frequency band, so this is not always the best playback condition. On the other hand, when the variable target level PR (a, b, c, d) class is used, the PRML target signal level changes according to the playback signal, so the distribution of S-SEAT and V-SEAT is the center. There is little dispersion.

  FIG. 57 shows the result of evaluating the edge shift amount of the pattern sorted according to the relationship between the preceding and following spaces and the marks by MLSE, S-SEAT, and V-SEAT in the above measurement. For MLSE and S-SEAT captured by the run length restriction, the front edge shift SFP (2,2) and the rear edge shift ELP (2,2) cannot be evaluated. On the other hand, it has been shown that V-SEAT with virtual states can evaluate these edge shifts. In V-SEAT, the value of the portion not including the minimum run length (= 2Tw) is the same value as S-SEAT. Thus, it was shown that the shift amount of each edge pattern can be evaluated using S-SEAT or V-SEAT. At the time of recording, a recording condition suitable for PRML can be obtained by performing trial writing to determine a pulse parameter including a width of a recording pulse and an edge position so that these values approach zero most. Similarly, by performing trial readings that determine playback equalization conditions and focus / offset amounts so that they are closest to zero during playback, or so that the value of S-SEAT or V-SEAT is minimized, Playback conditions suitable for PRML can be obtained.

  FIG. 58 shows experimental results showing the relationship among equalization boost amount, bit error rate, and V-SEAT value as an example of trial reading using V-SEAT of the present invention. Here, the PR (a, b, c, d) class was used as the PR class. In order to demonstrate that V-SEAT is applicable to an absolute value Viterbi decoder, FIG. 58 (b) shows the results for an absolute value Viterbi decoder. As can be seen in the figure, the marginal center condition of the bit error rate can be almost obtained by selecting an equalization boost amount that minimizes V-SEAT. In trial reading, it is recommended to measure V-SEAT while changing the equalization boost amount and determine the equalization boost amount so that they are minimized. Here, the experimental results are shown only for V-SEAT, but it is also possible to determine equalization conditions for S-SEAT in the same manner as described above. Of course, S-SEAT can also be applied to an absolute value Viterbi decoder.

Optical Disk Device FIG. 50 is an example showing the configuration of the optical disk device of the present invention. The optical disk medium 100 is rotated by a motor 160. At the time of reproduction, the laser power / pulse controller 120 controls the current passed through the semiconductor laser 112 in the optical head 110 to generate the laser beam 114 so that the light intensity commanded by the CPU 140 is obtained. To form a light spot 101 on the optical disc medium 100. The reflected light 115 from the light spot 101 is detected by the photodetector 113 through the objective lens 111. The photodetector is composed of a plurality of photodetecting elements. The reproduction signal processing circuit 130 reproduces information recorded on the optical disc medium 100 using the signal detected by the optical head 110. At the time of recording, the laser power / pulse controller 120 converts predetermined recording data into a predetermined recording pulse current and controls the pulsed light to be emitted from the semiconductor laser 112. The decoding unit 10, the target level learning unit 20, and the signal evaluation unit 30 constituting the reproduction signal evaluation circuit of the present invention are built in the reproduction signal processing circuit 130.

  When evaluating the quality of the reproduction signal, it is sufficient to evaluate the S-SEAT or V-SEAT by reproducing the data according to an instruction from the CPU 140 during trial writing. By learning (1) focus offset, (2) equalization conditions, and (3) recording power and pulse conditions so that these values are minimized, the recording and playback conditions can be optimized. The operation can be stabilized.

The figure which shows the structural example of the calculation circuit of S-SEAT mounted in the optical disk apparatus of this invention. A diagram summarizing some of the bit error patterns when decoding using the PR (1,2,2,1) class in the RLL (1,7) code. The figure which summarized the error pattern and Euclidean distance of PR (1,2,1) class in RLL (1,7) code. A diagram summarizing PR (1,2,2,2,1) class error patterns and Euclidean distance in the RLL (1,7) code. The figure which summarized the error pattern and Euclidean distance of PR (1,1,1,1) class in RLL (1,7) code. The figure which put together the direction of edge shift with respect to the minimum Euclidean distance pattern of PR (1,2,2,1) class in RLL (1,7) code. The figure which summarized about the target signal level of PR (1,2,2,1) class corresponding to RLL (1,7) code. Summarizes the signal levels corresponding to each bit string of the PR (1,2,2,1) Viterbi decoder unit and playback signal quality evaluation unit corresponding to the RLL (1,7) code, and whether they are valid or invalid. Figure. A diagram summarizing error patterns when calculating V-SEAT for the PR (1,2,2,1) class. The figure which put together the bit string of PRML of the variable target level of 4 class bits, and the target signal level. A diagram summarizing the definitions and features of MLSE, S-SEAT, and V-SEAT. The figure which put together the Euclidean distance and the direction of edge shift about the 1-bit error pattern with respect to PR (1, 2, 1) and PR (a, b, c) class corresponding to RLL (1, 7) code. The figure which put together the target signal level of the PR (a, b, c) ML decoder in which the target level corresponding to the RLL (1, 7) code is variable. The figure which summarized the detection pattern of V-SEAT and the direction of edge shift with respect to PR (1, 2, 1) and PR (a, b, c) class corresponding to RLL (1, 7) code. The figure which put together the target signal level of PR (1,2,1) ML decoder with a fixed target level corresponding to RLL (1,7) code. The figure which put together the target signal level of the PR (a, b, c) ML decoder in which the target level corresponding to the RLL (1, 7) code is variable. For 1-bit error patterns for PR (1,2,2,2,1) and PR (a, b, c, d, e) classes corresponding to RLL (1,7) codes, the Euclidean distance and edge shift The figure which summarized direction. The figure which put together the target signal level of PR (a, b, c, d, e) ML decoder with variable target level corresponding to RLL (1,7) code. V-SEAT detection pattern and edge shift direction for PR (1,2,2,2,1) and PR (a, b, c, d, e) classes corresponding to RLL (1,7) code Summary figure. The figure which put together the target signal level of PR (1,2,2,2,1) ML decoder with a fixed target level corresponding to a RLL (1,7) code. The figure which put together the target signal level of PR (a, b, c, d, e) ML decoder with variable target level corresponding to RLL (1,7) code. For 1-bit error patterns for PR (1,2,3,3,2,1) and PR (a, b, c, d, e, f) classes corresponding to RLL (1,7) codes, The figure which summarized the direction of edge shift. The figure which put together the target signal level of PR (a, b, c, d, e, f) ML decoder with variable target level corresponding to RLL (1, 7) code. V-SEAT detection pattern and edge for PR (1,2,3,3,2,1) and PR (a, b, c, d, e, f) classes corresponding to RLL (1,7) code The figure which summarized the direction of the shift. The figure which put together the target signal level of PR (1,2,3,3,2,1) ML decoder with a fixed target level corresponding to a RLL (1,7) code. The figure which put together the target signal level of PR (1,2,3,3,2,1) ML decoder with a fixed target level corresponding to a RLL (1,7) code. The figure which put together the target signal level of PR (a, b, c, d, e, f) ML decoder with variable target level corresponding to RLL (1, 7) code. The figure which put together the target signal level of PR (a, b, c, d, e, f) ML decoder with variable target level corresponding to RLL (1, 7) code. Summary of Euclidean distance and edge shift direction for 1-bit error patterns for PR (1,2,2,1) and PR (a, b, c, d) classes corresponding to RLL (1,7) codes Figure. The figure which put together the target signal level of the PR (a, b, c, d) ML decoder in which the target level corresponding to the RLL (1, 7) code is variable. The figure which put together the detection pattern of V-SEAT and the direction of edge shift with respect to PR (1, 2, 2, 1) and PR (a, b, c, d) classes corresponding to RLL (1, 7) codes. The figure which put together the target signal level of PR (1,2,2,1) ML decoder with a fixed target level corresponding to RLL (1,7) code. The figure which put together the target signal level of the PR (a, b, c, d) ML decoder in which the target level corresponding to the RLL (1, 7) code is variable. Summary of Euclidean distance and edge shift direction for 1-bit error patterns for PR (3,4,4,3) and PR (a, b, c, d) classes corresponding to RLL (2,10) code Figure. The figure which put together the target signal level of the PR (a, b, c, d) ML decoder in which the target level corresponding to the RLL (2, 10) code is variable. The figure which put together the detection pattern of V-SEAT and the direction of edge shift with respect to PR (3,4,4,3) and PR (a, b, c, d) class corresponding to RLL (2, 10) code. The figure which put together the target signal level of PR (3,4,4,3) ML decoder with a fixed target level corresponding to RLL (2,10) code. The figure which put together the target signal level of the PR (a, b, c, d) ML decoder in which the target level corresponding to the RLL (2, 10) code is variable. The figure which shows the Example in the case of calculating | requiring on the assumption that the target signal level of PR (a, b, c) ML decoder with a variable target level corresponding to RLL (1,7) code | symbol is zero asymmetry amount. The figure which shows the Example in the case of calculating | requiring the target signal level of PR (a, b, c, d) ML decoder with variable target level corresponding to RLL (1,7) code | symbol assuming that the amount of asymmetry is zero. The figure which shows the Example in the case of calculating | requiring on the assumption that the target signal level of PR (a, b, c, d) ML decoder with variable target level corresponding to RLL (2,10) code | symbol is zero. The figure which shows the structural example of the calculation circuit of V-SEAT mounted in the optical disk apparatus of this invention. The figure which shows another structural example of the calculation circuit of S-SEAT mounted in the optical disk apparatus of this invention. The figure which shows another structural example of the calculation circuit of S-SEAT mounted in the optical disk apparatus of this invention. The figure which shows another structural example of the calculation circuit of S-SEAT mounted in the optical disk apparatus of this invention. The figure which shows the structural example of the calculation circuit of S-SEAT and V-SEAT mounted in the optical disk apparatus of this invention. (1 + D) A diagram of experimental results showing the relationship between recording capacity and bit error rate for ⁿ series. The figure of the experimental result which shows the relationship between recording capacity and a bit error rate with respect to (1,2, ..., 2,1) series. The figure of the experimental result which shows the relationship between recording capacity and a bit error rate with respect to an impulse response approximation series. Explanatory drawing of the Example which shows the basic concept of the information reproduction method of a compensation type PRML system. The figure of the experimental result which shows the difference in capacity increase performance with a compensation type PRML system and other PRML systems. The figure which shows the structural example of the optical disk apparatus of this invention. The figure which shows the measurement result of MLSE, S-SEAT, and V-SEAT when a DVD-RAM disk is reproduced using PR (3,4,4,3) class. Edge shift of patterns sorted according to the relationship between front and rear spaces and marks when DVD-RAM discs are played using PR (3,4,4,3) and PR (a, b, c, d) classes The figure which shows the result of having evaluated quantity by MLSE, S-SEAT, and V-SEAT. The schematic diagram which shows the flow of the test writing which optimizes the conditions of a recording pulse. The figure of the experimental result which measured the relationship between the shift amount of the position of a recording pulse, and each evaluation value as an example of trial writing using S-SEAT or V-SEAT of this invention. The figure of the experimental result which shows the relationship between equalization boost amount, a bit error rate, and each evaluation value as an example of the trial reading using S-SEAT or V-SEAT of this invention. The figure which shows the measurement result of MLSE, S-SEAT, and V-SEAT when a prototype disk is reproduced using PR (1, 2, 2, 1) and PR (a, b, c, d) classes. When the prototype disc was reproduced using the PR (1, 2, 2, 1) and PR (a, b, c, d) classes, the edge shift amount of the pattern sorted according to the relationship between the space before and after and the mark The figure which shows the result evaluated by MLSE, S-SEAT, and V-SEAT. The figure of the experimental result which shows the relationship between equalization boost amount, a bit error rate, and V-SEAT value as an example of the trial reading using V-SEAT of this invention. FIG. 6 is a schematic diagram showing a pattern / detector determination status and an evaluation value calculation operation for time t. The figure which shows the measurement result of MLSE, S-SEAT, and V-SEAT when a DVD-RAM disk is reproduced using PR (3,4,4,3) class. The figure which shows the measurement result of MLSE, S-SEAT, and V-SEAT when reproducing a DVD-RAM disc using PR (a, b, c, d) using a class. The figure which shows the measurement result of MLSE, S-SEAT, and V-SEAT when reproducing the DVD-RAM disc using PR (a, b, c, d) of absolute value system using classes. The figure which shows the measurement result of V-SEAT by the difference in the handling of the value of an edge part when reproducing a DVD-RAM disc using PR (a, b, c, d) using a class. The figure which shows the measurement result of V-SEAT by the difference in the handling of the value of an edge part when reproducing the PR-value (a, b, c, d) of the absolute value type | system | group using a class.

DESCRIPTION OF SYMBOLS 10 ... Decoding unit 11 ... Waveform equalizer 12 ... Branch metric calculation unit 13 ... ACS unit 14 ... Path memory 15 ... PR target table 16 ... Pattern compensation table 17 ... Target level table 18 ... Limited target level table 19 ... Mode control unit 191 ... Switch 20 ... Target level learning unit 21 ... Target level calculation unit 22 ... Error calculation And averaging unit 24 ... pattern detector 25 ... averaging unit 26 ... error calculation and operation control unit 27 ... switch 30 ... signal evaluation unit 31 ... pattern selection unit 32 ... Target level calculation unit 33 ... Target level calculation unit 34 ... Sequence error evaluation unit 35 ... Target target level calculation unit 50 ... reproduction signal 51 ... binarization result 52 ... correction value 53 ... "True" pattern 54 ... "False" pattern 55 ... evaluation value 100 ... Optical disc 101 ... Optical spot 110 ... Optical head 111 ... Objective lens 112 ... Semiconductor laser 113 ... Photo detector 120 ... Recording data controller 130 ... Reproduction signal processor 140 ... CPU
150 ... Servo controller 160 ... Spindle motor 170 ... Interface 180 ... Host computer

Claims (1)

A method for evaluating a playback signal corresponding to the PRML system,
In the PRML system, the target signal level can be changed according to the reproduction signal,
A process of generating a decoded positive bit string and an erroneous bit string shifted from the bit string by one bit edge,
A step of generating a positive target signal and an erroneous target signal from the positive bit sequence and the erroneous bit sequence with reference to the target signal level
Calculating a sum of squares of signal level differences at each time of the positive target signal and the reproduction signal to calculate a positive Euclidean distance;
Calculating a sum of squares of signal level differences at each time of the erroneous target signal and the reproduction signal to calculate an erroneous Euclidean distance;
Calculating a Euclidean distance difference as a difference between the positive Euclidean distance and the incorrect Euclidean distance;
Calculating an average Euclidean distance corresponding to a 1-bit shift pattern of the target signal level from the target signal level;
Subtracting the average Euclidean distance from the Euclidean distance difference and then dividing by the average Euclidean distance to calculate a normalized sequence error;
A method for evaluating a reproduction signal, comprising the step of evaluating the reproduction signal using a normalized sequence error.