JP2007034431A - Memory controller - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To efficiently reduce write frequency of data in a non-volatile memory such as an EEPROM, and to prolong a service life. <P>SOLUTION: The control part 11 of a memory controller 1 temporarily writes data to be written in a non-volatile memory 2 in the data region of a volatile memory 12. In this case, a control part 11 writes ID showing the written data in the ID region of a volatile memory 12. When the data are written in the non-volatile memory 2, the control part 11 specifies data to be written in the same block from the data written in the data region on the basis of the ID registered in the ID region, and collectively writes the specified data in the non-volatile memory 2. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a technique for efficiently writing data to a nonvolatile memory.

  In some nonvolatile memories, the value of the storage area becomes undefined when data is repeatedly written. This type of memory is provided with a limit value for the number of times of writing by the manufacturer. The value is, for example, about 100,000 to 1,000,000 times in the case of an EEPROM (Electronically Erasable and Programmable Read Only Memory). In the EEPROM, a block is formed for each storage area of a predetermined size, and the above limit value is set for each block.

When such a nonvolatile memory is used in a computer, control is performed such that the number of times of writing processing to the nonvolatile memory is reduced in order to extend the life of the nonvolatile memory. For example, in the technique described in Patent Document 1, data to be written to a nonvolatile memory (nonvolatile memory circuit unit 22) is updated while being stored in a volatile memory (volatile memory circuit unit 21), and is volatile when the power is turned off. The number of times data is written to the non-volatile memory is reduced by performing batch processing of writing data in the non-volatile memory into the non-volatile memory. Further, in the technique described in Patent Document 2, when writing the number of times the motor is driven and the lighting time of the light source as a count value in the nonvolatile memory (EEPROM), “1” is originally written every time it is counted. The number of times of writing to the non-volatile memory is reduced by performing a process of writing “n” once when n is counted.
JP-A-8-241599 JP 2000-339506 A

  However, the following inconveniences are recognized in the techniques described in Patent Documents 1 and 2 described above. In the case of the technique described in Japanese Patent Laid-Open No. 2004-260, a single write process is required to write one piece of data, although the batch write is performed when the power is turned off. That is, if x pieces of data are to be written, x number of writing processes will eventually occur, and it cannot be said that the number of times of writing has been efficiently reduced.

  In the case of the technique described in Patent Document 2, the same inconvenience as in Patent Document 1 can occur. In addition, in the case of the technique described in Patent Document 2, since the number of times of writing is merely reduced by thinning out the writing process, the value that should be originally written and the value that is actually written In some cases, errors occurred.

  The present invention has been made in view of the above-described circumstances, and an object of the present invention is to provide a technique for efficiently reducing the number of times data is written to a nonvolatile memory and extending its life.

  In order to achieve the above object, the present invention provides a memory control device that reads or writes data via a volatile memory with respect to a nonvolatile memory in which a storage area is divided into blocks. First writing means for writing data to be written in a predetermined block of the volatile memory to the volatile memory together with identification information indicating the block, and using the identification information written by the first writing means, Search means for specifying data to be written to the same block among data written to the volatile memory, and second writing for collectively writing the data specified by the search means to the block to be written Means.

  According to such a memory control device, the data to be written to the nonvolatile memory by the first writing means is once written to the volatile memory, and the searching means is stored in the same block from the data written to the volatile memory. Identify the data to be written. The second writing means collectively writes one or a plurality of data specified at this time to the nonvolatile memory, so that the data written to the same block can be written in one time regardless of the number of data. Can write.

  In the present invention, the memory control device compares the data specified by the search means with the data written in the block to be written, which is the block in which the data is to be written, and whether there is a difference between the two. The second writing means has a configuration in which writing to the block to be written is not performed when it is determined by the determining means that there is no difference between them. And more desirable. In this way, the writing process is performed only for blocks in which a difference occurs before and after writing.

  In the present invention, the memory control device includes a detection unit that detects the occurrence of a predetermined process, and the second writing unit writes data when the detection unit detects the occurrence of the process. You may have the structure which performs. In this case, the “determined process” is, for example, a process of shutting off the power supply or a process of starting the power saving mode by the connected host device. Of course, this instruction may be input directly by the user.

  As described above, according to the present invention, it is possible to efficiently reduce the number of times data is written to the nonvolatile memory and extend its life.

Embodiments of the present invention will be described below with reference to the drawings.
[1. Constitution]
FIG. 1 is a block diagram showing a data processing apparatus 100 according to an embodiment of the present invention. The data processing apparatus 100 is mounted on, for example, an electrophotographic image forming apparatus, and controls reading and writing of data with respect to the nonvolatile memory 2. The data processing device 100 is roughly divided into a memory control device 1, a nonvolatile memory 2, and an ASIC (Application Specific Integrated Circuit) 3.

  The memory control device 1 includes a control unit 11 and a volatile memory 12. The control unit 11 is, for example, a CPU (Central Processing Unit), and controls reading and writing of data in the data processing apparatus 100 by executing a predetermined program (not shown). The volatile memory 12 is, for example, a RAM (Random Access Memory), and is used as a working area of the control unit 11. A part of the volatile memory 12 is used as a “data area” or an “ID area”. Data stored in the nonvolatile memory 2 is written in the data area, and an ID for identifying data to be written in the nonvolatile memory 2 is written in the ID area.

  Note that the control unit 11 is configured to be able to detect the states of the switch SW and the timer TM. Here, the switch SW is an operator for controlling on / off of a host device such as an image forming apparatus, and the control unit 11 stops the host device when the switch SW is turned off. The timer TM is a timing device that measures the idle time of the host device, that is, the time during which no operation is instructed by the user. Here, the state in which the user does not instruct the host device for any operation is referred to as an “idle state”.

  The nonvolatile memory 2 is, for example, an EEPROM, and retains the stored contents even when the host device is turned off. For example, when the host device is an electrophotographic image forming apparatus, the data stored in the non-volatile memory 2 includes a “registration adjustment value” for determining an image position on a sheet and a “transfer potential” for transferring toner. ”Or various parameters such as“ fixing temperature ”for fixing the toner onto the paper. These values are rewritten based on an instruction from the user or a well-known calibration execution result.

  Here, the data configuration of the nonvolatile memory 2 is illustrated in FIG. In the figure, each cell represents a 1-byte storage area, and n bytes form one block. By providing m such blocks, the nonvolatile memory 2 has a storage capacity of “m × n” bytes as a whole.

  Further, the nonvolatile memory 2 has a configuration in which a counter is provided. Here, the leftmost cell of each block is secured as counters B1_Cnt to Bm_Cnt, and when data is written to the corresponding block, the value increases by “1”. Since these cells are exclusively used as the counter of the number of times of writing, they are not included in the storage capacity described above.

In the following, the entire cell in the i-th row is referred to as “block Bi”, and the cell in the i-th row and j-th column is referred to as “cell B _i D _j ”. That is, the leftmost cell of the block “B1” is “B ₁ D ₁ ”, the right and lower cells are “B ₁ D ₂ ” and “B ₂ D ₁ ”, respectively. In this manner, the definition is made up to the cell “B _m D _n ” at the lower right corner of the figure. The block Bm is also referred to as a “final block”.

  The ASIC 3 is an integrated circuit for executing specific image processing. In the present embodiment, a read or write operation is performed on the nonvolatile memory 2 under the control of the memory control device 1. The ASIC 3 is connected to the nonvolatile memory 2 by wire or wirelessly and performs serial communication with the nonvolatile memory 2.

[2. Operation]
Based on the above configuration, the data processing apparatus 100 reads and writes data. The specific operation of the data processing apparatus 100 will be described below. First, in order to clarify the difference from the conventional data writing process represented by Patent Documents 1 and 2, the conventional data processing apparatus 100 is used. An operation example will be described, and then two operation examples of the present embodiment will be shown.

[2-1. Conventional example]
FIG. 3 is a flowchart showing a conventional writing process. Explaining along the figure, first, the control unit 11 of the data processing apparatus 100 detects that the power is turned on by the user and the switch SW is turned on (step S101). When detecting the ON state of the switch SW, the control unit 11 reads all data in the nonvolatile memory 2 and copies it to the data area of the volatile memory 12 (step S102).

  Here, the control unit 11 determines whether or not a rewrite instruction is generated for the data in the nonvolatile memory 2 (step S103). An instruction to rewrite data in the nonvolatile memory 2 is generated based on the above-described instruction from the user or the execution result of the calibration. When a data rewrite instruction is generated (step S103; YES), the control unit 11 specifies data to be rewritten from the data area of the volatile memory 12 and writes the value (step S104). Note that the data written at this time is not limited to data corresponding to a single cell but may be data corresponding to a plurality of cells.

After writing data in the volatile memory 12, the control unit 11 registers an ID for specifying the position of the data in the ID area of the volatile memory 12 (step S105). The ID registered in the ID area may be in any format as long as the position of the data in the nonvolatile memory 2 can be identified and specified, but here, for convenience of explanation, the code of each cell, that is, “B ₁ D It will be used ₁ "to the" _B m _{D n} "as ID.

  Subsequently, the control unit 11 determines whether or not an ID is registered in the ID area of the volatile memory 12 (step S106). If the ID is registered in the ID area (step S106; YES), this means that there is data to be written to the nonvolatile memory 2, and therefore the control unit 11 writes the data to the nonvolatile memory 2. Process. On the other hand, when the ID is not registered in the ID area (step S106; NO), the control unit 11 again waits for an instruction to rewrite data in the nonvolatile memory 2 (step S103).

The process of writing data to the nonvolatile memory 2 is performed in the following procedure. First, the control unit 11 reads out data to be rewritten from the nonvolatile memory 2 in units of blocks based on the head ID registered in the ID area (step S107). For example, when the ID of the ID area indicates data of the cell “B ₁ D ₁ ”, the control unit 11 reads the entire data of the block “B 1” of the nonvolatile memory 2. The block read at this time is hereinafter referred to as a “written block”.

  Subsequently, the control unit 11 updates the read data of the block to be written using the data stored in the data area of the volatile memory 12 (step S108). At this time, the control unit 11 updates the entire block to be written at once, but the values of the portions other than the data indicated by the ID registered in the ID area are not changed before and after the update. Thereafter, the control unit 11 adds “1” to the counter of the read block to be written (step S109), and writes the updated data in the nonvolatile memory 2 (step S110).

  After writing data in the nonvolatile memory 2, the control unit 11 deletes the ID corresponding to the written data from the ID area of the volatile memory 12 (step S111). And the control part 11 judges the presence or absence of ID again (step S106), and if there exists ID registered into the ID area | region of the volatile memory 12, the process of step S107-S111 mentioned above will be repeated.

As described above, the control unit 11 determines the presence or absence of an ID registered in the ID area, and sequentially writes the rewritten data to the nonvolatile memory 2 based on the ID. Hereinafter, this process will be described with a specific example. In this example, four IDs indicating data of cells “B ₁ D ₁ ”, “B ₂ D ₁ ”, “B ₁ D ₃ ”, and “B ₁ D _n ” are registered in order in the ID area. (“B ₁ D ₁ ” is the head ID). The data written to each cell at this time is “B ₁ D ₁ ” is “α”, “B ₂ D ₁ ” is “β”, “B ₁ D ₃ ” is “γ”, and “B ₁ D _n”. ”Is“ δ ”, and the counters of each block are all“ 0 ”.

FIG. 4 is a schematic diagram showing the writing process performed according to the above-described example. First, when the data “α” is written, the control unit 11 specifies the block to be written as “B1” from the ID in the ID area, updates this data, and writes it in the nonvolatile memory 2. As a result, as shown in FIG. 4A, the cell “B ₁ D ₁ ” is rewritten to “α”, and the counter “B1_Cnt” of the block B1 is increased to “1”. Further, the ID indicating the cell “B ₁ D ₁ ” is deleted from the ID area, and the ID indicating the cell “B ₂ D ₁ ” is the head, that is, the processing target.

Subsequently, when the data “β” is written, the control unit 11 specifies the block to be written as “B2” from the ID of the ID area. Thereafter, data is written in the nonvolatile memory 2 in the same manner as in FIG. As a result, as shown in FIG. 4B, the cell “B ₂ D ₁ ” is rewritten to “β”, and the counter “B2_Cnt” of the block B2 is increased to “1”. Further, the ID indicating the cell “B ₂ D ₁ ” is deleted from the ID area, and the ID indicating the cell “B ₁ D ₃ ” is the top.

Subsequently, when the data “γ” is written, the control unit 11 similarly identifies the block to be written and writes the data. As a result, as shown in FIG. 4 (3), the cell “B ₁ D ₃ ” is rewritten to “γ”, and the counter “B1_Cnt” of the block B1 is increased to “2”. Further, when the data “δ” is written, the cell “B ₁ D _n ” is rewritten to “δ” as shown in FIG. 4 (4), and the counter “B1_Cnt” of the block B1 is increased to “3”. When these processes are completed, the ID area of the volatile memory 12 becomes empty, and the state returns to an unregistered state.

  As described above, when the process of writing data α to δ is performed according to the conventional example, the total number of times is four. As a result of these processes, the counter “B1_Cnt” of the block B1 is increased by “3” from before the process, and the counter “B2_Cnt” of the block B2 is increased by “1” from before the process.

[2-2. Operation example 1]
Subsequently, a first operation example according to the present embodiment will be described with reference to FIG. FIG. 5 is a flowchart showing the writing process of this operation example. In the writing process of this operation example, the procedure (steps S101 to S107) from the detection of the ON state of the data processing apparatus 100 to the reading of the data in the nonvolatile memory 2 is the same as that of the above-described conventional example. . Therefore, the description of these processes is omitted.

  In this operation example, the control unit 11 reads the data to be rewritten from the nonvolatile memory 2 in block units in step S107, and then writes the data to the same block as the ID at the head of the ID area of the volatile memory 12 Is searched from the volatile memory 12 (step S201). That is, when the data indicated by the head ID in the ID area is data to be written in the block “B1”, the control unit 11 searches the ID area of the volatile memory 12 for the ID in which the block to be written indicates “B1”. To do. Based on the search result, the control unit 11 determines whether other IDs having the same write target block are registered (step S202).

  When IDs having the same write target block are registered (step S202; YES), the control unit 11 updates the read data of the write target block using data indicated by these IDs (step S202). S203). At this time, since there are a plurality of IDs having the same write target block, the values of the plurality of data change simultaneously. After updating the data, the control unit 11 adds “1” to the counter of the block to be written (step S204), and writes the updated data to the nonvolatile memory 2 (step S207).

  On the other hand, when IDs with the same block to be written are not registered (step S202; NO), the same processing as steps S108 and S109 of the conventional example described above is performed. That is, the control unit 11 updates the read data of the block to be written using the data stored in the data area of the volatile memory 12 (step S205). The data whose value changes before and after the update is only one data indicated by the ID registered in the ID area, as in the conventional example. After updating the data, the control unit 11 adds “1” to the counter of the block to be written (step S206), and writes the updated data in the nonvolatile memory 2 (step S207).

  After writing the data in the nonvolatile memory 2, the control unit 11 deletes the ID corresponding to the written data from the ID area of the volatile memory 12 (step S208). At this time, if the determination in step S202 is “YES”, a plurality of IDs indicating the same block are simultaneously deleted. And the control part 11 judges the presence or absence of ID again (step S106), and repeats a subsequent process.

The writing process of this operation example is as described above. Subsequently, the operation when such a writing process is performed will be described, and the difference from the conventional example will be clarified. Therefore, here, as in the above-described conventional example, four IDs indicating data of cells “B ₁ D ₁ ”, “B ₂ D ₁ ”, “B ₁ D ₃ ”, and “B ₁ D _n ” in the ID area. A case where is registered will be described as an example. At this time, the data written to each cell is “B ₁ D ₁ ” is “α”, “B ₂ D ₁ ” is “β”, “B ₁ D ₃ ” is “γ”, and “B ₁ D _n ” is “B ₁ D ₁ ”. It is assumed that “δ”, and the counters of each block are “0”.

FIG. 6 is a schematic diagram showing the writing process performed according to the above-described example. First, when data “α” is written, the control unit 11 identifies the block to be written as “B1” from the ID in the ID area, and searches for an ID indicating data to be written in this block “B1”. To do. In this case, in addition to the data “α”, the data “γ” and “δ” are data to be written in the block “B1”, and therefore “B ₁ D ₃ ” and “B ₁ D _n ” are specified. The control unit 11 simultaneously updates these data “α”, “γ”, and “δ”, and writes them in the write target block of the nonvolatile memory 2.

As a result, as shown in FIG. 6A, the cells “B ₁ D ₁ ”, “B ₁ D ₃ ”, and “B ₁ D _n ” are rewritten to “α”, “γ”, and “δ”, respectively. The counter “B1_Cnt” of the block B1 increases to “1”. At this time, three IDs indicating the cells “B ₁ D ₁ ”, “B ₁ D ₃ ”, and “B ₁ D _n ” are deleted from the ID area, and the ID indicating the cell “B ₂ D ₁ ” is the top, It becomes a processing target.

Next, a case where data “β” is written will be described. At this time, the control unit 11 identifies the block to be written as “B2” from the ID in the ID area, and writes the updated value of the cell “B ₂ D ₁ ” in the block to be written. The control unit 11 increases the counter “B2_Cnt” of the block B2 to “1” and deletes the ID indicating the cell “B ₂ D ₁ ” from the ID area. As a result, as shown in FIG. 6 (2), the ID area of the volatile memory 12 becomes empty, and the state returns to an unregistered state.

  As described above, when the process of writing the data α to δ is performed according to this operation example, the total number of times is two. As a result of these processes, the counters “B1_Cnt” and “B2_Cnt” of the blocks B1 and B2 respectively increase by “1” from before the processes. As is clear from comparison of FIG. 6 with FIG. 4, in this operation example, when data similar to that in the above-described conventional example is written, the number of times of writing can be reduced to suppress an increase in the value of the counter. It becomes possible. Therefore, it is possible to extend the lifetime of the nonvolatile memory 2 by performing such a writing process.

[2-3. Operation example 2]
Next, a second operation example according to this embodiment will be described. This operation example is different from operation example 1 described above in two points. The first point is that in this operation example, the control unit 11 does not register an ID in the ID area of the volatile memory 12 until a predetermined event that instructs writing to the volatile memory 12 occurs. . The second point is that in this operation example, when there is no difference between the data of the block to be written and the data to be written to the block, the data is not updated. Hereinafter, description will be made centering on these differences, and description of portions where processing similar to that of the above-described operation example 1 is performed will be omitted as appropriate.

  FIG. 7 is a flowchart showing the writing process of this operation example. In the writing process of this operation example, the procedure (steps S101 to S104) from the detection of the ON state of the data processing apparatus 100 to the writing of data to the volatile memory 12 is the above-described conventional example and operation example 1 described above. It is the same.

  After writing data to the volatile memory 12, the control unit 11 waits for a write instruction event (step S301). Here, the “write instruction event” refers to an event (event) that needs to be written to the nonvolatile memory 2 that occurs in the host device. When a write instruction event occurs, a signal indicating the occurrence of the event is supplied from the host device to the control unit 11.

  Note that the write instruction event includes a plurality of events. For example, an instruction to start a “power saving mode” for reducing power consumption of the host apparatus or an instruction to shut down the power of the host apparatus by the user is an example. . Here, the “power saving mode” is a mode that is started when the host device is in an idle state (a state in which no data is input or operated) for a certain period of time. A predetermined operation by the user may be included in the write instruction event.

  While there is no write instruction event (step S301; NO), the control unit 11 waits for a rewrite instruction for data in the nonvolatile memory 2 (step S103), and writes data to the volatile memory 12 as needed according to the rewrite instruction. (Step S104). When the occurrence of a write instruction event is detected (step S301; YES), IDs corresponding to all data written in the data area of the volatile memory 12 so far are registered in the ID area of the volatile memory 12. (Step S302).

  When the ID registration is completed, the control unit 11 searches for an ID having the block to be written as the block “B1” (step S303). In FIG. 7, the block to be written is described as “Bi” for convenience of explanation. Here, the value “i” is defined as a variable that increases by 1 with “1” as an initial value. This variable i is incremented in step S312 described later. Therefore, in the following description, “Bi” is read as “B1” in each step until the process of step S312 is performed, and thereafter “B2” and “B3” are performed every time the process of step S312 is performed. It shall be read as appropriate.

  Subsequently, the control unit 11 determines the presence / absence of an ID whose block to be written is the block “B1” based on the result of the search (step S304). When there is an ID in which the data write block is the block “B1” (step S304; YES), the control unit 11 reads the data from the block “B1” of the nonvolatile memory 2 in units of blocks (step S305). The read data of the block “B1” is compared with the data to be written to the block “B1” to determine whether or not there is a difference between them (step S306).

  In this comparison, if there is a difference in both places (step S306; YES), the control unit 11 updates the entire data of the block “B1” (step S307). Then, the control unit 11 adds “1” to the counter of the block “B1” (step S308), and writes the updated data to the block “B1” of the nonvolatile memory 2 (step S309). At this time, similarly to the above-described operation example 1, data corresponding to a plurality of IDs is written by one writing process, so the increment of the counter is “1”. When the writing of data to the nonvolatile memory 2 is completed, the control unit 11 deletes the ID corresponding to the written data from the ID area of the volatile memory 12 (step S310).

  On the other hand, if there is no difference between the two in the comparison in step S306 (step S306; NO), the control unit 11 skips the processes in steps S307 to S309 described above and deletes the ID (step S310). That is, at this time, the control unit 11 continues the process without writing to the nonvolatile memory 2. Since the process of step S308 is not performed, the counter is not added at this time.

  After deleting the ID, the control unit 11 subsequently determines whether or not the block to be written is “Bm” (step S311). That is, this means that it is determined whether or not the block to be written is the last block in the data area. Here, since the block to be written is the block “B1”, it is not the final block (step S311; NO). Therefore, the control unit 11 increments the variable i to set the value to “2” (step S312), sets the block to be written to block “B2”, and repeats the processing from step S303.

  If there is no ID in which the data writing block is the block “B1” (step S304; NO), the control unit 11 skips the processing from step S305 to S310. That is, at this time, the control unit 11 advances the processing to the next block without performing any processing on the block to be written.

  The controller 11 writes data sequentially from the block “B1” in the manner described above. Then, when the block to be written finally becomes the block “Bm”, that is, the final block, the control unit 11 ends this processing. After the end of this process, the data processing apparatus 100 performs an operation for shutting off the power, starting the power saving mode, or the like according to the type of the write instruction event.

  By performing the processing as described above, the number of times of writing to the nonvolatile memory 2 can be further reduced as compared with the above-described operation example 1. In this operation example, as shown in step S301, data is written to the nonvolatile memory 2 using a write instruction event as a trigger (trigger). Therefore, more IDs can be registered in the ID area than in the first operation example in which data is written to the nonvolatile memory 2 using the ID registration as a trigger. If more IDs are registered, naturally, the number of data to be simultaneously written at one time increases, so that the number of times of writing can be reduced accordingly. In addition, in this processing, since each block is written only once or once, even if the number of data instructed to be rewritten is large, the counter of each block increases by “2” or more. There is nothing.

  In this operation example, the data of the block read from the nonvolatile memory 2 in step S306 is compared with the data to be written to this block, and if there is no difference between them, the data is not written to the nonvolatile memory 2. The number of times of writing is also reduced by performing an appropriate process.

  As described above, the data written in the nonvolatile memory 2 includes various parameters such as “registration adjustment value”, “transfer potential”, and “fixing temperature”. Although these parameters are instructed to be rewritten, the instructed data may be the same as before rewriting. In the conventional example and the operation example 1 described above, all the data instructed to be rewritten are written without comparing the data contents before and after the rewriting. For this reason, even when there is no difference between the data before and after the writing, the data is written into the nonvolatile memory 2 and the counter value may be wasted. In this case, the operation example is devised so that writing to the nonvolatile memory 2 is skipped and the number of times of writing is not increased.

[3. Modified example]
In the above-described embodiment, the present invention has been described by exemplifying the data processing apparatus 100. However, the present invention is not limited to this embodiment, and various modifications are possible. The modification is shown below.

  In the above-described embodiment, the configuration in which the data processing device 100 includes the ASIC 3 has been described. However, the memory control device 1 may directly read / write data from / to the nonvolatile memory 2. That is, in the present invention, the ASIC is not an essential component. In the above-described embodiment, the case where the host device of the data processing device 100 is an image forming device has been described. However, the host device is not limited to this and can be applied to various control devices and computers. Furthermore, the data processing device 100 does not need to be mounted inside the host device, and may be configured such that the data processing device 100 and the host device are connected wirelessly or by wire.

  In the above-described embodiment, the nonvolatile memory 2 is described as an EEPROM, but the application of the present invention is not limited to this type of memory. In short, the nonvolatile memory in the present invention is any memory as long as the storage area is divided into blocks and the number of times of writing is restricted for each block. Also good.

  As is clear from the above-described embodiment, the present invention is characterized by data write processing performed by the control unit 11 of the memory control device 1. Therefore, the present invention can be specified as a data writing method performed by the memory control device 1 and a program describing the writing method. Further, the present invention can be implemented not by the memory control device 1 but by the control unit 11 alone.

1 is a block diagram illustrating a data processing apparatus according to an embodiment of the present invention. It is the figure which illustrated the data structure of the non-volatile memory of the apparatus. It is the flowchart which showed the conventional writing process. FIG. 4 is a schematic diagram illustrating a writing process performed according to the example of FIG. 3. 5 is a flowchart showing a writing process according to the present invention. FIG. 6 is a schematic diagram illustrating a writing process performed according to the example of FIG. 5. 5 is a flowchart showing a writing process according to the present invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 ... Data processing apparatus, 1 ... Memory control apparatus, 11 ... Control part, 12 ... Volatile memory, 2 ... Non-volatile memory, 3 ... ASIC

Claims (5)

In a memory control device that reads or writes data via a volatile memory with respect to a nonvolatile memory in which a storage area is divided into block units,
First writing means for writing data to be written to a predetermined block of the nonvolatile memory together with identification information indicating the block to the volatile memory;
Search means for specifying data to be written to the same block from among data written to the volatile memory using the identification information written by the first writing means;
A memory control device comprising: a second writing unit that collectively writes the data specified by the search unit into a block to be written. Comparing the data specified by the search means with data written in a block to be written, which is a block in which the data is to be written, and comprising a judging means for judging whether or not there is a difference between the two,
2. The memory control device according to claim 1, wherein the second writing unit does not write to the block to be written when the determining unit determines that there is no difference between the two. Equipped with detection means for detecting the occurrence of a predetermined process,
The memory control device according to claim 1, wherein the second writing unit writes data when the detecting unit detects the occurrence of the processing. The detection means includes
The memory control device according to claim 3, wherein power-off is detected as the determined process. The detection means includes
The memory control apparatus according to claim 3, wherein a process for suppressing power consumption performed by a connected host apparatus is detected as the determined process.

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