JP2007033337A - Sampling data analyzing apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a sampling data analyzing apparatus for showing favoritism to data processing of sampling data collected at a differential sampling frequency. <P>SOLUTION: A frequency setting section 23 sets a different sampling frequency to each data collector, and a synchronous clock generator 4 transmits a synchronous clock signal to each data collector. Each data collector transmits the synchronous clock signal input together with sampling data to a PC 20. A display processing section 25 displays each of the sampling data collectively collected by a data input section 21 on a common time axis by synchronizing the sampling data with the synchronous clock signal input together with sampling data. At this time, data is not actually sampled between display positions of the sampling data collected at relatively low sampling frequency on the common time axis. Therefore, the display processing section 25 generates display data from the sampling data by interpolation, and displays it. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a sampling data analysis apparatus, and more particularly to data processing for sampling data collected at different sampling frequencies.

  The logic analyzer is a sampling data analyzer having a function of displaying a change state of digital data output from a connected digital device on a display. By using the logic analyzer, the user can analyze the change state of the digital data displayed on the display and check the operation state of the digital device.

  In general, a logic analyzer has a plurality of device connection ports for connecting digital devices. By connecting multiple measurement points and ports of a digital device with wires using probes, the logic analyzer can be connected simultaneously from a plurality of measurement points. To collect digital data. For example, if the digital device to be measured is a multifunction device, the measurement location in the multifunction device may be a motor that drives the paper or a computer CPU that controls the operation of the entire multifunction device. The analyzer can simultaneously collect and monitor digital data output from each measurement location such as a motor in the multifunction peripheral.

  However, it is not always necessary to set the speed at which data is collected, that is, the sampling cycle of digital data to be the same at all measurement points. Taking the above-mentioned multi-function device as an example, it is sufficient to set the digital data sampling cycle in units of kilohertz of several kilohertz for a motor, whereas for a CPU having a high operating frequency, it is in units of kilohertz. However, setting in megahertz is not enough. In this way, when you want to collect in parallel by mixing a location that may be sampled at a relatively low frequency depending on the measurement location and a location that requires sampling at a relatively high frequency There are many. For example, there is a technique of performing sampling with a clock independently so that sampling can be performed at different sampling frequencies (for example, Patent Document 1).

JP-A-61-292570

  However, in the related art, if sampling data collected in parallel is simply displayed, each sampling data is displayed with a time axis shifted. In other words, in the past, sampling data was collected using independent clocks, so even when sampling data was collected concurrently, each sampling data was synchronized on a common time axis. It was difficult to display.

  As described above, in the past, even if digital data could be sampled from a plurality of ports simultaneously in parallel with different frequencies, it was not possible to adjust the time between the collected sampling data. There is an inconvenience at the stage of performing data processing that considers the time relationship of each sampling data, such as display of data on the same time axis.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a sampling data analyzer that facilitates data processing on sampling data collected at different sampling frequencies.

  In order to achieve the above object, a sampling data analyzing apparatus according to the present invention includes a synchronous clock generating means for transmitting a synchronous clock signal, a synchronization control port for connecting the synchronous clock generating means, and a digital to be measured. A plurality of device connection ports for connecting devices, data collection means for sampling and collecting digital data output by a digital device at a set sampling frequency, and for each device connection port of the data collection means Frequency setting means for individually setting the sampling frequency, sampling data collected by each of the data collecting means and data input means for collecting synchronous clock signals input together with the sampling data, and input to the data input means According to each synchronous clock signal, the input sample And having a data processing means for performing data processing after synchronizing the Gudeta.

  Further, the data processing means sets a time axis used when displaying sampling data according to each synchronous clock signal input to the data input means, and all or part of the sampling data is set on the set time axis. It has a display processing unit for displaying.

  In addition, when the display processing unit displays the sampling data collected at different sampling frequencies on the same time axis, the unsampled data on the sampling data side collected at a relatively low sampling frequency is displayed. It is characterized by interpolating and displaying.

  Alternatively, the display processing unit is characterized in that the display form of the interpolated data portion is different from others.

  Alternatively, the display processing unit is characterized in that the display form of the cursor moving on the sampling data displayed on the screen is different depending on whether the interpolated data portion is moved or not.

  Further, the data collection means is constituted by a plurality of data collection devices having one to a plurality of device connection ports, and the frequency setting means sets a sampling frequency for each data collection device. .

  According to the present invention, sampling data is collected together with a synchronous clock signal even when data sampling is performed at different sampling frequencies simultaneously on a plurality of measurement locations. Sampling data can be synchronized. As a result, it is possible to perform data processing in consideration of the time relationship of each sampling data. In particular, when data sampled at different sampling frequencies is displayed on the same screen, the time axis of each sampling data is aligned on the common time axis by the synchronized clock signal input together with the sampling data. Each sampling data can be displayed. At the same time, since the data to be displayed at the position where there is no sampling data is generated and interpolated by the sampling data, the time relationship between each sampling data even when data sampling is performed at different sampling frequencies. Can be understood at a glance.

  Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 is a hardware configuration diagram showing a logic analyzer which is an embodiment of a sampling data analysis apparatus according to the present invention. FIG. 1 shows a digital device 2 as a measurement target of digital data, a synchronous clock generator 4 constituting a logic analyzer in the present embodiment, a plurality of data collection devices 8 provided as data collection means 6, and a HUB. A (hub) 10 and a personal computer (PC) 20 are shown. The synchronous clock generation device 4 generates a synchronous clock signal in accordance with an instruction from the PC 20 and sends it to each data collection device 8. The synchronous clock signal is generated as unique synchronous clock data. The data collection devices 8 constituting the data collection means 6 are basically assumed to be devices of the same specification. Each data collection device 8 has ports for 26 channels, of which one port is a synchronization control port for inputting a synchronous clock signal transmitted by the synchronous clock generator 4 and the remaining ports are digital devices. Used as a connection port. Each data collection device 8 collects digital data output from the digital device 2 via the probe 12 connected to the device connection port at a fixed period according to a preset sampling frequency, and temporarily stores the digital data in the inside. A total of 4 bytes of data including the data is output to the PC 20. The HUB 10 is provided as a concentrator for connecting various peripheral devices, in this embodiment, the synchronous clock generator 4 and the data collector 8 to the PC 20. In the present embodiment, only one unit is shown for convenience, but when the number of units connected to the PC 20 such as the data collection device 8 is increased, it is possible to cope by cascade-connecting hubs. The PC 20 inputs and stores the digital data collected by the data collection device 8 and performs various data processing such as display and analysis.

  FIG. 2 is a block diagram showing the PC 8 in the present embodiment. FIG. 2 shows a data processing unit 26 and a data storage unit 27 having a data input unit 21, a data output unit 22, a frequency setting unit 23, a synchronous clock control unit 24, and a display processing unit 25. The data input unit 21 inputs data output from the data collection unit 6. The data output unit 22 accumulates the data input by the data input unit 21 in the data storage unit 27. The frequency setting unit 23 individually sets the sampling frequency for each device connection port included in the data collection unit 6. In this embodiment, the sampling frequency is set for each data collection device 8. The synchronous clock control unit 24 performs generation and transmission control of the synchronous clock signal by giving an instruction to the synchronous clock generator 4. The data processing unit 26 performs data processing such as analysis and display of data input by the data input unit 21. Among these, the display processing unit 25 performs display processing of collected sampling data. Each of the components 21 to 26 included in the PC 20 of the present embodiment is realized by a cooperative operation of a software program that realizes the processing function of each component and hardware resources that construct the PC 20. The data storage unit 27 is assumed to be realized by an external storage device such as a hard disk drive (HDD).

  Next, the operation in the present embodiment, specifically, the sampling data collected by the data collecting means 6 is collectively collected in the PC 20 and the processing until the sampling data is displayed on the display (not shown) in the PC 20 is shown in FIG. This will be described with reference to the flowchart shown.

  Before starting the collection of digital data, the frequency setting unit 23 of the PC 20 sets a sampling frequency for each data collection device 8 (step 110). This can be set, for example, by setting each sampling frequency input and set by the user as a control command for setting the sampling frequency and sending the control command to the corresponding data collection device 8. In the present embodiment, the sampling frequency is set using the control command as described above, but the specific method of the sampling frequency setting process depends on the specification of each data collection device 8. The sampling frequencies set for each data collection device 8 may all be the same, but this embodiment is characterized by the handling of sampling data when different sampling frequencies are set when sampling digital data. Because there are, do not make all the same. Subsequently, the synchronous clock controller 24 of the PC 20 instructs the synchronous clock generator 4 to generate and send a synchronous clock signal (step 120). The synchronous clock generator 4 generates a synchronous clock signal according to this instruction and sends it to all the data collectors 8 connected by the cable. It should be noted that steps 110 and 120 need only be completed before data sampling is actually started, and the execution order of each step may be reversed.

  Then, each data collection device 8 collects digital data emitted from a predetermined portion of the digital device 2 under the data sampling control by the PC 20 at a sampling frequency set for each (Step 130). At this time, each data collection device 8 receives the synchronous clock signal together with the digital data to be sampled, but sends each of the inputted data to the PC 20. An example of the format of the data to be sent is shown in FIG.

  Since each data collection device 8 has 26 channels as described above, digital data for a maximum of 25 channels collected from the digital device 2 is set between bit 0 and bit 24. Then, the data input from the synchronization control port is set in bit 25. Bits 26 to 30 are used for a compression flag indicating whether or not data is compressed, and the most significant bit 31 is used as an error bit. Of course, the bit position for storing each data may be determined in advance with the PC 20, and is not limited to this example.

  In the PC 20, when the data input unit 21 inputs data sent from each data collection device 8, the data output unit 22 sequentially stores the input data in the data storage unit 27 (step 140). Since different sampling frequencies are set for each data collection device 8, sampling data is not sent from all the data collection devices 8 in one synchronous clock cycle. For example, when the sampling frequency is set to 500 Hz and 1 kHz for the two data collection devices A and B, the data collection device A sends the sampling data to the data collection device B at a rate of once every two times. It will be sent to the PC 20.

  The data sampling process (step 130) by each data collection device 8 and the batch collection and storage process (step 140) of the sampling data in the PC 20 are repeatedly executed, so that each channel is sampled from the start to the end of sampling. Sampling data is accumulated in the data storage unit 27 in time series.

  Subsequently, characteristic sampling data display processing of the present embodiment will be described. Here, for convenience of explanation, only the sampling data for two channels of the two data collection devices are focused, and the present embodiment is performed. In order to make it easier to grasp the characteristics of the form, the digital data output from the digital device collected by each channel with the same channel number of interest will be described as having the same value.

  FIG. 5 is a diagram showing an example of digital data collected from the two channels 0 and 1 of the two data collection devices A and B, respectively. Here, the data collection device B has a sampling frequency five times that of the data collection device A, and a specific example is that the synchronization clock is 500 Hz (2 ms), and the data collection device A has 1 kHz (1 ms), Assume that the sampling frequency is set to 5 kHz (100 μs) in the data collection device Bn. Also, it is assumed that digital data of the same value is input from the channels 0 and 1 of the data collection devices A and B as described above. An example of sampling data according to this condition is shown in FIG. In FIG. 5, data sampled from each port of the data collection devices A and B at the same timing when the synchronous clock signal transmitted from the synchronous clock generator 4 is input are shown in association with arrows.

  Here, the display processing unit 25 takes out the data illustrated in FIG. 5 from the data storage unit 27 and displays it on the screen. At this time, the sampling data of the data collection device B as illustrated in FIG. Since data five times that of the data collection device A has been collected, if each sampling data is simply displayed in the time series in the same width, the time relationship is displayed in a shifted state. Therefore, in the present embodiment, time axis alignment is performed by first setting a common time axis for each sampling data (step 150). That is, the display processing unit 25 obtains the sampling frequency of each of the data collection devices A and B by referring to storage means (not shown) stored when the frequency setting unit 23 sets the data collection device 8. Therefore, the time width on the time axis is set by obtaining the ratio of the set values of the respective sampling frequencies. Further, each sampling data is synchronized with the synchronizing clock signal input together with the sampling data. According to the above-described example, since the sampling frequency five times that of the data collecting device A is set in the data collecting device B, the time axis of the data collecting device A is set to five times. However, since the data collection device A collects only one fifth of the data of the data collection device B, after interpolating the four-fifth data portion not collected (step 160), the sampling data is displayed on the screen. Display (step 170). An example of this display is shown in FIG.

  In FIG. 6, similarly to FIG. 5, the sampling data collected by the data collection devices A and B is shown corresponding to each channel. Here, the display processing unit 25 displays the input sampling data in order with a certain width for the data collection device B sampled at a relatively high sampling frequency. On the other hand, for the data acquisition device A sampled at a relatively low sampling frequency, the input sampling data is displayed at a position corresponding to the sampling clock, and the data at the timing of not sampling is displayed as the previous sampling data. Display after interpolating with the value of. For example, as is apparent from FIG. 5, sampling data is input in the order of “0”, “1”, “0”, “1” from the channel 0 of the data collecting apparatus A. The data to be displayed on the data display portion 30 between “0” and the subsequent “1” is generated by interpolating with the immediately preceding data “0”. In this embodiment, the interpolation data to be displayed on the data display portion 30 is displayed with the display form on the data display portion 30 different from the others so that it can be visually recognized that it is not actual sampling data. In the present embodiment, the actual sampling data is drawn with a solid line, whereas the interpolation data displayed on the data display portion 30 is displayed with a broken line and lightly. Of course, the distinction between the sampling data and the interpolated data may be made visible at a glance by making other attributes such as the display color different from the line type and the color of the line.

  In the above description, the description has been given focusing on the two channels in the two data collection devices. However, the same processing is performed in the other channels and other data collection devices, so that the desired data collection device has a desired value. Channel sampling data can be displayed.

  According to the present embodiment, as described above, data sampling can be performed at different sampling frequencies. This eliminates the need to perform data sampling by matching a relatively low sampling frequency to a relatively high sampling frequency, thereby preventing unnecessary sampling data from being collected. It can prevent becoming enormous.

  Even when data sampling is performed at different sampling frequencies, the sampling data is collected together with the synchronous clock signal, so that each sampling data can be synchronized with reference to the synchronous clock signal. As a result, it is possible to perform data processing in consideration of the time relationship of each sampling data. In particular, when data sampled at different sampling frequencies is displayed on the same screen, the time axis of each sampling data is aligned on the common time axis by the synchronized clock signal input together with the sampling data. In addition to being able to display, the data to be displayed at a position where there is no sampling data is generated by interpolating with the actual sampling data and displayed. As a result, even when sampling is performed at different sampling frequencies, the time relationship between the sampling data can be clearly understood.

  When the sampling frequency is different, the data is interpolated by the sampling data and then displayed on the screen. At this time, the difference between the sampling data and the interpolation data is displayed so as to be visible. This is convenient in the following cases.

  For example, as shown in FIG. 6, in the data portion 32 that displays the digital data collected at the time of the seventh data sampling in the data collection device B, it is clear if each data of the data collection devices A and B is compared. Data values are different. That is, the display data of the data collection device A generated by the interpolation is “1”, while the display data of the data collection device B by actual data sampling is “0”. In this case, if the same display form is used, it is not possible to know which value is correct. Therefore, in this embodiment, when the data value is different as in this example by changing the display form of the interpolation data from the actual sampling data, the display data of the data collection device B is more reliable. It can be easily determined that the value is high.

  Thus, the data displayed in the data portion 32 of the data collection device A may not be correct. However, since the sampling frequency is set in the data collection apparatus A at a period in which digital data is desired to be collected, sampling data can be collected at a necessary timing. Accordingly, the interpolation data is generated and displayed for the convenience of display, and it is considered that there is no particular problem even if there is a slight shift in display data other than this cycle.

  In the above display example, it is possible to distinguish between actual sampling data and interpolation data by changing the display form of the lines for displaying data. In FIG. 7, the display form of the cursor moving on the sampling data displayed on the screen is made different so that the data can be distinguished. For example, as illustrated in FIG. 7, when the moving bar-shaped cursor is positioned on the actual sampling data display, the cursor 36 is displayed with a solid line indicating that fact. On the other hand, when the moving cursor is positioned on the display of the interpolation data, the cursor 34 is displayed with a broken line indicating that fact. As described above, the difference between the actual sampling data and the interpolation data can be visually recognized by changing the display form of the cursor. In particular, when analyzing a plurality of interpolated data on a single screen, changing the cursor display makes it easier for the measurer to recognize the position of the data to be observed, and prevents erroneous data analysis.

  In FIG. 7, the type of display data can be determined by the shape of the cursor, which is a solid line or a broken line. However, as a modified example shown in FIG. 7, other display colors of the cursor, lighting, blinking, etc. The display form may be changed. Instead of displaying the entire cursor with a solid line or a broken line, the cursor part corresponding to the actual sampling data display position is displayed with a solid line, and the cursor part corresponding to the interpolation data display position is displayed with a broken line. The display form of the cursor may be partially changed according to the data type.

  Furthermore, the display form is not limited to the cursor. For example, when the cursor is positioned on the actual sampling data display, an actual measurement value or the like may be displayed on the screen. That is, since there is no actual measurement value for interpolation data, it is not displayed. Or you may make it display on a screen the character, symbol, etc. which show that a cursor is located on actual sampling data or interpolation data. The display of characters, symbols, etc. may be performed only for at least one data.

  In the present embodiment, the sampling frequency is set for each data collection device 8, but it may be set for each port as long as it is a compatible model.

  In this embodiment, the logic analyzer is divided into separate devices such as the synchronous clock generator 4, the data collection means 6, and the PC 20, but the PC 20 has the processing functions of the devices 4 and 6. By doing so, the logic analyzer may be formed by a single device.

  Further, in the present embodiment, the case where the sampling data analysis apparatus according to the present invention is applied to a logic analyzer that analyzes digital data has been described as an example. A logic analyzer generally has both the data collection processing function and the data display processing function described above, but each processing function can be implemented in a separate computer. It can also be applied to devices other than logic analyzers.

It is a hardware block diagram which showed the logic analyzer which is one Embodiment of the sampling data analyzer which concerns on this invention. It is the block block diagram which showed the logic analyzer in this Embodiment. It is the flowchart which showed the process until it collects and displays the data of the logic analyzer in this Embodiment. It is the figure which showed the structural example of the data sent to data from the data collection device in this Embodiment. It is the figure which showed the correspondence of the sampling data collected with the different sampling frequency in this Embodiment. It is the figure which showed the example of a display of the sampling data collected with the different sampling frequency in this Embodiment. It is the figure which showed the example of a different display of the sampling data collected with the different sampling frequency in this Embodiment.

Explanation of symbols

  2 digital equipment, 4 synchronous clock generator, 6 data collection means, 8 data collection device, 10 HUB (hub), 12 probe, 20 personal computer (PC), 21 data input section, 22 data output section, 23 frequency setting section , 24 Synchronous clock control unit, 25 Display processing unit, 26 Data processing unit, 27 Data storage unit, 34, 36 Cursor.

Claims (6)

Synchronous clock generating means for transmitting a synchronous clock signal;
Data collection for sampling and collecting digital data output by a digital device at a set sampling frequency, having a synchronization control port for connecting the synchronization clock generating means and a plurality of device connection ports for connecting digital devices to be measured Means,
Frequency setting means for individually setting a sampling frequency for each device connection port of the data collection means;
Data input means for collectively collecting sampling data collected by each of the data collecting means and a synchronous clock signal input together with the sampling data;
In accordance with each synchronous clock signal input to the data input means, data processing means for performing data processing after synchronizing the input sampling data;
A sampling data analysis apparatus comprising: The sampling data analyzer according to claim 1, wherein
The data processing means sets a time axis used when displaying sampling data according to each synchronous clock signal input to the data input means, and displays all or part of the sampling data on the set time axis. A sampling data analysis apparatus comprising a display processing unit. The sampling data analyzer according to claim 2, wherein
When the display processing unit displays sampling data collected at different sampling frequencies on the same time axis, the display processing unit interpolates unsampled data on the sampling data side collected at a relatively low sampling frequency. A sampling data analysis device characterized by being displayed. The sampling data analyzer according to claim 3, wherein
The sampling data analyzing apparatus, wherein the display processing unit changes a display form of the interpolated data portion from others. The sampling data analyzer according to claim 3, wherein
The display processing unit is characterized in that the display form of the cursor that moves on the sampling data displayed on the screen differs depending on whether the interpolated data portion is moved or not. The sampling data analyzer according to claim 1, wherein
The data collection means is composed of a plurality of data collection devices having one to a plurality of device connection ports,
The sampling data analysis apparatus, wherein the frequency setting means sets a sampling frequency for each of the data collection apparatuses.

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