JP2007027787A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To lessen an alignment margin of a contact hole formed adjacent to a capacitor with respect to a semiconductor device having a ferroelectric capacitor. <P>SOLUTION: The semiconductor device comprises capacitor protective films 16 and 18 which cover a top surface and a side surface of a ferroelectric capacitor Q<SB>1</SB>formed on a first insulating film 8; capacitor protective films 16 and 18; a hole 19a which is formed in a second insulating film 19 formed on the first insulating film 8 and is formed adjacent to the side surface of the ferroelectric capacitor Q<SB>1</SB>via the capacitor protective films 16 and 18; and a conductive plug 21 which is formed in the hole 19a. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a ferroelectric capacitor.

  A ferroelectric memory (FeRAM) is known as a nonvolatile memory that can store information even when the power is turned off.

  The FeRAM has a memory cell that stores information using the hysteresis characteristic of a ferroelectric capacitor. A ferroelectric capacitor has a structure in which a ferroelectric film is formed between a pair of electrodes, generates polarization according to the magnitude of an applied voltage between the electrodes, and has spontaneous polarization even when the applied voltage is removed. . If the polarity of the applied voltage is reversed, the polarity of the spontaneous polarization is also reversed. Information can be read by detecting spontaneous polarization.

  FeRAM memory cells include a 1T / 1C type that uses one transistor and one capacitor to store 1-bit information, and a 2T / 2C type that uses two transistors and two capacitors to store 1-bit information. is there. A 1T / 1C type memory cell can be highly integrated with a smaller cell area than a 2T / 2C type memory cell.

  Next, a process for forming a 1T / 1C type memory cell having a stack capacitor will be described.

  First, steps required until a structure shown in FIG.

  An element isolation insulating film 102 is formed around the element formation region of the silicon substrate 101, and then a well 103 is formed in the element formation region. Further, two MOS transistors 104 are formed in the well 103.

  The MOS transistor 104 includes a gate electrode 104b formed on the well 103 via a gate insulating film 104a, and impurity diffusion regions 104c and 104d formed in the well regions 103 on both sides of the gate electrode 104b and serving as source / drain. Have. Insulating sidewalls 105 for forming a high impurity concentration region 104d in the impurity diffusion region 104c are formed on both side surfaces of the gate electrode 104b.

  Thereafter, a transistor protective insulating film 106 covering the MOS transistor 104 is formed on the silicon substrate 101, and a first interlayer insulating film 107 is further formed on the transistor protective insulating film 106.

  Subsequently, after forming the first contact hole 107a on one impurity diffusion region 104c of the MOS transistor 104 in the first interlayer insulating film 107, the first contact plug 108 is embedded in the first contact hole 107a.

  Further, a first metal film 109, a ferroelectric film 110, and a second metal film 111 are sequentially formed on the first contact plug 108 and the first interlayer insulating film 107.

  Next, as shown in FIG. 1B, the capacitor 112 is formed by patterning the first metal film 109, the ferroelectric film 110, and the second metal film 111 by photolithography. In the capacitor 112, the first metal film 109 is the lower electrode 109a, the ferroelectric film 110 is the dielectric film 110a, and the second metal film 111 is the upper electrode 111a. The capacitor 112 is a stack type, and the lower electrode 109a is connected to one impurity diffusion layer 104c of the MOS transistor 104 through the first contact plug 108 therebelow.

  Thereafter, as shown in FIG. 1C, a single-layer capacitor protective film 113 is formed only once on the capacitor 112 and the first interlayer insulating film 107, and further on the capacitor protective film 113, the second interlayer insulating film is formed. After the film 114 is formed, the second interlayer insulating film 114, the capacitor protective film 113, the first interlayer insulating film 107, and the transistor protective film 106 are patterned by photolithography, whereby the other impurity diffusion region 104d of the MOS transistor 104 is formed. A second contact hole 114a is formed thereon. Thereafter, a second contact plug 115 is formed in the second contact hole 114a.

  Next, steps required until a structure shown in FIG.

  By patterning the second interlayer insulating film 114, a third contact hole 114 b is formed on the upper electrode 110 a of the capacitor 112. Further, after forming a conductive film on the second interlayer insulating film 114 and in the third contact hole 114b, the conductive film is patterned to form the wiring 116a connected to the upper electrode 111a of the capacitor 112 and at the same time the second contact. A conductive pad 116 b is formed on the plug 115.

  Further, a third interlayer insulating film 117 covering the wiring 116 a and the conductive pad 116 b is formed on the second interlayer insulating film 114. Thereafter, the third interlayer insulating film 117 is patterned to form a hole 117a on the conductive pad 116b, and further, a fourth conductive plug 118 is formed in the hole 117a.

  Thereafter, a bit line 118 connected to the conductive plug 118 is formed on the third interlayer insulating film 117.

  The arrangement of the MOS transistors, capacitors, and word lines in the 1T / 1C type memory cell as described above is as shown in the plan view of FIG. 2 is a cross-sectional view taken along the line II of FIG.

  By the way, when the second contact hole 114 a is opened in the first and second interlayer insulating films 107 and 114, an alignment margin is necessary so that the second contact hole 114 a does not contact the capacitor 112. In this case, the distance between the second contact hole 114 a and the capacitor 112 needs to be separated to ensure an alignment margin, whereby the interval between the two capacitors 112 adjacent to each other above the well 103 is also determined.

  If such an alignment margin is not ensured, the second contact hole 114a may overlap part of the capacitor 112.

  When the second contact hole 114 a is formed in contact with the capacitor 112, the second contact plug 115 in the second contact hole 114 a is short-circuited to the capacitor 112. When the second contact hole 114a is in contact with the capacitor 112, when the second contact plug 115 is formed by the CVD method, the ferroelectric film 110 is reduced by the reactive gas, and the ferroelectric film 110 of the capacitor is deteriorated. There is a fear.

  Furthermore, if the area of the capacitor 112 is reduced in order to achieve high integration of memory cells, the memory cell characteristics are likely to deteriorate.

  An object of the present invention is to provide a semiconductor device having a structure for reducing the alignment margin of a contact hole formed next to a capacitor.

  The above-described problems include a first impurity diffusion region formed in a semiconductor substrate, a first insulating film formed above the semiconductor substrate, a lower electrode, a strong electrode formed on the first insulating film. A capacitor having a dielectric film and an upper electrode, an insulating capacitor protective film made of alumina covering the upper and side surfaces of the capacitor, and silicon dioxide formed on the capacitor protective film and the first insulating film A first hole formed in the second insulating film and exposing the capacitor protection film covering a side surface of the capacitor, and formed in the first hole. A first conductive plug electrically connected to one impurity diffusion region and insulated from the capacitor only by the capacitor protective film, and the capacitor is provided on both sides of the first hole, respectively. It is solved by a semiconductor device according to claim two of said capacitor via a protective film is formed.

  Next, the operation of the present invention will be described.

  According to the semiconductor device of the present invention, the capacitor protective film covering the upper surface and the side surface of the ferroelectric capacitor formed on the first insulating film, and the second formed on the capacitor protective film and the first insulating film. The insulating film has a hole formed adjacent to the side surface of the ferroelectric capacitor via a capacitor protective film, and a conductive plug formed in the hole.

  Therefore, the distance between the ferroelectric capacitor and the conductive plug becomes equal to the film thickness of the capacitor protective film, and the area where the ferroelectric capacitor is formed approaches the hole side, so that the capacitor area becomes wider than before.

  Note that the capacitor protective film is a material that prevents the reduction of the capacitor, and a material that selectively selects an insulating film during etching.

  Embodiments of the present invention will be described below with reference to the drawings.

  4 to 10 are cross-sectional views showing manufacturing steps of the semiconductor device according to the embodiment of the present invention. FIG. 11 is a plan view showing the arrangement of transistors and capacitors in the memory cell region of the semiconductor device according to the embodiment of the present invention.

  First, steps required until a sectional structure shown in FIG.

As shown in FIG. 4A, after an element isolation trench is formed by photolithography around the transistor formation region of an n-type or p-type silicon (semiconductor) substrate 1, silicon oxide (SiO ₂₎ is formed therein. ) Is embedded to form the element isolation insulating film 2. The element isolation insulating film 2 having such a structure is called STI (Shallow Trench Isolation). Note that an insulating film formed by a LOCOS (Local Oxidation of Silicon) method may be employed as the element isolation insulating film.

  Subsequently, a p-type well 1a is formed by selectively introducing p-type impurities into the transistor formation region of the silicon substrate 1 in the memory cell region.

  Further, the surface of the p-type well 1a of the silicon substrate 1 is thermally oxidized to form a silicon oxide film that becomes the gate insulating film 3.

  Next, an amorphous or polycrystalline silicon film and a tungsten silicide film are sequentially formed on the entire upper surface of the silicon substrate 1. After that, the silicon film and the tungsten silicide film are patterned by photolithography to form gate electrodes 4a and 4b on the well 1a in the memory cell region. These gate electrodes 4 a and 4 b are formed on the silicon substrate 1 via the gate insulating film 3.

  In the memory cell region, two gate electrodes 4a and 4b are formed in parallel on one p-type well 1a, and these gate electrodes 4a and 4b constitute part of a word line.

  Next, n-type impurities, such as phosphorus, are ion-implanted on both sides of the gate electrodes 4a and 4b in the p-type well 1a to form first to third n-type impurity diffusion regions 5a to 5c serving as source / drain. .

Further, after an insulating film, for example, a silicon oxide (SiO ₂ ) film is formed on the entire surface of the silicon substrate 1 by the CVD method, the insulating film is etched back and insulating sidewall spacers are formed on both sides of the gate electrodes 4a and 4b. Leave as 6.

  Subsequently, n-type impurities are ion-implanted again into the first to third n-type impurity diffusion regions 5a to 5c using the gate electrodes 4a and 4b and the sidewall spacers 6 as masks in the p-type well 1a. A high impurity concentration region is formed in each of the first to third n-type impurity diffusion regions 5a to 5c.

  In one p-type well 1a, the first n-type impurity diffusion region 5a between the two gate electrodes 4a and 4b is electrically connected to a bit line to be described later, and a second near the both ends of the well 1a. The third n-type impurity diffusion regions 5b and 5c are electrically connected to the lower electrode of the capacitor described later.

Through the above process, two n-type MOS transistors T ₁ and T ₂ having gate electrodes 4a and 4b and n-type impurity diffusion regions 5a to 5c having an LDD structure are formed in the p-type well 1a. The region 5a is formed in common.

Next, a silicon oxynitride (SiON) film having a thickness of about 200 nm is formed on the entire surface of the silicon substrate 1 as a cover insulating film 7 covering the MOS transistors T ₁ and T ₂ by plasma CVD. Thereafter, silicon oxide (SiO ₂ ) having a film thickness of about 1.0 μm is formed on the cover insulating film 7 as the first interlayer insulating film 8 by plasma CVD using TEOS gas.

  Subsequently, for example, the first interlayer insulating film 8 is heated at a temperature of 700 ° C. for 30 minutes in a normal-pressure nitrogen atmosphere, thereby densifying the first interlayer insulating film 8. Thereafter, the upper surface of the first interlayer insulating film 8 is planarized by a chemical mechanical polishing (CMP) method.

  Next, as shown in FIG. 4B, by etching the first interlayer insulating film 8 and the cover insulating film 7 using a resist pattern (not shown), the second and third n of the memory cell region are etched. First and second contact holes 8b and 8c are formed on the type impurity diffusion regions 5b and 5c, respectively.

  Next, steps required until a structure shown in FIG.

First, a titanium nitride (TiN) film having a thickness of 50 nm is formed as a glue film 9a on the upper surface of the first interlayer insulating film 8 and the inner surfaces of the first and second contact holes 8b and 8c by sputtering. Further, a tungsten (W) film 9b is grown on the glue film 9a by the CVD method using WF ₆ to completely fill the contact holes 8b and 8c.

  Subsequently, the tungsten film 9 b and the glue film 9 a are polished by CMP to be removed from the upper surface of the first interlayer insulating film 8. As a result, the tungsten film 9b and the glue film 9a left in the first and second contact holes 8b and 8c are connected to the second and third n-type impurity diffusion regions 5b and 5c. 2 conductive plugs 10b and 10c.

  Next, steps required until a structure shown in FIG.

  First, as a first conductive film 13 on the first and second conductive plugs 10b, 10c and the first interlayer insulating film 8, for example, an iridium (Ir) film 13a having a thickness of 200 nm, a platinum oxide having a thickness of 23 nm ( A PtO) film 13b and a platinum (Pt) film 13c having a thickness of 50 nm are sequentially formed by sputtering.

  Note that the upper surface of the first interlayer insulating film 8 is annealed before or after the first conductive film 13 is formed, for example, to prevent film peeling. As an annealing method, for example, RTA (rapid thermal annealing) at 600 to 750 ° C. is employed in an argon atmosphere.

Subsequently, a PZT film having a thickness of, for example, 200 nm is formed as the ferroelectric film 14 on the first conductive film 13 by a sputtering method. Other methods for forming the ferroelectric film 14 include a MOD (metal organic deposition) method, a MOCVD (organometallic CVD) method, and a sol-gel method. In addition to PZT, the ferroelectric film 14 may be made of other PZT materials such as PLCSZT and PLZT, and Bi layers such as SrBi ₂ Ta ₂ O ₉ and SrBi ₂ (Ta, Nb) ₂ O _9. Structural compound materials and other metal oxide ferroelectrics may be employed.

Subsequently, the ferroelectric film 14 is crystallized by annealing in an oxygen-containing atmosphere. As the annealing, for example, the substrate temperature is 600 ° C. and the time is 90 seconds in a mixed gas atmosphere of argon (Ar) and oxygen (O ₂ ). The first step is the substrate temperature 750 ° C. and the time is 60 seconds in the oxygen atmosphere. A two-step RTA process is adopted with the second step as the second step.

Further, iridium oxide (IrO ₂ ) having a film thickness of 200 nm, for example, is formed as the second conductive film 15 on the ferroelectric film 14 by sputtering. Further, a first capacitor protective film 16 made of alumina having a thickness of about 170 nm is formed on the second conductive film 15, for example. The first capacitor protective film 16 may be made of any one of PZT-based materials such as PZT film and PLZT film, titanium oxide and other anti-reduction materials instead of alumina.

Thereafter, a TiN film and a SiO ₂ film are sequentially formed on the first capacitor protection film 16 as a hard film above and around the p-type well 1a, and then the hard film is patterned by a photolithography method. First and second hard masks 17a and 17b for forming capacitors are formed above one p-type well 1a with a space therebetween.

  The first and second hard masks 17a and 17b have a capacitor planar shape that overlaps the upper surfaces of the first and second conductive plugs 10b and 10c. The interval w between the first and second hard masks 17a and 17b on one p-type well 1a is, for example, a third conductivity described later to be formed on the first n-type impurity diffusion region 5a. A value obtained by adding a size twice as large as a film thickness of a second capacitor protective film described later to the diameter of the plug.

Subsequently, the first capacitor protection film 16, the second conductive film 15, the ferroelectric film 14, and the first conductive film 13 in a region not covered with the first and second hard masks 17 a and 17 b are sequentially etched. Thus, the first and second capacitors Q ₁ and Q ₂ are formed on the first interlayer insulating film 8. Subsequently, by removing the hard mask 16, a state as shown in FIG.

The first and second capacitors Q ₁ and Q ₂ include lower electrodes 13 a and 13 b made of the first conductive film 13, capacitor dielectric films 14 a and 14 b made of the ferroelectric film 14, and a second conductive film 15. The upper electrodes 15a and 15b are formed. In this case, the upper electrodes 15 a and 15 b are covered with the first capacitor protective film 16. The first lower electrode 13a of the capacitor Q ₁ is electrically connected to the second n-type impurity diffusion region 5b via the first conductive plug 12a, also, the second lower electrode of the capacitor Q ₂ 13b is electrically connected to the third n-type impurity diffusion region 5c through the second conductive plug 12b.

Here, the capacitors Q ₁ and Q ₂ have a size covering the conductive plugs 12a and 12b and the gate electrodes 4a and 4b, and the centers of the lower electrodes 15a and 15b are from the conductive plugs 12a and 12b to the gate electrode 4a. , 4b side and is formed. Also, in on one p-type well 1a, first capacitor Q ₁ and the second capacitor Q ₂ are formed as a space between them are located directly above the first n-type impurity diffusion regions 5a Is done. The space between the first and second capacitors Q ₁ and Q ₂ can be designed to be narrower than the distance between the two gate electrodes 4 a and 4 b on the p-type well 1 in consideration of positional deviation. preferable.

  Subsequently, recovery annealing is performed in order to recover the ferroelectric film 14 due to etching from damage. In this case, the recovery annealing is performed, for example, in a furnace containing oxygen at a substrate temperature of 650 ° C. for 60 minutes.

Next, as shown in FIG. 6B, a second capacitor protective film 18 made of alumina having a film thickness of 50 to 150 nm covering the capacitors Q ₁ and Q ₂ is sputtered or deposited on the first interlayer insulating film 8. It is formed by the MOCVD method. In this manner, a state capacitors Q _1, Q ₂ of the upper electrode 15a, the total film thickness on the 15b is about 220~320nm capacitor protection films 16 and 18 are formed. In this case, since the sidewalls of the capacitors Q ₁ and Q ₂ have a steep slope, the film thickness of the second capacitor protection film 18 covering these sidewalls is 25 to 135 nm. The capacitor protective films 16 and 18 protect the capacitors Q ₁ and Q ₂ from process damage, and may be made of an anti-reduction material such as PZT material or titanium oxide in addition to alumina.

Thereafter, the first and second capacitors Q ₁ and Q ₂ are annealed in an oxygen-containing atmosphere at 650 ° C. for 60 minutes.

  Next, steps required until a structure shown in FIG.

First, a silicon oxide (SiO ₂ ) film having a thickness of about 1.0 μm is formed on the second capacitor protective film 18 and the first interlayer insulating film 8 as the second interlayer insulating film 19 by plasma CVD using TEOS gas. Form. Further, the upper surface of the second interlayer insulating film 19 is planarized by the CMP method. In this example, the remaining film thickness of the second interlayer insulating film 19 after CMP is about 300 nm above the upper electrodes 15a and 15b, and 800 nm above the first interlayer insulating film 8 on the sides of the capacitors Q ₁ and Q _2. To the extent.

Subsequently, a resist 20 is applied on the second interlayer insulating film 19, and is exposed and developed, whereby the adjacent first and second capacitors Q ₁ and Q ₂ on one p-type well 1a. An opening 20a for forming a contact hole is formed therebetween. The opening 20a may have a diameter larger than the interval between the capacitors Q ₁ and Q ₂ in consideration of misalignment.

  Next, as shown in FIG. 7B, the second interlayer insulating film 19 is etched using a fluorine-based reactive gas through the opening 20a of the resist 20 and anisotropic etching is performed in the vertical direction. The upper part of the third contact hole 19a is formed.

  Subsequently, as shown in FIG. 8A, through the opening 20a of the resist 20 and the upper portion of the third contact hole 19a, a fluorine-based reactive gas is used to form the first interlayer of the second capacitor protective film 18. A portion in contact with the upper surface of the insulating film 8 is etched, and subsequently, the first interlayer insulating film 8 and the transistor protective film 7 below the third contact hole 19a are etched to form a lower portion of the third contact hole 19a. Form. As a result, the first n-type impurity diffusion region 5a is exposed through the third contact hole 19a.

The third contact hole 19a is formed by self-alignment using the capacitor protection films 16 and 18 on the upper and side surfaces of the capacitors Q ₁ and Q ₂ as a part of the mask, and is substantially positioned by the capacitors Q ₁ and Q ₂ . Will be.

Accordingly, even if misalignment formation position of the opening 20a of the resist 20, at least one side of the position and shape of the third contact hole 19a is one side of the capacitors Q ₁ or Q ₂ the capacitor protection film thereon 16 , 18 to control the speed.

  In such an etching process for forming the third contact hole 19a, the etching conditions are such that the first and second interlayer insulating films 8 and 19 are etched with high selectivity with respect to the capacitor protective films 16 and 18.

For example, when the interlayer insulating film is made of SiO ₂ (hereinafter referred to as TEOS-SiO ₂ ) formed using TEOS and the capacitor protective film is made of alumina, the following etching conditions are used.

For example, by using a parallel plate etching apparatus, using C ₄ F ₈ , Ar, and CF ₄ as etching gases, setting the vacuum degree of the etching atmosphere to 46 Pa, and setting the RF power to 1000 W at 13.56 MHz, TEOS The etching selectivity of the —SiO ₂ film to the alumina film can be about 7.

Therefore, after opening the upper portion of the third contact hole 19a by etching the second interlayer insulating film 19, the first and second capacitor protective films 16, exposed from the third contact hole 19a on the upper electrode 15a, 18 is etched from the top by about 120 nm, leaving 100 to 200 nm. Further, since the second capacitor protection film 18 on the side walls of the first and second capacitors Q ₁ and Q ₂ is etched in the vertical direction, the film thickness in the lateral direction is difficult to decrease. The sides of the capacitors Q ₁ and Q ₂ are kept covered. That is, the second capacitor protective film 18 is formed to a thickness that keeps the side surfaces of the capacitors Q ₁ and Q ₂ covered with the formation of the third contact hole 19a. Further, the first and second capacitor protective films 16 and 18 are formed on the upper surfaces of the capacitors Q ₁ and Q ₂ in a state where all of the third contact holes 19a have been formed. In addition, the film thicknesses of the first and second capacitor protective films 16 and 18 are set so that the second capacitor protective film 18 remains on the side surface, and the etching conditions are set.

As a result, the capacitors Q ₁ and Q ₂ are kept covered with the capacitor protective films 16 and 18 after the third contact hole 19a has been formed.

As described above, the alumina film has a high blocking property against a reducing atmosphere (hydrogen or the like) that degrades the capacitors Q ₁ and Q ₂ , and also reduces the etching selectivity with respect to the etching of the TEOS-SiO ₂ film. Therefore, it is one of effective materials as a capacitor protective film. Even when PZT, PLZT, or titanium oxide is applied as a material constituting the capacitor protective films 16 and 18 in addition to alumina, the film thickness and etching conditions are set in the same manner as described above.

  Since the capacitor protection films 16 and 18 are thin in the portion exposed from the third contact hole 19a and thick in the other portions, a step is formed in the third contact hole 19a and its periphery on the upper electrode 15a. It will be.

Next, as shown in FIG. 8B, after removing the resist 20, a titanium nitride film having a thickness of 50 nm is formed as a glue film 21a on the upper surface of the second interlayer insulating film 19 and the inner surface of the third contact hole 19a. It is formed by sputtering. Subsequently, a tungsten film 21b is grown on the glue film 21a by a CVD method using tungsten hexafluoride (WF ₆ ) gas to completely fill the third contact hole 19a.

  Subsequently, as shown in FIG. 9A, the tungsten film 21 b and the glue film 21 a are polished by the CMP method and removed from the upper surface of the second interlayer insulating film 19. Thereby, the tungsten film 21b and the glue film 21a left in the third contact hole 19a are used as the third conductive plug 21 connected to the first n-type impurity diffusion region 5a.

  Further, the second interlayer insulating film 19 is annealed at 350 ° C. for 120 seconds in a nitrogen atmosphere.

  Next, steps required until a structure shown in FIG.

  First, an antioxidant film 22 made of SiON having a thickness of 100 nm is formed on the second interlayer insulating film 19 and the third conductive plug 21.

Next, the antioxidant film 22, the second interlayer insulating film 19, and the capacitor protection films 16 and 18 are patterned by photolithography to form holes 23b and 23c on the upper electrodes 15a and 15b of the capacitors Q ₁ and Q _2. . The capacitors Q ₁ and Q ₂ damaged by the formation of the holes 23b and 23c are recovered by annealing. The annealing is performed for 60 minutes at a substrate temperature of 550 ° C. in an oxygen-containing atmosphere, for example.

  Thereafter, the antioxidant film 22 formed on the second interlayer insulating film 19 is removed by etch back.

  Next, steps required until a structure shown in FIG.

First, a multilayer metal film is formed in the holes 23 a and 23 b on the upper electrodes 15 a and 15 b of the capacitors Q ₁ and Q ₂ and on the second interlayer insulating film 19. As the multilayer metal film, for example, Ti with a thickness of 60 nm, TiN with a thickness of 30 nm, Al—Cu with a thickness of 400 nm, Ti with a thickness of 5 nm, and a TiN film with a thickness of 70 nm are sequentially formed.

Thereafter, by patterning the multilayer metal film, first-layer metal wirings 24b and 24c connected to the upper electrodes 15a and 15b through the holes 23a and 23b on the capacitors Q ₁ and Q ₂ are formed in the memory cell region, At the same time, a conductive pad 24a connected to the third conductive plug 21 is formed.

  An antireflection film (not shown) such as silicon oxynitride (SiON) may be formed on the multilayer metal film in order to prevent a decrease in pattern accuracy due to reflection of exposure light when patterning the multilayer metal film. .

  Thereafter, a third interlayer insulating film 25 is formed on the second interlayer insulating film 19, the first layer metal wirings 24b and 24c and the conductive pad 24a, and a via hole 25a is formed on the conductive pad 24c. A fourth conductive plug 26 is formed in 25 a, and then a bit line 27 connected to the upper surface of the fourth conductive plug 26 is formed on the third interlayer insulating film 25. The bit line 27 is electrically connected to the first n-type impurity diffusion region 5a via the third and fourth conductive plugs 26 and 21 and the conductive pad 24a.

By the way, when the arrangement relationship among the capacitors Q ₁ and Q ₂ , the gate electrodes 5 a and 5 b, the n-type well 1 a and the first to third contact holes 8 b, 8 c and 19 a in the memory cell region is shown in a plan view, FIG. become that way. First and second conductive plugs 12a and 12b are formed in the first and second contact holes 8b and 8c, respectively, and a third conductive plug 21 is formed in the third contact hole 19a. Is formed.

In FIG. 11, between the first capacitor Q ₁ and the second capacitor Q ₂ formed on one p well 1a, two gate electrodes 4a and 4b passing over one p well 1a are provided. There is a portion where only the conductive plug 21 between them and the second capacitor protection film 18 on both sides thereof are formed. That is, above one p-well 1a, there are portions where the capacitors Q ₁ and Q ₂ and the third conductive plug 21 are insulated only by the second capacitor protection film 18. As shown in FIGS. 7A, 7B, and 8A, the third contact hole 19a includes the opening 20a of the resist 20, the capacitors Q ₁ and Q _2, and the capacitor protective film 16. , 18 as a mask.

Therefore, the capacitors Q ₁ and Q ₂ of the present embodiment are formed larger than the capacitor 112 having the conventional structure shown in FIG. 3 by extending to the third contact hole 19a, so that the FeRAM memory cell can be miniaturized. However, the capacitance of the capacitor can be made larger than before.

  For the planar shape of the conventional capacitor 112 shown in FIG. 3, for example, the width in the extending direction of the gate electrodes 104a and 104b is 0.7 μm, and the length in the direction perpendicular to the extending direction of the gate electrodes 104a and 104b is 0. .7 μm. In this case, it is necessary to secure 0.2 μm between the contact hole 114a and the capacitors 112 on both sides thereof as an alignment margin for forming the contact hole 114a for bit line contact. If the diameter of the contact hole 114a is 0.28 μm, it is necessary to secure at least 0.68 μm between the capacitors.

Capacitors Q ₁ and Q ₂ as shown in FIG. 11 are formed with the same design rule as FIG. In this case, it is not necessary to secure an alignment margin for forming the contact hole 19a. The diameter of the contact hole 19a for bit line contact formed between the capacitors Q ₁ and Q ₂ is 0.28 μm, and the thickness of the second capacitor protection film 18 on the side surfaces of the capacitors Q ₁ and Q ₂ is about 50 nm. If this is the case, the distance between the capacitors Q ₁ and Q ₂ is 0.38 μm, which is narrower than in the prior art. Therefore, the planar shape of the capacitors Q ₁ and Q ₂ according to the present embodiment is such that the width in the extending direction of the gate electrodes 4a and 4b is 0.70 μm and the length in the direction orthogonal to the extending direction of the gate electrodes 4a and 4b. Becomes about 0.85 μm, and the area can be increased by 20 to 30% compared to the conventional case.

Meanwhile, after forming all the third contact holes 19a in the region between the capacitors Q _1, Q ₂ as described above, in the periphery of the third contact hole 19a, the side surface and the upper surface the capacitors Q _1, Q ₂ Needs to be completely covered by the capacitor protection films 16 and 18.

  For this purpose, the first capacitor protection film 16 needs to have a film thickness necessary for functioning as a capacitor protection film after etching for forming the third contact hole (bit line contact hole) 19a. There is.

The thickness T _encap capacitor protection film 16, 18, when forming a third contact hole 19a, and the etching selectivity of the thickness and the capacitor protection layer 16, 18 of the interlayer insulating film 8, 19 to be etched, the capacitor protection The film thickness is determined by the following formula (1).

However, in the formula (1), T _insulate is the film thickness (nm) of the interlayer insulating films 8 and 19, ER _encap is the etching rate (nm / min) of the capacitor protective films 8 and 19, and ER _insulate is the interlayer insulating film 8, An etching rate (nm / min) of 19 and T _protect indicate the film thicknesses of the capacitor protection films 16 and 18 necessary for capacitor protection.

T _encap = (T _insulate × ER _encap / ER _insulate ) + T _protect (1)
By the way, when the capacitor protective film 18 is selectively etched and removed from the bottom of the third contact hole 19a in the state shown in FIG. 7B, the first and second capacitors Q ₁ , Q ₂ are removed. In the meantime, it is necessary to etch the capacitor protection film 18 on the upper surface of the first interlayer insulating film 8. In this case, the capacitor protective film 18 on the side surfaces of the capacitors Q ₁ and Q ₂ may also be etched and become too thin. When the capacitors Q _1, Q ₂ on the side surface of the capacitor protection film 18 becomes thin, it may not be sufficiently isolate the capacitors Q _1, Q ₂ from the reducing atmosphere.

Therefore, as described below, after the second capacitor protective film 18 is formed as shown in FIG. 6B, the upper surface of the first interlayer insulating film 8 between the capacitors Q ₁ and Q ₂ is formed. The second capacitor protective film 18 may be removed. One example will be described below.

First, as shown in FIG. 6B, the second capacitor protection film 18 is formed on the upper and side surfaces of the capacitors Q ₁ and Q _{2 and the} upper surface of the first interlayer insulating film 8. For example, the second capacitor protection insulating film 18 is formed to a thickness of 100 nm on the capacitors Q ₁ and Q ₂ and is formed to a thickness of 90 nm on the side surface.

Thereafter, as shown in FIG. 12A, the second capacitor protection film 18 is etched in the direction perpendicular to the substrate surface, so that the second capacitor protection film 18 and the first interlayer insulating film 8 are 1 is removed from the upper surface of each capacitor protection film 16, and the side surfaces of the capacitors Q ₁ and Q ₂ are left completely covered. In this state, a region where the first interlayer insulating film 8 is exposed exists between the first and second capacitors Q ₁ and Q ₂ .

In this case, the film thickness T _encap of the first capacitor protection film 16 on the capacitors Q ₁ and Q ₂ is greater than that obtained by the above equation (1) in consideration of excessive etching of the second capacitor protection film 18. Thickened. Further, since the second capacitor protection film 18 is removed from the first capacitor protection film 16, the first capacitor protection film 16 is thicker than the above-described embodiment, for example, a thickness of about 220 to 320 nm. Is previously formed.

  Next, steps required until a structure shown in FIG.

First, an SiO ₂ film as the second interlayer insulating film 19 is formed on the second capacitor protective film 18 and the first interlayer insulating film 8 under the same conditions as in the first embodiment. Further, the upper surface of the second interlayer insulating film 19 is planarized by the CMP method. In this example, the remaining film thickness of the second interlayer insulating film 19 after CMP is set to about 300 nm above the upper electrodes 15a and 15b, and 800 nm on the first interlayer insulating film 8 on the side of the capacitors Q ₁ and Q _2. To the extent.

Subsequently, a resist 20 is applied on the second interlayer insulating film 19, and is exposed and developed to thereby develop first and second capacitors Q ₁ and Q ₂ formed above one p-type well 1a. In the meantime, an opening 20 a for forming a contact hole is formed in the resist 20. The opening 20a may have a diameter larger than the interval between the capacitors Q ₁ and Q ₂ in consideration of misalignment.

  Next, as shown in FIG. 13A, the second interlayer insulating film 19, the first interlayer insulating film 8 and the transistor protective film 7 are etched through the opening 20a of the resist 20 and anisotropically etched in the vertical direction. Thus, the third contact hole 19a is formed by self-alignment. As a result, the first n-type impurity diffusion region 5a is exposed through the third contact hole 19a. Thereafter, the resist 20 is removed.

In the etching process for forming the third contact hole 9a, the first interlayer insulating film 8, the second interlayer insulating film 19 and the transistor protective film 7 are selected with respect to the capacitor protective films 16 and 18 made of alumina. Etching conditions for etching with good performance. For example, when the first and second interlayer insulating films 8 and 19 are made of SiO ₂ and the capacitor protective films 16 and 18 are made of alumina, a parallel plate etching apparatus is used and C ₄ F is used as a reaction gas. _The etching selectivity of the SiO ₂ film to the alumina film is set to about 7 by using ₈ and Ar and CF ₄ and setting the vacuum degree of the etching atmosphere to 46 Pa and the RF power to 1000 W at 13.56 MHz.

  Next, as shown in FIG. 13B, a third conductive plug 21 is formed in the third contact hole 19a. The third conductive plug 21 is formed by the method described above.

  Further, the second interlayer insulating film 19 is annealed at 350 ° C. for 120 seconds in a nitrogen atmosphere.

  Next, steps required until a structure shown in FIG.

First, according to the process shown in FIG. 9B, holes 23b and 23c are formed on the upper electrodes 15a of the capacitors Q ₁ and Q ₂ . The capacitors Q ₁ and Q ₂ damaged by the formation of the holes 23b and 23c are recovered from the damage by oxygen annealing. The antioxidant film formed on the second interlayer insulating film 19 is removed.

Further, according to the process shown in FIG. 10, _first- layer metal wirings 24b and 24c connected to the upper electrodes 15a and 15b of the capacitors Q ₁ and Q ₂ through the holes 23a and 23b are formed, and at the same time, the third conductive plug 21 is formed. A conductive pad 24a connected to the is formed.

  Thereafter, a third interlayer insulating film 25 is formed on the second interlayer insulating film 19, the first layer metal wirings 24b and 24c and the conductive pad 24a, and a via hole 25a is formed on the conductive pad 24c. A fourth conductive plug 26 is formed in 25 a, and then a bit line 27 connected to the upper surface of the fourth conductive plug 26 is formed on the third interlayer insulating film 25.

  12 to 14, the third contact hole 19 a is formed in the first and second interlayer insulating films 8 and 19 and the transistor protection film 7, and the second interlayer insulating film 19 is formed. The second capacitor protective film 18 does not exist at the bottom of the upper portion of the third contact hole 19a. Accordingly, when the third contact hole 19a is formed, it is not necessary to etch the second capacitor protective film 18 crossing the third contact hole 19a, so that the second capacitor protective film 18 on the side surface of the capacitor is excessive. The third contact hole 19a can be easily formed.

In the above-described embodiment, the process of forming the third contact hole 19a continuously with the first and second interlayer insulating films 8 and 19 and forming one conductive plug 21 therein has been described. However, the third contact hole 19 a may be formed separately in the first interlayer insulating film 8 and the second interlayer insulating film 19. That is, a contact hole is formed in the first interlayer insulating film 8 on the first impurity diffusion region 5a, and a first conductive plug for bit line contact is formed therein, and capacitors Q ₁ , Q ₂ are formed. Is formed on the first interlayer insulating film 8, capacitor protective films 16 and 18 covering the capacitors Q ₁ and Q ₂ and a second interlayer insulating film 19 are formed, and then the second interlayer is formed on the first conductive plug. A contact hole penetrating the insulating film and the protective films 16 and 18 may be formed, and a second-layer conductive plug for bit line contact may be formed therein. In this case, the bit line 27 is electrically connected to the first impurity diffusion region 5a via the first and second conductive plugs.

  As described above, according to the present invention, the upper surface and the side surface of the ferroelectric capacitor formed on the first insulating film are covered with the capacitor protective film, and the first capacitor formed on the capacitor protective film and the first insulating film. 2 Since the holes formed in the insulating film are adjacent to each other on the side surface of the capacitor via the capacitor protective film, the distance between the ferroelectric capacitor and the contact hole becomes equal to the film thickness of the capacitor protective film. It is possible to make the capacitor area larger than the conventional one by making the formation region of the capacitor close to the hole side.

  In addition, by selecting the material of the capacitor protective film so that the second insulating film can be selectively etched with respect to the capacitor protective film, the second insulating film is in contact with the capacitor protective film on the side surface of the ferroelectric capacitor. Since the conductive plug is formed in the hole and formed in the film, the hole can be aligned in a self-aligned manner by the capacitor protective film on the surface of the ferroelectric capacitor. It is not necessary to ensure a wide alignment margin, and hole formation can be facilitated.

(Supplementary note 1) a first impurity diffusion region formed in a semiconductor substrate;
A first insulating film formed above the semiconductor substrate;
A capacitor formed on the first insulating film and having a lower electrode, a ferroelectric film, and an upper electrode;
An insulating capacitor protective film that covers the upper and side surfaces of the capacitor and is made of a material different from that of the first insulating film;
A second insulating film formed on the capacitor protective film and the first insulating film and made of a material that can be selectively etched with respect to the capacitor protective film;
A first hole formed in the second insulating film and adjacent to a side surface of the capacitor with the capacitor protective film interposed therebetween;
A semiconductor device comprising: a first conductive plug formed in the first hole and electrically connected to the first impurity diffusion region.

  (Supplementary note 2) The semiconductor device according to supplementary note 1, wherein two capacitors are formed on both sides of the first hole via the capacitor protective film.

  (Additional remark 3) The said capacitor protective film is comprised from either an alumina, a PZT type material, or a titanium oxide, The semiconductor device of Additional remark 1 or Additional remark 2 characterized by the above-mentioned.

(Appendix 4) a second impurity diffusion region formed in the semiconductor substrate;
A second hole formed below the lower electrode of the capacitor and on the second impurity diffusion region of the first insulating film;
The semiconductor according to any one of appendix 1 to appendix 3, further comprising: a second conductive plug formed in the second hole and electrically connected to the second impurity diffusion region. apparatus.

  (Supplementary note 5) The semiconductor device according to supplementary note 4, wherein the second impurity diffusion region and the first impurity diffusion region constitute a part of a transistor formed in the semiconductor substrate.

  (Supplementary note 6) The semiconductor device according to any one of supplementary notes 1 to 5, wherein the capacitor protective film is formed only on a surface of the capacitor.

  (Supplementary note 7) Any one of Supplementary notes 1 to 5, wherein the capacitor protective film extends between the first insulating film and the second insulating film around the capacitor. A semiconductor device according to 1.

  (Supplementary note 8) The semiconductor device according to supplementary note 7, wherein the capacitor protective film is also formed around the first hole.

  (Supplementary note 9) The semiconductor device according to any one of supplementary notes 1 to 8, wherein the capacitor protective film has a plurality of layer structures on the upper electrode of the capacitor.

(Supplementary note 10) forming a first impurity diffusion region in a semiconductor substrate;
Forming a first insulating film above the semiconductor substrate;
Forming a first conductive film, a ferroelectric film and a second conductive film on the first insulating film in order;
Patterning the second conductive film, the ferroelectric film, and the first conductive film using a first mask to form a capacitor;
Forming an insulating capacitor protective film made of a material different from that of the first insulating film on an upper surface and a side surface of the capacitor;
Forming a second insulating film made of a material that can be selectively etched with respect to the capacitor protective film on the capacitor protective film and the first insulating film;
Forming a first hole in the second insulating film in contact with the capacitor protection film on a side surface of the capacitor;
Forming a conductive plug electrically connected to the first impurity diffusion region in the first hole.

  (Additional remark 11) The said 1st hole is extended in the said 1st insulating film, The manufacturing method of the semiconductor device of Additional remark 10 characterized by the above-mentioned.

(Supplementary Note 12) Two capacitors are formed above the first impurity diffusion region with an interval between them.
The supplementary note 10 or the supplementary note, wherein the first hole is formed in a self-aligned manner between the two capacitors by the capacitor protective film on the top surface and the side surface of each capacitor. 11. A method for manufacturing a semiconductor device according to 11.

(Supplementary Note 13) The first hole is formed by etching the second insulating film through an opening of a second mask formed on the second insulating film,
13. The method of manufacturing a semiconductor device according to appendix 12, wherein the opening of the second mask has a diameter larger than an interval between the two capacitors.

  (Supplementary Note 14) The capacitor protective film is formed by forming a first protective insulating film on the second conductive film, the first conductive film, the ferroelectric film, and the second conductive film. Patterning the first protective insulating film using the first mask together with the film, and forming a second protective insulating film on the first protective insulating film and on the side surface of the capacitor 14. The method for manufacturing a semiconductor device according to any one of appendix 10 to appendix 13, characterized by comprising:

  (Supplementary Note 15) By anisotropically etching the second protective insulating film, the second protective insulating film is removed from above the first insulating film around the capacitor and on the side surface of the capacitor 15. The method for manufacturing a semiconductor device according to appendix 14, further comprising a remaining step.

  (Supplementary note 16) The method according to any one of supplementary notes 10 to 15, further comprising a step of forming the first hole in the capacitor protective film extending from the capacitor onto the first insulating film. Semiconductor device manufacturing method.

(Supplementary Note 17) Forming a second impurity diffusion region in the semiconductor substrate simultaneously with the first impurity diffusion region;
Forming a second hole under the lower electrode of the capacitor in the first insulating film;
The method according to any one of appendices 10 to 16, further comprising: forming a second conductive plug electrically connected to the second impurity diffusion region in the second hole. Semiconductor device.

  (Supplementary note 18) The supplementary note 17, further comprising a step of forming a gate electrode between the first impurity diffusion region and the second impurity diffusion region of the semiconductor substrate through a gate insulating film. The manufacturing method of the semiconductor device as described in 2.

  (Supplementary note 19) The process according to any one of supplementary notes 10 to 18, wherein the step of forming the capacitor protection insulating film is a step of forming a film of any one of alumina, a PZT material, and titanium oxide. A method for manufacturing a semiconductor device.

FIGS. 1A to 1C are sectional views (No. 1) of a conventional semiconductor device formation process. FIG. 2 is a cross-sectional view of a conventional semiconductor device formation process (part 2). FIG. 3 is a plan view showing the arrangement of transistors and capacitors in the memory cell region of a conventional semiconductor device. 4A and 4B are cross-sectional views (part 1) showing the manufacturing process of the semiconductor device according to the embodiment of the present invention. 5A and 5B are cross-sectional views (part 2) illustrating the manufacturing process of the semiconductor device according to the embodiment of the present invention. 6A and 6B are cross-sectional views (part 3) illustrating the manufacturing process of the semiconductor device according to the embodiment of the present invention. 7A and 7B are cross-sectional views (part 4) showing the manufacturing process of the semiconductor device according to the embodiment of the present invention. 8A and 8B are cross-sectional views (part 5) showing the manufacturing process of the semiconductor device according to the embodiment of the present invention. FIGS. 9A and 9B are cross-sectional views (part 6) illustrating the manufacturing process of the semiconductor device according to the embodiment of the present invention. FIG. 10 is a sectional view (No. 7) showing the manufacturing process of the semiconductor device according to the embodiment of the invention. FIG. 11 is a plan view showing the arrangement of transistors and capacitors in the memory cell region of the semiconductor device according to the embodiment of the present invention. 12A and 12B are cross-sectional views (part 1) showing another manufacturing process of the semiconductor device according to the embodiment of the present invention. 13A and 13B are cross-sectional views (part 2) showing another manufacturing process of the semiconductor device according to the embodiment of the present invention. FIG. 14 is a cross-sectional view (part 3) illustrating another manufacturing process of the semiconductor device according to the embodiment of the present invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Silicon substrate (semiconductor substrate), 2 ... Element isolation insulating film, 3 ... Gate insulating film, 4a, 4b ... Gate electrode, 5a-5c ... Impurity diffusion region, 6 ... Side wall, 7 ... Cover film, 8, 19 ... Interlayer insulating film, 8a, 8b, 19a ... Contact hole, 9a ... Glue film, 9b ... Tungsten film, 10b, 10c ... Conductive plug, 13, 15 ... Conductive film, 14 ... Ferroelectric film, 16 ... Capacitor protection 17a, 17b ... mask, 18 ... capacitor protective film, 20 ... resist, 20a ... opening, 21a ... glue film, 21b ... tungsten film, 21 ... conductive plug, 22 ... antioxidant film, 23b, 23c ... hole , 24a ... conductive pads, 24b, 24c ... wire, 25 ... interlayer insulation film, 26 ... conductive plug, 27 ... bit lines, T _1, T ₂ ... MOS transistor, Q _{1, 2} ... capacitor.

Claims (4)

A first impurity diffusion region formed in the semiconductor substrate;
A first insulating film formed above the semiconductor substrate;
A capacitor formed on the first insulating film and having a lower electrode, a ferroelectric film, and an upper electrode;
Covering the upper and side surfaces of the capacitor, and an insulating capacitor protective film made of alumina;
A second insulating film made of silicon dioxide formed on the capacitor protective film and the first insulating film;
A first hole formed in the second insulating film and exposing the capacitor protection film covering a side surface of the capacitor;
A first conductive plug formed in the first hole and electrically connected to the first impurity diffusion region and insulated from the capacitor only by the capacitor protection film;
2. The semiconductor device according to claim 1, wherein two capacitors are formed on both sides of the first hole via the capacitor protective film. A second impurity diffusion region formed in the semiconductor substrate;
A second hole formed below the lower electrode of the capacitor and on the second impurity diffusion region of the first insulating film;
The semiconductor device according to claim 1, further comprising: a second conductive plug formed in the second hole and electrically connected to the second impurity diffusion region.   3. The semiconductor device according to claim 1, wherein the capacitor protective film extends between the first insulating film and the second insulating film around the capacitor. .   4. The semiconductor device according to claim 1, wherein the capacitor protective film has a plurality of layer structures on the upper electrode of the capacitor. 5.

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