JP2009105332A - Method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device for improving yield of the semiconductor device provided with a ferroelectric capacitor. <P>SOLUTION: The method of manufacturing the semiconductor device includes: a step of forming a first interlayer dielectric 31 above a silicon substrate 20; a step of forming a capacitor Q formed by laminating a lower electrode 41a, a capacitor dielectric film 42a made of a ferroelectric material and an upper electrode 43a made of a conductive oxide on the first interlayer dielectric 31 in this order; a step of forming a second interlayer dielectric 54 coating the capacitor Q; a step of forming a hole 54a exposing the upper electrode 43a in the second interlayer dielectric 54 on the upper electrode 43a; a step of forming a single-layer glue film 58 made of a conductive nitride connected to the upper electrode 43a in the hole 54a by a sputtering method; a step of annealing the glue film 58; and a step of forming a conductive plug 59a on the glue film 58 in the hole 54a. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device.

  In recent years, with the progress of digital technology, development of a nonvolatile memory capable of storing a large amount of data at high speed has been advanced.

  As such a nonvolatile memory, a flash memory and a ferroelectric memory are known.

  Among these, the flash memory has a floating gate embedded in a gate insulating film of an insulated gate field effect transistor (IGFET), and stores information by accumulating charges representing stored information in the floating gate. However, such a flash memory has a drawback that a tunnel current needs to flow through the gate insulating film when writing or erasing information, and a relatively high voltage is required.

  On the other hand, the ferroelectric memory is also called FeRAM (Ferroelectric Random Access Memory), and stores information using the hysteresis characteristic of the ferroelectric film provided in the ferroelectric capacitor. The ferroelectric film is polarized according to the voltage applied between the upper electrode and the lower electrode of the capacitor, and the spontaneous polarization remains even if the voltage is removed. When the polarity of the applied voltage is reversed, this spontaneous polarization is also reversed, and the direction of the spontaneous polarization is made to correspond to “1” and “0”, whereby information is written in the ferroelectric film. FeARM has the advantage that the voltage required for this writing is lower than that in the flash memory and that writing can be performed at a higher speed than the flash memory.

  Such FeRAM has already been put into practical use in some fields such as IC cards, and its high performance has already been demonstrated, but further improvement in reliability and improvement in yield are required.

In addition, the technique relevant to this application is disclosed by the following patent documents 1-3.
JP 2006-202848 A JP 2006-108625 A Japanese Patent Laid-Open No. 11-307738

  An object of the present invention is to provide a method of manufacturing a semiconductor device capable of improving the yield of a semiconductor device having a ferroelectric capacitor.

  According to one aspect of the present invention, a step of forming a first insulating film over a semiconductor substrate, a lower electrode, a capacitor dielectric film made of a ferroelectric material, and a conductive material on the first insulating film. Forming a capacitor formed by stacking an upper electrode made of an oxide in this order; forming a second insulating film covering the capacitor; and forming the upper electrode on the second insulating film above the upper electrode. Forming a hole exposing the gate electrode, forming a glue film made of a conductive nitride connected to the upper electrode in the hole, and annealing the glue film in an atmosphere containing nitrogen, And a step of forming a conductive plug on the glue film in the hole after the annealing.

  According to the present invention, since the glue film made of conductive nitride is annealed, a portion of the glue film where nitriding is insufficient is nitrided or oxidized. This prevents defects in the conductive plug due to insufficiently nitrided conductive nitride, and the conductive plug becomes dense, so that reducing substances such as hydrogen and moisture pass through the conductive plug. Intrusion routes are less likely to occur. For this reason, it is difficult for the reducing substance to enter the capacitor dielectric film during the manufacturing process, the deterioration of the capacitor dielectric film is prevented, and the yield of the semiconductor device is improved.

  Furthermore, since the glue film is made of conductive nitride, the glue film is less likely to be oxidized by the upper electrode made of conductive oxide, compared to the case where a pure metal film is formed as the glue film. The contact resistance between the upper electrode and the upper electrode is improved.

  In addition, by configuring the upper electrode with a conductive oxide in this way, it becomes easy to prevent the ferroelectric characteristics of the capacitor dielectric film made of a ferroelectric material from being deteriorated during the manufacturing.

  Further, by performing the above annealing on the glue film at a substrate temperature of 400 ° C. or lower, it is possible to suppress the deterioration of the ferroelectric capacitor Q due to the annealing.

  According to the present invention, since the glue film is annealed, it becomes difficult for defects to enter the conductive plug formed on the glue film, and the yield of the semiconductor device can be improved.

  Next, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

  1 to 10 are cross-sectional views in the course of manufacturing the semiconductor device according to the present embodiment.

The semiconductor device is a planar type FeRAM in which a conductive plug is formed on a contact region of a capacitor lower electrode. First, steps required until a sectional structure shown in FIG.

  First, a trench for STI (Shallow Trench Isolation) that defines an active region of a transistor is formed on the surface of an n-type or p-type silicon (semiconductor) substrate 20, and an insulating film such as silicon oxide is embedded therein. The element isolation insulating film 21 is used. The element isolation structure is not limited to STI, and the element isolation insulating film 21 may be formed by a LOCOS (Local Oxidation of Silicon) method.

  Next, a p-type impurity is introduced into the active region of the silicon substrate 20 to form the p-well 22, and then the surface of the active region is thermally oxidized to form a thermal oxide film that becomes the gate insulating film 28.

  Subsequently, an amorphous or polycrystalline silicon film and a tungsten silicide film are sequentially formed on the entire upper surface of the silicon substrate 20, and these films are patterned by photolithography to form gate electrodes 25a and 25b.

  On the p-well 22, the two gate electrodes 25 a and 25 b are arranged substantially in parallel with a space therebetween, and the gate electrodes 25 a and 25 b constitute a part of the word line.

  Next, n-type impurities are introduced into the silicon substrate 20 beside the gate electrodes 25a and 25b by ion implantation using the gate electrodes 25a and 25b as masks to form first to third source / drain extensions 24a to 24c. .

  After that, an insulating film is formed on the entire upper surface of the silicon substrate 20, and the insulating film is etched back to leave the insulating sidewalls 26 beside the gate electrodes 25a and 25b. As the insulating film, a silicon oxide film is formed by, for example, a CVD (Chemical Vapor Deposition) method.

  Subsequently, the n-type impurity is ion-implanted again into the silicon substrate 20 while using the insulating sidewalls 26 and the gate electrodes 25a and 25b as masks, whereby the first silicon substrate 20 on the side of each gate electrode 25a and 25b. -Third source / drain regions 23a-23c are formed.

Through the above steps, the active region of the silicon substrate 20 includes the first and second MOS transistors TR including the gate insulating film 28, the gate electrodes 25a and 25b, and the first to third source / drain regions 23a to 23c. ₁ , TR ₂ is formed.

  Next, after a refractory metal layer such as a cobalt layer is formed on the entire upper surface of the silicon substrate 20 by sputtering, the refractory metal layer is heated and reacted with silicon to form a refractory metal silicide on the silicon substrate 20. Layer 27 is formed. The refractory metal silicide layer 27 is also formed on the surface layer portion of the gate electrodes 25a and 25b, whereby the resistance of the gate electrodes 25a and 25b is lowered.

  Thereafter, the unreacted refractory metal layer on the element isolation insulating film 21 and the like is removed by wet etching.

  Subsequently, as shown in FIG. 1B, a silicon oxide film having a thickness of about 20 nm and a silicon nitride (SiN) film having a thickness of about 80 nm are formed in this order by the plasma CVD method, and these laminated films are covered. The insulating film 29 is used. Next, a silicon oxide film having a thickness of about 1000 nm is formed on the cover insulating film 29 as the first insulating film 30 by plasma CVD using TEOS gas.

  Then, the upper surface of the first insulating film 30 is polished and planarized by a CMP (Chemical Mechanical Polishing) method, and the remaining first insulating film 30 and the cover insulating film 29 are used as a first interlayer insulating film 31. As a result of the CMP described above, the thickness of the first interlayer insulating film 31 is about 700 nm on the flat surface of the silicon substrate 20.

  Next, as shown in FIG. 1C, the first interlayer insulating film 31 is patterned by photolithography to form contact holes 31a to 31c on the first to third source / drain regions 23a to 23c, respectively. Form.

  The diameters of these contact holes 31a to 31c are not particularly limited, but are about 0.25 μm in this embodiment.

  Then, as shown in FIG. 2A, a titanium film having a thickness of about 30 nm and a titanium nitride film having a thickness of about 20 nm are formed on the inner surfaces of the contact holes 31a to 31c and the upper surface of the first interlayer insulating film 31 by sputtering. Are formed as a glue film in this order. Further, a tungsten film is formed on the glue film by a CVD method using tungsten hexafluoride gas, and the contact holes 31a to 31c are completely filled with the tungsten film.

  Thereafter, excess tungsten film and glue film on the first interlayer insulating film 31 are removed by polishing by the CMP method, and the above film is removed into the first to third conductive plugs 32a in the contact holes 31a to 31c. Leave as ~ 32c. These first to third contact plugs 32a to 32c are electrically connected to the first to third source / drain regions 23a to 23c therebelow.

  By the way, the first to third contact plugs 32a to 32c are mainly composed of tungsten. However, tungsten is very easily oxidized, and if it is oxidized in the process, a contact failure is caused.

  Therefore, in the next step, as shown in FIG. 2B, as the antioxidant film 36 for protecting the first to third contact plugs 32a to 32c from the oxidizing atmosphere, silicon oxynitride is formed by plasma CVD. An (SiON) film 36a and a silicon oxide film 36b are formed in this order. The thickness of the silicon oxynitride film 36a is, for example, 100 nm, and the thickness of the silicon oxide film 36b is about 130 nm. Further, TEOS is adopted as a film forming gas for the silicon oxide film 36b.

  Next, as shown in FIG. 2C, in order to improve the crystallinity of the lower electrode of the ferroelectric capacitor, which will be described later, and finally improve the crystallinity of the capacitor dielectric film, A first alumina film 37 is formed to a thickness of about 20 nm by sputtering.

  Next, steps required until a sectional structure shown in FIG.

  First, a platinum film is formed to a thickness of about 150 nm by sputtering, and this is used as the lower electrode conductive film 41.

Next, as the ferroelectric film 42, a PZT film is formed on the lower electrode conductive film 41 to a thickness of about 150 nm by sputtering. As a method for forming the ferroelectric film 42, there are a MOCVD (Metal Organic CVD) method and a sol-gel method in addition to the sputtering method. Further, the material of the ferroelectric film 42 is not limited to the above-described PZT, and Bi layer structure compounds such as SrBi ₂ Ta ₂ O ₉ and SrBi ₂ (Ta, Nb) ₂ O _9, or PLZT doped with lanthanum in PZT. Alternatively, the ferroelectric film 42 may be composed of other metal oxide ferroelectrics.

  Subsequently, PZT constituting the ferroelectric film 42 is lightly crystallized by RTA (Rapid Thermal Anneal) in an oxygen-containing atmosphere. Such annealing is called crystallization annealing. The crystallization annealing conditions are, for example, a substrate temperature of 560 ° C. and a processing time of 90 seconds.

Thereafter, an iridium oxide (IrO ₂ ) film having a thickness of about 50 nm is formed on the ferroelectric film 42 by sputtering, and the iridium oxide film is used as a first conductive metal oxide film 43b.

  Then, the ferroelectric film 42 is again subjected to crystallization annealing while being covered with the first conductive metal oxide film 43b in this manner, so that the ferroelectric film 42 is completely crystallized. The conditions for this crystallization annealing are not particularly limited, but in this embodiment, the substrate temperature is 700 ° C. and the processing time is 120 seconds.

  Further, an iridium oxide film having a thickness of about 200 nm is formed on the first conductive metal oxide film 43b as a second conductive metal oxide film 43c by sputtering. As a result, the upper electrode conductive film 43 composed of the first and second conductive metal oxide films 43b and 43c is formed on the ferroelectric film.

In this embodiment, the upper electrode conductive film 43 is formed of iridium oxide as described above. However, the upper electrode conductive film 43 is formed of a conductive oxide other than iridium oxide, for example, strontium ruthenate (SrRuO ₃ ). May be.

  Subsequently, as shown in FIG. 3B, the lower electrode conductive film 41, the ferroelectric film 42, and the upper electrode conductive film 43 are separately patterned to form a lower electrode 41a, a capacitor dielectric film 42a, The capacitor Q including the upper electrode 43a is formed. In this patterning, the portion of the first alumina film 37 not covered with the lower electrode 41a is also patterned and removed.

  Since the capacitor dielectric film 42a constituting the capacitor Q is made of an oxide ferroelectric material such as PZT, it is easily reduced when it comes into contact with a reducing substance such as hydrogen in the subsequent manufacturing process. Body characteristics are likely to deteriorate.

  However, when the upper electrode 43a is made of a conductive oxide such as iridium oxide as in the present embodiment, it is possible to easily prevent the capacitor dielectric film 42a from being reduced during the manufacturing process. This is presumed to be because the conductive oxide of the upper electrode 43a traps the reducing substance, and the reducing substance hardly reaches the capacitor dielectric film 42a.

  Next, as shown in FIG. 4A, a second alumina film 50 for protecting the capacitor Q from a reducing substance such as moisture and hydrogen and preventing the capacitor dielectric film 42a from being deteriorated is formed on the silicon substrate 20. It is formed on the entire upper surface. The second alumina film 50 is formed to a thickness of about 50 nm, for example, by sputtering.

  Then, in order to recover the damage received by the capacitor dielectric film 42a in the steps so far by etching, sputtering, etc., the capacitor is used under the conditions of a substrate temperature of 650 ° C. and a processing time of 90 minutes in an atmosphere of 100% oxygen in the furnace. Recovery annealing is performed on the dielectric film 42a.

  Next, as shown in FIG. 4B, the second alumina film 50 is patterned to selectively remove the second alumina film 50 on the first to third contact plugs 32a to 32c.

  Thereafter, as shown in FIG. 5A, a silicon oxide film having a thickness of about 1500 nm is formed as a second interlayer insulating film 54 on the second alumina film 50 by plasma CVD using TEOS gas as a reaction gas. To do. Concavities and convexities reflecting the capacitor Q are formed on the upper surface of the second interlayer insulating film 54. Therefore, in order to eliminate this unevenness, the upper surface of the second interlayer insulating film 54 is polished and planarized by the CMP method, and the thickness of the second interlayer insulating film 54 on the flat surface of the second alumina film 50 is about 1000 nm. To.

Thereafter, as a dehydration treatment of the second interlayer insulating film 54, the surface of the second interlayer insulating film 54 is exposed to N ₂ O plasma. Instead of such N ₂ O plasma treatment, the second interlayer insulating film 54 may be annealed and dehydrated in a furnace.

  Next, as shown in FIG. 5B, a photoresist is applied on the second interlayer insulating film 54 and developed to form a first window having hole-shaped first and second windows 55a and 55b. One resist pattern 55 is formed.

  Then, the second interlayer insulating film 54 and the underlying second alumina film 50 are etched through the first and second windows 55a and 55b. As a result, a first hole 54a in which the upper electrode 43a is exposed is formed in the second interlayer insulating film 54 on the upper electrode 43a, and a second hole 54b is formed in the contact region of the lower electrode 41a. .

  Thereafter, the first resist pattern 55 is removed.

  Next, as shown in FIG. 6A, a photoresist is applied again on the second interlayer insulating film 54, developed, and first coated on the first to third contact plugs 32a to 32c. A second resist pattern 57 having third to fifth windows 57c to 57e is formed.

  Further, by etching the second interlayer insulating film 54 and the silicon oxide film 36b through the third to fifth windows 57c to 57e, third to fifth holes 54c to 54e are formed on the contact plugs 32a to 32c. To do.

Such etching is performed by a parallel plate plasma etching apparatus using a mixed gas of C ₄ F ₈ , Ar, O ₂ , and CO as an etching gas, and the silicon oxynitride film 36a becomes a stopper film in this etching.

  4B, since the second alumina film 50 on the contact plugs 32a to 32c has been removed in advance, the second alumina film 50, which is difficult to chemically etch, is formed. It is not necessary to perform etching in the process, and the holes 54c to 54e can be easily formed by etching.

  Thereafter, the fifth resist pattern 57 is removed.

  Next, steps required until a sectional structure shown in FIG.

First, the silicon substrate 20 is put in a parallel plate plasma etching apparatus, and a mixed gas of CHF ₃ , Ar, and O ₂ is supplied to the etching apparatus as an etching gas. As a result, the silicon oxynitride film 36a under the third to fifth holes 54c to 54e is etched, and the first to third contact plugs 32a to 32c are exposed to these holes, and the first and second holes 54a are exposed. , 54b are removed, and the upper surfaces of the upper electrode 43a and the lower electrode 41a are cleaned.

  Since the first to third contact plugs 32a to 32c are covered with the silicon oxynitride film 36a constituting the antioxidant film 36 until this process is completed, the tungsten constituting each contact plug 32a to 32c is oxidized. This prevents contact failure.

  Next, steps required until a sectional structure shown in FIG.

  First, in order to clean the inner surfaces of the first to fifth holes 54a to 54e, the inner surfaces of the holes 54a to 54e are exposed to an argon atmosphere that has been made plasma by high-frequency power, and the inner surfaces are sputter etched. The etching amount is about 10 nm, for example.

  Next, a titanium nitride film is formed to a thickness of about 100 nm as a glue film 58 on the inner surfaces of the first to fifth holes 54a to 54e and the upper surface of the second interlayer insulating film 54 by sputtering.

  In addition to the role as a barrier metal film, the glue film 58 also plays a role of improving adhesion between a tungsten film described later and the second interlayer insulating film 54. In the first hole 54a, the glue film 58 is connected to the upper electrode 43a.

  The conditions for forming the glue film 58 are not particularly limited. In this embodiment, a titanium target is sputtered in a sputtering atmosphere composed of a mixed atmosphere of nitrogen gas and argon gas, and titanium scattered from the titanium target is nitrided in the sputtering atmosphere to form a titanium nitride film. The substrate temperature at the time of forming the glue film 58 is, for example, 200 ° C.

  Here, it is conceivable to form a titanium nitride film by MOCVD instead of sputtering. However, the film formation of titanium nitride by the MOCVD method involves a hydrogen / nitrogen plasma treatment for removing carbon remaining in the film, so that the capacitor dielectric film 42a is easily reduced and deteriorated during the film formation. .

  In particular, since the glue film 58 is formed in the first hole 54a and very close to the capacitor dielectric film 42a, the capacitor film is formed when formed by the CVD method as compared with the glue film formed in other parts. The degree of influence on the dielectric film 42a is remarkable. Therefore, from the viewpoint of preventing deterioration of the capacitor dielectric film 42a due to hydrogen, it is preferable to form the glue film 58 by sputtering as in the present embodiment.

  Incidentally, in the contact plugs 32a to 32c on the source / drain regions 23a and 23b, as described with reference to FIG. 2A, a laminated film of a titanium film and a titanium nitride film is formed as the glue film.

  However, when a titanium film is formed as the lowermost layer of the glue film 58 formed in the first hole 54a, the upper electrode 43a and the titanium film come into contact with each other, whereby oxygen in the conductive oxide constituting the upper electrode 43a. As a result, titanium is oxidized, and insulating titanium oxide is formed between the glue film 58 and the upper electrode 43a, and the contact resistance between the upper electrode 43a and the glue film 58 is increased.

  Therefore, when the upper electrode 43a is made of a conductive oxide, it is not preferable to form a titanium film in the lowermost layer of the glue film 58, and the glue film is a single layer film of a titanium nitride film as in this embodiment. 58 is preferred.

  The glue film 58 is not limited to a titanium nitride film. As the glue film 58, a single layer film made of conductive nitride can be used. Examples of such conductive nitride include tantalum nitride (TaN) and titanium aluminum nitride (TiAlN) in addition to titanium nitride.

  Here, in the glue film 58 formed by the sputtering method, the conductive nitride such as titanium nitride is not necessarily completely nitrided, and there is a possibility that titanium with insufficient nitriding is exposed slightly. There is.

  Titanium that is insufficiently nitrided may cause abnormal growth in the tungsten film formed on the glue film 58 and may cause micro defects such as small “su” in the tungsten film.

  Therefore, in the next step, as shown in FIG. 7B, the glue film 58 is annealed in an atmosphere containing nitrogen, thereby nitriding titanium that is insufficiently nitrided that appears to be present in the glue film 58. .

  The annealing conditions are not particularly limited, but in this embodiment, annealing is performed in a furnace at a substrate temperature of 300 ° C. to 400 ° C., for example, 350 ° C. for about 10 minutes in an atmosphere of 100% nitrogen.

  In this case, annealing is performed in a 100% nitrogen atmosphere excluding oxygen from the annealing atmosphere, so that titanium is prevented from being oxidized during the annealing to become insulating titanium oxide, and the glue film 58 and the upper electrode 43a are prevented. It is possible to prevent the contact resistance from increasing.

  If the annealing atmosphere contains hydrogen, the capacitor dielectric film 42a may be reduced and deteriorated by the hydrogen. Therefore, it is preferable to perform the annealing in an atmosphere from which hydrogen is excluded.

Alternatively, annealing may be performed in a plasma atmosphere containing N ₂ O instead of the above. The annealing conditions in that case are not particularly limited, but the flow rate ratio of N ₂ O gas and nitrogen gas may be 4: 1, and annealing may be performed at a substrate temperature of 300 ° C. to 400 ° C., for example, 350 ° C. for 1 minute. . The pressure of the plasma atmosphere is, for example, 3.0 Torr, and the power for converting to plasma is 525 W.

  Furthermore, instead of annealing in an atmosphere containing nitrogen as described above, this annealing may be performed in a rare gas atmosphere such as argon.

  In that case, after the annealing is completed, when the silicon substrate 20 is taken out of the annealing chamber and the glue film 58 is exposed to the atmosphere, titanium that has been insufficiently nitrided in the glue film 58 remains on the silicon substrate 20. Since it is oxidized by the remaining heat of annealing, the state where unreacted titanium is exposed to the glue film 58 can be avoided. If oxidation is caused by such residual heat, the glue film 58 is not excessively oxidized, and the resistance of the glue film 58 is not significantly increased by the insulating titanium oxide.

  The conditions for annealing in such a rare gas atmosphere are not particularly limited. For example, the annealing can be performed at a substrate temperature of 300 to 400 ° C., for example, 350 ° C. for about 10 minutes in a furnace having a 100% argon atmosphere.

  Further, by removing oxygen from the rare gas atmosphere as in the case of annealing in a nitrogen atmosphere, it is possible to prevent the glue film 58 from being excessively oxidized by the annealing and increasing its resistance value.

  Further, this annealing may be performed in a mixed atmosphere of a rare gas and nitrogen.

Subsequently, as shown in FIG. 8A, a tungsten film is formed as a plug conductive film 59 on the glue film 58, and the third to fifth holes 54 c to 54 e are completely formed by the plug conductive film 59. Embed in. The tungsten film is formed by a CVD method using tungsten hexafluoride (WF ₆ ) and hydrogen as reaction gases.

  Here, since the glue film 58 is annealed in advance in the step of FIG. 7B so that unreacted titanium is not exposed to the glue film 58, the plug conductive film 59 made of tungsten is unreacted. Thus, abnormal growth is prevented by the titanium, and minute defects such as “su” can be prevented from being formed in the plug conductive film 59.

  As a result, hydrogen contained in the reaction gas for the tungsten film can be prevented from passing through the minute defects and reaching the capacitor dielectric film 42a, and the ferroelectric characteristics of the capacitor dielectric film 42a can be reduced by the reduction action of hydrogen. Deterioration can be prevented.

  Next, as shown in FIG. 8B, the excess plug conductive film 59 on the second interlayer insulating film 54 is removed by polishing by the CMP method, and plugs are only plugged into the first to fifth holes 54a to 54e. The conductive film 59 is left as the first to fifth conductive plugs 59a to 59e.

  Next, steps required until a sectional structure shown in FIG.

  First, a metal laminated film is formed on each of the first to fifth conductive plugs 59a to 59e and the glue film 58 by sputtering. The metal laminated film is formed by forming a copper-containing aluminum film having a thickness of 360 nm, a titanium film having a thickness of 5 nm, and a titanium nitride film having a thickness of 70 nm in this order from the bottom.

  Further, a silicon oxynitride (SiON) film (not shown) is formed as an antireflection film on the metal laminated film. Then, by patterning the metal laminated film and the glue film 58 by photolithography, a first-layer metal wiring 62 as shown is formed.

  Subsequently, as shown in FIG. 10, after a silicon oxide film is formed as a third interlayer insulating film 65 by a plasma CVD method, the third interlayer insulating film 65 is planarized by a CMP method.

  Next, the third interlayer insulating film 65 is patterned by photolithography to form a hole on the first-layer metal wiring 62, and a sixth conductive plug 67 mainly composed of a tungsten film is formed in the hole. .

  Then, on the third interlayer insulating film 65, a second metal wiring 68, a fourth interlayer insulating film 69 made of a silicon oxide film, and a seventh conductive plug 70 mainly composed of tungsten are illustrated as shown. To form.

  Here, unlike the first conductive plug 59a, the sixth and seventh conductive plugs 67 and 70 are not formed on the conductive oxide such as the upper electrode 43a, so that the glue film constituting these plugs is formed. There is no need to worry about oxidation of titanium, and a titanium film can be formed as a glue film. In the present embodiment, a titanium film having a thickness of 10 nm and a titanium nitride film having a thickness of 14 nm are stacked in this order, and these films serve as glue films for the sixth and seventh conductive plugs 67 and 70.

  Among these, since the titanium nitride film is separated from the capacitor Q, there is no fear that the capacitor Q is deteriorated by hydrogen in the reaction gas even if it is formed by the MOCVD method. Therefore, it is preferable to form the titanium nitride film by the MOCVD method having better coverage than the sputtering method.

  Thereafter, the metal wiring and interlayer insulating film forming steps are repeated to form a total of five layers of metal wiring. Then, a passivation film (not shown) made of a laminated film of a silicon oxide film and a silicon nitride film is formed on the uppermost metal wiring. Thereafter, a window for exposing the bonding pad formed in the uppermost metal wiring is formed in the passivation film, thereby completing the basic structure of the semiconductor device according to the present embodiment.

  According to the present embodiment described above, as described with reference to FIG. 7B, the single-layer glue film 58 made of a conductive nitride such as titanium nitride is annealed.

  By performing this annealing in an atmosphere containing nitrogen, it is possible to nitride unreacted titanium that tends to occur in a titanium nitride film formed by sputtering.

  On the other hand, when this annealing is performed in a rare gas atmosphere, unreacted titanium can be oxidized by the residual heat of annealing by exposing the titanium nitride film to the atmosphere after the annealing is completed.

  Thus, when a tungsten film is formed as the plug conductive film 59 (FIG. 8A), abnormal growth of tungsten due to unreacted titanium is prevented, so that the first conductive plug 59a is formed. Become precise. Therefore, it is difficult for a reducing substance such as hydrogen or moisture to enter through the first conductive plug 59a, and the reducing substance does not easily enter the capacitor dielectric film 42a during the manufacturing process. As a result, the deterioration of the capacitor dielectric film 42a is prevented, and as a result, the yield of the semiconductor device including the ferroelectric capacitor Q can be improved.

  Such a yield improvement effect is particularly easily exhibited by annealing a glue film that forms a conductive plug in a region close to the capacitor Q, such as the first conductive plug 59a connected to the upper electrode 43a. .

  FIG. 11 is a graph obtained by investigating the yield rate when the glue film 58 is annealed and when it is not annealed.

In this investigation, the above-described annealing was performed on two silicon substrates, but the annealing was not performed on three silicon substrates for comparison. Then, three types of tests PT1 to PT3 were performed in this order for the capacitor Q formed on each silicon substrate. Among these, PT1 is a functional test of the transistor and the capacitor Q, and PT2 and PT3 are tests for checking whether the data written in the capacitor Q can be read after applying heat, as shown in FIG. When annealing is not performed, the rate of non-defective products in the final PT3 test is markedly reduced.

  On the other hand, when annealing is performed as in this embodiment, the non-defective rate is maintained at a high value in all tests PT1 to PT3.

  From this, it was confirmed that in the semiconductor device provided with the ferroelectric capacitor Q, the yield is improved by annealing the glue film 58.

  FIG. 12 is an enlarged cross-sectional view of the vicinity of the capacitor Q when such annealing is omitted.

  As shown in this figure, when annealing is omitted, “su” 59x is formed in the conductive plug 59a due to abnormal growth of tungsten. A reducing substance such as hydrogen tends to reach the capacitor dielectric film 42a through the "su" 59a, and the capacitor dielectric film 42a is easily reduced. In the investigation result of FIG. 11, it is considered that the reason why the non-defective product rate is reduced when annealing is omitted is due to such “su” 59x.

  Incidentally, since the capacitor dielectric film 42a is vulnerable to heat, if the annealing shown in FIG. 7B is performed at a high temperature, the yield of FeRAM may be lowered.

  Therefore, the inventor of the present application investigated the substrate temperature allowed for the annealing. The investigation results are shown in FIG. 13 and FIG. In both of the investigations in FIGS. 13 and 14, annealing was performed in a furnace in which nitrogen was 100%.

  In the investigation of FIG. 13, the substrate temperature during annealing for the glue film 58 was changed in steps of 50 ° C. in the range from 300 ° C. to 450 ° C. Thereafter, the switching charge amount of the capacitor dielectric film 42a was investigated at 48 points in the surface of the silicon substrate 20. This study was also conducted for the case of no annealing for reference. In addition, the switching charge amount was investigated when the potential difference between the lower electrode 41a and the upper electrode 43a was 1.8V and 3.0V.

  As shown in this figure, when the substrate temperature was between 300 ° C. and 400 ° C., the switching charge amount was as high as that when annealing was not performed.

  On the other hand, when the substrate temperature exceeds 400 ° C. and reaches 450 ° C., it has been clarified that the amount of switching charge rapidly decreases. As shown in the figure, some of the measurement points have a switching charge amount that is reduced by five orders of magnitude compared to the case where annealing is not performed.

  Further, in the investigation of FIG. 14, after the glue film 58 is annealed at the same substrate temperature as in FIG. 13, the leakage current between the lower electrode 41a and the upper electrode 43a is 48 points in the plane of the silicon substrate 20. The survey was conducted. The leakage current was investigated for the case where the potential of the upper electrode 43a with respect to the lower electrode 41a was + 5V and -5V.

  As shown in FIG. 14, when the substrate temperature was 300 ° C. to 400 ° C., the leakage current was as low as that when annealing was not performed.

  However, when the substrate temperature exceeded 400 ° C. and reached 450 ° C., the leak current increased rapidly, and some of the measurement points increased the leak current by 4 digits.

  As apparent from FIGS. 13 and 14, in the semiconductor device provided with the ferroelectric capacitor Q, the upper limit of the substrate temperature when the glue film 58 is annealed is set to 400 ° C. in order to prevent the deterioration of the ferroelectric capacitor Q. It is necessary to. This study found that this temperature is lower than that allowed in a normal logic product without the ferroelectric capacitor Q, and that the annealing temperature conditions are severe in FeRAM.

  As described above, in the present embodiment, the glue film 58 connected to the upper electrode 43a of the ferroelectric capacitor Q is annealed at the substrate temperature of 400 ° C. or lower to generate the first conductive plug 59a. The deterioration of the ferroelectric capacitor Q as shown in FIGS. 13 and 14 can be prevented while suppressing the minute defects that occur, and the yield of the semiconductor device can be improved.

FIGS. 1A to 1C are cross-sectional views (part 1) in the course of manufacturing the semiconductor device according to the embodiment of the present invention. 2A to 2C are cross-sectional views (part 2) in the course of manufacturing the semiconductor device according to the embodiment of the present invention. FIGS. 3A and 3B are cross-sectional views (part 3) in the course of manufacturing the semiconductor device according to the embodiment of the present invention. 4A and 4B are cross-sectional views (part 4) in the middle of the manufacture of the semiconductor device according to the embodiment of the present invention. 5A and 5B are cross-sectional views (part 5) in the course of manufacturing the semiconductor device according to the embodiment of the present invention. 6A and 6B are cross-sectional views (part 6) of the semiconductor device according to the embodiment of the present invention during manufacture. 7A and 7B are cross-sectional views (part 7) of the semiconductor device according to the embodiment of the present invention in the middle of manufacture. 8A and 8B are cross-sectional views (part 8) in the middle of the manufacture of the semiconductor device according to the embodiment of the present invention. FIG. 9 is a sectional view (No. 9) in the middle of manufacturing the semiconductor device according to the embodiment of the present invention. FIG. 10 is a sectional view (No. 9) in the middle of manufacturing the semiconductor device according to the embodiment of the present invention. FIG. 11 is a graph obtained by investigating the yield rate when the glue film is annealed and when it is not annealed. FIG. 12 is a cross-sectional view showing a minute defect of the conductive plug generated when the glue film is not annealed. FIG. 13 is a diagram showing a result of investigation on the switching charge amount of the capacitor dielectric film when the substrate temperature during annealing of the glue film is changed. FIG. 14 is a diagram showing a result of investigating the leakage current of the capacitor when the substrate temperature during annealing for the glue film is changed.

Explanation of symbols

DESCRIPTION OF SYMBOLS 20 ... Silicon substrate, 21 ... Element isolation insulating film, 22 ... P well, 23a-23c ... 1st-3rd source / drain region, 24a-24c ... 1st-3rd source / drain extension, 25a, 25b ... Gate Electrode 26 ... Insulating side wall 27 ... Refractory metal silicide layer 28 ... Gate insulating film 29 ... Cover insulating film 30 ... First insulating film 31 ... First interlayer insulating film 32a-32c ... First To third conductive plug, 36 ... antioxidation film, 36a ... silicon oxynitride film, 36b ... silicon oxide film, 37 ... first alumina film, 41 ... conductive film for lower electrode, 41a ... lower electrode, 42 ... ferroelectric Body film, 42a ... capacitor dielectric film, 43 ... conductive film for upper electrode, 43a ... upper electrode, 43b, 43c ... first and second conductive metal oxide films, 50 ... second alumina film, 54 ... second Interlayer insulating film, 54a to 54e ... 1st to 5th hole, 55 ... 1st resist pattern, 55a, 55b ... 1st, 2nd window, 57 ... 2nd resist pattern, 57c-57e ... 3rd-5th window 58 ... glue film, 59 ... plug conductive film, 59a-59e ... first to fifth conductive plugs, 62 ... first layer metal wiring, 65 ... third interlayer insulating film, 67 ... sixth conductive plug, 68 ... second-layer metal wiring, 69 ... fourth interlayer insulating film, 70 ... seventh conductive plug.

Claims (5)

Forming a first insulating film above the semiconductor substrate;
Forming a capacitor by laminating a lower electrode, a capacitor dielectric film made of a ferroelectric material, and an upper electrode made of a conductive oxide in this order on the first insulating film;
Forming a second insulating film covering the capacitor;
Forming a hole exposing the upper electrode in the second insulating film on the upper electrode;
Forming a glue film made of conductive nitride connected to the upper electrode in the hole;
Annealing the glue film in an atmosphere containing nitrogen;
After the annealing, forming a conductive plug on the glue film in the hole;
A method for manufacturing a semiconductor device, comprising:   2. The method of manufacturing a semiconductor device according to claim 1, wherein in the step of annealing the glue film, the upper limit of the substrate temperature is set to 400 [deg.] C. or less. The method of manufacturing a semiconductor device according to claim 1, wherein the atmosphere is a plasma atmosphere containing N ₂ O.   4. The semiconductor device according to claim 1, wherein any one of titanium nitride, tantalum nitride, and titanium aluminum nitride is used as the conductive nitride constituting the glue film. 5. Production method.   The method of manufacturing a semiconductor device according to claim 1, wherein the step of forming the glue film is performed by a sputtering method.

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